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[SPARC64]: Elminate all usage of hard-coded trap globals.
[deliverable/linux.git] / arch / sparc64 / kernel / etrap.S
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1da177e4
LT		 1/* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
3 *
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8#include <linux/config.h>
9
10#include <asm/asi.h>
11#include <asm/pstate.h>
12#include <asm/ptrace.h>
13#include <asm/page.h>
14#include <asm/spitfire.h>
15#include <asm/head.h>
16#include <asm/processor.h>
17#include <asm/mmu.h>
18
19#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
20#define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
21#define ETRAP_PSTATE2 \
22 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
23
24/*
25 * On entry, %g7 is return address - 0x4.
26 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
27 */
28
29 .text
30 .align 64
31 .globl etrap, etrap_irq, etraptl1
32etrap: rdpr %pil, %g2
33etrap_irq:
56fb4df6 34 TRAP_LOAD_THREAD_REG
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LT		 35 rdpr %tstate, %g1
36 sllx %g2, 20, %g3
37 andcc %g1, TSTATE_PRIV, %g0
38 or %g1, %g3, %g1
39 bne,pn %xcc, 1f
40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
41 wrpr %g0, 7, %cleanwin
42
43 sethi %hi(TASK_REGOFF), %g2
44 sethi %hi(TSTATE_PEF), %g3
45 or %g2, %lo(TASK_REGOFF), %g2
46 and %g1, %g3, %g3
47 brnz,pn %g3, 1f
48 add %g6, %g2, %g2
49 wr %g0, 0, %fprs
501: rdpr %tpc, %g3
51
52 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
53 rdpr %tnpc, %g1
54 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
55 rd %y, %g3
56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
57 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
58 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
59 mov %g6, %l6
60
61 bne,pn %xcc, 3f
62 mov PRIMARY_CONTEXT, %l4
63 rdpr %canrestore, %g3
64 rdpr %wstate, %g2
65 wrpr %g0, 0, %canrestore
66 sll %g2, 3, %g2
67 mov 1, %l5
68 stb %l5, [%l6 + TI_FPDEPTH]
69
70 wrpr %g3, 0, %otherwin
71 wrpr %g2, 0, %wstate
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DM		 72 sethi %hi(sparc64_kern_pri_context), %g2
73 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
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LT		 74 stxa %g3, [%l4] ASI_DMMU
75 flush %l6
76 wr %g0, ASI_AIUS, %asi
772: wrpr %g0, 0x0, %tl
78 mov %g4, %l4
79 mov %g5, %l5
80
81 mov %g7, %l2
82 wrpr %g0, ETRAP_PSTATE1, %pstate
83 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
84 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
85 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
86 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
87 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
88 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
89
90 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
91 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
92 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
93 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
94 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
95 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
96 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
97
98 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
99 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
100 wrpr %g0, ETRAP_PSTATE2, %pstate
101 mov %l6, %g6
56fb4df6 102 LOAD_PER_CPU_BASE(%g4, %g3)
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LT		 103 jmpl %l2 + 0x4, %g0
104 ldx [%g6 + TI_TASK], %g4
105
1063: ldub [%l6 + TI_FPDEPTH], %l5
107 add %l6, TI_FPSAVED + 1, %l4
108 srl %l5, 1, %l3
109 add %l5, 2, %l5
110 stb %l5, [%l6 + TI_FPDEPTH]
111 ba,pt %xcc, 2b
112 stb %g0, [%l4 + %l3]
113 nop
114
115etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
116 * We place this right after pt_regs on the trap stack.
117 * The layout is:
118 * 0x00 TL1's TSTATE
119 * 0x08 TL1's TPC
120 * 0x10 TL1's TNPC
121 * 0x18 TL1's TT
122 * ...
123 * 0x58 TL4's TT
124 * 0x60 TL
125 */
56fb4df6 126 TRAP_LOAD_THREAD_REG
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LT		 127 sub %sp, ((4 * 8) * 4) + 8, %g2
128 rdpr %tl, %g1
129
130 wrpr %g0, 1, %tl
131 rdpr %tstate, %g3
132 stx %g3, [%g2 + STACK_BIAS + 0x00]
133 rdpr %tpc, %g3
134 stx %g3, [%g2 + STACK_BIAS + 0x08]
135 rdpr %tnpc, %g3
136 stx %g3, [%g2 + STACK_BIAS + 0x10]
137 rdpr %tt, %g3
138 stx %g3, [%g2 + STACK_BIAS + 0x18]
139
140 wrpr %g0, 2, %tl
141 rdpr %tstate, %g3
142 stx %g3, [%g2 + STACK_BIAS + 0x20]
143 rdpr %tpc, %g3
144 stx %g3, [%g2 + STACK_BIAS + 0x28]
145 rdpr %tnpc, %g3
146 stx %g3, [%g2 + STACK_BIAS + 0x30]
147 rdpr %tt, %g3
148 stx %g3, [%g2 + STACK_BIAS + 0x38]
149
150 wrpr %g0, 3, %tl
151 rdpr %tstate, %g3
152 stx %g3, [%g2 + STACK_BIAS + 0x40]
153 rdpr %tpc, %g3
154 stx %g3, [%g2 + STACK_BIAS + 0x48]
155 rdpr %tnpc, %g3
156 stx %g3, [%g2 + STACK_BIAS + 0x50]
157 rdpr %tt, %g3
158 stx %g3, [%g2 + STACK_BIAS + 0x58]
159
160 wrpr %g0, 4, %tl
161 rdpr %tstate, %g3
162 stx %g3, [%g2 + STACK_BIAS + 0x60]
163 rdpr %tpc, %g3
164 stx %g3, [%g2 + STACK_BIAS + 0x68]
165 rdpr %tnpc, %g3
166 stx %g3, [%g2 + STACK_BIAS + 0x70]
167 rdpr %tt, %g3
168 stx %g3, [%g2 + STACK_BIAS + 0x78]
169
170 wrpr %g1, %tl
171 stx %g1, [%g2 + STACK_BIAS + 0x80]
172
173 rdpr %tstate, %g1
174 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
175 ba,pt %xcc, 1b
176 andcc %g1, TSTATE_PRIV, %g0
177
178 .align 64
179 .globl scetrap
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DM		 180scetrap:
181 TRAP_LOAD_THREAD_REG
182 rdpr %pil, %g2
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LT		 183 rdpr %tstate, %g1
184 sllx %g2, 20, %g3
185 andcc %g1, TSTATE_PRIV, %g0
186 or %g1, %g3, %g1
187 bne,pn %xcc, 1f
188 sub %sp, (STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS), %g2
189 wrpr %g0, 7, %cleanwin
190
191 sllx %g1, 51, %g3
192 sethi %hi(TASK_REGOFF), %g2
193 or %g2, %lo(TASK_REGOFF), %g2
194 brlz,pn %g3, 1f
195 add %g6, %g2, %g2
196 wr %g0, 0, %fprs
1971: rdpr %tpc, %g3
198 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
199
200 rdpr %tnpc, %g1
201 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
202 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
203 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
204 mov %g6, %l6
205 bne,pn %xcc, 2f
206 mov ASI_P, %l7
207 rdpr %canrestore, %g3
208
209 rdpr %wstate, %g2
210 wrpr %g0, 0, %canrestore
211 sll %g2, 3, %g2
212 mov PRIMARY_CONTEXT, %l4
213 wrpr %g3, 0, %otherwin
214 wrpr %g2, 0, %wstate
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DM		 215 sethi %hi(sparc64_kern_pri_context), %g2
216 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
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LT		 217 stxa %g3, [%l4] ASI_DMMU
218 flush %l6
219
220 mov ASI_AIUS, %l7
2212: mov %g4, %l4
222 mov %g5, %l5
223 add %g7, 0x4, %l2
224 wrpr %g0, ETRAP_PSTATE1, %pstate
225 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
226 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
227 sllx %l7, 24, %l7
228
229 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
230 rdpr %cwp, %l0
231 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
232 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
233 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
234 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
235 or %l7, %l0, %l7
236 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
237
238 or %l7, %l0, %l7
239 wrpr %l2, %tnpc
240 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
241 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
242 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
243 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
244 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
245 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
246
247 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
248 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
249 mov %l6, %g6
250 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
56fb4df6 251 LOAD_PER_CPU_BASE(%g4, %g3)
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LT		 252 ldx [%g6 + TI_TASK], %g4
253 done
254
255#undef TASK_REGOFF
256#undef ETRAP_PSTATE1
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