Commit | Line | Data |
---|---|---|
ad7ad57c | 1 | /* iommu.c: Generic sparc64 IOMMU support. |
1da177e4 | 2 | * |
16ce82d8 | 3 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com) |
5 | */ | |
6 | ||
7 | #include <linux/kernel.h> | |
ad7ad57c | 8 | #include <linux/module.h> |
4dbc30fb | 9 | #include <linux/delay.h> |
ad7ad57c DM |
10 | #include <linux/device.h> |
11 | #include <linux/dma-mapping.h> | |
12 | #include <linux/errno.h> | |
13 | ||
14 | #ifdef CONFIG_PCI | |
c57c2ffb | 15 | #include <linux/pci.h> |
ad7ad57c | 16 | #endif |
1da177e4 | 17 | |
ad7ad57c | 18 | #include <asm/iommu.h> |
1da177e4 LT |
19 | |
20 | #include "iommu_common.h" | |
21 | ||
ad7ad57c | 22 | #define STC_CTXMATCH_ADDR(STC, CTX) \ |
1da177e4 | 23 | ((STC)->strbuf_ctxmatch_base + ((CTX) << 3)) |
ad7ad57c DM |
24 | #define STC_FLUSHFLAG_INIT(STC) \ |
25 | (*((STC)->strbuf_flushflag) = 0UL) | |
26 | #define STC_FLUSHFLAG_SET(STC) \ | |
27 | (*((STC)->strbuf_flushflag) != 0UL) | |
1da177e4 | 28 | |
ad7ad57c | 29 | #define iommu_read(__reg) \ |
1da177e4 LT |
30 | ({ u64 __ret; \ |
31 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
32 | : "=r" (__ret) \ | |
33 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
34 | : "memory"); \ | |
35 | __ret; \ | |
36 | }) | |
ad7ad57c | 37 | #define iommu_write(__reg, __val) \ |
1da177e4 LT |
38 | __asm__ __volatile__("stxa %0, [%1] %2" \ |
39 | : /* no outputs */ \ | |
40 | : "r" (__val), "r" (__reg), \ | |
41 | "i" (ASI_PHYS_BYPASS_EC_E)) | |
42 | ||
43 | /* Must be invoked under the IOMMU lock. */ | |
16ce82d8 | 44 | static void __iommu_flushall(struct iommu *iommu) |
1da177e4 | 45 | { |
861fe906 | 46 | if (iommu->iommu_flushinv) { |
ad7ad57c | 47 | iommu_write(iommu->iommu_flushinv, ~(u64)0); |
861fe906 DM |
48 | } else { |
49 | unsigned long tag; | |
50 | int entry; | |
1da177e4 | 51 | |
ad7ad57c | 52 | tag = iommu->iommu_tags; |
861fe906 | 53 | for (entry = 0; entry < 16; entry++) { |
ad7ad57c | 54 | iommu_write(tag, 0); |
861fe906 DM |
55 | tag += 8; |
56 | } | |
1da177e4 | 57 | |
861fe906 | 58 | /* Ensure completion of previous PIO writes. */ |
ad7ad57c | 59 | (void) iommu_read(iommu->write_complete_reg); |
861fe906 | 60 | } |
1da177e4 LT |
61 | } |
62 | ||
63 | #define IOPTE_CONSISTENT(CTX) \ | |
64 | (IOPTE_VALID | IOPTE_CACHE | \ | |
65 | (((CTX) << 47) & IOPTE_CONTEXT)) | |
66 | ||
67 | #define IOPTE_STREAMING(CTX) \ | |
68 | (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF) | |
69 | ||
70 | /* Existing mappings are never marked invalid, instead they | |
71 | * are pointed to a dummy page. | |
72 | */ | |
73 | #define IOPTE_IS_DUMMY(iommu, iopte) \ | |
74 | ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa) | |
75 | ||
16ce82d8 | 76 | static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte) |
1da177e4 LT |
77 | { |
78 | unsigned long val = iopte_val(*iopte); | |
79 | ||
80 | val &= ~IOPTE_PAGE; | |
81 | val |= iommu->dummy_page_pa; | |
82 | ||
83 | iopte_val(*iopte) = val; | |
84 | } | |
85 | ||
688cb30b | 86 | /* Based largely upon the ppc64 iommu allocator. */ |
ad7ad57c | 87 | static long arena_alloc(struct iommu *iommu, unsigned long npages) |
688cb30b | 88 | { |
9b3627f3 | 89 | struct iommu_arena *arena = &iommu->arena; |
688cb30b DM |
90 | unsigned long n, i, start, end, limit; |
91 | int pass; | |
92 | ||
93 | limit = arena->limit; | |
94 | start = arena->hint; | |
95 | pass = 0; | |
96 | ||
97 | again: | |
98 | n = find_next_zero_bit(arena->map, limit, start); | |
99 | end = n + npages; | |
100 | if (unlikely(end >= limit)) { | |
101 | if (likely(pass < 1)) { | |
102 | limit = start; | |
103 | start = 0; | |
104 | __iommu_flushall(iommu); | |
105 | pass++; | |
106 | goto again; | |
107 | } else { | |
108 | /* Scanned the whole thing, give up. */ | |
109 | return -1; | |
110 | } | |
111 | } | |
112 | ||
113 | for (i = n; i < end; i++) { | |
114 | if (test_bit(i, arena->map)) { | |
115 | start = i + 1; | |
116 | goto again; | |
117 | } | |
118 | } | |
119 | ||
120 | for (i = n; i < end; i++) | |
121 | __set_bit(i, arena->map); | |
122 | ||
123 | arena->hint = end; | |
124 | ||
125 | return n; | |
126 | } | |
127 | ||
ad7ad57c | 128 | static void arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages) |
688cb30b DM |
129 | { |
130 | unsigned long i; | |
131 | ||
132 | for (i = base; i < (base + npages); i++) | |
133 | __clear_bit(i, arena->map); | |
134 | } | |
135 | ||
ad7ad57c DM |
136 | int iommu_table_init(struct iommu *iommu, int tsbsize, |
137 | u32 dma_offset, u32 dma_addr_mask) | |
1da177e4 | 138 | { |
688cb30b DM |
139 | unsigned long i, tsbbase, order, sz, num_tsb_entries; |
140 | ||
141 | num_tsb_entries = tsbsize / sizeof(iopte_t); | |
51e85136 DM |
142 | |
143 | /* Setup initial software IOMMU state. */ | |
144 | spin_lock_init(&iommu->lock); | |
145 | iommu->ctx_lowest_free = 1; | |
146 | iommu->page_table_map_base = dma_offset; | |
147 | iommu->dma_addr_mask = dma_addr_mask; | |
148 | ||
688cb30b DM |
149 | /* Allocate and initialize the free area map. */ |
150 | sz = num_tsb_entries / 8; | |
151 | sz = (sz + 7UL) & ~7UL; | |
9132983a | 152 | iommu->arena.map = kzalloc(sz, GFP_KERNEL); |
688cb30b | 153 | if (!iommu->arena.map) { |
ad7ad57c DM |
154 | printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n"); |
155 | return -ENOMEM; | |
51e85136 | 156 | } |
688cb30b | 157 | iommu->arena.limit = num_tsb_entries; |
1da177e4 | 158 | |
51e85136 DM |
159 | /* Allocate and initialize the dummy page which we |
160 | * set inactive IO PTEs to point to. | |
161 | */ | |
162 | iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); | |
163 | if (!iommu->dummy_page) { | |
ad7ad57c DM |
164 | printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n"); |
165 | goto out_free_map; | |
51e85136 DM |
166 | } |
167 | memset((void *)iommu->dummy_page, 0, PAGE_SIZE); | |
168 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); | |
169 | ||
170 | /* Now allocate and setup the IOMMU page table itself. */ | |
171 | order = get_order(tsbsize); | |
172 | tsbbase = __get_free_pages(GFP_KERNEL, order); | |
173 | if (!tsbbase) { | |
ad7ad57c DM |
174 | printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n"); |
175 | goto out_free_dummy_page; | |
51e85136 DM |
176 | } |
177 | iommu->page_table = (iopte_t *)tsbbase; | |
1da177e4 | 178 | |
688cb30b | 179 | for (i = 0; i < num_tsb_entries; i++) |
1da177e4 | 180 | iopte_make_dummy(iommu, &iommu->page_table[i]); |
ad7ad57c DM |
181 | |
182 | return 0; | |
183 | ||
184 | out_free_dummy_page: | |
185 | free_page(iommu->dummy_page); | |
186 | iommu->dummy_page = 0UL; | |
187 | ||
188 | out_free_map: | |
189 | kfree(iommu->arena.map); | |
190 | iommu->arena.map = NULL; | |
191 | ||
192 | return -ENOMEM; | |
1da177e4 LT |
193 | } |
194 | ||
16ce82d8 | 195 | static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages) |
1da177e4 | 196 | { |
688cb30b | 197 | long entry; |
1da177e4 | 198 | |
ad7ad57c | 199 | entry = arena_alloc(iommu, npages); |
688cb30b DM |
200 | if (unlikely(entry < 0)) |
201 | return NULL; | |
1da177e4 | 202 | |
688cb30b | 203 | return iommu->page_table + entry; |
1da177e4 LT |
204 | } |
205 | ||
16ce82d8 | 206 | static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages) |
1da177e4 | 207 | { |
ad7ad57c | 208 | arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages); |
1da177e4 LT |
209 | } |
210 | ||
16ce82d8 | 211 | static int iommu_alloc_ctx(struct iommu *iommu) |
7c963ad1 DM |
212 | { |
213 | int lowest = iommu->ctx_lowest_free; | |
214 | int sz = IOMMU_NUM_CTXS - lowest; | |
215 | int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest); | |
216 | ||
217 | if (unlikely(n == sz)) { | |
218 | n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1); | |
219 | if (unlikely(n == lowest)) { | |
220 | printk(KERN_WARNING "IOMMU: Ran out of contexts.\n"); | |
221 | n = 0; | |
222 | } | |
223 | } | |
224 | if (n) | |
225 | __set_bit(n, iommu->ctx_bitmap); | |
226 | ||
227 | return n; | |
228 | } | |
229 | ||
16ce82d8 | 230 | static inline void iommu_free_ctx(struct iommu *iommu, int ctx) |
7c963ad1 DM |
231 | { |
232 | if (likely(ctx)) { | |
233 | __clear_bit(ctx, iommu->ctx_bitmap); | |
234 | if (ctx < iommu->ctx_lowest_free) | |
235 | iommu->ctx_lowest_free = ctx; | |
236 | } | |
237 | } | |
238 | ||
ad7ad57c DM |
239 | static void *dma_4u_alloc_coherent(struct device *dev, size_t size, |
240 | dma_addr_t *dma_addrp, gfp_t gfp) | |
1da177e4 | 241 | { |
16ce82d8 | 242 | struct iommu *iommu; |
1da177e4 | 243 | iopte_t *iopte; |
688cb30b | 244 | unsigned long flags, order, first_page; |
1da177e4 LT |
245 | void *ret; |
246 | int npages; | |
247 | ||
248 | size = IO_PAGE_ALIGN(size); | |
249 | order = get_order(size); | |
250 | if (order >= 10) | |
251 | return NULL; | |
252 | ||
42f14237 | 253 | first_page = __get_free_pages(gfp, order); |
1da177e4 LT |
254 | if (first_page == 0UL) |
255 | return NULL; | |
256 | memset((char *)first_page, 0, PAGE_SIZE << order); | |
257 | ||
ad7ad57c | 258 | iommu = dev->archdata.iommu; |
1da177e4 LT |
259 | |
260 | spin_lock_irqsave(&iommu->lock, flags); | |
688cb30b DM |
261 | iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT); |
262 | spin_unlock_irqrestore(&iommu->lock, flags); | |
263 | ||
264 | if (unlikely(iopte == NULL)) { | |
1da177e4 LT |
265 | free_pages(first_page, order); |
266 | return NULL; | |
267 | } | |
268 | ||
269 | *dma_addrp = (iommu->page_table_map_base + | |
270 | ((iopte - iommu->page_table) << IO_PAGE_SHIFT)); | |
271 | ret = (void *) first_page; | |
272 | npages = size >> IO_PAGE_SHIFT; | |
1da177e4 LT |
273 | first_page = __pa(first_page); |
274 | while (npages--) { | |
688cb30b | 275 | iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) | |
1da177e4 LT |
276 | IOPTE_WRITE | |
277 | (first_page & IOPTE_PAGE)); | |
278 | iopte++; | |
279 | first_page += IO_PAGE_SIZE; | |
280 | } | |
281 | ||
1da177e4 LT |
282 | return ret; |
283 | } | |
284 | ||
ad7ad57c DM |
285 | static void dma_4u_free_coherent(struct device *dev, size_t size, |
286 | void *cpu, dma_addr_t dvma) | |
1da177e4 | 287 | { |
16ce82d8 | 288 | struct iommu *iommu; |
1da177e4 | 289 | iopte_t *iopte; |
688cb30b | 290 | unsigned long flags, order, npages; |
1da177e4 LT |
291 | |
292 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
ad7ad57c | 293 | iommu = dev->archdata.iommu; |
1da177e4 LT |
294 | iopte = iommu->page_table + |
295 | ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
296 | ||
297 | spin_lock_irqsave(&iommu->lock, flags); | |
298 | ||
012d64ff | 299 | free_npages(iommu, dvma - iommu->page_table_map_base, npages); |
7c963ad1 | 300 | |
1da177e4 LT |
301 | spin_unlock_irqrestore(&iommu->lock, flags); |
302 | ||
303 | order = get_order(size); | |
304 | if (order < 10) | |
305 | free_pages((unsigned long)cpu, order); | |
306 | } | |
307 | ||
ad7ad57c DM |
308 | static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz, |
309 | enum dma_data_direction direction) | |
1da177e4 | 310 | { |
16ce82d8 DM |
311 | struct iommu *iommu; |
312 | struct strbuf *strbuf; | |
1da177e4 LT |
313 | iopte_t *base; |
314 | unsigned long flags, npages, oaddr; | |
315 | unsigned long i, base_paddr, ctx; | |
316 | u32 bus_addr, ret; | |
317 | unsigned long iopte_protection; | |
318 | ||
ad7ad57c DM |
319 | iommu = dev->archdata.iommu; |
320 | strbuf = dev->archdata.stc; | |
1da177e4 | 321 | |
ad7ad57c | 322 | if (unlikely(direction == DMA_NONE)) |
688cb30b | 323 | goto bad_no_ctx; |
1da177e4 LT |
324 | |
325 | oaddr = (unsigned long)ptr; | |
326 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); | |
327 | npages >>= IO_PAGE_SHIFT; | |
328 | ||
329 | spin_lock_irqsave(&iommu->lock, flags); | |
688cb30b DM |
330 | base = alloc_npages(iommu, npages); |
331 | ctx = 0; | |
332 | if (iommu->iommu_ctxflush) | |
333 | ctx = iommu_alloc_ctx(iommu); | |
334 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 335 | |
688cb30b | 336 | if (unlikely(!base)) |
1da177e4 | 337 | goto bad; |
688cb30b | 338 | |
1da177e4 LT |
339 | bus_addr = (iommu->page_table_map_base + |
340 | ((base - iommu->page_table) << IO_PAGE_SHIFT)); | |
341 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
342 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
1da177e4 LT |
343 | if (strbuf->strbuf_enabled) |
344 | iopte_protection = IOPTE_STREAMING(ctx); | |
345 | else | |
346 | iopte_protection = IOPTE_CONSISTENT(ctx); | |
ad7ad57c | 347 | if (direction != DMA_TO_DEVICE) |
1da177e4 LT |
348 | iopte_protection |= IOPTE_WRITE; |
349 | ||
350 | for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) | |
351 | iopte_val(*base) = iopte_protection | base_paddr; | |
352 | ||
1da177e4 LT |
353 | return ret; |
354 | ||
355 | bad: | |
688cb30b DM |
356 | iommu_free_ctx(iommu, ctx); |
357 | bad_no_ctx: | |
358 | if (printk_ratelimit()) | |
359 | WARN_ON(1); | |
ad7ad57c | 360 | return DMA_ERROR_CODE; |
1da177e4 LT |
361 | } |
362 | ||
ad7ad57c DM |
363 | static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu, |
364 | u32 vaddr, unsigned long ctx, unsigned long npages, | |
365 | enum dma_data_direction direction) | |
4dbc30fb DM |
366 | { |
367 | int limit; | |
368 | ||
4dbc30fb DM |
369 | if (strbuf->strbuf_ctxflush && |
370 | iommu->iommu_ctxflush) { | |
371 | unsigned long matchreg, flushreg; | |
7c963ad1 | 372 | u64 val; |
4dbc30fb DM |
373 | |
374 | flushreg = strbuf->strbuf_ctxflush; | |
ad7ad57c | 375 | matchreg = STC_CTXMATCH_ADDR(strbuf, ctx); |
4dbc30fb | 376 | |
ad7ad57c DM |
377 | iommu_write(flushreg, ctx); |
378 | val = iommu_read(matchreg); | |
88314ee7 DM |
379 | val &= 0xffff; |
380 | if (!val) | |
7c963ad1 DM |
381 | goto do_flush_sync; |
382 | ||
7c963ad1 DM |
383 | while (val) { |
384 | if (val & 0x1) | |
ad7ad57c | 385 | iommu_write(flushreg, ctx); |
7c963ad1 | 386 | val >>= 1; |
a228dfd5 | 387 | } |
ad7ad57c | 388 | val = iommu_read(matchreg); |
7c963ad1 | 389 | if (unlikely(val)) { |
ad7ad57c | 390 | printk(KERN_WARNING "strbuf_flush: ctx flush " |
7c963ad1 DM |
391 | "timeout matchreg[%lx] ctx[%lx]\n", |
392 | val, ctx); | |
393 | goto do_page_flush; | |
394 | } | |
4dbc30fb DM |
395 | } else { |
396 | unsigned long i; | |
397 | ||
7c963ad1 | 398 | do_page_flush: |
4dbc30fb | 399 | for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE) |
ad7ad57c | 400 | iommu_write(strbuf->strbuf_pflush, vaddr); |
4dbc30fb DM |
401 | } |
402 | ||
7c963ad1 DM |
403 | do_flush_sync: |
404 | /* If the device could not have possibly put dirty data into | |
405 | * the streaming cache, no flush-flag synchronization needs | |
406 | * to be performed. | |
407 | */ | |
ad7ad57c | 408 | if (direction == DMA_TO_DEVICE) |
7c963ad1 DM |
409 | return; |
410 | ||
ad7ad57c DM |
411 | STC_FLUSHFLAG_INIT(strbuf); |
412 | iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa); | |
413 | (void) iommu_read(iommu->write_complete_reg); | |
4dbc30fb | 414 | |
a228dfd5 | 415 | limit = 100000; |
ad7ad57c | 416 | while (!STC_FLUSHFLAG_SET(strbuf)) { |
4dbc30fb DM |
417 | limit--; |
418 | if (!limit) | |
419 | break; | |
a228dfd5 | 420 | udelay(1); |
4f07118f | 421 | rmb(); |
4dbc30fb DM |
422 | } |
423 | if (!limit) | |
ad7ad57c | 424 | printk(KERN_WARNING "strbuf_flush: flushflag timeout " |
4dbc30fb DM |
425 | "vaddr[%08x] ctx[%lx] npages[%ld]\n", |
426 | vaddr, ctx, npages); | |
427 | } | |
428 | ||
ad7ad57c DM |
429 | static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr, |
430 | size_t sz, enum dma_data_direction direction) | |
1da177e4 | 431 | { |
16ce82d8 DM |
432 | struct iommu *iommu; |
433 | struct strbuf *strbuf; | |
1da177e4 | 434 | iopte_t *base; |
688cb30b | 435 | unsigned long flags, npages, ctx, i; |
1da177e4 | 436 | |
ad7ad57c | 437 | if (unlikely(direction == DMA_NONE)) { |
688cb30b DM |
438 | if (printk_ratelimit()) |
439 | WARN_ON(1); | |
440 | return; | |
441 | } | |
1da177e4 | 442 | |
ad7ad57c DM |
443 | iommu = dev->archdata.iommu; |
444 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
445 | |
446 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
447 | npages >>= IO_PAGE_SHIFT; | |
448 | base = iommu->page_table + | |
449 | ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
1da177e4 LT |
450 | bus_addr &= IO_PAGE_MASK; |
451 | ||
452 | spin_lock_irqsave(&iommu->lock, flags); | |
453 | ||
454 | /* Record the context, if any. */ | |
455 | ctx = 0; | |
456 | if (iommu->iommu_ctxflush) | |
457 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
458 | ||
459 | /* Step 1: Kick data out of streaming buffers if necessary. */ | |
4dbc30fb | 460 | if (strbuf->strbuf_enabled) |
ad7ad57c DM |
461 | strbuf_flush(strbuf, iommu, bus_addr, ctx, |
462 | npages, direction); | |
1da177e4 | 463 | |
688cb30b DM |
464 | /* Step 2: Clear out TSB entries. */ |
465 | for (i = 0; i < npages; i++) | |
466 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 467 | |
688cb30b | 468 | free_npages(iommu, bus_addr - iommu->page_table_map_base, npages); |
1da177e4 | 469 | |
7c963ad1 DM |
470 | iommu_free_ctx(iommu, ctx); |
471 | ||
1da177e4 LT |
472 | spin_unlock_irqrestore(&iommu->lock, flags); |
473 | } | |
474 | ||
ad7ad57c DM |
475 | static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist, |
476 | int nelems, enum dma_data_direction direction) | |
1da177e4 | 477 | { |
38192d52 DM |
478 | unsigned long flags, ctx, i, npages, iopte_protection; |
479 | struct scatterlist *sg; | |
16ce82d8 | 480 | struct strbuf *strbuf; |
38192d52 | 481 | struct iommu *iommu; |
1da177e4 LT |
482 | iopte_t *base; |
483 | u32 dma_base; | |
1da177e4 LT |
484 | |
485 | /* Fast path single entry scatterlists. */ | |
486 | if (nelems == 1) { | |
487 | sglist->dma_address = | |
58b053e4 | 488 | dma_4u_map_single(dev, sg_virt(sglist), |
18397944 | 489 | sglist->length, direction); |
ad7ad57c | 490 | if (unlikely(sglist->dma_address == DMA_ERROR_CODE)) |
688cb30b | 491 | return 0; |
1da177e4 LT |
492 | sglist->dma_length = sglist->length; |
493 | return 1; | |
494 | } | |
495 | ||
ad7ad57c DM |
496 | iommu = dev->archdata.iommu; |
497 | strbuf = dev->archdata.stc; | |
498 | ||
499 | if (unlikely(direction == DMA_NONE)) | |
688cb30b | 500 | goto bad_no_ctx; |
1da177e4 | 501 | |
38192d52 | 502 | npages = calc_npages(sglist, nelems); |
1da177e4 LT |
503 | |
504 | spin_lock_irqsave(&iommu->lock, flags); | |
505 | ||
688cb30b DM |
506 | base = alloc_npages(iommu, npages); |
507 | ctx = 0; | |
508 | if (iommu->iommu_ctxflush) | |
509 | ctx = iommu_alloc_ctx(iommu); | |
510 | ||
511 | spin_unlock_irqrestore(&iommu->lock, flags); | |
512 | ||
1da177e4 LT |
513 | if (base == NULL) |
514 | goto bad; | |
688cb30b DM |
515 | |
516 | dma_base = iommu->page_table_map_base + | |
517 | ((base - iommu->page_table) << IO_PAGE_SHIFT); | |
1da177e4 | 518 | |
1da177e4 LT |
519 | if (strbuf->strbuf_enabled) |
520 | iopte_protection = IOPTE_STREAMING(ctx); | |
521 | else | |
522 | iopte_protection = IOPTE_CONSISTENT(ctx); | |
ad7ad57c | 523 | if (direction != DMA_TO_DEVICE) |
1da177e4 | 524 | iopte_protection |= IOPTE_WRITE; |
688cb30b | 525 | |
38192d52 DM |
526 | for_each_sg(sglist, sg, nelems, i) { |
527 | unsigned long paddr = SG_ENT_PHYS_ADDRESS(sg); | |
528 | unsigned long slen = sg->length; | |
529 | unsigned long this_npages; | |
688cb30b | 530 | |
38192d52 | 531 | this_npages = iommu_num_pages(paddr, slen); |
1da177e4 | 532 | |
38192d52 DM |
533 | sg->dma_address = dma_base | (paddr & ~IO_PAGE_MASK); |
534 | sg->dma_length = slen; | |
535 | ||
536 | paddr &= IO_PAGE_MASK; | |
537 | while (this_npages--) { | |
538 | iopte_val(*base) = iopte_protection | paddr; | |
539 | ||
540 | base++; | |
541 | paddr += IO_PAGE_SIZE; | |
542 | dma_base += IO_PAGE_SIZE; | |
543 | } | |
544 | } | |
545 | ||
546 | return nelems; | |
1da177e4 LT |
547 | |
548 | bad: | |
688cb30b DM |
549 | iommu_free_ctx(iommu, ctx); |
550 | bad_no_ctx: | |
551 | if (printk_ratelimit()) | |
552 | WARN_ON(1); | |
553 | return 0; | |
1da177e4 LT |
554 | } |
555 | ||
ad7ad57c DM |
556 | static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist, |
557 | int nelems, enum dma_data_direction direction) | |
1da177e4 | 558 | { |
38192d52 | 559 | unsigned long flags, ctx, i, npages; |
16ce82d8 | 560 | struct strbuf *strbuf; |
38192d52 | 561 | struct iommu *iommu; |
1da177e4 | 562 | iopte_t *base; |
1da177e4 LT |
563 | u32 bus_addr; |
564 | ||
ad7ad57c | 565 | if (unlikely(direction == DMA_NONE)) { |
688cb30b DM |
566 | if (printk_ratelimit()) |
567 | WARN_ON(1); | |
568 | } | |
1da177e4 | 569 | |
ad7ad57c DM |
570 | iommu = dev->archdata.iommu; |
571 | strbuf = dev->archdata.stc; | |
572 | ||
1da177e4 LT |
573 | bus_addr = sglist->dma_address & IO_PAGE_MASK; |
574 | ||
38192d52 | 575 | npages = calc_npages(sglist, nelems); |
1da177e4 LT |
576 | |
577 | base = iommu->page_table + | |
578 | ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
579 | ||
1da177e4 LT |
580 | spin_lock_irqsave(&iommu->lock, flags); |
581 | ||
582 | /* Record the context, if any. */ | |
583 | ctx = 0; | |
584 | if (iommu->iommu_ctxflush) | |
585 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
586 | ||
587 | /* Step 1: Kick data out of streaming buffers if necessary. */ | |
4dbc30fb | 588 | if (strbuf->strbuf_enabled) |
ad7ad57c | 589 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 | 590 | |
688cb30b DM |
591 | /* Step 2: Clear out the TSB entries. */ |
592 | for (i = 0; i < npages; i++) | |
593 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 594 | |
688cb30b | 595 | free_npages(iommu, bus_addr - iommu->page_table_map_base, npages); |
1da177e4 | 596 | |
7c963ad1 DM |
597 | iommu_free_ctx(iommu, ctx); |
598 | ||
1da177e4 LT |
599 | spin_unlock_irqrestore(&iommu->lock, flags); |
600 | } | |
601 | ||
ad7ad57c DM |
602 | static void dma_4u_sync_single_for_cpu(struct device *dev, |
603 | dma_addr_t bus_addr, size_t sz, | |
604 | enum dma_data_direction direction) | |
1da177e4 | 605 | { |
16ce82d8 DM |
606 | struct iommu *iommu; |
607 | struct strbuf *strbuf; | |
1da177e4 LT |
608 | unsigned long flags, ctx, npages; |
609 | ||
ad7ad57c DM |
610 | iommu = dev->archdata.iommu; |
611 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
612 | |
613 | if (!strbuf->strbuf_enabled) | |
614 | return; | |
615 | ||
616 | spin_lock_irqsave(&iommu->lock, flags); | |
617 | ||
618 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
619 | npages >>= IO_PAGE_SHIFT; | |
620 | bus_addr &= IO_PAGE_MASK; | |
621 | ||
622 | /* Step 1: Record the context, if any. */ | |
623 | ctx = 0; | |
624 | if (iommu->iommu_ctxflush && | |
625 | strbuf->strbuf_ctxflush) { | |
626 | iopte_t *iopte; | |
627 | ||
628 | iopte = iommu->page_table + | |
629 | ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT); | |
630 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; | |
631 | } | |
632 | ||
633 | /* Step 2: Kick data out of streaming buffers. */ | |
ad7ad57c | 634 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
635 | |
636 | spin_unlock_irqrestore(&iommu->lock, flags); | |
637 | } | |
638 | ||
ad7ad57c DM |
639 | static void dma_4u_sync_sg_for_cpu(struct device *dev, |
640 | struct scatterlist *sglist, int nelems, | |
641 | enum dma_data_direction direction) | |
1da177e4 | 642 | { |
16ce82d8 DM |
643 | struct iommu *iommu; |
644 | struct strbuf *strbuf; | |
4dbc30fb | 645 | unsigned long flags, ctx, npages, i; |
2c941a20 | 646 | struct scatterlist *sg, *sgprv; |
4dbc30fb | 647 | u32 bus_addr; |
1da177e4 | 648 | |
ad7ad57c DM |
649 | iommu = dev->archdata.iommu; |
650 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
651 | |
652 | if (!strbuf->strbuf_enabled) | |
653 | return; | |
654 | ||
655 | spin_lock_irqsave(&iommu->lock, flags); | |
656 | ||
657 | /* Step 1: Record the context, if any. */ | |
658 | ctx = 0; | |
659 | if (iommu->iommu_ctxflush && | |
660 | strbuf->strbuf_ctxflush) { | |
661 | iopte_t *iopte; | |
662 | ||
663 | iopte = iommu->page_table + | |
664 | ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
665 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; | |
666 | } | |
667 | ||
668 | /* Step 2: Kick data out of streaming buffers. */ | |
4dbc30fb | 669 | bus_addr = sglist[0].dma_address & IO_PAGE_MASK; |
2c941a20 JA |
670 | sgprv = NULL; |
671 | for_each_sg(sglist, sg, nelems, i) { | |
672 | if (sg->dma_length == 0) | |
4dbc30fb | 673 | break; |
2c941a20 JA |
674 | sgprv = sg; |
675 | } | |
676 | ||
677 | npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) | |
4dbc30fb | 678 | - bus_addr) >> IO_PAGE_SHIFT; |
ad7ad57c | 679 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
680 | |
681 | spin_unlock_irqrestore(&iommu->lock, flags); | |
682 | } | |
683 | ||
ad7ad57c DM |
684 | const struct dma_ops sun4u_dma_ops = { |
685 | .alloc_coherent = dma_4u_alloc_coherent, | |
686 | .free_coherent = dma_4u_free_coherent, | |
687 | .map_single = dma_4u_map_single, | |
688 | .unmap_single = dma_4u_unmap_single, | |
689 | .map_sg = dma_4u_map_sg, | |
690 | .unmap_sg = dma_4u_unmap_sg, | |
691 | .sync_single_for_cpu = dma_4u_sync_single_for_cpu, | |
692 | .sync_sg_for_cpu = dma_4u_sync_sg_for_cpu, | |
8f6a93a1 DM |
693 | }; |
694 | ||
ad7ad57c DM |
695 | const struct dma_ops *dma_ops = &sun4u_dma_ops; |
696 | EXPORT_SYMBOL(dma_ops); | |
1da177e4 | 697 | |
ad7ad57c | 698 | int dma_supported(struct device *dev, u64 device_mask) |
1da177e4 | 699 | { |
ad7ad57c DM |
700 | struct iommu *iommu = dev->archdata.iommu; |
701 | u64 dma_addr_mask = iommu->dma_addr_mask; | |
1da177e4 | 702 | |
ad7ad57c DM |
703 | if (device_mask >= (1UL << 32UL)) |
704 | return 0; | |
1da177e4 | 705 | |
ad7ad57c DM |
706 | if ((device_mask & dma_addr_mask) == dma_addr_mask) |
707 | return 1; | |
1da177e4 | 708 | |
ad7ad57c DM |
709 | #ifdef CONFIG_PCI |
710 | if (dev->bus == &pci_bus_type) | |
711 | return pci_dma_supported(to_pci_dev(dev), device_mask); | |
712 | #endif | |
1da177e4 | 713 | |
ad7ad57c DM |
714 | return 0; |
715 | } | |
716 | EXPORT_SYMBOL(dma_supported); | |
1da177e4 | 717 | |
ad7ad57c DM |
718 | int dma_set_mask(struct device *dev, u64 dma_mask) |
719 | { | |
720 | #ifdef CONFIG_PCI | |
721 | if (dev->bus == &pci_bus_type) | |
722 | return pci_set_dma_mask(to_pci_dev(dev), dma_mask); | |
723 | #endif | |
724 | return -EINVAL; | |
1da177e4 | 725 | } |
ad7ad57c | 726 | EXPORT_SYMBOL(dma_set_mask); |