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1da177e4 LT |
1 | /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $ |
2 | * irq.c: UltraSparc IRQ handling/init/registry. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/ptrace.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/signal.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/random.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/proc_fs.h> | |
23 | #include <linux/seq_file.h> | |
24 | ||
25 | #include <asm/ptrace.h> | |
26 | #include <asm/processor.h> | |
27 | #include <asm/atomic.h> | |
28 | #include <asm/system.h> | |
29 | #include <asm/irq.h> | |
30 | #include <asm/sbus.h> | |
31 | #include <asm/iommu.h> | |
32 | #include <asm/upa.h> | |
33 | #include <asm/oplib.h> | |
34 | #include <asm/timer.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/starfire.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/cache.h> | |
39 | #include <asm/cpudata.h> | |
63b61452 | 40 | #include <asm/auxio.h> |
1da177e4 LT |
41 | |
42 | #ifdef CONFIG_SMP | |
43 | static void distribute_irqs(void); | |
44 | #endif | |
45 | ||
46 | /* UPA nodes send interrupt packet to UltraSparc with first data reg | |
47 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
48 | * delivered. We must translate this into a non-vector IRQ so we can | |
49 | * set the softint on this cpu. | |
50 | * | |
51 | * To make processing these packets efficient and race free we use | |
52 | * an array of irq buckets below. The interrupt vector handler in | |
53 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
54 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
55 | * code uses CAS to get an atomic snapshot of the list and clear it | |
56 | * at the same time. | |
57 | */ | |
58 | ||
59 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); | |
60 | ||
61 | /* This has to be in the main kernel image, it cannot be | |
62 | * turned into per-cpu data. The reason is that the main | |
63 | * kernel image is locked into the TLB and this structure | |
64 | * is accessed from the vectored interrupt trap handler. If | |
65 | * access to this structure takes a TLB miss it could cause | |
66 | * the 5-level sparc v9 trap stack to overflow. | |
67 | */ | |
68 | struct irq_work_struct { | |
69 | unsigned int irq_worklists[16]; | |
70 | }; | |
71 | struct irq_work_struct __irq_work[NR_CPUS]; | |
72 | #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)]) | |
73 | ||
088dd1f8 | 74 | static struct irqaction *irq_action[NR_IRQS+1]; |
1da177e4 LT |
75 | |
76 | /* This only synchronizes entities which modify IRQ handler | |
77 | * state and some selected user-level spots that want to | |
78 | * read things in the table. IRQ handler processing orders | |
79 | * its' accesses such that no locking is needed. | |
80 | */ | |
81 | static DEFINE_SPINLOCK(irq_action_lock); | |
82 | ||
83 | static void register_irq_proc (unsigned int irq); | |
84 | ||
85 | /* | |
86 | * Upper 2b of irqaction->flags holds the ino. | |
87 | * irqaction->mask holds the smp affinity information. | |
88 | */ | |
89 | #define put_ino_in_irqaction(action, irq) \ | |
90 | action->flags &= 0xffffffffffffUL; \ | |
91 | if (__bucket(irq) == &pil0_dummy_bucket) \ | |
92 | action->flags |= 0xdeadUL << 48; \ | |
93 | else \ | |
94 | action->flags |= __irq_ino(irq) << 48; | |
95 | #define get_ino_in_irqaction(action) (action->flags >> 48) | |
96 | ||
97 | #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff) | |
98 | #define get_smpaff_in_irqaction(action) ((action)->mask) | |
99 | ||
100 | int show_interrupts(struct seq_file *p, void *v) | |
101 | { | |
102 | unsigned long flags; | |
103 | int i = *(loff_t *) v; | |
104 | struct irqaction *action; | |
105 | #ifdef CONFIG_SMP | |
106 | int j; | |
107 | #endif | |
108 | ||
109 | spin_lock_irqsave(&irq_action_lock, flags); | |
110 | if (i <= NR_IRQS) { | |
111 | if (!(action = *(i + irq_action))) | |
112 | goto out_unlock; | |
113 | seq_printf(p, "%3d: ", i); | |
114 | #ifndef CONFIG_SMP | |
115 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
116 | #else | |
117 | for (j = 0; j < NR_CPUS; j++) { | |
118 | if (!cpu_online(j)) | |
119 | continue; | |
120 | seq_printf(p, "%10u ", | |
121 | kstat_cpu(j).irqs[i]); | |
122 | } | |
123 | #endif | |
124 | seq_printf(p, " %s:%lx", action->name, | |
125 | get_ino_in_irqaction(action)); | |
126 | for (action = action->next; action; action = action->next) { | |
127 | seq_printf(p, ", %s:%lx", action->name, | |
128 | get_ino_in_irqaction(action)); | |
129 | } | |
130 | seq_putc(p, '\n'); | |
131 | } | |
132 | out_unlock: | |
133 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | /* Now these are always passed a true fully specified sun4u INO. */ | |
139 | void enable_irq(unsigned int irq) | |
140 | { | |
141 | struct ino_bucket *bucket = __bucket(irq); | |
142 | unsigned long imap; | |
143 | unsigned long tid; | |
144 | ||
145 | imap = bucket->imap; | |
146 | if (imap == 0UL) | |
147 | return; | |
148 | ||
149 | preempt_disable(); | |
150 | ||
151 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
152 | unsigned long ver; | |
153 | ||
154 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
155 | if ((ver >> 32) == 0x003e0016) { | |
156 | /* We set it to our JBUS ID. */ | |
157 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
158 | : "=r" (tid) | |
159 | : "i" (ASI_JBUS_CONFIG)); | |
160 | tid = ((tid & (0x1fUL<<17)) << 9); | |
161 | tid &= IMAP_TID_JBUS; | |
162 | } else { | |
163 | /* We set it to our Safari AID. */ | |
164 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
165 | : "=r" (tid) | |
166 | : "i" (ASI_SAFARI_CONFIG)); | |
167 | tid = ((tid & (0x3ffUL<<17)) << 9); | |
168 | tid &= IMAP_AID_SAFARI; | |
169 | } | |
170 | } else if (this_is_starfire == 0) { | |
171 | /* We set it to our UPA MID. */ | |
172 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
173 | : "=r" (tid) | |
174 | : "i" (ASI_UPA_CONFIG)); | |
175 | tid = ((tid & UPA_CONFIG_MID) << 9); | |
176 | tid &= IMAP_TID_UPA; | |
177 | } else { | |
178 | tid = (starfire_translate(imap, smp_processor_id()) << 26); | |
179 | tid &= IMAP_TID_UPA; | |
180 | } | |
181 | ||
182 | /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product | |
183 | * of this SYSIO's preconfigured IGN in the SYSIO Control | |
184 | * Register, the hardware just mirrors that value here. | |
185 | * However for Graphics and UPA Slave devices the full | |
186 | * IMAP_INR field can be set by the programmer here. | |
187 | * | |
188 | * Things like FFB can now be handled via the new IRQ mechanism. | |
189 | */ | |
190 | upa_writel(tid | IMAP_VALID, imap); | |
191 | ||
192 | preempt_enable(); | |
193 | } | |
194 | ||
195 | /* This now gets passed true ino's as well. */ | |
196 | void disable_irq(unsigned int irq) | |
197 | { | |
198 | struct ino_bucket *bucket = __bucket(irq); | |
199 | unsigned long imap; | |
200 | ||
201 | imap = bucket->imap; | |
202 | if (imap != 0UL) { | |
203 | u32 tmp; | |
204 | ||
205 | /* NOTE: We do not want to futz with the IRQ clear registers | |
206 | * and move the state to IDLE, the SCSI code does call | |
207 | * disable_irq() to assure atomicity in the queue cmd | |
208 | * SCSI adapter driver code. Thus we'd lose interrupts. | |
209 | */ | |
210 | tmp = upa_readl(imap); | |
211 | tmp &= ~IMAP_VALID; | |
212 | upa_writel(tmp, imap); | |
213 | } | |
214 | } | |
215 | ||
216 | /* The timer is the one "weird" interrupt which is generated by | |
217 | * the CPU %tick register and not by some normal vectored interrupt | |
218 | * source. To handle this special case, we use this dummy INO bucket. | |
219 | */ | |
088dd1f8 | 220 | static struct irq_desc pil0_dummy_desc; |
1da177e4 | 221 | static struct ino_bucket pil0_dummy_bucket = { |
088dd1f8 | 222 | .irq_info = &pil0_dummy_desc, |
1da177e4 LT |
223 | }; |
224 | ||
088dd1f8 DM |
225 | static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup, |
226 | unsigned long iclr, unsigned long imap, | |
227 | struct ino_bucket *bucket) | |
228 | { | |
229 | prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> " | |
230 | "(%d:%d:%016lx:%016lx), halting...\n", | |
231 | ino, bucket->pil, bucket->iclr, bucket->imap, | |
232 | pil, inofixup, iclr, imap); | |
233 | prom_halt(); | |
234 | } | |
235 | ||
1da177e4 LT |
236 | unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap) |
237 | { | |
238 | struct ino_bucket *bucket; | |
239 | int ino; | |
240 | ||
241 | if (pil == 0) { | |
242 | if (iclr != 0UL || imap != 0UL) { | |
243 | prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n", | |
244 | iclr, imap); | |
245 | prom_halt(); | |
246 | } | |
247 | return __irq(&pil0_dummy_bucket); | |
248 | } | |
249 | ||
250 | /* RULE: Both must be specified in all other cases. */ | |
251 | if (iclr == 0UL || imap == 0UL) { | |
252 | prom_printf("Invalid build_irq %d %d %016lx %016lx\n", | |
253 | pil, inofixup, iclr, imap); | |
254 | prom_halt(); | |
255 | } | |
256 | ||
257 | ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; | |
258 | if (ino > NUM_IVECS) { | |
259 | prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n", | |
260 | ino, pil, inofixup, iclr, imap); | |
261 | prom_halt(); | |
262 | } | |
263 | ||
1da177e4 | 264 | bucket = &ivector_table[ino]; |
088dd1f8 DM |
265 | if (bucket->flags & IBF_ACTIVE) |
266 | build_irq_error("IRQ: Trying to build active INO bucket.\n", | |
267 | ino, pil, inofixup, iclr, imap, bucket); | |
268 | ||
269 | if (bucket->irq_info) { | |
270 | if (bucket->imap != imap || bucket->iclr != iclr) | |
271 | build_irq_error("IRQ: Trying to reinit INO bucket.\n", | |
272 | ino, pil, inofixup, iclr, imap, bucket); | |
273 | ||
274 | goto out; | |
275 | } | |
276 | ||
277 | bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC); | |
278 | if (!bucket->irq_info) { | |
279 | prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n"); | |
1da177e4 LT |
280 | prom_halt(); |
281 | } | |
088dd1f8 DM |
282 | memset(bucket->irq_info, 0, sizeof(struct irq_desc)); |
283 | ||
284 | /* Ok, looks good, set it up. Don't touch the irq_chain or | |
285 | * the pending flag. | |
286 | */ | |
1da177e4 LT |
287 | bucket->imap = imap; |
288 | bucket->iclr = iclr; | |
289 | bucket->pil = pil; | |
290 | bucket->flags = 0; | |
291 | ||
088dd1f8 | 292 | out: |
1da177e4 LT |
293 | return __irq(bucket); |
294 | } | |
295 | ||
296 | static void atomic_bucket_insert(struct ino_bucket *bucket) | |
297 | { | |
298 | unsigned long pstate; | |
299 | unsigned int *ent; | |
300 | ||
301 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
302 | __asm__ __volatile__("wrpr %0, %1, %%pstate" | |
303 | : : "r" (pstate), "i" (PSTATE_IE)); | |
304 | ent = irq_work(smp_processor_id(), bucket->pil); | |
305 | bucket->irq_chain = *ent; | |
306 | *ent = __irq(bucket); | |
307 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate)); | |
308 | } | |
309 | ||
088dd1f8 DM |
310 | static int check_irq_sharing(int pil, unsigned long irqflags) |
311 | { | |
312 | struct irqaction *action, *tmp; | |
313 | ||
314 | action = *(irq_action + pil); | |
315 | if (action) { | |
316 | if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) { | |
317 | for (tmp = action; tmp->next; tmp = tmp->next) | |
318 | ; | |
319 | } else { | |
320 | return -EBUSY; | |
321 | } | |
322 | } | |
323 | return 0; | |
324 | } | |
325 | ||
326 | static void append_irq_action(int pil, struct irqaction *action) | |
327 | { | |
328 | struct irqaction **pp = irq_action + pil; | |
329 | ||
330 | while (*pp) | |
331 | pp = &((*pp)->next); | |
332 | *pp = action; | |
333 | } | |
334 | ||
335 | static struct irqaction *get_action_slot(struct ino_bucket *bucket) | |
336 | { | |
337 | struct irq_desc *desc = bucket->irq_info; | |
338 | int max_irq, i; | |
339 | ||
340 | max_irq = 1; | |
341 | if (bucket->flags & IBF_PCI) | |
342 | max_irq = MAX_IRQ_DESC_ACTION; | |
343 | for (i = 0; i < max_irq; i++) { | |
344 | struct irqaction *p = &desc->action[i]; | |
345 | u32 mask = (1 << i); | |
346 | ||
347 | if (desc->action_active_mask & mask) | |
348 | continue; | |
349 | ||
350 | desc->action_active_mask |= mask; | |
351 | return p; | |
352 | } | |
353 | return NULL; | |
354 | } | |
355 | ||
1da177e4 LT |
356 | int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), |
357 | unsigned long irqflags, const char *name, void *dev_id) | |
358 | { | |
088dd1f8 | 359 | struct irqaction *action; |
1da177e4 LT |
360 | struct ino_bucket *bucket = __bucket(irq); |
361 | unsigned long flags; | |
362 | int pending = 0; | |
363 | ||
088dd1f8 | 364 | if (unlikely(!handler)) |
1da177e4 | 365 | return -EINVAL; |
088dd1f8 DM |
366 | |
367 | if (unlikely(!bucket->irq_info)) | |
368 | return -ENODEV; | |
1da177e4 LT |
369 | |
370 | if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) { | |
371 | /* | |
372 | * This function might sleep, we want to call it first, | |
373 | * outside of the atomic block. In SA_STATIC_ALLOC case, | |
374 | * random driver's kmalloc will fail, but it is safe. | |
375 | * If already initialized, random driver will not reinit. | |
376 | * Yes, this might clear the entropy pool if the wrong | |
377 | * driver is attempted to be loaded, without actually | |
378 | * installing a new handler, but is this really a problem, | |
379 | * only the sysadmin is able to do this. | |
380 | */ | |
381 | rand_initialize_irq(irq); | |
382 | } | |
383 | ||
384 | spin_lock_irqsave(&irq_action_lock, flags); | |
385 | ||
088dd1f8 DM |
386 | if (check_irq_sharing(bucket->pil, irqflags)) { |
387 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
388 | return -EBUSY; | |
1da177e4 LT |
389 | } |
390 | ||
088dd1f8 | 391 | action = get_action_slot(bucket); |
1da177e4 LT |
392 | if (!action) { |
393 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
394 | return -ENOMEM; | |
395 | } | |
396 | ||
088dd1f8 DM |
397 | bucket->flags |= IBF_ACTIVE; |
398 | pending = 0; | |
399 | if (bucket != &pil0_dummy_bucket) { | |
1da177e4 LT |
400 | pending = bucket->pending; |
401 | if (pending) | |
402 | bucket->pending = 0; | |
403 | } | |
404 | ||
405 | action->handler = handler; | |
406 | action->flags = irqflags; | |
407 | action->name = name; | |
408 | action->next = NULL; | |
409 | action->dev_id = dev_id; | |
410 | put_ino_in_irqaction(action, irq); | |
411 | put_smpaff_in_irqaction(action, CPU_MASK_NONE); | |
412 | ||
088dd1f8 | 413 | append_irq_action(bucket->pil, action); |
1da177e4 LT |
414 | |
415 | enable_irq(irq); | |
416 | ||
417 | /* We ate the IVEC already, this makes sure it does not get lost. */ | |
418 | if (pending) { | |
419 | atomic_bucket_insert(bucket); | |
420 | set_softint(1 << bucket->pil); | |
421 | } | |
088dd1f8 | 422 | |
1da177e4 | 423 | spin_unlock_irqrestore(&irq_action_lock, flags); |
088dd1f8 DM |
424 | |
425 | if (bucket != &pil0_dummy_bucket) | |
1da177e4 LT |
426 | register_irq_proc(__irq_ino(irq)); |
427 | ||
428 | #ifdef CONFIG_SMP | |
429 | distribute_irqs(); | |
430 | #endif | |
431 | return 0; | |
1da177e4 LT |
432 | } |
433 | ||
434 | EXPORT_SYMBOL(request_irq); | |
435 | ||
088dd1f8 | 436 | static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id) |
1da177e4 | 437 | { |
088dd1f8 DM |
438 | struct ino_bucket *bucket = __bucket(irq); |
439 | struct irqaction *action, **pp; | |
1da177e4 | 440 | |
088dd1f8 DM |
441 | pp = irq_action + bucket->pil; |
442 | action = *pp; | |
443 | if (unlikely(!action)) | |
444 | return NULL; | |
1da177e4 | 445 | |
088dd1f8 | 446 | if (unlikely(!action->handler)) { |
1da177e4 | 447 | printk("Freeing free IRQ %d\n", bucket->pil); |
088dd1f8 | 448 | return NULL; |
1da177e4 LT |
449 | } |
450 | ||
088dd1f8 DM |
451 | while (action && action->dev_id != dev_id) { |
452 | pp = &action->next; | |
453 | action = *pp; | |
1da177e4 LT |
454 | } |
455 | ||
088dd1f8 DM |
456 | if (likely(action)) |
457 | *pp = action->next; | |
458 | ||
459 | return action; | |
460 | } | |
461 | ||
462 | void free_irq(unsigned int irq, void *dev_id) | |
463 | { | |
464 | struct irqaction *action; | |
465 | struct ino_bucket *bucket; | |
466 | unsigned long flags; | |
467 | ||
468 | spin_lock_irqsave(&irq_action_lock, flags); | |
469 | ||
470 | action = unlink_irq_action(irq, dev_id); | |
1da177e4 LT |
471 | |
472 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
473 | ||
088dd1f8 DM |
474 | if (unlikely(!action)) |
475 | return; | |
476 | ||
1da177e4 LT |
477 | synchronize_irq(irq); |
478 | ||
479 | spin_lock_irqsave(&irq_action_lock, flags); | |
480 | ||
088dd1f8 | 481 | bucket = __bucket(irq); |
1da177e4 | 482 | if (bucket != &pil0_dummy_bucket) { |
088dd1f8 | 483 | struct irq_desc *desc = bucket->irq_info; |
1da177e4 | 484 | unsigned long imap = bucket->imap; |
088dd1f8 | 485 | int ent, i; |
1da177e4 | 486 | |
088dd1f8 DM |
487 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { |
488 | struct irqaction *p = &desc->action[i]; | |
489 | ||
490 | if (p == action) { | |
491 | desc->action_active_mask &= ~(1 << i); | |
492 | break; | |
1da177e4 | 493 | } |
1da177e4 LT |
494 | } |
495 | ||
088dd1f8 DM |
496 | if (!desc->action_active_mask) { |
497 | /* This unique interrupt source is now inactive. */ | |
498 | bucket->flags &= ~IBF_ACTIVE; | |
1da177e4 | 499 | |
088dd1f8 DM |
500 | /* See if any other buckets share this bucket's IMAP |
501 | * and are still active. | |
502 | */ | |
503 | for (ent = 0; ent < NUM_IVECS; ent++) { | |
504 | struct ino_bucket *bp = &ivector_table[ent]; | |
505 | if (bp != bucket && | |
506 | bp->imap == imap && | |
507 | (bp->flags & IBF_ACTIVE) != 0) | |
508 | break; | |
509 | } | |
1da177e4 | 510 | |
088dd1f8 DM |
511 | /* Only disable when no other sub-irq levels of |
512 | * the same IMAP are active. | |
513 | */ | |
514 | if (ent == NUM_IVECS) | |
515 | disable_irq(irq); | |
516 | } | |
1da177e4 LT |
517 | } |
518 | ||
1da177e4 LT |
519 | spin_unlock_irqrestore(&irq_action_lock, flags); |
520 | } | |
521 | ||
522 | EXPORT_SYMBOL(free_irq); | |
523 | ||
524 | #ifdef CONFIG_SMP | |
525 | void synchronize_irq(unsigned int irq) | |
526 | { | |
527 | struct ino_bucket *bucket = __bucket(irq); | |
528 | ||
529 | #if 0 | |
530 | /* The following is how I wish I could implement this. | |
531 | * Unfortunately the ICLR registers are read-only, you can | |
532 | * only write ICLR_foo values to them. To get the current | |
533 | * IRQ status you would need to get at the IRQ diag registers | |
534 | * in the PCI/SBUS controller and the layout of those vary | |
535 | * from one controller to the next, sigh... -DaveM | |
536 | */ | |
537 | unsigned long iclr = bucket->iclr; | |
538 | ||
539 | while (1) { | |
540 | u32 tmp = upa_readl(iclr); | |
541 | ||
542 | if (tmp == ICLR_TRANSMIT || | |
543 | tmp == ICLR_PENDING) { | |
544 | cpu_relax(); | |
545 | continue; | |
546 | } | |
547 | break; | |
548 | } | |
549 | #else | |
550 | /* So we have to do this with a INPROGRESS bit just like x86. */ | |
551 | while (bucket->flags & IBF_INPROGRESS) | |
552 | cpu_relax(); | |
553 | #endif | |
554 | } | |
555 | #endif /* CONFIG_SMP */ | |
556 | ||
088dd1f8 | 557 | static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs) |
1da177e4 | 558 | { |
088dd1f8 DM |
559 | struct irq_desc *desc = bp->irq_info; |
560 | unsigned char flags = bp->flags; | |
561 | u32 action_mask, i; | |
562 | int random; | |
1da177e4 | 563 | |
088dd1f8 | 564 | bp->flags |= IBF_INPROGRESS; |
1da177e4 | 565 | |
088dd1f8 DM |
566 | if (unlikely(!(flags & IBF_ACTIVE))) { |
567 | bp->pending = 1; | |
1da177e4 | 568 | goto out; |
1da177e4 LT |
569 | } |
570 | ||
088dd1f8 DM |
571 | if (desc->pre_handler) |
572 | desc->pre_handler(bp, | |
573 | desc->pre_handler_arg1, | |
574 | desc->pre_handler_arg2); | |
1da177e4 | 575 | |
088dd1f8 DM |
576 | action_mask = desc->action_active_mask; |
577 | random = 0; | |
578 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { | |
579 | struct irqaction *p = &desc->action[i]; | |
580 | u32 mask = (1 << i); | |
1da177e4 | 581 | |
088dd1f8 DM |
582 | if (!(action_mask & mask)) |
583 | continue; | |
1da177e4 | 584 | |
088dd1f8 | 585 | action_mask &= ~mask; |
1da177e4 | 586 | |
088dd1f8 DM |
587 | if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED) |
588 | random |= p->flags; | |
589 | ||
590 | if (!action_mask) | |
591 | break; | |
592 | } | |
593 | if (bp->pil != 0) { | |
594 | upa_writel(ICLR_IDLE, bp->iclr); | |
595 | /* Test and add entropy */ | |
596 | if (random & SA_SAMPLE_RANDOM) | |
597 | add_interrupt_randomness(irq); | |
598 | } | |
1da177e4 | 599 | out: |
088dd1f8 | 600 | bp->flags &= ~IBF_INPROGRESS; |
1da177e4 LT |
601 | } |
602 | ||
1da177e4 LT |
603 | void handler_irq(int irq, struct pt_regs *regs) |
604 | { | |
088dd1f8 | 605 | struct ino_bucket *bp; |
1da177e4 LT |
606 | int cpu = smp_processor_id(); |
607 | ||
608 | #ifndef CONFIG_SMP | |
609 | /* | |
610 | * Check for TICK_INT on level 14 softint. | |
611 | */ | |
612 | { | |
613 | unsigned long clr_mask = 1 << irq; | |
614 | unsigned long tick_mask = tick_ops->softint_mask; | |
615 | ||
616 | if ((irq == 14) && (get_softint() & tick_mask)) { | |
617 | irq = 0; | |
618 | clr_mask = tick_mask; | |
619 | } | |
620 | clear_softint(clr_mask); | |
621 | } | |
622 | #else | |
1da177e4 LT |
623 | clear_softint(1 << irq); |
624 | #endif | |
625 | ||
626 | irq_enter(); | |
627 | kstat_this_cpu.irqs[irq]++; | |
628 | ||
629 | /* Sliiiick... */ | |
630 | #ifndef CONFIG_SMP | |
631 | bp = ((irq != 0) ? | |
632 | __bucket(xchg32(irq_work(cpu, irq), 0)) : | |
633 | &pil0_dummy_bucket); | |
634 | #else | |
635 | bp = __bucket(xchg32(irq_work(cpu, irq), 0)); | |
636 | #endif | |
088dd1f8 DM |
637 | while (bp) { |
638 | struct ino_bucket *nbp = __bucket(bp->irq_chain); | |
1da177e4 | 639 | |
1da177e4 | 640 | bp->irq_chain = 0; |
088dd1f8 DM |
641 | process_bucket(irq, bp, regs); |
642 | bp = nbp; | |
1da177e4 LT |
643 | } |
644 | irq_exit(); | |
645 | } | |
646 | ||
647 | #ifdef CONFIG_BLK_DEV_FD | |
63b61452 | 648 | extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);; |
1da177e4 | 649 | |
63b61452 DM |
650 | /* XXX No easy way to include asm/floppy.h XXX */ |
651 | extern unsigned char *pdma_vaddr; | |
652 | extern unsigned long pdma_size; | |
653 | extern volatile int doing_pdma; | |
654 | extern unsigned long fdc_status; | |
1da177e4 | 655 | |
63b61452 | 656 | irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs) |
1da177e4 | 657 | { |
63b61452 DM |
658 | if (likely(doing_pdma)) { |
659 | void __iomem *stat = (void __iomem *) fdc_status; | |
660 | unsigned char *vaddr = pdma_vaddr; | |
661 | unsigned long size = pdma_size; | |
662 | u8 val; | |
663 | ||
664 | while (size) { | |
665 | val = readb(stat); | |
666 | if (unlikely(!(val & 0x80))) { | |
667 | pdma_vaddr = vaddr; | |
668 | pdma_size = size; | |
669 | return IRQ_HANDLED; | |
670 | } | |
671 | if (unlikely(!(val & 0x20))) { | |
672 | pdma_vaddr = vaddr; | |
673 | pdma_size = size; | |
674 | doing_pdma = 0; | |
675 | goto main_interrupt; | |
676 | } | |
677 | if (val & 0x40) { | |
678 | /* read */ | |
679 | *vaddr++ = readb(stat + 1); | |
680 | } else { | |
681 | unsigned char data = *vaddr++; | |
1da177e4 | 682 | |
63b61452 DM |
683 | /* write */ |
684 | writeb(data, stat + 1); | |
685 | } | |
686 | size--; | |
687 | } | |
1da177e4 | 688 | |
63b61452 DM |
689 | pdma_vaddr = vaddr; |
690 | pdma_size = size; | |
1da177e4 | 691 | |
63b61452 DM |
692 | /* Send Terminal Count pulse to floppy controller. */ |
693 | val = readb(auxio_register); | |
694 | val |= AUXIO_AUX1_FTCNT; | |
695 | writeb(val, auxio_register); | |
696 | val &= AUXIO_AUX1_FTCNT; | |
697 | writeb(val, auxio_register); | |
1da177e4 | 698 | |
63b61452 | 699 | doing_pdma = 0; |
1da177e4 | 700 | } |
1da177e4 | 701 | |
63b61452 DM |
702 | main_interrupt: |
703 | return floppy_interrupt(irq, dev_cookie, regs); | |
1da177e4 | 704 | } |
63b61452 DM |
705 | EXPORT_SYMBOL(sparc_floppy_irq); |
706 | #endif | |
1da177e4 LT |
707 | |
708 | /* We really don't need these at all on the Sparc. We only have | |
709 | * stubs here because they are exported to modules. | |
710 | */ | |
711 | unsigned long probe_irq_on(void) | |
712 | { | |
713 | return 0; | |
714 | } | |
715 | ||
716 | EXPORT_SYMBOL(probe_irq_on); | |
717 | ||
718 | int probe_irq_off(unsigned long mask) | |
719 | { | |
720 | return 0; | |
721 | } | |
722 | ||
723 | EXPORT_SYMBOL(probe_irq_off); | |
724 | ||
725 | #ifdef CONFIG_SMP | |
726 | static int retarget_one_irq(struct irqaction *p, int goal_cpu) | |
727 | { | |
728 | struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table; | |
729 | unsigned long imap = bucket->imap; | |
730 | unsigned int tid; | |
731 | ||
732 | while (!cpu_online(goal_cpu)) { | |
733 | if (++goal_cpu >= NR_CPUS) | |
734 | goal_cpu = 0; | |
735 | } | |
736 | ||
737 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
738 | tid = goal_cpu << 26; | |
739 | tid &= IMAP_AID_SAFARI; | |
740 | } else if (this_is_starfire == 0) { | |
741 | tid = goal_cpu << 26; | |
742 | tid &= IMAP_TID_UPA; | |
743 | } else { | |
744 | tid = (starfire_translate(imap, goal_cpu) << 26); | |
745 | tid &= IMAP_TID_UPA; | |
746 | } | |
747 | upa_writel(tid | IMAP_VALID, imap); | |
748 | ||
cee2824f | 749 | do { |
1da177e4 LT |
750 | if (++goal_cpu >= NR_CPUS) |
751 | goal_cpu = 0; | |
cee2824f | 752 | } while (!cpu_online(goal_cpu)); |
1da177e4 LT |
753 | |
754 | return goal_cpu; | |
755 | } | |
756 | ||
757 | /* Called from request_irq. */ | |
758 | static void distribute_irqs(void) | |
759 | { | |
760 | unsigned long flags; | |
761 | int cpu, level; | |
762 | ||
763 | spin_lock_irqsave(&irq_action_lock, flags); | |
764 | cpu = 0; | |
765 | ||
766 | /* | |
767 | * Skip the timer at [0], and very rare error/power intrs at [15]. | |
768 | * Also level [12], it causes problems on Ex000 systems. | |
769 | */ | |
770 | for (level = 1; level < NR_IRQS; level++) { | |
771 | struct irqaction *p = irq_action[level]; | |
088dd1f8 DM |
772 | |
773 | if (level == 12) | |
774 | continue; | |
775 | ||
1da177e4 LT |
776 | while(p) { |
777 | cpu = retarget_one_irq(p, cpu); | |
778 | p = p->next; | |
779 | } | |
780 | } | |
781 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
782 | } | |
783 | #endif | |
784 | ||
785 | ||
786 | struct sun5_timer *prom_timers; | |
787 | static u64 prom_limit0, prom_limit1; | |
788 | ||
789 | static void map_prom_timers(void) | |
790 | { | |
791 | unsigned int addr[3]; | |
792 | int tnode, err; | |
793 | ||
794 | /* PROM timer node hangs out in the top level of device siblings... */ | |
795 | tnode = prom_finddevice("/counter-timer"); | |
796 | ||
797 | /* Assume if node is not present, PROM uses different tick mechanism | |
798 | * which we should not care about. | |
799 | */ | |
800 | if (tnode == 0 || tnode == -1) { | |
801 | prom_timers = (struct sun5_timer *) 0; | |
802 | return; | |
803 | } | |
804 | ||
805 | /* If PROM is really using this, it must be mapped by him. */ | |
806 | err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr)); | |
807 | if (err == -1) { | |
808 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); | |
809 | prom_timers = (struct sun5_timer *) 0; | |
810 | return; | |
811 | } | |
812 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
813 | } | |
814 | ||
815 | static void kill_prom_timer(void) | |
816 | { | |
817 | if (!prom_timers) | |
818 | return; | |
819 | ||
820 | /* Save them away for later. */ | |
821 | prom_limit0 = prom_timers->limit0; | |
822 | prom_limit1 = prom_timers->limit1; | |
823 | ||
824 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
825 | * We turn both off here just to be paranoid. | |
826 | */ | |
827 | prom_timers->limit0 = 0; | |
828 | prom_timers->limit1 = 0; | |
829 | ||
830 | /* Wheee, eat the interrupt packet too... */ | |
831 | __asm__ __volatile__( | |
832 | " mov 0x40, %%g2\n" | |
833 | " ldxa [%%g0] %0, %%g1\n" | |
834 | " ldxa [%%g2] %1, %%g1\n" | |
835 | " stxa %%g0, [%%g0] %0\n" | |
836 | " membar #Sync\n" | |
837 | : /* no outputs */ | |
838 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
839 | : "g1", "g2"); | |
840 | } | |
841 | ||
842 | void enable_prom_timer(void) | |
843 | { | |
844 | if (!prom_timers) | |
845 | return; | |
846 | ||
847 | /* Set it to whatever was there before. */ | |
848 | prom_timers->limit1 = prom_limit1; | |
849 | prom_timers->count1 = 0; | |
850 | prom_timers->limit0 = prom_limit0; | |
851 | prom_timers->count0 = 0; | |
852 | } | |
853 | ||
854 | void init_irqwork_curcpu(void) | |
855 | { | |
856 | register struct irq_work_struct *workp asm("o2"); | |
857 | register unsigned long tmp asm("o3"); | |
858 | int cpu = hard_smp_processor_id(); | |
859 | ||
860 | memset(__irq_work + cpu, 0, sizeof(*workp)); | |
861 | ||
862 | /* Make sure we are called with PSTATE_IE disabled. */ | |
863 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
864 | : "=r" (tmp)); | |
865 | if (tmp & PSTATE_IE) { | |
866 | prom_printf("BUG: init_irqwork_curcpu() called with " | |
867 | "PSTATE_IE enabled, bailing.\n"); | |
868 | __asm__ __volatile__("mov %%i7, %0\n\t" | |
869 | : "=r" (tmp)); | |
870 | prom_printf("BUG: Called from %lx\n", tmp); | |
871 | prom_halt(); | |
872 | } | |
873 | ||
874 | /* Set interrupt globals. */ | |
875 | workp = &__irq_work[cpu]; | |
876 | __asm__ __volatile__( | |
877 | "rdpr %%pstate, %0\n\t" | |
878 | "wrpr %0, %1, %%pstate\n\t" | |
879 | "mov %2, %%g6\n\t" | |
880 | "wrpr %0, 0x0, %%pstate\n\t" | |
881 | : "=&r" (tmp) | |
882 | : "i" (PSTATE_IG), "r" (workp)); | |
883 | } | |
884 | ||
885 | /* Only invoked on boot processor. */ | |
886 | void __init init_IRQ(void) | |
887 | { | |
888 | map_prom_timers(); | |
889 | kill_prom_timer(); | |
890 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
891 | ||
892 | /* We need to clear any IRQ's pending in the soft interrupt | |
893 | * registers, a spurious one could be left around from the | |
894 | * PROM timer which we just disabled. | |
895 | */ | |
896 | clear_softint(get_softint()); | |
897 | ||
898 | /* Now that ivector table is initialized, it is safe | |
899 | * to receive IRQ vector traps. We will normally take | |
900 | * one or two right now, in case some device PROM used | |
901 | * to boot us wants to speak to us. We just ignore them. | |
902 | */ | |
903 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
904 | "or %%g1, %0, %%g1\n\t" | |
905 | "wrpr %%g1, 0x0, %%pstate" | |
906 | : /* No outputs */ | |
907 | : "i" (PSTATE_IE) | |
908 | : "g1"); | |
909 | } | |
910 | ||
911 | static struct proc_dir_entry * root_irq_dir; | |
912 | static struct proc_dir_entry * irq_dir [NUM_IVECS]; | |
913 | ||
914 | #ifdef CONFIG_SMP | |
915 | ||
916 | static int irq_affinity_read_proc (char *page, char **start, off_t off, | |
917 | int count, int *eof, void *data) | |
918 | { | |
919 | struct ino_bucket *bp = ivector_table + (long)data; | |
920 | struct irqaction *ap = bp->irq_info; | |
921 | cpumask_t mask; | |
922 | int len; | |
923 | ||
924 | mask = get_smpaff_in_irqaction(ap); | |
925 | if (cpus_empty(mask)) | |
926 | mask = cpu_online_map; | |
927 | ||
928 | len = cpumask_scnprintf(page, count, mask); | |
929 | if (count - len < 2) | |
930 | return -EINVAL; | |
931 | len += sprintf(page + len, "\n"); | |
932 | return len; | |
933 | } | |
934 | ||
935 | static inline void set_intr_affinity(int irq, cpumask_t hw_aff) | |
936 | { | |
937 | struct ino_bucket *bp = ivector_table + irq; | |
938 | ||
939 | /* Users specify affinity in terms of hw cpu ids. | |
940 | * As soon as we do this, handler_irq() might see and take action. | |
941 | */ | |
942 | put_smpaff_in_irqaction((struct irqaction *)bp->irq_info, hw_aff); | |
943 | ||
944 | /* Migration is simply done by the next cpu to service this | |
945 | * interrupt. | |
946 | */ | |
947 | } | |
948 | ||
949 | static int irq_affinity_write_proc (struct file *file, const char __user *buffer, | |
950 | unsigned long count, void *data) | |
951 | { | |
952 | int irq = (long) data, full_count = count, err; | |
953 | cpumask_t new_value; | |
954 | ||
955 | err = cpumask_parse(buffer, count, new_value); | |
956 | ||
957 | /* | |
958 | * Do not allow disabling IRQs completely - it's a too easy | |
959 | * way to make the system unusable accidentally :-) At least | |
960 | * one online CPU still has to be targeted. | |
961 | */ | |
962 | cpus_and(new_value, new_value, cpu_online_map); | |
963 | if (cpus_empty(new_value)) | |
964 | return -EINVAL; | |
965 | ||
966 | set_intr_affinity(irq, new_value); | |
967 | ||
968 | return full_count; | |
969 | } | |
970 | ||
971 | #endif | |
972 | ||
973 | #define MAX_NAMELEN 10 | |
974 | ||
975 | static void register_irq_proc (unsigned int irq) | |
976 | { | |
977 | char name [MAX_NAMELEN]; | |
978 | ||
979 | if (!root_irq_dir || irq_dir[irq]) | |
980 | return; | |
981 | ||
982 | memset(name, 0, MAX_NAMELEN); | |
983 | sprintf(name, "%x", irq); | |
984 | ||
985 | /* create /proc/irq/1234 */ | |
986 | irq_dir[irq] = proc_mkdir(name, root_irq_dir); | |
987 | ||
988 | #ifdef CONFIG_SMP | |
989 | /* XXX SMP affinity not supported on starfire yet. */ | |
990 | if (this_is_starfire == 0) { | |
991 | struct proc_dir_entry *entry; | |
992 | ||
993 | /* create /proc/irq/1234/smp_affinity */ | |
994 | entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); | |
995 | ||
996 | if (entry) { | |
997 | entry->nlink = 1; | |
998 | entry->data = (void *)(long)irq; | |
999 | entry->read_proc = irq_affinity_read_proc; | |
1000 | entry->write_proc = irq_affinity_write_proc; | |
1001 | } | |
1002 | } | |
1003 | #endif | |
1004 | } | |
1005 | ||
1006 | void init_irq_proc (void) | |
1007 | { | |
1008 | /* create /proc/irq */ | |
1009 | root_irq_dir = proc_mkdir("irq", NULL); | |
1010 | } | |
1011 |