Commit | Line | Data |
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4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
4a907dec | 3 | * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/sched.h> | |
10 | #include <linux/ptrace.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/signal.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/random.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/proc_fs.h> | |
21 | #include <linux/seq_file.h> | |
b5a37e96 | 22 | #include <linux/bootmem.h> |
e18e2a00 | 23 | #include <linux/irq.h> |
35a17eb6 | 24 | #include <linux/msi.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/irq.h> | |
2e457ef6 | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include <asm/sbus.h> |
33 | #include <asm/iommu.h> | |
34 | #include <asm/upa.h> | |
35 | #include <asm/oplib.h> | |
25c7581b | 36 | #include <asm/prom.h> |
1da177e4 LT |
37 | #include <asm/timer.h> |
38 | #include <asm/smp.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/cache.h> | |
42 | #include <asm/cpudata.h> | |
63b61452 | 43 | #include <asm/auxio.h> |
92704a1c | 44 | #include <asm/head.h> |
4a907dec | 45 | #include <asm/hypervisor.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /* UPA nodes send interrupt packet to UltraSparc with first data reg |
48 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
49 | * delivered. We must translate this into a non-vector IRQ so we can | |
50 | * set the softint on this cpu. | |
51 | * | |
52 | * To make processing these packets efficient and race free we use | |
53 | * an array of irq buckets below. The interrupt vector handler in | |
54 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
55 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
56 | * code uses CAS to get an atomic snapshot of the list and clear it | |
57 | * at the same time. | |
e18e2a00 DM |
58 | * |
59 | * If you make changes to ino_bucket, please update hand coded assembler | |
60 | * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S | |
1da177e4 | 61 | */ |
e18e2a00 DM |
62 | struct ino_bucket { |
63 | /* Next handler in per-CPU IRQ worklist. We know that | |
64 | * bucket pointers have the high 32-bits clear, so to | |
65 | * save space we only store the bits we need. | |
66 | */ | |
67 | /*0x00*/unsigned int irq_chain; | |
1da177e4 | 68 | |
e18e2a00 DM |
69 | /* Virtual interrupt number assigned to this INO. */ |
70 | /*0x04*/unsigned int virt_irq; | |
71 | }; | |
72 | ||
73 | #define NUM_IVECS (IMAP_INR + 1) | |
1da177e4 LT |
74 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); |
75 | ||
e18e2a00 DM |
76 | #define __irq_ino(irq) \ |
77 | (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0]) | |
78 | #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq)) | |
79 | #define __irq(bucket) ((unsigned int)(unsigned long)(bucket)) | |
80 | ||
1da177e4 LT |
81 | /* This has to be in the main kernel image, it cannot be |
82 | * turned into per-cpu data. The reason is that the main | |
83 | * kernel image is locked into the TLB and this structure | |
84 | * is accessed from the vectored interrupt trap handler. If | |
85 | * access to this structure takes a TLB miss it could cause | |
86 | * the 5-level sparc v9 trap stack to overflow. | |
87 | */ | |
fd0504c3 | 88 | #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist) |
1da177e4 | 89 | |
93b3238e DM |
90 | static struct { |
91 | unsigned int irq; | |
92 | unsigned int dev_handle; | |
93 | unsigned int dev_ino; | |
94 | } virt_to_real_irq_table[NR_IRQS]; | |
8047e247 DM |
95 | |
96 | static unsigned char virt_irq_alloc(unsigned int real_irq) | |
97 | { | |
98 | unsigned char ent; | |
99 | ||
100 | BUILD_BUG_ON(NR_IRQS >= 256); | |
101 | ||
35a17eb6 | 102 | for (ent = 1; ent < NR_IRQS; ent++) { |
93b3238e | 103 | if (!virt_to_real_irq_table[ent].irq) |
35a17eb6 DM |
104 | break; |
105 | } | |
8047e247 DM |
106 | if (ent >= NR_IRQS) { |
107 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
108 | return 0; | |
109 | } | |
110 | ||
93b3238e | 111 | virt_to_real_irq_table[ent].irq = real_irq; |
8047e247 DM |
112 | |
113 | return ent; | |
114 | } | |
115 | ||
5746c99d | 116 | #ifdef CONFIG_PCI_MSI |
35a17eb6 | 117 | static void virt_irq_free(unsigned int virt_irq) |
8047e247 | 118 | { |
35a17eb6 | 119 | unsigned int real_irq; |
8047e247 | 120 | |
35a17eb6 DM |
121 | if (virt_irq >= NR_IRQS) |
122 | return; | |
123 | ||
93b3238e DM |
124 | real_irq = virt_to_real_irq_table[virt_irq].irq; |
125 | virt_to_real_irq_table[virt_irq].irq = 0; | |
35a17eb6 DM |
126 | |
127 | __bucket(real_irq)->virt_irq = 0; | |
8047e247 | 128 | } |
5746c99d | 129 | #endif |
8047e247 DM |
130 | |
131 | static unsigned int virt_to_real_irq(unsigned char virt_irq) | |
132 | { | |
93b3238e | 133 | return virt_to_real_irq_table[virt_irq].irq; |
8047e247 DM |
134 | } |
135 | ||
1da177e4 | 136 | /* |
e18e2a00 | 137 | * /proc/interrupts printing: |
1da177e4 | 138 | */ |
1da177e4 LT |
139 | |
140 | int show_interrupts(struct seq_file *p, void *v) | |
141 | { | |
e18e2a00 DM |
142 | int i = *(loff_t *) v, j; |
143 | struct irqaction * action; | |
1da177e4 | 144 | unsigned long flags; |
1da177e4 | 145 | |
e18e2a00 DM |
146 | if (i == 0) { |
147 | seq_printf(p, " "); | |
148 | for_each_online_cpu(j) | |
149 | seq_printf(p, "CPU%d ",j); | |
150 | seq_putc(p, '\n'); | |
151 | } | |
152 | ||
153 | if (i < NR_IRQS) { | |
154 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
155 | action = irq_desc[i].action; | |
156 | if (!action) | |
157 | goto skip; | |
158 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
159 | #ifndef CONFIG_SMP |
160 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
161 | #else | |
e18e2a00 DM |
162 | for_each_online_cpu(j) |
163 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 164 | #endif |
d1bef4ed | 165 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
166 | seq_printf(p, " %s", action->name); |
167 | ||
168 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 169 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 170 | |
1da177e4 | 171 | seq_putc(p, '\n'); |
e18e2a00 DM |
172 | skip: |
173 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 174 | } |
1da177e4 LT |
175 | return 0; |
176 | } | |
177 | ||
ebd8c56c DM |
178 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
179 | { | |
180 | unsigned int tid; | |
181 | ||
182 | if (this_is_starfire) { | |
183 | tid = starfire_translate(imap, cpuid); | |
184 | tid <<= IMAP_TID_SHIFT; | |
185 | tid &= IMAP_TID_UPA; | |
186 | } else { | |
187 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
188 | unsigned long ver; | |
189 | ||
190 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
191 | if ((ver >> 32UL) == __JALAPENO_ID || | |
192 | (ver >> 32UL) == __SERRANO_ID) { | |
193 | tid = cpuid << IMAP_TID_SHIFT; | |
194 | tid &= IMAP_TID_JBUS; | |
195 | } else { | |
196 | unsigned int a = cpuid & 0x1f; | |
197 | unsigned int n = (cpuid >> 5) & 0x1f; | |
198 | ||
199 | tid = ((a << IMAP_AID_SHIFT) | | |
200 | (n << IMAP_NID_SHIFT)); | |
201 | tid &= (IMAP_AID_SAFARI | | |
202 | IMAP_NID_SAFARI);; | |
203 | } | |
204 | } else { | |
205 | tid = cpuid << IMAP_TID_SHIFT; | |
206 | tid &= IMAP_TID_UPA; | |
207 | } | |
208 | } | |
209 | ||
210 | return tid; | |
211 | } | |
212 | ||
e18e2a00 DM |
213 | struct irq_handler_data { |
214 | unsigned long iclr; | |
215 | unsigned long imap; | |
8047e247 | 216 | |
e18e2a00 DM |
217 | void (*pre_handler)(unsigned int, void *, void *); |
218 | void *pre_handler_arg1; | |
219 | void *pre_handler_arg2; | |
220 | }; | |
1da177e4 | 221 | |
e18e2a00 | 222 | static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq) |
1da177e4 | 223 | { |
8047e247 | 224 | unsigned int real_irq = virt_to_real_irq(virt_irq); |
e18e2a00 | 225 | struct ino_bucket *bucket = NULL; |
1da177e4 | 226 | |
e18e2a00 DM |
227 | if (likely(real_irq)) |
228 | bucket = __bucket(real_irq); | |
8047e247 | 229 | |
e18e2a00 | 230 | return bucket; |
1da177e4 LT |
231 | } |
232 | ||
e18e2a00 DM |
233 | #ifdef CONFIG_SMP |
234 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 235 | { |
a53da52f | 236 | cpumask_t mask = irq_desc[virt_irq].affinity; |
e18e2a00 | 237 | int cpuid; |
088dd1f8 | 238 | |
e18e2a00 DM |
239 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
240 | static int irq_rover; | |
241 | static DEFINE_SPINLOCK(irq_rover_lock); | |
242 | unsigned long flags; | |
1da177e4 | 243 | |
e18e2a00 DM |
244 | /* Round-robin distribution... */ |
245 | do_round_robin: | |
246 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 247 | |
e18e2a00 DM |
248 | while (!cpu_online(irq_rover)) { |
249 | if (++irq_rover >= NR_CPUS) | |
250 | irq_rover = 0; | |
251 | } | |
252 | cpuid = irq_rover; | |
253 | do { | |
254 | if (++irq_rover >= NR_CPUS) | |
255 | irq_rover = 0; | |
256 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 257 | |
e18e2a00 DM |
258 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
259 | } else { | |
260 | cpumask_t tmp; | |
088dd1f8 | 261 | |
e18e2a00 | 262 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 263 | |
e18e2a00 DM |
264 | if (cpus_empty(tmp)) |
265 | goto do_round_robin; | |
088dd1f8 | 266 | |
e18e2a00 | 267 | cpuid = first_cpu(tmp); |
1da177e4 | 268 | } |
088dd1f8 | 269 | |
e18e2a00 DM |
270 | return cpuid; |
271 | } | |
272 | #else | |
273 | static int irq_choose_cpu(unsigned int virt_irq) | |
274 | { | |
275 | return real_hard_smp_processor_id(); | |
1da177e4 | 276 | } |
e18e2a00 | 277 | #endif |
1da177e4 | 278 | |
e18e2a00 | 279 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 280 | { |
68c92186 | 281 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 282 | |
e18e2a00 | 283 | if (likely(data)) { |
861fe906 | 284 | unsigned long cpuid, imap, val; |
e18e2a00 | 285 | unsigned int tid; |
e3999574 | 286 | |
e18e2a00 DM |
287 | cpuid = irq_choose_cpu(virt_irq); |
288 | imap = data->imap; | |
e3999574 | 289 | |
e18e2a00 | 290 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 291 | |
861fe906 DM |
292 | val = upa_readq(imap); |
293 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
294 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
295 | val |= tid | IMAP_VALID; | |
296 | upa_writeq(val, imap); | |
e3999574 | 297 | } |
e3999574 DM |
298 | } |
299 | ||
b53bcb67 DM |
300 | static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask) |
301 | { | |
302 | sun4u_irq_enable(virt_irq); | |
303 | } | |
304 | ||
e18e2a00 | 305 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 306 | { |
68c92186 | 307 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 308 | |
e18e2a00 DM |
309 | if (likely(data)) { |
310 | unsigned long imap = data->imap; | |
861fe906 | 311 | u32 tmp = upa_readq(imap); |
1da177e4 | 312 | |
e18e2a00 | 313 | tmp &= ~IMAP_VALID; |
861fe906 | 314 | upa_writeq(tmp, imap); |
088dd1f8 | 315 | } |
088dd1f8 DM |
316 | } |
317 | ||
e18e2a00 | 318 | static void sun4u_irq_end(unsigned int virt_irq) |
088dd1f8 | 319 | { |
68c92186 | 320 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
5a606b72 DM |
321 | struct irq_desc *desc = irq_desc + virt_irq; |
322 | ||
323 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
324 | return; | |
088dd1f8 | 325 | |
e18e2a00 | 326 | if (likely(data)) |
861fe906 | 327 | upa_writeq(ICLR_IDLE, data->iclr); |
088dd1f8 DM |
328 | } |
329 | ||
e18e2a00 | 330 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 331 | { |
e18e2a00 DM |
332 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
333 | unsigned int ino = bucket - &ivector_table[0]; | |
088dd1f8 | 334 | |
e18e2a00 DM |
335 | if (likely(bucket)) { |
336 | unsigned long cpuid; | |
337 | int err; | |
088dd1f8 | 338 | |
e18e2a00 | 339 | cpuid = irq_choose_cpu(virt_irq); |
088dd1f8 | 340 | |
e18e2a00 DM |
341 | err = sun4v_intr_settarget(ino, cpuid); |
342 | if (err != HV_EOK) | |
e83fb17f DM |
343 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " |
344 | "err(%d)\n", ino, cpuid, err); | |
a357b8f4 DM |
345 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
346 | if (err != HV_EOK) | |
e83fb17f | 347 | printk(KERN_ERR "sun4v_intr_setstate(%x): " |
a357b8f4 | 348 | "err(%d)\n", ino, err); |
e18e2a00 DM |
349 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); |
350 | if (err != HV_EOK) | |
e83fb17f | 351 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", |
e18e2a00 | 352 | ino, err); |
088dd1f8 | 353 | } |
088dd1f8 DM |
354 | } |
355 | ||
b53bcb67 DM |
356 | static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask) |
357 | { | |
358 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
359 | unsigned int ino = bucket - &ivector_table[0]; | |
360 | ||
361 | if (likely(bucket)) { | |
362 | unsigned long cpuid; | |
363 | int err; | |
364 | ||
365 | cpuid = irq_choose_cpu(virt_irq); | |
366 | ||
367 | err = sun4v_intr_settarget(ino, cpuid); | |
368 | if (err != HV_EOK) | |
e83fb17f DM |
369 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " |
370 | "err(%d)\n", ino, cpuid, err); | |
b53bcb67 DM |
371 | } |
372 | } | |
373 | ||
e18e2a00 | 374 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 375 | { |
e18e2a00 DM |
376 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
377 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 378 | |
e18e2a00 DM |
379 | if (likely(bucket)) { |
380 | int err; | |
1da177e4 | 381 | |
e18e2a00 DM |
382 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
383 | if (err != HV_EOK) | |
e83fb17f | 384 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " |
e18e2a00 | 385 | "err(%d)\n", ino, err); |
1da177e4 | 386 | } |
e18e2a00 | 387 | } |
1da177e4 | 388 | |
35a17eb6 DM |
389 | #ifdef CONFIG_PCI_MSI |
390 | static void sun4v_msi_enable(unsigned int virt_irq) | |
391 | { | |
392 | sun4v_irq_enable(virt_irq); | |
393 | unmask_msi_irq(virt_irq); | |
394 | } | |
395 | ||
396 | static void sun4v_msi_disable(unsigned int virt_irq) | |
397 | { | |
398 | mask_msi_irq(virt_irq); | |
399 | sun4v_irq_disable(virt_irq); | |
400 | } | |
401 | #endif | |
402 | ||
e18e2a00 DM |
403 | static void sun4v_irq_end(unsigned int virt_irq) |
404 | { | |
405 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
406 | unsigned int ino = bucket - &ivector_table[0]; | |
5a606b72 DM |
407 | struct irq_desc *desc = irq_desc + virt_irq; |
408 | ||
409 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
410 | return; | |
1da177e4 | 411 | |
e18e2a00 DM |
412 | if (likely(bucket)) { |
413 | int err; | |
1da177e4 | 414 | |
e18e2a00 DM |
415 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
416 | if (err != HV_EOK) | |
e83fb17f | 417 | printk(KERN_ERR "sun4v_intr_setstate(%x): " |
e18e2a00 | 418 | "err(%d)\n", ino, err); |
1da177e4 | 419 | } |
1da177e4 LT |
420 | } |
421 | ||
4a907dec DM |
422 | static void sun4v_virq_enable(unsigned int virt_irq) |
423 | { | |
424 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
4a907dec DM |
425 | |
426 | if (likely(bucket)) { | |
427 | unsigned long cpuid, dev_handle, dev_ino; | |
428 | int err; | |
429 | ||
430 | cpuid = irq_choose_cpu(virt_irq); | |
431 | ||
93b3238e DM |
432 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
433 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
4a907dec DM |
434 | |
435 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
436 | if (err != HV_EOK) | |
e83fb17f | 437 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " |
4a907dec DM |
438 | "err(%d)\n", |
439 | dev_handle, dev_ino, cpuid, err); | |
440 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
12450884 DM |
441 | HV_INTR_STATE_IDLE); |
442 | if (err != HV_EOK) | |
e83fb17f | 443 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
12450884 DM |
444 | "HV_INTR_STATE_IDLE): err(%d)\n", |
445 | dev_handle, dev_ino, err); | |
446 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
4a907dec DM |
447 | HV_INTR_ENABLED); |
448 | if (err != HV_EOK) | |
e83fb17f | 449 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
4a907dec DM |
450 | "HV_INTR_ENABLED): err(%d)\n", |
451 | dev_handle, dev_ino, err); | |
452 | } | |
453 | } | |
454 | ||
b53bcb67 DM |
455 | static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask) |
456 | { | |
457 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
b53bcb67 DM |
458 | |
459 | if (likely(bucket)) { | |
460 | unsigned long cpuid, dev_handle, dev_ino; | |
461 | int err; | |
462 | ||
463 | cpuid = irq_choose_cpu(virt_irq); | |
464 | ||
93b3238e DM |
465 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
466 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
b53bcb67 DM |
467 | |
468 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
469 | if (err != HV_EOK) | |
e83fb17f | 470 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " |
b53bcb67 DM |
471 | "err(%d)\n", |
472 | dev_handle, dev_ino, cpuid, err); | |
473 | } | |
474 | } | |
475 | ||
4a907dec DM |
476 | static void sun4v_virq_disable(unsigned int virt_irq) |
477 | { | |
478 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
4a907dec DM |
479 | |
480 | if (likely(bucket)) { | |
481 | unsigned long dev_handle, dev_ino; | |
482 | int err; | |
483 | ||
93b3238e DM |
484 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
485 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
4a907dec | 486 | |
12450884 | 487 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, |
4a907dec DM |
488 | HV_INTR_DISABLED); |
489 | if (err != HV_EOK) | |
e83fb17f | 490 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
4a907dec DM |
491 | "HV_INTR_DISABLED): err(%d)\n", |
492 | dev_handle, dev_ino, err); | |
493 | } | |
494 | } | |
495 | ||
496 | static void sun4v_virq_end(unsigned int virt_irq) | |
497 | { | |
498 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
5a606b72 DM |
499 | struct irq_desc *desc = irq_desc + virt_irq; |
500 | ||
501 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
502 | return; | |
4a907dec DM |
503 | |
504 | if (likely(bucket)) { | |
505 | unsigned long dev_handle, dev_ino; | |
506 | int err; | |
507 | ||
93b3238e DM |
508 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
509 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
4a907dec DM |
510 | |
511 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
512 | HV_INTR_STATE_IDLE); | |
513 | if (err != HV_EOK) | |
e83fb17f | 514 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
4a907dec DM |
515 | "HV_INTR_STATE_IDLE): err(%d)\n", |
516 | dev_handle, dev_ino, err); | |
517 | } | |
518 | } | |
519 | ||
e18e2a00 | 520 | static void run_pre_handler(unsigned int virt_irq) |
1da177e4 | 521 | { |
e18e2a00 | 522 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
68c92186 | 523 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 524 | |
e18e2a00 DM |
525 | if (likely(data->pre_handler)) { |
526 | data->pre_handler(__irq_ino(__irq(bucket)), | |
527 | data->pre_handler_arg1, | |
528 | data->pre_handler_arg2); | |
1da177e4 | 529 | } |
088dd1f8 DM |
530 | } |
531 | ||
729e7d7e | 532 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
533 | .typename = "sun4u", |
534 | .enable = sun4u_irq_enable, | |
535 | .disable = sun4u_irq_disable, | |
536 | .end = sun4u_irq_end, | |
b53bcb67 | 537 | .set_affinity = sun4u_set_affinity, |
e18e2a00 | 538 | }; |
8047e247 | 539 | |
729e7d7e | 540 | static struct irq_chip sun4u_irq_ack = { |
e18e2a00 DM |
541 | .typename = "sun4u+ack", |
542 | .enable = sun4u_irq_enable, | |
543 | .disable = sun4u_irq_disable, | |
544 | .ack = run_pre_handler, | |
545 | .end = sun4u_irq_end, | |
b53bcb67 | 546 | .set_affinity = sun4u_set_affinity, |
e18e2a00 | 547 | }; |
088dd1f8 | 548 | |
729e7d7e | 549 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
550 | .typename = "sun4v", |
551 | .enable = sun4v_irq_enable, | |
552 | .disable = sun4v_irq_disable, | |
553 | .end = sun4v_irq_end, | |
b53bcb67 | 554 | .set_affinity = sun4v_set_affinity, |
e18e2a00 | 555 | }; |
1da177e4 | 556 | |
729e7d7e | 557 | static struct irq_chip sun4v_irq_ack = { |
e18e2a00 DM |
558 | .typename = "sun4v+ack", |
559 | .enable = sun4v_irq_enable, | |
560 | .disable = sun4v_irq_disable, | |
561 | .ack = run_pre_handler, | |
562 | .end = sun4v_irq_end, | |
b53bcb67 | 563 | .set_affinity = sun4v_set_affinity, |
e18e2a00 | 564 | }; |
1da177e4 | 565 | |
35a17eb6 DM |
566 | #ifdef CONFIG_PCI_MSI |
567 | static struct irq_chip sun4v_msi = { | |
568 | .typename = "sun4v+msi", | |
569 | .mask = mask_msi_irq, | |
570 | .unmask = unmask_msi_irq, | |
571 | .enable = sun4v_msi_enable, | |
572 | .disable = sun4v_msi_disable, | |
573 | .ack = run_pre_handler, | |
574 | .end = sun4v_irq_end, | |
b53bcb67 | 575 | .set_affinity = sun4v_set_affinity, |
35a17eb6 DM |
576 | }; |
577 | #endif | |
578 | ||
4a907dec DM |
579 | static struct irq_chip sun4v_virq = { |
580 | .typename = "vsun4v", | |
581 | .enable = sun4v_virq_enable, | |
582 | .disable = sun4v_virq_disable, | |
583 | .end = sun4v_virq_end, | |
b53bcb67 | 584 | .set_affinity = sun4v_virt_set_affinity, |
4a907dec DM |
585 | }; |
586 | ||
587 | static struct irq_chip sun4v_virq_ack = { | |
588 | .typename = "vsun4v+ack", | |
589 | .enable = sun4v_virq_enable, | |
590 | .disable = sun4v_virq_disable, | |
591 | .ack = run_pre_handler, | |
592 | .end = sun4v_virq_end, | |
b53bcb67 | 593 | .set_affinity = sun4v_virt_set_affinity, |
4a907dec DM |
594 | }; |
595 | ||
e18e2a00 DM |
596 | void irq_install_pre_handler(int virt_irq, |
597 | void (*func)(unsigned int, void *, void *), | |
598 | void *arg1, void *arg2) | |
599 | { | |
68c92186 DM |
600 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
601 | struct irq_chip *chip; | |
088dd1f8 | 602 | |
e18e2a00 DM |
603 | data->pre_handler = func; |
604 | data->pre_handler_arg1 = arg1; | |
605 | data->pre_handler_arg2 = arg2; | |
1da177e4 | 606 | |
68c92186 DM |
607 | chip = get_irq_chip(virt_irq); |
608 | if (chip == &sun4u_irq_ack || | |
4a907dec DM |
609 | chip == &sun4v_irq_ack || |
610 | chip == &sun4v_virq_ack | |
35a17eb6 DM |
611 | #ifdef CONFIG_PCI_MSI |
612 | || chip == &sun4v_msi | |
613 | #endif | |
614 | ) | |
24ac26d4 DM |
615 | return; |
616 | ||
68c92186 | 617 | chip = (chip == &sun4u_irq ? |
4a907dec DM |
618 | &sun4u_irq_ack : |
619 | (chip == &sun4v_irq ? | |
620 | &sun4v_irq_ack : &sun4v_virq_ack)); | |
68c92186 | 621 | set_irq_chip(virt_irq, chip); |
e18e2a00 | 622 | } |
1da177e4 | 623 | |
e18e2a00 DM |
624 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
625 | { | |
626 | struct ino_bucket *bucket; | |
627 | struct irq_handler_data *data; | |
e18e2a00 | 628 | int ino; |
1da177e4 | 629 | |
e18e2a00 | 630 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 631 | |
861fe906 | 632 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 DM |
633 | bucket = &ivector_table[ino]; |
634 | if (!bucket->virt_irq) { | |
635 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
68c92186 | 636 | set_irq_chip(bucket->virt_irq, &sun4u_irq); |
fd0504c3 | 637 | } |
1da177e4 | 638 | |
68c92186 DM |
639 | data = get_irq_chip_data(bucket->virt_irq); |
640 | if (unlikely(data)) | |
e18e2a00 | 641 | goto out; |
fd0504c3 | 642 | |
e18e2a00 DM |
643 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
644 | if (unlikely(!data)) { | |
645 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
646 | prom_halt(); | |
1da177e4 | 647 | } |
68c92186 | 648 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 649 | |
e18e2a00 DM |
650 | data->imap = imap; |
651 | data->iclr = iclr; | |
1da177e4 | 652 | |
e18e2a00 DM |
653 | out: |
654 | return bucket->virt_irq; | |
655 | } | |
1da177e4 | 656 | |
4a907dec DM |
657 | static unsigned int sun4v_build_common(unsigned long sysino, |
658 | struct irq_chip *chip) | |
1da177e4 | 659 | { |
8047e247 | 660 | struct ino_bucket *bucket; |
e18e2a00 | 661 | struct irq_handler_data *data; |
8047e247 | 662 | |
e18e2a00 | 663 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 664 | |
e18e2a00 DM |
665 | bucket = &ivector_table[sysino]; |
666 | if (!bucket->virt_irq) { | |
667 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
4a907dec | 668 | set_irq_chip(bucket->virt_irq, chip); |
1da177e4 | 669 | } |
1da177e4 | 670 | |
68c92186 DM |
671 | data = get_irq_chip_data(bucket->virt_irq); |
672 | if (unlikely(data)) | |
1da177e4 | 673 | goto out; |
1da177e4 | 674 | |
e18e2a00 DM |
675 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
676 | if (unlikely(!data)) { | |
677 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
678 | prom_halt(); | |
679 | } | |
68c92186 | 680 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 681 | |
e18e2a00 DM |
682 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
683 | * is done by hypervisor calls on sun4v platforms, not by direct | |
684 | * register accesses. | |
685 | */ | |
686 | data->imap = ~0UL; | |
687 | data->iclr = ~0UL; | |
1da177e4 | 688 | |
e18e2a00 DM |
689 | out: |
690 | return bucket->virt_irq; | |
691 | } | |
1da177e4 | 692 | |
4a907dec DM |
693 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
694 | { | |
695 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
696 | ||
697 | return sun4v_build_common(sysino, &sun4v_irq); | |
698 | } | |
699 | ||
700 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
701 | { | |
702 | unsigned long sysino, hv_err; | |
93b3238e | 703 | unsigned int virq; |
4a907dec | 704 | |
5f7426c0 | 705 | BUG_ON(devhandle & devino); |
4a907dec DM |
706 | |
707 | sysino = devhandle | devino; | |
5f7426c0 | 708 | BUG_ON(sysino & ~(IMAP_IGN | IMAP_INO)); |
4a907dec DM |
709 | |
710 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, sysino); | |
711 | if (hv_err) { | |
712 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
713 | "err=%lu\n", devhandle, devino, hv_err); | |
714 | prom_halt(); | |
715 | } | |
716 | ||
93b3238e DM |
717 | virq = sun4v_build_common(sysino, &sun4v_virq); |
718 | ||
719 | virt_to_real_irq_table[virq].dev_handle = devhandle; | |
720 | virt_to_real_irq_table[virq].dev_ino = devino; | |
721 | ||
722 | return virq; | |
4a907dec DM |
723 | } |
724 | ||
35a17eb6 DM |
725 | #ifdef CONFIG_PCI_MSI |
726 | unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, | |
727 | unsigned int msi_start, unsigned int msi_end) | |
728 | { | |
729 | struct ino_bucket *bucket; | |
730 | struct irq_handler_data *data; | |
731 | unsigned long sysino; | |
732 | unsigned int devino; | |
733 | ||
734 | BUG_ON(tlb_type != hypervisor); | |
735 | ||
736 | /* Find a free devino in the given range. */ | |
737 | for (devino = msi_start; devino < msi_end; devino++) { | |
738 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
739 | bucket = &ivector_table[sysino]; | |
740 | if (!bucket->virt_irq) | |
741 | break; | |
742 | } | |
743 | if (devino >= msi_end) | |
744 | return 0; | |
745 | ||
746 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
747 | bucket = &ivector_table[sysino]; | |
748 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
749 | *virt_irq_p = bucket->virt_irq; | |
750 | set_irq_chip(bucket->virt_irq, &sun4v_msi); | |
751 | ||
752 | data = get_irq_chip_data(bucket->virt_irq); | |
753 | if (unlikely(data)) | |
754 | return devino; | |
755 | ||
756 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); | |
757 | if (unlikely(!data)) { | |
758 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
759 | prom_halt(); | |
760 | } | |
761 | set_irq_chip_data(bucket->virt_irq, data); | |
762 | ||
763 | data->imap = ~0UL; | |
764 | data->iclr = ~0UL; | |
765 | ||
766 | return devino; | |
767 | } | |
768 | ||
769 | void sun4v_destroy_msi(unsigned int virt_irq) | |
770 | { | |
771 | virt_irq_free(virt_irq); | |
772 | } | |
773 | #endif | |
774 | ||
e18e2a00 DM |
775 | void ack_bad_irq(unsigned int virt_irq) |
776 | { | |
777 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
778 | unsigned int ino = 0xdeadbeef; | |
ab66a50e | 779 | |
e18e2a00 DM |
780 | if (bucket) |
781 | ino = bucket - &ivector_table[0]; | |
6a76267f | 782 | |
e18e2a00 DM |
783 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
784 | ino, virt_irq); | |
1da177e4 LT |
785 | } |
786 | ||
1da177e4 LT |
787 | void handler_irq(int irq, struct pt_regs *regs) |
788 | { | |
e18e2a00 | 789 | struct ino_bucket *bucket; |
6d24c8dc | 790 | struct pt_regs *old_regs; |
1da177e4 | 791 | |
1da177e4 | 792 | clear_softint(1 << irq); |
1da177e4 | 793 | |
6d24c8dc | 794 | old_regs = set_irq_regs(regs); |
1da177e4 | 795 | irq_enter(); |
1da177e4 LT |
796 | |
797 | /* Sliiiick... */ | |
e18e2a00 DM |
798 | bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0)); |
799 | while (bucket) { | |
800 | struct ino_bucket *next = __bucket(bucket->irq_chain); | |
1da177e4 | 801 | |
e18e2a00 | 802 | bucket->irq_chain = 0; |
6d24c8dc | 803 | __do_IRQ(bucket->virt_irq); |
fd0504c3 | 804 | |
e18e2a00 | 805 | bucket = next; |
1da177e4 | 806 | } |
e18e2a00 | 807 | |
1da177e4 | 808 | irq_exit(); |
6d24c8dc | 809 | set_irq_regs(old_regs); |
1da177e4 LT |
810 | } |
811 | ||
e0204409 DM |
812 | #ifdef CONFIG_HOTPLUG_CPU |
813 | void fixup_irqs(void) | |
814 | { | |
815 | unsigned int irq; | |
816 | ||
817 | for (irq = 0; irq < NR_IRQS; irq++) { | |
818 | unsigned long flags; | |
819 | ||
820 | spin_lock_irqsave(&irq_desc[irq].lock, flags); | |
821 | if (irq_desc[irq].action && | |
822 | !(irq_desc[irq].status & IRQ_PER_CPU)) { | |
823 | if (irq_desc[irq].chip->set_affinity) | |
824 | irq_desc[irq].chip->set_affinity(irq, | |
825 | irq_desc[irq].affinity); | |
826 | } | |
827 | spin_unlock_irqrestore(&irq_desc[irq].lock, flags); | |
828 | } | |
829 | } | |
830 | #endif | |
831 | ||
cdd5186f DM |
832 | struct sun5_timer { |
833 | u64 count0; | |
834 | u64 limit0; | |
835 | u64 count1; | |
836 | u64 limit1; | |
837 | }; | |
1da177e4 | 838 | |
cdd5186f | 839 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
840 | static u64 prom_limit0, prom_limit1; |
841 | ||
842 | static void map_prom_timers(void) | |
843 | { | |
25c7581b | 844 | struct device_node *dp; |
6a23acf3 | 845 | const unsigned int *addr; |
1da177e4 LT |
846 | |
847 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
848 | dp = of_find_node_by_path("/"); |
849 | dp = dp->child; | |
850 | while (dp) { | |
851 | if (!strcmp(dp->name, "counter-timer")) | |
852 | break; | |
853 | dp = dp->sibling; | |
854 | } | |
1da177e4 LT |
855 | |
856 | /* Assume if node is not present, PROM uses different tick mechanism | |
857 | * which we should not care about. | |
858 | */ | |
25c7581b | 859 | if (!dp) { |
1da177e4 LT |
860 | prom_timers = (struct sun5_timer *) 0; |
861 | return; | |
862 | } | |
863 | ||
864 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
865 | addr = of_get_property(dp, "address", NULL); |
866 | if (!addr) { | |
1da177e4 LT |
867 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
868 | prom_timers = (struct sun5_timer *) 0; | |
869 | return; | |
870 | } | |
871 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
872 | } | |
873 | ||
874 | static void kill_prom_timer(void) | |
875 | { | |
876 | if (!prom_timers) | |
877 | return; | |
878 | ||
879 | /* Save them away for later. */ | |
880 | prom_limit0 = prom_timers->limit0; | |
881 | prom_limit1 = prom_timers->limit1; | |
882 | ||
883 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
884 | * We turn both off here just to be paranoid. | |
885 | */ | |
886 | prom_timers->limit0 = 0; | |
887 | prom_timers->limit1 = 0; | |
888 | ||
889 | /* Wheee, eat the interrupt packet too... */ | |
890 | __asm__ __volatile__( | |
891 | " mov 0x40, %%g2\n" | |
892 | " ldxa [%%g0] %0, %%g1\n" | |
893 | " ldxa [%%g2] %1, %%g1\n" | |
894 | " stxa %%g0, [%%g0] %0\n" | |
895 | " membar #Sync\n" | |
896 | : /* no outputs */ | |
897 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
898 | : "g1", "g2"); | |
899 | } | |
900 | ||
1da177e4 LT |
901 | void init_irqwork_curcpu(void) |
902 | { | |
1da177e4 LT |
903 | int cpu = hard_smp_processor_id(); |
904 | ||
fd0504c3 | 905 | trap_block[cpu].irq_worklist = 0; |
1da177e4 LT |
906 | } |
907 | ||
5cbc3073 DM |
908 | /* Please be very careful with register_one_mondo() and |
909 | * sun4v_register_mondo_queues(). | |
910 | * | |
911 | * On SMP this gets invoked from the CPU trampoline before | |
912 | * the cpu has fully taken over the trap table from OBP, | |
913 | * and it's kernel stack + %g6 thread register state is | |
914 | * not fully cooked yet. | |
915 | * | |
916 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
917 | * from these two routines. | |
918 | */ | |
919 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) | |
ac29c11d | 920 | { |
5cbc3073 | 921 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
922 | unsigned long status; |
923 | ||
924 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
925 | if (status != HV_EOK) { | |
926 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
927 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
928 | prom_halt(); |
929 | } | |
930 | } | |
931 | ||
b434e719 | 932 | void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 933 | { |
b5a37e96 DM |
934 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
935 | ||
5cbc3073 DM |
936 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
937 | tb->cpu_mondo_qmask); | |
938 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
939 | tb->dev_mondo_qmask); | |
940 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
941 | tb->resum_qmask); | |
942 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
943 | tb->nonresum_qmask); | |
b5a37e96 DM |
944 | } |
945 | ||
b434e719 | 946 | static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 947 | { |
5cbc3073 | 948 | unsigned long size = PAGE_ALIGN(qmask + 1); |
b434e719 | 949 | void *p = __alloc_bootmem_low(size, size, 0); |
5cbc3073 | 950 | if (!p) { |
b5a37e96 DM |
951 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
952 | prom_halt(); | |
953 | } | |
954 | ||
5cbc3073 | 955 | *pa_ptr = __pa(p); |
b5a37e96 DM |
956 | } |
957 | ||
b434e719 | 958 | static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 959 | { |
5cbc3073 | 960 | unsigned long size = PAGE_ALIGN(qmask + 1); |
b434e719 | 961 | void *p = __alloc_bootmem_low(size, size, 0); |
5b0c0572 | 962 | |
5cbc3073 | 963 | if (!p) { |
5b0c0572 DM |
964 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
965 | prom_halt(); | |
966 | } | |
967 | ||
5cbc3073 | 968 | *pa_ptr = __pa(p); |
5b0c0572 DM |
969 | } |
970 | ||
b434e719 | 971 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
1d2f1f90 DM |
972 | { |
973 | #ifdef CONFIG_SMP | |
b5a37e96 | 974 | void *page; |
1d2f1f90 DM |
975 | |
976 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
977 | ||
b434e719 | 978 | page = alloc_bootmem_low_pages(PAGE_SIZE); |
1d2f1f90 DM |
979 | if (!page) { |
980 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
981 | prom_halt(); | |
982 | } | |
983 | ||
984 | tb->cpu_mondo_block_pa = __pa(page); | |
985 | tb->cpu_list_pa = __pa(page + 64); | |
986 | #endif | |
987 | } | |
988 | ||
b434e719 DM |
989 | /* Allocate mondo and error queues for all possible cpus. */ |
990 | static void __init sun4v_init_mondo_queues(void) | |
ac29c11d | 991 | { |
b434e719 | 992 | int cpu; |
ac29c11d | 993 | |
b434e719 DM |
994 | for_each_possible_cpu(cpu) { |
995 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 996 | |
b434e719 DM |
997 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
998 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); | |
999 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); | |
1000 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); | |
1001 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); | |
1002 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, | |
1003 | tb->nonresum_qmask); | |
1d2f1f90 | 1004 | |
b434e719 | 1005 | init_cpu_send_mondo_info(tb); |
72aff53f | 1006 | } |
b434e719 DM |
1007 | |
1008 | /* Load up the boot cpu's entries. */ | |
1009 | sun4v_register_mondo_queues(hard_smp_processor_id()); | |
ac29c11d DM |
1010 | } |
1011 | ||
e18e2a00 DM |
1012 | static struct irqaction timer_irq_action = { |
1013 | .name = "timer", | |
1014 | }; | |
1015 | ||
1da177e4 LT |
1016 | /* Only invoked on boot processor. */ |
1017 | void __init init_IRQ(void) | |
1018 | { | |
1019 | map_prom_timers(); | |
1020 | kill_prom_timer(); | |
1021 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
1022 | ||
ac29c11d | 1023 | if (tlb_type == hypervisor) |
b434e719 | 1024 | sun4v_init_mondo_queues(); |
ac29c11d | 1025 | |
1da177e4 LT |
1026 | /* We need to clear any IRQ's pending in the soft interrupt |
1027 | * registers, a spurious one could be left around from the | |
1028 | * PROM timer which we just disabled. | |
1029 | */ | |
1030 | clear_softint(get_softint()); | |
1031 | ||
1032 | /* Now that ivector table is initialized, it is safe | |
1033 | * to receive IRQ vector traps. We will normally take | |
1034 | * one or two right now, in case some device PROM used | |
1035 | * to boot us wants to speak to us. We just ignore them. | |
1036 | */ | |
1037 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
1038 | "or %%g1, %0, %%g1\n\t" | |
1039 | "wrpr %%g1, 0x0, %%pstate" | |
1040 | : /* No outputs */ | |
1041 | : "i" (PSTATE_IE) | |
1042 | : "g1"); | |
1da177e4 | 1043 | |
e18e2a00 | 1044 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 1045 | } |