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1da177e4 LT |
1 | /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $ |
2 | * irq.c: UltraSparc IRQ handling/init/registry. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/ptrace.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/kernel_stat.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/random.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/proc_fs.h> | |
22 | #include <linux/seq_file.h> | |
b5a37e96 | 23 | #include <linux/bootmem.h> |
e18e2a00 | 24 | #include <linux/irq.h> |
35a17eb6 | 25 | #include <linux/msi.h> |
1da177e4 LT |
26 | |
27 | #include <asm/ptrace.h> | |
28 | #include <asm/processor.h> | |
29 | #include <asm/atomic.h> | |
30 | #include <asm/system.h> | |
31 | #include <asm/irq.h> | |
2e457ef6 | 32 | #include <asm/io.h> |
1da177e4 LT |
33 | #include <asm/sbus.h> |
34 | #include <asm/iommu.h> | |
35 | #include <asm/upa.h> | |
36 | #include <asm/oplib.h> | |
25c7581b | 37 | #include <asm/prom.h> |
1da177e4 LT |
38 | #include <asm/timer.h> |
39 | #include <asm/smp.h> | |
40 | #include <asm/starfire.h> | |
41 | #include <asm/uaccess.h> | |
42 | #include <asm/cache.h> | |
43 | #include <asm/cpudata.h> | |
63b61452 | 44 | #include <asm/auxio.h> |
92704a1c | 45 | #include <asm/head.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /* UPA nodes send interrupt packet to UltraSparc with first data reg |
48 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
49 | * delivered. We must translate this into a non-vector IRQ so we can | |
50 | * set the softint on this cpu. | |
51 | * | |
52 | * To make processing these packets efficient and race free we use | |
53 | * an array of irq buckets below. The interrupt vector handler in | |
54 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
55 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
56 | * code uses CAS to get an atomic snapshot of the list and clear it | |
57 | * at the same time. | |
e18e2a00 DM |
58 | * |
59 | * If you make changes to ino_bucket, please update hand coded assembler | |
60 | * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S | |
1da177e4 | 61 | */ |
e18e2a00 DM |
62 | struct ino_bucket { |
63 | /* Next handler in per-CPU IRQ worklist. We know that | |
64 | * bucket pointers have the high 32-bits clear, so to | |
65 | * save space we only store the bits we need. | |
66 | */ | |
67 | /*0x00*/unsigned int irq_chain; | |
1da177e4 | 68 | |
e18e2a00 DM |
69 | /* Virtual interrupt number assigned to this INO. */ |
70 | /*0x04*/unsigned int virt_irq; | |
71 | }; | |
72 | ||
73 | #define NUM_IVECS (IMAP_INR + 1) | |
1da177e4 LT |
74 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); |
75 | ||
e18e2a00 DM |
76 | #define __irq_ino(irq) \ |
77 | (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0]) | |
78 | #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq)) | |
79 | #define __irq(bucket) ((unsigned int)(unsigned long)(bucket)) | |
80 | ||
1da177e4 LT |
81 | /* This has to be in the main kernel image, it cannot be |
82 | * turned into per-cpu data. The reason is that the main | |
83 | * kernel image is locked into the TLB and this structure | |
84 | * is accessed from the vectored interrupt trap handler. If | |
85 | * access to this structure takes a TLB miss it could cause | |
86 | * the 5-level sparc v9 trap stack to overflow. | |
87 | */ | |
fd0504c3 | 88 | #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist) |
1da177e4 | 89 | |
8047e247 | 90 | static unsigned int virt_to_real_irq_table[NR_IRQS]; |
8047e247 DM |
91 | |
92 | static unsigned char virt_irq_alloc(unsigned int real_irq) | |
93 | { | |
94 | unsigned char ent; | |
95 | ||
96 | BUILD_BUG_ON(NR_IRQS >= 256); | |
97 | ||
35a17eb6 DM |
98 | for (ent = 1; ent < NR_IRQS; ent++) { |
99 | if (!virt_to_real_irq_table[ent]) | |
100 | break; | |
101 | } | |
8047e247 DM |
102 | if (ent >= NR_IRQS) { |
103 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
104 | return 0; | |
105 | } | |
106 | ||
8047e247 DM |
107 | virt_to_real_irq_table[ent] = real_irq; |
108 | ||
109 | return ent; | |
110 | } | |
111 | ||
5746c99d | 112 | #ifdef CONFIG_PCI_MSI |
35a17eb6 | 113 | static void virt_irq_free(unsigned int virt_irq) |
8047e247 | 114 | { |
35a17eb6 | 115 | unsigned int real_irq; |
8047e247 | 116 | |
35a17eb6 DM |
117 | if (virt_irq >= NR_IRQS) |
118 | return; | |
119 | ||
120 | real_irq = virt_to_real_irq_table[virt_irq]; | |
121 | virt_to_real_irq_table[virt_irq] = 0; | |
122 | ||
123 | __bucket(real_irq)->virt_irq = 0; | |
8047e247 | 124 | } |
5746c99d | 125 | #endif |
8047e247 DM |
126 | |
127 | static unsigned int virt_to_real_irq(unsigned char virt_irq) | |
128 | { | |
129 | return virt_to_real_irq_table[virt_irq]; | |
130 | } | |
131 | ||
1da177e4 | 132 | /* |
e18e2a00 | 133 | * /proc/interrupts printing: |
1da177e4 | 134 | */ |
1da177e4 LT |
135 | |
136 | int show_interrupts(struct seq_file *p, void *v) | |
137 | { | |
e18e2a00 DM |
138 | int i = *(loff_t *) v, j; |
139 | struct irqaction * action; | |
1da177e4 | 140 | unsigned long flags; |
1da177e4 | 141 | |
e18e2a00 DM |
142 | if (i == 0) { |
143 | seq_printf(p, " "); | |
144 | for_each_online_cpu(j) | |
145 | seq_printf(p, "CPU%d ",j); | |
146 | seq_putc(p, '\n'); | |
147 | } | |
148 | ||
149 | if (i < NR_IRQS) { | |
150 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
151 | action = irq_desc[i].action; | |
152 | if (!action) | |
153 | goto skip; | |
154 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
155 | #ifndef CONFIG_SMP |
156 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
157 | #else | |
e18e2a00 DM |
158 | for_each_online_cpu(j) |
159 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 160 | #endif |
d1bef4ed | 161 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
162 | seq_printf(p, " %s", action->name); |
163 | ||
164 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 165 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 166 | |
1da177e4 | 167 | seq_putc(p, '\n'); |
e18e2a00 DM |
168 | skip: |
169 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 170 | } |
1da177e4 LT |
171 | return 0; |
172 | } | |
173 | ||
ebd8c56c DM |
174 | extern unsigned long real_hard_smp_processor_id(void); |
175 | ||
176 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) | |
177 | { | |
178 | unsigned int tid; | |
179 | ||
180 | if (this_is_starfire) { | |
181 | tid = starfire_translate(imap, cpuid); | |
182 | tid <<= IMAP_TID_SHIFT; | |
183 | tid &= IMAP_TID_UPA; | |
184 | } else { | |
185 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
186 | unsigned long ver; | |
187 | ||
188 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
189 | if ((ver >> 32UL) == __JALAPENO_ID || | |
190 | (ver >> 32UL) == __SERRANO_ID) { | |
191 | tid = cpuid << IMAP_TID_SHIFT; | |
192 | tid &= IMAP_TID_JBUS; | |
193 | } else { | |
194 | unsigned int a = cpuid & 0x1f; | |
195 | unsigned int n = (cpuid >> 5) & 0x1f; | |
196 | ||
197 | tid = ((a << IMAP_AID_SHIFT) | | |
198 | (n << IMAP_NID_SHIFT)); | |
199 | tid &= (IMAP_AID_SAFARI | | |
200 | IMAP_NID_SAFARI);; | |
201 | } | |
202 | } else { | |
203 | tid = cpuid << IMAP_TID_SHIFT; | |
204 | tid &= IMAP_TID_UPA; | |
205 | } | |
206 | } | |
207 | ||
208 | return tid; | |
209 | } | |
210 | ||
e18e2a00 DM |
211 | struct irq_handler_data { |
212 | unsigned long iclr; | |
213 | unsigned long imap; | |
8047e247 | 214 | |
e18e2a00 DM |
215 | void (*pre_handler)(unsigned int, void *, void *); |
216 | void *pre_handler_arg1; | |
217 | void *pre_handler_arg2; | |
218 | }; | |
1da177e4 | 219 | |
e18e2a00 | 220 | static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq) |
1da177e4 | 221 | { |
8047e247 | 222 | unsigned int real_irq = virt_to_real_irq(virt_irq); |
e18e2a00 | 223 | struct ino_bucket *bucket = NULL; |
1da177e4 | 224 | |
e18e2a00 DM |
225 | if (likely(real_irq)) |
226 | bucket = __bucket(real_irq); | |
8047e247 | 227 | |
e18e2a00 | 228 | return bucket; |
1da177e4 LT |
229 | } |
230 | ||
e18e2a00 DM |
231 | #ifdef CONFIG_SMP |
232 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 233 | { |
a53da52f | 234 | cpumask_t mask = irq_desc[virt_irq].affinity; |
e18e2a00 | 235 | int cpuid; |
088dd1f8 | 236 | |
e18e2a00 DM |
237 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
238 | static int irq_rover; | |
239 | static DEFINE_SPINLOCK(irq_rover_lock); | |
240 | unsigned long flags; | |
1da177e4 | 241 | |
e18e2a00 DM |
242 | /* Round-robin distribution... */ |
243 | do_round_robin: | |
244 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 245 | |
e18e2a00 DM |
246 | while (!cpu_online(irq_rover)) { |
247 | if (++irq_rover >= NR_CPUS) | |
248 | irq_rover = 0; | |
249 | } | |
250 | cpuid = irq_rover; | |
251 | do { | |
252 | if (++irq_rover >= NR_CPUS) | |
253 | irq_rover = 0; | |
254 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 255 | |
e18e2a00 DM |
256 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
257 | } else { | |
258 | cpumask_t tmp; | |
088dd1f8 | 259 | |
e18e2a00 | 260 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 261 | |
e18e2a00 DM |
262 | if (cpus_empty(tmp)) |
263 | goto do_round_robin; | |
088dd1f8 | 264 | |
e18e2a00 | 265 | cpuid = first_cpu(tmp); |
1da177e4 | 266 | } |
088dd1f8 | 267 | |
e18e2a00 DM |
268 | return cpuid; |
269 | } | |
270 | #else | |
271 | static int irq_choose_cpu(unsigned int virt_irq) | |
272 | { | |
273 | return real_hard_smp_processor_id(); | |
1da177e4 | 274 | } |
e18e2a00 | 275 | #endif |
1da177e4 | 276 | |
e18e2a00 | 277 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 278 | { |
68c92186 | 279 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 280 | |
e18e2a00 DM |
281 | if (likely(data)) { |
282 | unsigned long cpuid, imap; | |
283 | unsigned int tid; | |
e3999574 | 284 | |
e18e2a00 DM |
285 | cpuid = irq_choose_cpu(virt_irq); |
286 | imap = data->imap; | |
e3999574 | 287 | |
e18e2a00 | 288 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 289 | |
e18e2a00 | 290 | upa_writel(tid | IMAP_VALID, imap); |
e3999574 | 291 | } |
e3999574 DM |
292 | } |
293 | ||
e18e2a00 | 294 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 295 | { |
68c92186 | 296 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 297 | |
e18e2a00 DM |
298 | if (likely(data)) { |
299 | unsigned long imap = data->imap; | |
300 | u32 tmp = upa_readl(imap); | |
1da177e4 | 301 | |
e18e2a00 DM |
302 | tmp &= ~IMAP_VALID; |
303 | upa_writel(tmp, imap); | |
088dd1f8 | 304 | } |
088dd1f8 DM |
305 | } |
306 | ||
e18e2a00 | 307 | static void sun4u_irq_end(unsigned int virt_irq) |
088dd1f8 | 308 | { |
68c92186 | 309 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
088dd1f8 | 310 | |
e18e2a00 DM |
311 | if (likely(data)) |
312 | upa_writel(ICLR_IDLE, data->iclr); | |
088dd1f8 DM |
313 | } |
314 | ||
e18e2a00 | 315 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 316 | { |
e18e2a00 DM |
317 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
318 | unsigned int ino = bucket - &ivector_table[0]; | |
088dd1f8 | 319 | |
e18e2a00 DM |
320 | if (likely(bucket)) { |
321 | unsigned long cpuid; | |
322 | int err; | |
088dd1f8 | 323 | |
e18e2a00 | 324 | cpuid = irq_choose_cpu(virt_irq); |
088dd1f8 | 325 | |
e18e2a00 DM |
326 | err = sun4v_intr_settarget(ino, cpuid); |
327 | if (err != HV_EOK) | |
328 | printk("sun4v_intr_settarget(%x,%lu): err(%d)\n", | |
329 | ino, cpuid, err); | |
330 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
331 | if (err != HV_EOK) | |
332 | printk("sun4v_intr_setenabled(%x): err(%d)\n", | |
333 | ino, err); | |
088dd1f8 | 334 | } |
088dd1f8 DM |
335 | } |
336 | ||
e18e2a00 | 337 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 338 | { |
e18e2a00 DM |
339 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
340 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 341 | |
e18e2a00 DM |
342 | if (likely(bucket)) { |
343 | int err; | |
1da177e4 | 344 | |
e18e2a00 DM |
345 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
346 | if (err != HV_EOK) | |
347 | printk("sun4v_intr_setenabled(%x): " | |
348 | "err(%d)\n", ino, err); | |
1da177e4 | 349 | } |
e18e2a00 | 350 | } |
1da177e4 | 351 | |
35a17eb6 DM |
352 | #ifdef CONFIG_PCI_MSI |
353 | static void sun4v_msi_enable(unsigned int virt_irq) | |
354 | { | |
355 | sun4v_irq_enable(virt_irq); | |
356 | unmask_msi_irq(virt_irq); | |
357 | } | |
358 | ||
359 | static void sun4v_msi_disable(unsigned int virt_irq) | |
360 | { | |
361 | mask_msi_irq(virt_irq); | |
362 | sun4v_irq_disable(virt_irq); | |
363 | } | |
364 | #endif | |
365 | ||
e18e2a00 DM |
366 | static void sun4v_irq_end(unsigned int virt_irq) |
367 | { | |
368 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
369 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 370 | |
e18e2a00 DM |
371 | if (likely(bucket)) { |
372 | int err; | |
1da177e4 | 373 | |
e18e2a00 DM |
374 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
375 | if (err != HV_EOK) | |
376 | printk("sun4v_intr_setstate(%x): " | |
377 | "err(%d)\n", ino, err); | |
1da177e4 | 378 | } |
1da177e4 LT |
379 | } |
380 | ||
e18e2a00 | 381 | static void run_pre_handler(unsigned int virt_irq) |
1da177e4 | 382 | { |
e18e2a00 | 383 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
68c92186 | 384 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 385 | |
e18e2a00 DM |
386 | if (likely(data->pre_handler)) { |
387 | data->pre_handler(__irq_ino(__irq(bucket)), | |
388 | data->pre_handler_arg1, | |
389 | data->pre_handler_arg2); | |
1da177e4 | 390 | } |
088dd1f8 DM |
391 | } |
392 | ||
729e7d7e | 393 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
394 | .typename = "sun4u", |
395 | .enable = sun4u_irq_enable, | |
396 | .disable = sun4u_irq_disable, | |
397 | .end = sun4u_irq_end, | |
398 | }; | |
8047e247 | 399 | |
729e7d7e | 400 | static struct irq_chip sun4u_irq_ack = { |
e18e2a00 DM |
401 | .typename = "sun4u+ack", |
402 | .enable = sun4u_irq_enable, | |
403 | .disable = sun4u_irq_disable, | |
404 | .ack = run_pre_handler, | |
405 | .end = sun4u_irq_end, | |
406 | }; | |
088dd1f8 | 407 | |
729e7d7e | 408 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
409 | .typename = "sun4v", |
410 | .enable = sun4v_irq_enable, | |
411 | .disable = sun4v_irq_disable, | |
412 | .end = sun4v_irq_end, | |
413 | }; | |
1da177e4 | 414 | |
729e7d7e | 415 | static struct irq_chip sun4v_irq_ack = { |
e18e2a00 DM |
416 | .typename = "sun4v+ack", |
417 | .enable = sun4v_irq_enable, | |
418 | .disable = sun4v_irq_disable, | |
419 | .ack = run_pre_handler, | |
420 | .end = sun4v_irq_end, | |
421 | }; | |
1da177e4 | 422 | |
35a17eb6 DM |
423 | #ifdef CONFIG_PCI_MSI |
424 | static struct irq_chip sun4v_msi = { | |
425 | .typename = "sun4v+msi", | |
426 | .mask = mask_msi_irq, | |
427 | .unmask = unmask_msi_irq, | |
428 | .enable = sun4v_msi_enable, | |
429 | .disable = sun4v_msi_disable, | |
430 | .ack = run_pre_handler, | |
431 | .end = sun4v_irq_end, | |
432 | }; | |
433 | #endif | |
434 | ||
e18e2a00 DM |
435 | void irq_install_pre_handler(int virt_irq, |
436 | void (*func)(unsigned int, void *, void *), | |
437 | void *arg1, void *arg2) | |
438 | { | |
68c92186 DM |
439 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
440 | struct irq_chip *chip; | |
088dd1f8 | 441 | |
e18e2a00 DM |
442 | data->pre_handler = func; |
443 | data->pre_handler_arg1 = arg1; | |
444 | data->pre_handler_arg2 = arg2; | |
1da177e4 | 445 | |
68c92186 DM |
446 | chip = get_irq_chip(virt_irq); |
447 | if (chip == &sun4u_irq_ack || | |
35a17eb6 DM |
448 | chip == &sun4v_irq_ack |
449 | #ifdef CONFIG_PCI_MSI | |
450 | || chip == &sun4v_msi | |
451 | #endif | |
452 | ) | |
24ac26d4 DM |
453 | return; |
454 | ||
68c92186 DM |
455 | chip = (chip == &sun4u_irq ? |
456 | &sun4u_irq_ack : &sun4v_irq_ack); | |
457 | set_irq_chip(virt_irq, chip); | |
e18e2a00 | 458 | } |
1da177e4 | 459 | |
e18e2a00 DM |
460 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
461 | { | |
462 | struct ino_bucket *bucket; | |
463 | struct irq_handler_data *data; | |
e18e2a00 | 464 | int ino; |
1da177e4 | 465 | |
e18e2a00 | 466 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 467 | |
e18e2a00 DM |
468 | ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
469 | bucket = &ivector_table[ino]; | |
470 | if (!bucket->virt_irq) { | |
471 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
68c92186 | 472 | set_irq_chip(bucket->virt_irq, &sun4u_irq); |
fd0504c3 | 473 | } |
1da177e4 | 474 | |
68c92186 DM |
475 | data = get_irq_chip_data(bucket->virt_irq); |
476 | if (unlikely(data)) | |
e18e2a00 | 477 | goto out; |
fd0504c3 | 478 | |
e18e2a00 DM |
479 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
480 | if (unlikely(!data)) { | |
481 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
482 | prom_halt(); | |
1da177e4 | 483 | } |
68c92186 | 484 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 485 | |
e18e2a00 DM |
486 | data->imap = imap; |
487 | data->iclr = iclr; | |
1da177e4 | 488 | |
e18e2a00 DM |
489 | out: |
490 | return bucket->virt_irq; | |
491 | } | |
1da177e4 | 492 | |
e18e2a00 | 493 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
1da177e4 | 494 | { |
8047e247 | 495 | struct ino_bucket *bucket; |
e18e2a00 DM |
496 | struct irq_handler_data *data; |
497 | unsigned long sysino; | |
8047e247 | 498 | |
e18e2a00 | 499 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 500 | |
e18e2a00 DM |
501 | sysino = sun4v_devino_to_sysino(devhandle, devino); |
502 | bucket = &ivector_table[sysino]; | |
503 | if (!bucket->virt_irq) { | |
504 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
68c92186 | 505 | set_irq_chip(bucket->virt_irq, &sun4v_irq); |
1da177e4 | 506 | } |
1da177e4 | 507 | |
68c92186 DM |
508 | data = get_irq_chip_data(bucket->virt_irq); |
509 | if (unlikely(data)) | |
1da177e4 | 510 | goto out; |
1da177e4 | 511 | |
e18e2a00 DM |
512 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
513 | if (unlikely(!data)) { | |
514 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
515 | prom_halt(); | |
516 | } | |
68c92186 | 517 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 518 | |
e18e2a00 DM |
519 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
520 | * is done by hypervisor calls on sun4v platforms, not by direct | |
521 | * register accesses. | |
522 | */ | |
523 | data->imap = ~0UL; | |
524 | data->iclr = ~0UL; | |
1da177e4 | 525 | |
e18e2a00 DM |
526 | out: |
527 | return bucket->virt_irq; | |
528 | } | |
1da177e4 | 529 | |
35a17eb6 DM |
530 | #ifdef CONFIG_PCI_MSI |
531 | unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, | |
532 | unsigned int msi_start, unsigned int msi_end) | |
533 | { | |
534 | struct ino_bucket *bucket; | |
535 | struct irq_handler_data *data; | |
536 | unsigned long sysino; | |
537 | unsigned int devino; | |
538 | ||
539 | BUG_ON(tlb_type != hypervisor); | |
540 | ||
541 | /* Find a free devino in the given range. */ | |
542 | for (devino = msi_start; devino < msi_end; devino++) { | |
543 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
544 | bucket = &ivector_table[sysino]; | |
545 | if (!bucket->virt_irq) | |
546 | break; | |
547 | } | |
548 | if (devino >= msi_end) | |
549 | return 0; | |
550 | ||
551 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
552 | bucket = &ivector_table[sysino]; | |
553 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
554 | *virt_irq_p = bucket->virt_irq; | |
555 | set_irq_chip(bucket->virt_irq, &sun4v_msi); | |
556 | ||
557 | data = get_irq_chip_data(bucket->virt_irq); | |
558 | if (unlikely(data)) | |
559 | return devino; | |
560 | ||
561 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); | |
562 | if (unlikely(!data)) { | |
563 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
564 | prom_halt(); | |
565 | } | |
566 | set_irq_chip_data(bucket->virt_irq, data); | |
567 | ||
568 | data->imap = ~0UL; | |
569 | data->iclr = ~0UL; | |
570 | ||
571 | return devino; | |
572 | } | |
573 | ||
574 | void sun4v_destroy_msi(unsigned int virt_irq) | |
575 | { | |
576 | virt_irq_free(virt_irq); | |
577 | } | |
578 | #endif | |
579 | ||
e18e2a00 DM |
580 | void ack_bad_irq(unsigned int virt_irq) |
581 | { | |
582 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
583 | unsigned int ino = 0xdeadbeef; | |
ab66a50e | 584 | |
e18e2a00 DM |
585 | if (bucket) |
586 | ino = bucket - &ivector_table[0]; | |
6a76267f | 587 | |
e18e2a00 DM |
588 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
589 | ino, virt_irq); | |
1da177e4 LT |
590 | } |
591 | ||
1da177e4 LT |
592 | void handler_irq(int irq, struct pt_regs *regs) |
593 | { | |
e18e2a00 | 594 | struct ino_bucket *bucket; |
6d24c8dc | 595 | struct pt_regs *old_regs; |
1da177e4 | 596 | |
1da177e4 | 597 | clear_softint(1 << irq); |
1da177e4 | 598 | |
6d24c8dc | 599 | old_regs = set_irq_regs(regs); |
1da177e4 | 600 | irq_enter(); |
1da177e4 LT |
601 | |
602 | /* Sliiiick... */ | |
e18e2a00 DM |
603 | bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0)); |
604 | while (bucket) { | |
605 | struct ino_bucket *next = __bucket(bucket->irq_chain); | |
1da177e4 | 606 | |
e18e2a00 | 607 | bucket->irq_chain = 0; |
6d24c8dc | 608 | __do_IRQ(bucket->virt_irq); |
fd0504c3 | 609 | |
e18e2a00 | 610 | bucket = next; |
1da177e4 | 611 | } |
e18e2a00 | 612 | |
1da177e4 | 613 | irq_exit(); |
6d24c8dc | 614 | set_irq_regs(old_regs); |
1da177e4 LT |
615 | } |
616 | ||
cdd5186f DM |
617 | struct sun5_timer { |
618 | u64 count0; | |
619 | u64 limit0; | |
620 | u64 count1; | |
621 | u64 limit1; | |
622 | }; | |
1da177e4 | 623 | |
cdd5186f | 624 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
625 | static u64 prom_limit0, prom_limit1; |
626 | ||
627 | static void map_prom_timers(void) | |
628 | { | |
25c7581b | 629 | struct device_node *dp; |
6a23acf3 | 630 | const unsigned int *addr; |
1da177e4 LT |
631 | |
632 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
633 | dp = of_find_node_by_path("/"); |
634 | dp = dp->child; | |
635 | while (dp) { | |
636 | if (!strcmp(dp->name, "counter-timer")) | |
637 | break; | |
638 | dp = dp->sibling; | |
639 | } | |
1da177e4 LT |
640 | |
641 | /* Assume if node is not present, PROM uses different tick mechanism | |
642 | * which we should not care about. | |
643 | */ | |
25c7581b | 644 | if (!dp) { |
1da177e4 LT |
645 | prom_timers = (struct sun5_timer *) 0; |
646 | return; | |
647 | } | |
648 | ||
649 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
650 | addr = of_get_property(dp, "address", NULL); |
651 | if (!addr) { | |
1da177e4 LT |
652 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
653 | prom_timers = (struct sun5_timer *) 0; | |
654 | return; | |
655 | } | |
656 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
657 | } | |
658 | ||
659 | static void kill_prom_timer(void) | |
660 | { | |
661 | if (!prom_timers) | |
662 | return; | |
663 | ||
664 | /* Save them away for later. */ | |
665 | prom_limit0 = prom_timers->limit0; | |
666 | prom_limit1 = prom_timers->limit1; | |
667 | ||
668 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
669 | * We turn both off here just to be paranoid. | |
670 | */ | |
671 | prom_timers->limit0 = 0; | |
672 | prom_timers->limit1 = 0; | |
673 | ||
674 | /* Wheee, eat the interrupt packet too... */ | |
675 | __asm__ __volatile__( | |
676 | " mov 0x40, %%g2\n" | |
677 | " ldxa [%%g0] %0, %%g1\n" | |
678 | " ldxa [%%g2] %1, %%g1\n" | |
679 | " stxa %%g0, [%%g0] %0\n" | |
680 | " membar #Sync\n" | |
681 | : /* no outputs */ | |
682 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
683 | : "g1", "g2"); | |
684 | } | |
685 | ||
1da177e4 LT |
686 | void init_irqwork_curcpu(void) |
687 | { | |
1da177e4 LT |
688 | int cpu = hard_smp_processor_id(); |
689 | ||
fd0504c3 | 690 | trap_block[cpu].irq_worklist = 0; |
1da177e4 LT |
691 | } |
692 | ||
b5a37e96 | 693 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type) |
ac29c11d | 694 | { |
94f8762d DM |
695 | unsigned long num_entries = 128; |
696 | unsigned long status; | |
697 | ||
698 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
699 | if (status != HV_EOK) { | |
700 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
701 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
702 | prom_halt(); |
703 | } | |
704 | } | |
705 | ||
b5a37e96 | 706 | static void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 707 | { |
b5a37e96 DM |
708 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
709 | ||
710 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO); | |
711 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO); | |
712 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR); | |
713 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR); | |
714 | } | |
715 | ||
716 | static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem) | |
717 | { | |
718 | void *page; | |
719 | ||
720 | if (use_bootmem) | |
721 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
722 | else | |
723 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
724 | ||
725 | if (!page) { | |
726 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); | |
727 | prom_halt(); | |
728 | } | |
729 | ||
730 | *pa_ptr = __pa(page); | |
731 | } | |
732 | ||
733 | static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem) | |
734 | { | |
735 | void *page; | |
736 | ||
737 | if (use_bootmem) | |
738 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
739 | else | |
740 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
5b0c0572 DM |
741 | |
742 | if (!page) { | |
743 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); | |
744 | prom_halt(); | |
745 | } | |
746 | ||
747 | *pa_ptr = __pa(page); | |
748 | } | |
749 | ||
b5a37e96 | 750 | static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem) |
1d2f1f90 DM |
751 | { |
752 | #ifdef CONFIG_SMP | |
b5a37e96 | 753 | void *page; |
1d2f1f90 DM |
754 | |
755 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
756 | ||
b5a37e96 DM |
757 | if (use_bootmem) |
758 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
759 | else | |
760 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
761 | ||
1d2f1f90 DM |
762 | if (!page) { |
763 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
764 | prom_halt(); | |
765 | } | |
766 | ||
767 | tb->cpu_mondo_block_pa = __pa(page); | |
768 | tb->cpu_list_pa = __pa(page + 64); | |
769 | #endif | |
770 | } | |
771 | ||
b5a37e96 | 772 | /* Allocate and register the mondo and error queues for this cpu. */ |
72aff53f | 773 | void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load) |
ac29c11d | 774 | { |
ac29c11d DM |
775 | struct trap_per_cpu *tb = &trap_block[cpu]; |
776 | ||
72aff53f DM |
777 | if (alloc) { |
778 | alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem); | |
779 | alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem); | |
780 | alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem); | |
781 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem); | |
782 | alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem); | |
783 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem); | |
1d2f1f90 | 784 | |
72aff53f DM |
785 | init_cpu_send_mondo_info(tb, use_bootmem); |
786 | } | |
1d2f1f90 | 787 | |
72aff53f DM |
788 | if (load) { |
789 | if (cpu != hard_smp_processor_id()) { | |
790 | prom_printf("SUN4V: init mondo on cpu %d not %d\n", | |
791 | cpu, hard_smp_processor_id()); | |
792 | prom_halt(); | |
793 | } | |
794 | sun4v_register_mondo_queues(cpu); | |
795 | } | |
ac29c11d DM |
796 | } |
797 | ||
e18e2a00 DM |
798 | static struct irqaction timer_irq_action = { |
799 | .name = "timer", | |
800 | }; | |
801 | ||
1da177e4 LT |
802 | /* Only invoked on boot processor. */ |
803 | void __init init_IRQ(void) | |
804 | { | |
805 | map_prom_timers(); | |
806 | kill_prom_timer(); | |
807 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
808 | ||
ac29c11d | 809 | if (tlb_type == hypervisor) |
72aff53f | 810 | sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1); |
ac29c11d | 811 | |
1da177e4 LT |
812 | /* We need to clear any IRQ's pending in the soft interrupt |
813 | * registers, a spurious one could be left around from the | |
814 | * PROM timer which we just disabled. | |
815 | */ | |
816 | clear_softint(get_softint()); | |
817 | ||
818 | /* Now that ivector table is initialized, it is safe | |
819 | * to receive IRQ vector traps. We will normally take | |
820 | * one or two right now, in case some device PROM used | |
821 | * to boot us wants to speak to us. We just ignore them. | |
822 | */ | |
823 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
824 | "or %%g1, %0, %%g1\n\t" | |
825 | "wrpr %%g1, 0x0, %%pstate" | |
826 | : /* No outputs */ | |
827 | : "i" (PSTATE_IE) | |
828 | : "g1"); | |
1da177e4 | 829 | |
e18e2a00 | 830 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 831 | } |