Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $ |
2 | * irq.c: UltraSparc IRQ handling/init/registry. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/ptrace.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/signal.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/random.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/proc_fs.h> | |
23 | #include <linux/seq_file.h> | |
b5a37e96 | 24 | #include <linux/bootmem.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/irq.h> | |
2e457ef6 | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include <asm/sbus.h> |
33 | #include <asm/iommu.h> | |
34 | #include <asm/upa.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/timer.h> | |
37 | #include <asm/smp.h> | |
38 | #include <asm/starfire.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/cache.h> | |
41 | #include <asm/cpudata.h> | |
63b61452 | 42 | #include <asm/auxio.h> |
92704a1c | 43 | #include <asm/head.h> |
1da177e4 LT |
44 | |
45 | #ifdef CONFIG_SMP | |
46 | static void distribute_irqs(void); | |
47 | #endif | |
48 | ||
49 | /* UPA nodes send interrupt packet to UltraSparc with first data reg | |
50 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
51 | * delivered. We must translate this into a non-vector IRQ so we can | |
52 | * set the softint on this cpu. | |
53 | * | |
54 | * To make processing these packets efficient and race free we use | |
55 | * an array of irq buckets below. The interrupt vector handler in | |
56 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
57 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
58 | * code uses CAS to get an atomic snapshot of the list and clear it | |
59 | * at the same time. | |
60 | */ | |
61 | ||
62 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); | |
63 | ||
64 | /* This has to be in the main kernel image, it cannot be | |
65 | * turned into per-cpu data. The reason is that the main | |
66 | * kernel image is locked into the TLB and this structure | |
67 | * is accessed from the vectored interrupt trap handler. If | |
68 | * access to this structure takes a TLB miss it could cause | |
69 | * the 5-level sparc v9 trap stack to overflow. | |
70 | */ | |
71 | struct irq_work_struct { | |
72 | unsigned int irq_worklists[16]; | |
73 | }; | |
74 | struct irq_work_struct __irq_work[NR_CPUS]; | |
75 | #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)]) | |
76 | ||
088dd1f8 | 77 | static struct irqaction *irq_action[NR_IRQS+1]; |
1da177e4 LT |
78 | |
79 | /* This only synchronizes entities which modify IRQ handler | |
80 | * state and some selected user-level spots that want to | |
81 | * read things in the table. IRQ handler processing orders | |
82 | * its' accesses such that no locking is needed. | |
83 | */ | |
84 | static DEFINE_SPINLOCK(irq_action_lock); | |
85 | ||
86 | static void register_irq_proc (unsigned int irq); | |
87 | ||
88 | /* | |
89 | * Upper 2b of irqaction->flags holds the ino. | |
90 | * irqaction->mask holds the smp affinity information. | |
91 | */ | |
92 | #define put_ino_in_irqaction(action, irq) \ | |
93 | action->flags &= 0xffffffffffffUL; \ | |
94 | if (__bucket(irq) == &pil0_dummy_bucket) \ | |
95 | action->flags |= 0xdeadUL << 48; \ | |
96 | else \ | |
97 | action->flags |= __irq_ino(irq) << 48; | |
98 | #define get_ino_in_irqaction(action) (action->flags >> 48) | |
99 | ||
100 | #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff) | |
101 | #define get_smpaff_in_irqaction(action) ((action)->mask) | |
102 | ||
103 | int show_interrupts(struct seq_file *p, void *v) | |
104 | { | |
105 | unsigned long flags; | |
106 | int i = *(loff_t *) v; | |
107 | struct irqaction *action; | |
108 | #ifdef CONFIG_SMP | |
109 | int j; | |
110 | #endif | |
111 | ||
112 | spin_lock_irqsave(&irq_action_lock, flags); | |
113 | if (i <= NR_IRQS) { | |
114 | if (!(action = *(i + irq_action))) | |
115 | goto out_unlock; | |
116 | seq_printf(p, "%3d: ", i); | |
117 | #ifndef CONFIG_SMP | |
118 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
119 | #else | |
120 | for (j = 0; j < NR_CPUS; j++) { | |
121 | if (!cpu_online(j)) | |
122 | continue; | |
123 | seq_printf(p, "%10u ", | |
124 | kstat_cpu(j).irqs[i]); | |
125 | } | |
126 | #endif | |
127 | seq_printf(p, " %s:%lx", action->name, | |
128 | get_ino_in_irqaction(action)); | |
129 | for (action = action->next; action; action = action->next) { | |
130 | seq_printf(p, ", %s:%lx", action->name, | |
131 | get_ino_in_irqaction(action)); | |
132 | } | |
133 | seq_putc(p, '\n'); | |
134 | } | |
135 | out_unlock: | |
136 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | /* Now these are always passed a true fully specified sun4u INO. */ | |
142 | void enable_irq(unsigned int irq) | |
143 | { | |
144 | struct ino_bucket *bucket = __bucket(irq); | |
145 | unsigned long imap; | |
146 | unsigned long tid; | |
147 | ||
148 | imap = bucket->imap; | |
149 | if (imap == 0UL) | |
150 | return; | |
151 | ||
152 | preempt_disable(); | |
153 | ||
d82ace7d | 154 | if (tlb_type == hypervisor) { |
4bf447d6 | 155 | unsigned int ino = __irq_ino(irq); |
10951ee6 | 156 | int cpu = hard_smp_processor_id(); |
c4bea288 | 157 | int err; |
10951ee6 | 158 | |
c4bea288 DM |
159 | err = sun4v_intr_settarget(ino, cpu); |
160 | if (err != HV_EOK) | |
161 | printk("sun4v_intr_settarget(%x,%d): err(%d)\n", | |
162 | ino, cpu, err); | |
abd92b2d | 163 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); |
c4bea288 DM |
164 | if (err != HV_EOK) |
165 | printk("sun4v_intr_setenabled(%x): err(%d)\n", | |
166 | ino, err); | |
d82ace7d DM |
167 | } else { |
168 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
169 | unsigned long ver; | |
170 | ||
171 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
172 | if ((ver >> 32) == __JALAPENO_ID || | |
173 | (ver >> 32) == __SERRANO_ID) { | |
174 | /* We set it to our JBUS ID. */ | |
175 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
176 | : "=r" (tid) | |
177 | : "i" (ASI_JBUS_CONFIG)); | |
178 | tid = ((tid & (0x1fUL<<17)) << 9); | |
179 | tid &= IMAP_TID_JBUS; | |
180 | } else { | |
181 | /* We set it to our Safari AID. */ | |
182 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
183 | : "=r" (tid) | |
184 | : "i"(ASI_SAFARI_CONFIG)); | |
185 | tid = ((tid & (0x3ffUL<<17)) << 9); | |
186 | tid &= IMAP_AID_SAFARI; | |
187 | } | |
188 | } else if (this_is_starfire == 0) { | |
189 | /* We set it to our UPA MID. */ | |
1da177e4 LT |
190 | __asm__ __volatile__("ldxa [%%g0] %1, %0" |
191 | : "=r" (tid) | |
d82ace7d DM |
192 | : "i" (ASI_UPA_CONFIG)); |
193 | tid = ((tid & UPA_CONFIG_MID) << 9); | |
194 | tid &= IMAP_TID_UPA; | |
1da177e4 | 195 | } else { |
d82ace7d DM |
196 | tid = (starfire_translate(imap, |
197 | smp_processor_id()) << 26); | |
198 | tid &= IMAP_TID_UPA; | |
1da177e4 | 199 | } |
1da177e4 | 200 | |
d82ace7d DM |
201 | /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product |
202 | * of this SYSIO's preconfigured IGN in the SYSIO Control | |
203 | * Register, the hardware just mirrors that value here. | |
204 | * However for Graphics and UPA Slave devices the full | |
205 | * IMAP_INR field can be set by the programmer here. | |
206 | * | |
207 | * Things like FFB can now be handled via the new IRQ | |
208 | * mechanism. | |
209 | */ | |
210 | upa_writel(tid | IMAP_VALID, imap); | |
211 | } | |
1da177e4 LT |
212 | |
213 | preempt_enable(); | |
214 | } | |
215 | ||
216 | /* This now gets passed true ino's as well. */ | |
217 | void disable_irq(unsigned int irq) | |
218 | { | |
219 | struct ino_bucket *bucket = __bucket(irq); | |
220 | unsigned long imap; | |
221 | ||
222 | imap = bucket->imap; | |
223 | if (imap != 0UL) { | |
10951ee6 | 224 | if (tlb_type == hypervisor) { |
4bf447d6 | 225 | unsigned int ino = __irq_ino(irq); |
c4bea288 | 226 | int err; |
4bf447d6 | 227 | |
c4bea288 DM |
228 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
229 | if (err != HV_EOK) | |
230 | printk("sun4v_intr_setenabled(%x): " | |
231 | "err(%d)\n", ino, err); | |
10951ee6 DM |
232 | } else { |
233 | u32 tmp; | |
1da177e4 | 234 | |
10951ee6 DM |
235 | /* NOTE: We do not want to futz with the IRQ clear registers |
236 | * and move the state to IDLE, the SCSI code does call | |
237 | * disable_irq() to assure atomicity in the queue cmd | |
238 | * SCSI adapter driver code. Thus we'd lose interrupts. | |
239 | */ | |
240 | tmp = upa_readl(imap); | |
241 | tmp &= ~IMAP_VALID; | |
242 | upa_writel(tmp, imap); | |
243 | } | |
1da177e4 LT |
244 | } |
245 | } | |
246 | ||
247 | /* The timer is the one "weird" interrupt which is generated by | |
248 | * the CPU %tick register and not by some normal vectored interrupt | |
249 | * source. To handle this special case, we use this dummy INO bucket. | |
250 | */ | |
088dd1f8 | 251 | static struct irq_desc pil0_dummy_desc; |
1da177e4 | 252 | static struct ino_bucket pil0_dummy_bucket = { |
088dd1f8 | 253 | .irq_info = &pil0_dummy_desc, |
1da177e4 LT |
254 | }; |
255 | ||
088dd1f8 DM |
256 | static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup, |
257 | unsigned long iclr, unsigned long imap, | |
258 | struct ino_bucket *bucket) | |
259 | { | |
260 | prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> " | |
261 | "(%d:%d:%016lx:%016lx), halting...\n", | |
262 | ino, bucket->pil, bucket->iclr, bucket->imap, | |
263 | pil, inofixup, iclr, imap); | |
264 | prom_halt(); | |
265 | } | |
266 | ||
1da177e4 LT |
267 | unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap) |
268 | { | |
269 | struct ino_bucket *bucket; | |
270 | int ino; | |
271 | ||
272 | if (pil == 0) { | |
273 | if (iclr != 0UL || imap != 0UL) { | |
274 | prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n", | |
275 | iclr, imap); | |
276 | prom_halt(); | |
277 | } | |
278 | return __irq(&pil0_dummy_bucket); | |
279 | } | |
280 | ||
10951ee6 DM |
281 | BUG_ON(tlb_type == hypervisor); |
282 | ||
1da177e4 LT |
283 | /* RULE: Both must be specified in all other cases. */ |
284 | if (iclr == 0UL || imap == 0UL) { | |
285 | prom_printf("Invalid build_irq %d %d %016lx %016lx\n", | |
286 | pil, inofixup, iclr, imap); | |
287 | prom_halt(); | |
288 | } | |
289 | ||
290 | ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; | |
291 | if (ino > NUM_IVECS) { | |
292 | prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n", | |
293 | ino, pil, inofixup, iclr, imap); | |
294 | prom_halt(); | |
295 | } | |
296 | ||
1da177e4 | 297 | bucket = &ivector_table[ino]; |
088dd1f8 DM |
298 | if (bucket->flags & IBF_ACTIVE) |
299 | build_irq_error("IRQ: Trying to build active INO bucket.\n", | |
300 | ino, pil, inofixup, iclr, imap, bucket); | |
301 | ||
302 | if (bucket->irq_info) { | |
303 | if (bucket->imap != imap || bucket->iclr != iclr) | |
304 | build_irq_error("IRQ: Trying to reinit INO bucket.\n", | |
305 | ino, pil, inofixup, iclr, imap, bucket); | |
306 | ||
307 | goto out; | |
308 | } | |
309 | ||
310 | bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC); | |
311 | if (!bucket->irq_info) { | |
312 | prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n"); | |
1da177e4 LT |
313 | prom_halt(); |
314 | } | |
088dd1f8 DM |
315 | memset(bucket->irq_info, 0, sizeof(struct irq_desc)); |
316 | ||
317 | /* Ok, looks good, set it up. Don't touch the irq_chain or | |
318 | * the pending flag. | |
319 | */ | |
1da177e4 LT |
320 | bucket->imap = imap; |
321 | bucket->iclr = iclr; | |
322 | bucket->pil = pil; | |
323 | bucket->flags = 0; | |
324 | ||
088dd1f8 | 325 | out: |
1da177e4 LT |
326 | return __irq(bucket); |
327 | } | |
328 | ||
e3999574 DM |
329 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags) |
330 | { | |
331 | struct ino_bucket *bucket; | |
332 | unsigned long sysino; | |
333 | ||
334 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
335 | ||
e3999574 DM |
336 | bucket = &ivector_table[sysino]; |
337 | ||
338 | /* Catch accidental accesses to these things. IMAP/ICLR handling | |
339 | * is done by hypervisor calls on sun4v platforms, not by direct | |
340 | * register accesses. | |
341 | */ | |
342 | bucket->imap = ~0UL; | |
343 | bucket->iclr = ~0UL; | |
344 | ||
345 | bucket->pil = pil; | |
346 | bucket->flags = flags; | |
347 | ||
348 | bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC); | |
349 | if (!bucket->irq_info) { | |
350 | prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n"); | |
351 | prom_halt(); | |
352 | } | |
353 | memset(bucket->irq_info, 0, sizeof(struct irq_desc)); | |
354 | ||
355 | return __irq(bucket); | |
356 | } | |
357 | ||
1da177e4 LT |
358 | static void atomic_bucket_insert(struct ino_bucket *bucket) |
359 | { | |
360 | unsigned long pstate; | |
361 | unsigned int *ent; | |
362 | ||
363 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
364 | __asm__ __volatile__("wrpr %0, %1, %%pstate" | |
365 | : : "r" (pstate), "i" (PSTATE_IE)); | |
366 | ent = irq_work(smp_processor_id(), bucket->pil); | |
367 | bucket->irq_chain = *ent; | |
368 | *ent = __irq(bucket); | |
369 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate)); | |
370 | } | |
371 | ||
088dd1f8 DM |
372 | static int check_irq_sharing(int pil, unsigned long irqflags) |
373 | { | |
374 | struct irqaction *action, *tmp; | |
375 | ||
376 | action = *(irq_action + pil); | |
377 | if (action) { | |
378 | if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) { | |
379 | for (tmp = action; tmp->next; tmp = tmp->next) | |
380 | ; | |
381 | } else { | |
382 | return -EBUSY; | |
383 | } | |
384 | } | |
385 | return 0; | |
386 | } | |
387 | ||
388 | static void append_irq_action(int pil, struct irqaction *action) | |
389 | { | |
390 | struct irqaction **pp = irq_action + pil; | |
391 | ||
392 | while (*pp) | |
393 | pp = &((*pp)->next); | |
394 | *pp = action; | |
395 | } | |
396 | ||
397 | static struct irqaction *get_action_slot(struct ino_bucket *bucket) | |
398 | { | |
399 | struct irq_desc *desc = bucket->irq_info; | |
400 | int max_irq, i; | |
401 | ||
402 | max_irq = 1; | |
403 | if (bucket->flags & IBF_PCI) | |
404 | max_irq = MAX_IRQ_DESC_ACTION; | |
405 | for (i = 0; i < max_irq; i++) { | |
406 | struct irqaction *p = &desc->action[i]; | |
407 | u32 mask = (1 << i); | |
408 | ||
409 | if (desc->action_active_mask & mask) | |
410 | continue; | |
411 | ||
412 | desc->action_active_mask |= mask; | |
413 | return p; | |
414 | } | |
415 | return NULL; | |
416 | } | |
417 | ||
1da177e4 LT |
418 | int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), |
419 | unsigned long irqflags, const char *name, void *dev_id) | |
420 | { | |
088dd1f8 | 421 | struct irqaction *action; |
1da177e4 LT |
422 | struct ino_bucket *bucket = __bucket(irq); |
423 | unsigned long flags; | |
424 | int pending = 0; | |
425 | ||
088dd1f8 | 426 | if (unlikely(!handler)) |
1da177e4 | 427 | return -EINVAL; |
088dd1f8 DM |
428 | |
429 | if (unlikely(!bucket->irq_info)) | |
430 | return -ENODEV; | |
1da177e4 LT |
431 | |
432 | if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) { | |
433 | /* | |
434 | * This function might sleep, we want to call it first, | |
435 | * outside of the atomic block. In SA_STATIC_ALLOC case, | |
436 | * random driver's kmalloc will fail, but it is safe. | |
437 | * If already initialized, random driver will not reinit. | |
438 | * Yes, this might clear the entropy pool if the wrong | |
439 | * driver is attempted to be loaded, without actually | |
440 | * installing a new handler, but is this really a problem, | |
441 | * only the sysadmin is able to do this. | |
442 | */ | |
443 | rand_initialize_irq(irq); | |
444 | } | |
445 | ||
446 | spin_lock_irqsave(&irq_action_lock, flags); | |
447 | ||
088dd1f8 DM |
448 | if (check_irq_sharing(bucket->pil, irqflags)) { |
449 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
450 | return -EBUSY; | |
1da177e4 LT |
451 | } |
452 | ||
088dd1f8 | 453 | action = get_action_slot(bucket); |
1da177e4 LT |
454 | if (!action) { |
455 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
456 | return -ENOMEM; | |
457 | } | |
458 | ||
088dd1f8 DM |
459 | bucket->flags |= IBF_ACTIVE; |
460 | pending = 0; | |
461 | if (bucket != &pil0_dummy_bucket) { | |
1da177e4 LT |
462 | pending = bucket->pending; |
463 | if (pending) | |
464 | bucket->pending = 0; | |
465 | } | |
466 | ||
467 | action->handler = handler; | |
468 | action->flags = irqflags; | |
469 | action->name = name; | |
470 | action->next = NULL; | |
471 | action->dev_id = dev_id; | |
472 | put_ino_in_irqaction(action, irq); | |
473 | put_smpaff_in_irqaction(action, CPU_MASK_NONE); | |
474 | ||
088dd1f8 | 475 | append_irq_action(bucket->pil, action); |
1da177e4 LT |
476 | |
477 | enable_irq(irq); | |
478 | ||
479 | /* We ate the IVEC already, this makes sure it does not get lost. */ | |
480 | if (pending) { | |
481 | atomic_bucket_insert(bucket); | |
482 | set_softint(1 << bucket->pil); | |
483 | } | |
088dd1f8 | 484 | |
1da177e4 | 485 | spin_unlock_irqrestore(&irq_action_lock, flags); |
088dd1f8 DM |
486 | |
487 | if (bucket != &pil0_dummy_bucket) | |
1da177e4 LT |
488 | register_irq_proc(__irq_ino(irq)); |
489 | ||
490 | #ifdef CONFIG_SMP | |
491 | distribute_irqs(); | |
492 | #endif | |
493 | return 0; | |
1da177e4 LT |
494 | } |
495 | ||
496 | EXPORT_SYMBOL(request_irq); | |
497 | ||
088dd1f8 | 498 | static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id) |
1da177e4 | 499 | { |
088dd1f8 DM |
500 | struct ino_bucket *bucket = __bucket(irq); |
501 | struct irqaction *action, **pp; | |
1da177e4 | 502 | |
088dd1f8 DM |
503 | pp = irq_action + bucket->pil; |
504 | action = *pp; | |
505 | if (unlikely(!action)) | |
506 | return NULL; | |
1da177e4 | 507 | |
088dd1f8 | 508 | if (unlikely(!action->handler)) { |
1da177e4 | 509 | printk("Freeing free IRQ %d\n", bucket->pil); |
088dd1f8 | 510 | return NULL; |
1da177e4 LT |
511 | } |
512 | ||
088dd1f8 DM |
513 | while (action && action->dev_id != dev_id) { |
514 | pp = &action->next; | |
515 | action = *pp; | |
1da177e4 LT |
516 | } |
517 | ||
088dd1f8 DM |
518 | if (likely(action)) |
519 | *pp = action->next; | |
520 | ||
521 | return action; | |
522 | } | |
523 | ||
524 | void free_irq(unsigned int irq, void *dev_id) | |
525 | { | |
526 | struct irqaction *action; | |
527 | struct ino_bucket *bucket; | |
528 | unsigned long flags; | |
529 | ||
530 | spin_lock_irqsave(&irq_action_lock, flags); | |
531 | ||
532 | action = unlink_irq_action(irq, dev_id); | |
1da177e4 LT |
533 | |
534 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
535 | ||
088dd1f8 DM |
536 | if (unlikely(!action)) |
537 | return; | |
538 | ||
1da177e4 LT |
539 | synchronize_irq(irq); |
540 | ||
541 | spin_lock_irqsave(&irq_action_lock, flags); | |
542 | ||
088dd1f8 | 543 | bucket = __bucket(irq); |
1da177e4 | 544 | if (bucket != &pil0_dummy_bucket) { |
088dd1f8 | 545 | struct irq_desc *desc = bucket->irq_info; |
1da177e4 | 546 | unsigned long imap = bucket->imap; |
088dd1f8 | 547 | int ent, i; |
1da177e4 | 548 | |
088dd1f8 DM |
549 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { |
550 | struct irqaction *p = &desc->action[i]; | |
551 | ||
552 | if (p == action) { | |
553 | desc->action_active_mask &= ~(1 << i); | |
554 | break; | |
1da177e4 | 555 | } |
1da177e4 LT |
556 | } |
557 | ||
088dd1f8 DM |
558 | if (!desc->action_active_mask) { |
559 | /* This unique interrupt source is now inactive. */ | |
560 | bucket->flags &= ~IBF_ACTIVE; | |
1da177e4 | 561 | |
088dd1f8 DM |
562 | /* See if any other buckets share this bucket's IMAP |
563 | * and are still active. | |
564 | */ | |
565 | for (ent = 0; ent < NUM_IVECS; ent++) { | |
566 | struct ino_bucket *bp = &ivector_table[ent]; | |
567 | if (bp != bucket && | |
568 | bp->imap == imap && | |
569 | (bp->flags & IBF_ACTIVE) != 0) | |
570 | break; | |
571 | } | |
1da177e4 | 572 | |
088dd1f8 DM |
573 | /* Only disable when no other sub-irq levels of |
574 | * the same IMAP are active. | |
575 | */ | |
576 | if (ent == NUM_IVECS) | |
577 | disable_irq(irq); | |
578 | } | |
1da177e4 LT |
579 | } |
580 | ||
1da177e4 LT |
581 | spin_unlock_irqrestore(&irq_action_lock, flags); |
582 | } | |
583 | ||
584 | EXPORT_SYMBOL(free_irq); | |
585 | ||
586 | #ifdef CONFIG_SMP | |
587 | void synchronize_irq(unsigned int irq) | |
588 | { | |
589 | struct ino_bucket *bucket = __bucket(irq); | |
590 | ||
591 | #if 0 | |
592 | /* The following is how I wish I could implement this. | |
593 | * Unfortunately the ICLR registers are read-only, you can | |
594 | * only write ICLR_foo values to them. To get the current | |
595 | * IRQ status you would need to get at the IRQ diag registers | |
596 | * in the PCI/SBUS controller and the layout of those vary | |
597 | * from one controller to the next, sigh... -DaveM | |
598 | */ | |
599 | unsigned long iclr = bucket->iclr; | |
600 | ||
601 | while (1) { | |
602 | u32 tmp = upa_readl(iclr); | |
603 | ||
604 | if (tmp == ICLR_TRANSMIT || | |
605 | tmp == ICLR_PENDING) { | |
606 | cpu_relax(); | |
607 | continue; | |
608 | } | |
609 | break; | |
610 | } | |
611 | #else | |
612 | /* So we have to do this with a INPROGRESS bit just like x86. */ | |
613 | while (bucket->flags & IBF_INPROGRESS) | |
614 | cpu_relax(); | |
615 | #endif | |
616 | } | |
617 | #endif /* CONFIG_SMP */ | |
618 | ||
088dd1f8 | 619 | static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs) |
1da177e4 | 620 | { |
088dd1f8 DM |
621 | struct irq_desc *desc = bp->irq_info; |
622 | unsigned char flags = bp->flags; | |
623 | u32 action_mask, i; | |
624 | int random; | |
1da177e4 | 625 | |
088dd1f8 | 626 | bp->flags |= IBF_INPROGRESS; |
1da177e4 | 627 | |
088dd1f8 DM |
628 | if (unlikely(!(flags & IBF_ACTIVE))) { |
629 | bp->pending = 1; | |
1da177e4 | 630 | goto out; |
1da177e4 LT |
631 | } |
632 | ||
088dd1f8 DM |
633 | if (desc->pre_handler) |
634 | desc->pre_handler(bp, | |
635 | desc->pre_handler_arg1, | |
636 | desc->pre_handler_arg2); | |
1da177e4 | 637 | |
088dd1f8 DM |
638 | action_mask = desc->action_active_mask; |
639 | random = 0; | |
640 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { | |
641 | struct irqaction *p = &desc->action[i]; | |
642 | u32 mask = (1 << i); | |
1da177e4 | 643 | |
088dd1f8 DM |
644 | if (!(action_mask & mask)) |
645 | continue; | |
1da177e4 | 646 | |
088dd1f8 | 647 | action_mask &= ~mask; |
1da177e4 | 648 | |
088dd1f8 DM |
649 | if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED) |
650 | random |= p->flags; | |
651 | ||
652 | if (!action_mask) | |
653 | break; | |
654 | } | |
655 | if (bp->pil != 0) { | |
10951ee6 | 656 | if (tlb_type == hypervisor) { |
4bf447d6 | 657 | unsigned int ino = __irq_ino(bp); |
c4bea288 | 658 | int err; |
10951ee6 | 659 | |
c4bea288 DM |
660 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
661 | if (err != HV_EOK) | |
662 | printk("sun4v_intr_setstate(%x): " | |
663 | "err(%d)\n", ino, err); | |
10951ee6 DM |
664 | } else { |
665 | upa_writel(ICLR_IDLE, bp->iclr); | |
666 | /* Test and add entropy */ | |
667 | if (random & SA_SAMPLE_RANDOM) | |
668 | add_interrupt_randomness(irq); | |
669 | } | |
088dd1f8 | 670 | } |
1da177e4 | 671 | out: |
088dd1f8 | 672 | bp->flags &= ~IBF_INPROGRESS; |
1da177e4 LT |
673 | } |
674 | ||
1da177e4 LT |
675 | void handler_irq(int irq, struct pt_regs *regs) |
676 | { | |
088dd1f8 | 677 | struct ino_bucket *bp; |
1da177e4 LT |
678 | int cpu = smp_processor_id(); |
679 | ||
680 | #ifndef CONFIG_SMP | |
681 | /* | |
682 | * Check for TICK_INT on level 14 softint. | |
683 | */ | |
684 | { | |
685 | unsigned long clr_mask = 1 << irq; | |
686 | unsigned long tick_mask = tick_ops->softint_mask; | |
687 | ||
688 | if ((irq == 14) && (get_softint() & tick_mask)) { | |
689 | irq = 0; | |
690 | clr_mask = tick_mask; | |
691 | } | |
692 | clear_softint(clr_mask); | |
693 | } | |
694 | #else | |
1da177e4 LT |
695 | clear_softint(1 << irq); |
696 | #endif | |
697 | ||
698 | irq_enter(); | |
699 | kstat_this_cpu.irqs[irq]++; | |
700 | ||
701 | /* Sliiiick... */ | |
702 | #ifndef CONFIG_SMP | |
703 | bp = ((irq != 0) ? | |
704 | __bucket(xchg32(irq_work(cpu, irq), 0)) : | |
705 | &pil0_dummy_bucket); | |
706 | #else | |
707 | bp = __bucket(xchg32(irq_work(cpu, irq), 0)); | |
708 | #endif | |
088dd1f8 DM |
709 | while (bp) { |
710 | struct ino_bucket *nbp = __bucket(bp->irq_chain); | |
1da177e4 | 711 | |
1da177e4 | 712 | bp->irq_chain = 0; |
088dd1f8 DM |
713 | process_bucket(irq, bp, regs); |
714 | bp = nbp; | |
1da177e4 LT |
715 | } |
716 | irq_exit(); | |
717 | } | |
718 | ||
719 | #ifdef CONFIG_BLK_DEV_FD | |
63b61452 | 720 | extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);; |
1da177e4 | 721 | |
63b61452 DM |
722 | /* XXX No easy way to include asm/floppy.h XXX */ |
723 | extern unsigned char *pdma_vaddr; | |
724 | extern unsigned long pdma_size; | |
725 | extern volatile int doing_pdma; | |
726 | extern unsigned long fdc_status; | |
1da177e4 | 727 | |
63b61452 | 728 | irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs) |
1da177e4 | 729 | { |
63b61452 DM |
730 | if (likely(doing_pdma)) { |
731 | void __iomem *stat = (void __iomem *) fdc_status; | |
732 | unsigned char *vaddr = pdma_vaddr; | |
733 | unsigned long size = pdma_size; | |
734 | u8 val; | |
735 | ||
736 | while (size) { | |
737 | val = readb(stat); | |
738 | if (unlikely(!(val & 0x80))) { | |
739 | pdma_vaddr = vaddr; | |
740 | pdma_size = size; | |
741 | return IRQ_HANDLED; | |
742 | } | |
743 | if (unlikely(!(val & 0x20))) { | |
744 | pdma_vaddr = vaddr; | |
745 | pdma_size = size; | |
746 | doing_pdma = 0; | |
747 | goto main_interrupt; | |
748 | } | |
749 | if (val & 0x40) { | |
750 | /* read */ | |
751 | *vaddr++ = readb(stat + 1); | |
752 | } else { | |
753 | unsigned char data = *vaddr++; | |
1da177e4 | 754 | |
63b61452 DM |
755 | /* write */ |
756 | writeb(data, stat + 1); | |
757 | } | |
758 | size--; | |
759 | } | |
1da177e4 | 760 | |
63b61452 DM |
761 | pdma_vaddr = vaddr; |
762 | pdma_size = size; | |
1da177e4 | 763 | |
63b61452 DM |
764 | /* Send Terminal Count pulse to floppy controller. */ |
765 | val = readb(auxio_register); | |
766 | val |= AUXIO_AUX1_FTCNT; | |
767 | writeb(val, auxio_register); | |
94bbc176 | 768 | val &= ~AUXIO_AUX1_FTCNT; |
63b61452 | 769 | writeb(val, auxio_register); |
1da177e4 | 770 | |
63b61452 | 771 | doing_pdma = 0; |
1da177e4 | 772 | } |
1da177e4 | 773 | |
63b61452 DM |
774 | main_interrupt: |
775 | return floppy_interrupt(irq, dev_cookie, regs); | |
1da177e4 | 776 | } |
63b61452 DM |
777 | EXPORT_SYMBOL(sparc_floppy_irq); |
778 | #endif | |
1da177e4 LT |
779 | |
780 | /* We really don't need these at all on the Sparc. We only have | |
781 | * stubs here because they are exported to modules. | |
782 | */ | |
783 | unsigned long probe_irq_on(void) | |
784 | { | |
785 | return 0; | |
786 | } | |
787 | ||
788 | EXPORT_SYMBOL(probe_irq_on); | |
789 | ||
790 | int probe_irq_off(unsigned long mask) | |
791 | { | |
792 | return 0; | |
793 | } | |
794 | ||
795 | EXPORT_SYMBOL(probe_irq_off); | |
796 | ||
797 | #ifdef CONFIG_SMP | |
798 | static int retarget_one_irq(struct irqaction *p, int goal_cpu) | |
799 | { | |
800 | struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table; | |
801 | unsigned long imap = bucket->imap; | |
1da177e4 LT |
802 | |
803 | while (!cpu_online(goal_cpu)) { | |
804 | if (++goal_cpu >= NR_CPUS) | |
805 | goal_cpu = 0; | |
806 | } | |
807 | ||
10951ee6 | 808 | if (tlb_type == hypervisor) { |
4bf447d6 | 809 | unsigned int ino = __irq_ino(bucket); |
10951ee6 | 810 | |
4bf447d6 DM |
811 | sun4v_intr_settarget(ino, goal_cpu); |
812 | sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
1da177e4 | 813 | } else { |
10951ee6 DM |
814 | unsigned int tid; |
815 | ||
816 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
817 | tid = goal_cpu << 26; | |
818 | tid &= IMAP_AID_SAFARI; | |
819 | } else if (this_is_starfire == 0) { | |
820 | tid = goal_cpu << 26; | |
821 | tid &= IMAP_TID_UPA; | |
822 | } else { | |
823 | tid = (starfire_translate(imap, goal_cpu) << 26); | |
824 | tid &= IMAP_TID_UPA; | |
825 | } | |
826 | upa_writel(tid | IMAP_VALID, imap); | |
1da177e4 | 827 | } |
1da177e4 | 828 | |
cee2824f | 829 | do { |
1da177e4 LT |
830 | if (++goal_cpu >= NR_CPUS) |
831 | goal_cpu = 0; | |
cee2824f | 832 | } while (!cpu_online(goal_cpu)); |
1da177e4 LT |
833 | |
834 | return goal_cpu; | |
835 | } | |
836 | ||
837 | /* Called from request_irq. */ | |
838 | static void distribute_irqs(void) | |
839 | { | |
840 | unsigned long flags; | |
841 | int cpu, level; | |
842 | ||
843 | spin_lock_irqsave(&irq_action_lock, flags); | |
844 | cpu = 0; | |
845 | ||
846 | /* | |
847 | * Skip the timer at [0], and very rare error/power intrs at [15]. | |
848 | * Also level [12], it causes problems on Ex000 systems. | |
849 | */ | |
850 | for (level = 1; level < NR_IRQS; level++) { | |
851 | struct irqaction *p = irq_action[level]; | |
088dd1f8 DM |
852 | |
853 | if (level == 12) | |
854 | continue; | |
855 | ||
1da177e4 LT |
856 | while(p) { |
857 | cpu = retarget_one_irq(p, cpu); | |
858 | p = p->next; | |
859 | } | |
860 | } | |
861 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
862 | } | |
863 | #endif | |
864 | ||
cdd5186f DM |
865 | struct sun5_timer { |
866 | u64 count0; | |
867 | u64 limit0; | |
868 | u64 count1; | |
869 | u64 limit1; | |
870 | }; | |
1da177e4 | 871 | |
cdd5186f | 872 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
873 | static u64 prom_limit0, prom_limit1; |
874 | ||
875 | static void map_prom_timers(void) | |
876 | { | |
877 | unsigned int addr[3]; | |
878 | int tnode, err; | |
879 | ||
880 | /* PROM timer node hangs out in the top level of device siblings... */ | |
881 | tnode = prom_finddevice("/counter-timer"); | |
882 | ||
883 | /* Assume if node is not present, PROM uses different tick mechanism | |
884 | * which we should not care about. | |
885 | */ | |
886 | if (tnode == 0 || tnode == -1) { | |
887 | prom_timers = (struct sun5_timer *) 0; | |
888 | return; | |
889 | } | |
890 | ||
891 | /* If PROM is really using this, it must be mapped by him. */ | |
892 | err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr)); | |
893 | if (err == -1) { | |
894 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); | |
895 | prom_timers = (struct sun5_timer *) 0; | |
896 | return; | |
897 | } | |
898 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
899 | } | |
900 | ||
901 | static void kill_prom_timer(void) | |
902 | { | |
903 | if (!prom_timers) | |
904 | return; | |
905 | ||
906 | /* Save them away for later. */ | |
907 | prom_limit0 = prom_timers->limit0; | |
908 | prom_limit1 = prom_timers->limit1; | |
909 | ||
910 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
911 | * We turn both off here just to be paranoid. | |
912 | */ | |
913 | prom_timers->limit0 = 0; | |
914 | prom_timers->limit1 = 0; | |
915 | ||
916 | /* Wheee, eat the interrupt packet too... */ | |
917 | __asm__ __volatile__( | |
918 | " mov 0x40, %%g2\n" | |
919 | " ldxa [%%g0] %0, %%g1\n" | |
920 | " ldxa [%%g2] %1, %%g1\n" | |
921 | " stxa %%g0, [%%g0] %0\n" | |
922 | " membar #Sync\n" | |
923 | : /* no outputs */ | |
924 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
925 | : "g1", "g2"); | |
926 | } | |
927 | ||
1da177e4 LT |
928 | void init_irqwork_curcpu(void) |
929 | { | |
1da177e4 LT |
930 | int cpu = hard_smp_processor_id(); |
931 | ||
56fb4df6 | 932 | memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct)); |
1da177e4 LT |
933 | } |
934 | ||
b5a37e96 | 935 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type) |
ac29c11d | 936 | { |
164c220f DM |
937 | register unsigned long func __asm__("%o5"); |
938 | register unsigned long arg0 __asm__("%o0"); | |
939 | register unsigned long arg1 __asm__("%o1"); | |
940 | register unsigned long arg2 __asm__("%o2"); | |
ac29c11d DM |
941 | |
942 | func = HV_FAST_CPU_QCONF; | |
943 | arg0 = type; | |
b5a37e96 | 944 | arg1 = paddr; |
ac29c11d DM |
945 | arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */ |
946 | __asm__ __volatile__("ta %8" | |
947 | : "=&r" (func), "=&r" (arg0), | |
948 | "=&r" (arg1), "=&r" (arg2) | |
949 | : "0" (func), "1" (arg0), | |
950 | "2" (arg1), "3" (arg2), | |
951 | "i" (HV_FAST_TRAP)); | |
952 | ||
b5a37e96 | 953 | if (arg0 != HV_EOK) { |
ac29c11d DM |
954 | prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n", |
955 | type, func); | |
956 | prom_halt(); | |
957 | } | |
958 | } | |
959 | ||
b5a37e96 | 960 | static void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 961 | { |
b5a37e96 DM |
962 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
963 | ||
964 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO); | |
965 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO); | |
966 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR); | |
967 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR); | |
968 | } | |
969 | ||
970 | static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem) | |
971 | { | |
972 | void *page; | |
973 | ||
974 | if (use_bootmem) | |
975 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
976 | else | |
977 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
978 | ||
979 | if (!page) { | |
980 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); | |
981 | prom_halt(); | |
982 | } | |
983 | ||
984 | *pa_ptr = __pa(page); | |
985 | } | |
986 | ||
987 | static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem) | |
988 | { | |
989 | void *page; | |
990 | ||
991 | if (use_bootmem) | |
992 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
993 | else | |
994 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
5b0c0572 DM |
995 | |
996 | if (!page) { | |
997 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); | |
998 | prom_halt(); | |
999 | } | |
1000 | ||
1001 | *pa_ptr = __pa(page); | |
1002 | } | |
1003 | ||
b5a37e96 | 1004 | static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem) |
1d2f1f90 DM |
1005 | { |
1006 | #ifdef CONFIG_SMP | |
b5a37e96 | 1007 | void *page; |
1d2f1f90 DM |
1008 | |
1009 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
1010 | ||
b5a37e96 DM |
1011 | if (use_bootmem) |
1012 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
1013 | else | |
1014 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
1015 | ||
1d2f1f90 DM |
1016 | if (!page) { |
1017 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
1018 | prom_halt(); | |
1019 | } | |
1020 | ||
1021 | tb->cpu_mondo_block_pa = __pa(page); | |
1022 | tb->cpu_list_pa = __pa(page + 64); | |
1023 | #endif | |
1024 | } | |
1025 | ||
b5a37e96 DM |
1026 | /* Allocate and register the mondo and error queues for this cpu. */ |
1027 | void __cpuinit sun4v_init_mondo_queues(int use_bootmem) | |
ac29c11d DM |
1028 | { |
1029 | int cpu = hard_smp_processor_id(); | |
1030 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1031 | ||
b5a37e96 DM |
1032 | alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem); |
1033 | alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem); | |
1034 | alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem); | |
1035 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem); | |
1036 | alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem); | |
1037 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem); | |
1d2f1f90 | 1038 | |
b5a37e96 | 1039 | init_cpu_send_mondo_info(tb, use_bootmem); |
1d2f1f90 | 1040 | |
b5a37e96 | 1041 | sun4v_register_mondo_queues(cpu); |
ac29c11d DM |
1042 | } |
1043 | ||
1da177e4 LT |
1044 | /* Only invoked on boot processor. */ |
1045 | void __init init_IRQ(void) | |
1046 | { | |
1047 | map_prom_timers(); | |
1048 | kill_prom_timer(); | |
1049 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
1050 | ||
ac29c11d | 1051 | if (tlb_type == hypervisor) |
b5a37e96 | 1052 | sun4v_init_mondo_queues(1); |
ac29c11d | 1053 | |
1da177e4 LT |
1054 | /* We need to clear any IRQ's pending in the soft interrupt |
1055 | * registers, a spurious one could be left around from the | |
1056 | * PROM timer which we just disabled. | |
1057 | */ | |
1058 | clear_softint(get_softint()); | |
1059 | ||
1060 | /* Now that ivector table is initialized, it is safe | |
1061 | * to receive IRQ vector traps. We will normally take | |
1062 | * one or two right now, in case some device PROM used | |
1063 | * to boot us wants to speak to us. We just ignore them. | |
1064 | */ | |
1065 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
1066 | "or %%g1, %0, %%g1\n\t" | |
1067 | "wrpr %%g1, 0x0, %%pstate" | |
1068 | : /* No outputs */ | |
1069 | : "i" (PSTATE_IE) | |
1070 | : "g1"); | |
1071 | } | |
1072 | ||
1073 | static struct proc_dir_entry * root_irq_dir; | |
1074 | static struct proc_dir_entry * irq_dir [NUM_IVECS]; | |
1075 | ||
1076 | #ifdef CONFIG_SMP | |
1077 | ||
1078 | static int irq_affinity_read_proc (char *page, char **start, off_t off, | |
1079 | int count, int *eof, void *data) | |
1080 | { | |
1081 | struct ino_bucket *bp = ivector_table + (long)data; | |
12cf649f ED |
1082 | struct irq_desc *desc = bp->irq_info; |
1083 | struct irqaction *ap = desc->action; | |
1da177e4 LT |
1084 | cpumask_t mask; |
1085 | int len; | |
1086 | ||
1087 | mask = get_smpaff_in_irqaction(ap); | |
1088 | if (cpus_empty(mask)) | |
1089 | mask = cpu_online_map; | |
1090 | ||
1091 | len = cpumask_scnprintf(page, count, mask); | |
1092 | if (count - len < 2) | |
1093 | return -EINVAL; | |
1094 | len += sprintf(page + len, "\n"); | |
1095 | return len; | |
1096 | } | |
1097 | ||
1098 | static inline void set_intr_affinity(int irq, cpumask_t hw_aff) | |
1099 | { | |
1100 | struct ino_bucket *bp = ivector_table + irq; | |
12cf649f ED |
1101 | struct irq_desc *desc = bp->irq_info; |
1102 | struct irqaction *ap = desc->action; | |
1da177e4 LT |
1103 | |
1104 | /* Users specify affinity in terms of hw cpu ids. | |
1105 | * As soon as we do this, handler_irq() might see and take action. | |
1106 | */ | |
12cf649f | 1107 | put_smpaff_in_irqaction(ap, hw_aff); |
1da177e4 LT |
1108 | |
1109 | /* Migration is simply done by the next cpu to service this | |
1110 | * interrupt. | |
1111 | */ | |
1112 | } | |
1113 | ||
1114 | static int irq_affinity_write_proc (struct file *file, const char __user *buffer, | |
1115 | unsigned long count, void *data) | |
1116 | { | |
1117 | int irq = (long) data, full_count = count, err; | |
1118 | cpumask_t new_value; | |
1119 | ||
1120 | err = cpumask_parse(buffer, count, new_value); | |
1121 | ||
1122 | /* | |
1123 | * Do not allow disabling IRQs completely - it's a too easy | |
1124 | * way to make the system unusable accidentally :-) At least | |
1125 | * one online CPU still has to be targeted. | |
1126 | */ | |
1127 | cpus_and(new_value, new_value, cpu_online_map); | |
1128 | if (cpus_empty(new_value)) | |
1129 | return -EINVAL; | |
1130 | ||
1131 | set_intr_affinity(irq, new_value); | |
1132 | ||
1133 | return full_count; | |
1134 | } | |
1135 | ||
1136 | #endif | |
1137 | ||
1138 | #define MAX_NAMELEN 10 | |
1139 | ||
1140 | static void register_irq_proc (unsigned int irq) | |
1141 | { | |
1142 | char name [MAX_NAMELEN]; | |
1143 | ||
1144 | if (!root_irq_dir || irq_dir[irq]) | |
1145 | return; | |
1146 | ||
1147 | memset(name, 0, MAX_NAMELEN); | |
1148 | sprintf(name, "%x", irq); | |
1149 | ||
1150 | /* create /proc/irq/1234 */ | |
1151 | irq_dir[irq] = proc_mkdir(name, root_irq_dir); | |
1152 | ||
1153 | #ifdef CONFIG_SMP | |
1154 | /* XXX SMP affinity not supported on starfire yet. */ | |
1155 | if (this_is_starfire == 0) { | |
1156 | struct proc_dir_entry *entry; | |
1157 | ||
1158 | /* create /proc/irq/1234/smp_affinity */ | |
1159 | entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); | |
1160 | ||
1161 | if (entry) { | |
1162 | entry->nlink = 1; | |
1163 | entry->data = (void *)(long)irq; | |
1164 | entry->read_proc = irq_affinity_read_proc; | |
1165 | entry->write_proc = irq_affinity_write_proc; | |
1166 | } | |
1167 | } | |
1168 | #endif | |
1169 | } | |
1170 | ||
1171 | void init_irq_proc (void) | |
1172 | { | |
1173 | /* create /proc/irq */ | |
1174 | root_irq_dir = proc_mkdir("irq", NULL); | |
1175 | } | |
1176 |