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1da177e4 LT |
1 | /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $ |
2 | * irq.c: UltraSparc IRQ handling/init/registry. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/ptrace.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/signal.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/random.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/proc_fs.h> | |
23 | #include <linux/seq_file.h> | |
b5a37e96 | 24 | #include <linux/bootmem.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/irq.h> | |
2e457ef6 | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include <asm/sbus.h> |
33 | #include <asm/iommu.h> | |
34 | #include <asm/upa.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/timer.h> | |
37 | #include <asm/smp.h> | |
38 | #include <asm/starfire.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/cache.h> | |
41 | #include <asm/cpudata.h> | |
63b61452 | 42 | #include <asm/auxio.h> |
92704a1c | 43 | #include <asm/head.h> |
1da177e4 LT |
44 | |
45 | #ifdef CONFIG_SMP | |
46 | static void distribute_irqs(void); | |
47 | #endif | |
48 | ||
49 | /* UPA nodes send interrupt packet to UltraSparc with first data reg | |
50 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
51 | * delivered. We must translate this into a non-vector IRQ so we can | |
52 | * set the softint on this cpu. | |
53 | * | |
54 | * To make processing these packets efficient and race free we use | |
55 | * an array of irq buckets below. The interrupt vector handler in | |
56 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
57 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
58 | * code uses CAS to get an atomic snapshot of the list and clear it | |
59 | * at the same time. | |
60 | */ | |
61 | ||
62 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); | |
63 | ||
64 | /* This has to be in the main kernel image, it cannot be | |
65 | * turned into per-cpu data. The reason is that the main | |
66 | * kernel image is locked into the TLB and this structure | |
67 | * is accessed from the vectored interrupt trap handler. If | |
68 | * access to this structure takes a TLB miss it could cause | |
69 | * the 5-level sparc v9 trap stack to overflow. | |
70 | */ | |
71 | struct irq_work_struct { | |
72 | unsigned int irq_worklists[16]; | |
73 | }; | |
74 | struct irq_work_struct __irq_work[NR_CPUS]; | |
75 | #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)]) | |
76 | ||
088dd1f8 | 77 | static struct irqaction *irq_action[NR_IRQS+1]; |
1da177e4 LT |
78 | |
79 | /* This only synchronizes entities which modify IRQ handler | |
80 | * state and some selected user-level spots that want to | |
81 | * read things in the table. IRQ handler processing orders | |
82 | * its' accesses such that no locking is needed. | |
83 | */ | |
84 | static DEFINE_SPINLOCK(irq_action_lock); | |
85 | ||
86 | static void register_irq_proc (unsigned int irq); | |
87 | ||
88 | /* | |
89 | * Upper 2b of irqaction->flags holds the ino. | |
90 | * irqaction->mask holds the smp affinity information. | |
91 | */ | |
92 | #define put_ino_in_irqaction(action, irq) \ | |
93 | action->flags &= 0xffffffffffffUL; \ | |
94 | if (__bucket(irq) == &pil0_dummy_bucket) \ | |
95 | action->flags |= 0xdeadUL << 48; \ | |
96 | else \ | |
97 | action->flags |= __irq_ino(irq) << 48; | |
98 | #define get_ino_in_irqaction(action) (action->flags >> 48) | |
99 | ||
100 | #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff) | |
101 | #define get_smpaff_in_irqaction(action) ((action)->mask) | |
102 | ||
103 | int show_interrupts(struct seq_file *p, void *v) | |
104 | { | |
105 | unsigned long flags; | |
106 | int i = *(loff_t *) v; | |
107 | struct irqaction *action; | |
108 | #ifdef CONFIG_SMP | |
109 | int j; | |
110 | #endif | |
111 | ||
112 | spin_lock_irqsave(&irq_action_lock, flags); | |
113 | if (i <= NR_IRQS) { | |
114 | if (!(action = *(i + irq_action))) | |
115 | goto out_unlock; | |
116 | seq_printf(p, "%3d: ", i); | |
117 | #ifndef CONFIG_SMP | |
118 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
119 | #else | |
120 | for (j = 0; j < NR_CPUS; j++) { | |
121 | if (!cpu_online(j)) | |
122 | continue; | |
123 | seq_printf(p, "%10u ", | |
124 | kstat_cpu(j).irqs[i]); | |
125 | } | |
126 | #endif | |
127 | seq_printf(p, " %s:%lx", action->name, | |
128 | get_ino_in_irqaction(action)); | |
129 | for (action = action->next; action; action = action->next) { | |
130 | seq_printf(p, ", %s:%lx", action->name, | |
131 | get_ino_in_irqaction(action)); | |
132 | } | |
133 | seq_putc(p, '\n'); | |
134 | } | |
135 | out_unlock: | |
136 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | /* Now these are always passed a true fully specified sun4u INO. */ | |
142 | void enable_irq(unsigned int irq) | |
143 | { | |
144 | struct ino_bucket *bucket = __bucket(irq); | |
145 | unsigned long imap; | |
146 | unsigned long tid; | |
147 | ||
148 | imap = bucket->imap; | |
149 | if (imap == 0UL) | |
150 | return; | |
151 | ||
152 | preempt_disable(); | |
153 | ||
d82ace7d | 154 | if (tlb_type == hypervisor) { |
10951ee6 DM |
155 | int cpu = hard_smp_processor_id(); |
156 | ||
157 | sun4v_intr_settarget(irq, cpu); | |
158 | sun4v_intr_setenabled(irq, HV_INTR_ENABLED); | |
d82ace7d DM |
159 | } else { |
160 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
161 | unsigned long ver; | |
162 | ||
163 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
164 | if ((ver >> 32) == __JALAPENO_ID || | |
165 | (ver >> 32) == __SERRANO_ID) { | |
166 | /* We set it to our JBUS ID. */ | |
167 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
168 | : "=r" (tid) | |
169 | : "i" (ASI_JBUS_CONFIG)); | |
170 | tid = ((tid & (0x1fUL<<17)) << 9); | |
171 | tid &= IMAP_TID_JBUS; | |
172 | } else { | |
173 | /* We set it to our Safari AID. */ | |
174 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
175 | : "=r" (tid) | |
176 | : "i"(ASI_SAFARI_CONFIG)); | |
177 | tid = ((tid & (0x3ffUL<<17)) << 9); | |
178 | tid &= IMAP_AID_SAFARI; | |
179 | } | |
180 | } else if (this_is_starfire == 0) { | |
181 | /* We set it to our UPA MID. */ | |
1da177e4 LT |
182 | __asm__ __volatile__("ldxa [%%g0] %1, %0" |
183 | : "=r" (tid) | |
d82ace7d DM |
184 | : "i" (ASI_UPA_CONFIG)); |
185 | tid = ((tid & UPA_CONFIG_MID) << 9); | |
186 | tid &= IMAP_TID_UPA; | |
1da177e4 | 187 | } else { |
d82ace7d DM |
188 | tid = (starfire_translate(imap, |
189 | smp_processor_id()) << 26); | |
190 | tid &= IMAP_TID_UPA; | |
1da177e4 | 191 | } |
1da177e4 | 192 | |
d82ace7d DM |
193 | /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product |
194 | * of this SYSIO's preconfigured IGN in the SYSIO Control | |
195 | * Register, the hardware just mirrors that value here. | |
196 | * However for Graphics and UPA Slave devices the full | |
197 | * IMAP_INR field can be set by the programmer here. | |
198 | * | |
199 | * Things like FFB can now be handled via the new IRQ | |
200 | * mechanism. | |
201 | */ | |
202 | upa_writel(tid | IMAP_VALID, imap); | |
203 | } | |
1da177e4 LT |
204 | |
205 | preempt_enable(); | |
206 | } | |
207 | ||
208 | /* This now gets passed true ino's as well. */ | |
209 | void disable_irq(unsigned int irq) | |
210 | { | |
211 | struct ino_bucket *bucket = __bucket(irq); | |
212 | unsigned long imap; | |
213 | ||
214 | imap = bucket->imap; | |
215 | if (imap != 0UL) { | |
10951ee6 DM |
216 | if (tlb_type == hypervisor) { |
217 | sun4v_intr_setenabled(irq, HV_INTR_DISABLED); | |
218 | } else { | |
219 | u32 tmp; | |
1da177e4 | 220 | |
10951ee6 DM |
221 | /* NOTE: We do not want to futz with the IRQ clear registers |
222 | * and move the state to IDLE, the SCSI code does call | |
223 | * disable_irq() to assure atomicity in the queue cmd | |
224 | * SCSI adapter driver code. Thus we'd lose interrupts. | |
225 | */ | |
226 | tmp = upa_readl(imap); | |
227 | tmp &= ~IMAP_VALID; | |
228 | upa_writel(tmp, imap); | |
229 | } | |
1da177e4 LT |
230 | } |
231 | } | |
232 | ||
233 | /* The timer is the one "weird" interrupt which is generated by | |
234 | * the CPU %tick register and not by some normal vectored interrupt | |
235 | * source. To handle this special case, we use this dummy INO bucket. | |
236 | */ | |
088dd1f8 | 237 | static struct irq_desc pil0_dummy_desc; |
1da177e4 | 238 | static struct ino_bucket pil0_dummy_bucket = { |
088dd1f8 | 239 | .irq_info = &pil0_dummy_desc, |
1da177e4 LT |
240 | }; |
241 | ||
088dd1f8 DM |
242 | static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup, |
243 | unsigned long iclr, unsigned long imap, | |
244 | struct ino_bucket *bucket) | |
245 | { | |
246 | prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> " | |
247 | "(%d:%d:%016lx:%016lx), halting...\n", | |
248 | ino, bucket->pil, bucket->iclr, bucket->imap, | |
249 | pil, inofixup, iclr, imap); | |
250 | prom_halt(); | |
251 | } | |
252 | ||
1da177e4 LT |
253 | unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap) |
254 | { | |
255 | struct ino_bucket *bucket; | |
256 | int ino; | |
257 | ||
258 | if (pil == 0) { | |
259 | if (iclr != 0UL || imap != 0UL) { | |
260 | prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n", | |
261 | iclr, imap); | |
262 | prom_halt(); | |
263 | } | |
264 | return __irq(&pil0_dummy_bucket); | |
265 | } | |
266 | ||
10951ee6 DM |
267 | BUG_ON(tlb_type == hypervisor); |
268 | ||
1da177e4 LT |
269 | /* RULE: Both must be specified in all other cases. */ |
270 | if (iclr == 0UL || imap == 0UL) { | |
271 | prom_printf("Invalid build_irq %d %d %016lx %016lx\n", | |
272 | pil, inofixup, iclr, imap); | |
273 | prom_halt(); | |
274 | } | |
275 | ||
276 | ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; | |
277 | if (ino > NUM_IVECS) { | |
278 | prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n", | |
279 | ino, pil, inofixup, iclr, imap); | |
280 | prom_halt(); | |
281 | } | |
282 | ||
1da177e4 | 283 | bucket = &ivector_table[ino]; |
088dd1f8 DM |
284 | if (bucket->flags & IBF_ACTIVE) |
285 | build_irq_error("IRQ: Trying to build active INO bucket.\n", | |
286 | ino, pil, inofixup, iclr, imap, bucket); | |
287 | ||
288 | if (bucket->irq_info) { | |
289 | if (bucket->imap != imap || bucket->iclr != iclr) | |
290 | build_irq_error("IRQ: Trying to reinit INO bucket.\n", | |
291 | ino, pil, inofixup, iclr, imap, bucket); | |
292 | ||
293 | goto out; | |
294 | } | |
295 | ||
296 | bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC); | |
297 | if (!bucket->irq_info) { | |
298 | prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n"); | |
1da177e4 LT |
299 | prom_halt(); |
300 | } | |
088dd1f8 DM |
301 | memset(bucket->irq_info, 0, sizeof(struct irq_desc)); |
302 | ||
303 | /* Ok, looks good, set it up. Don't touch the irq_chain or | |
304 | * the pending flag. | |
305 | */ | |
1da177e4 LT |
306 | bucket->imap = imap; |
307 | bucket->iclr = iclr; | |
308 | bucket->pil = pil; | |
309 | bucket->flags = 0; | |
310 | ||
088dd1f8 | 311 | out: |
1da177e4 LT |
312 | return __irq(bucket); |
313 | } | |
314 | ||
e3999574 DM |
315 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags) |
316 | { | |
317 | struct ino_bucket *bucket; | |
318 | unsigned long sysino; | |
319 | ||
320 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
321 | ||
87bdc367 DM |
322 | printk(KERN_INFO "sun4v_irq: Mapping (%x:%x) --> sysino[%lx]\n", |
323 | devhandle, devino, sysino); | |
e3999574 DM |
324 | |
325 | bucket = &ivector_table[sysino]; | |
326 | ||
327 | /* Catch accidental accesses to these things. IMAP/ICLR handling | |
328 | * is done by hypervisor calls on sun4v platforms, not by direct | |
329 | * register accesses. | |
330 | */ | |
331 | bucket->imap = ~0UL; | |
332 | bucket->iclr = ~0UL; | |
333 | ||
334 | bucket->pil = pil; | |
335 | bucket->flags = flags; | |
336 | ||
337 | bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC); | |
338 | if (!bucket->irq_info) { | |
339 | prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n"); | |
340 | prom_halt(); | |
341 | } | |
342 | memset(bucket->irq_info, 0, sizeof(struct irq_desc)); | |
343 | ||
344 | return __irq(bucket); | |
345 | } | |
346 | ||
1da177e4 LT |
347 | static void atomic_bucket_insert(struct ino_bucket *bucket) |
348 | { | |
349 | unsigned long pstate; | |
350 | unsigned int *ent; | |
351 | ||
352 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
353 | __asm__ __volatile__("wrpr %0, %1, %%pstate" | |
354 | : : "r" (pstate), "i" (PSTATE_IE)); | |
355 | ent = irq_work(smp_processor_id(), bucket->pil); | |
356 | bucket->irq_chain = *ent; | |
357 | *ent = __irq(bucket); | |
358 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate)); | |
359 | } | |
360 | ||
088dd1f8 DM |
361 | static int check_irq_sharing(int pil, unsigned long irqflags) |
362 | { | |
363 | struct irqaction *action, *tmp; | |
364 | ||
365 | action = *(irq_action + pil); | |
366 | if (action) { | |
367 | if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) { | |
368 | for (tmp = action; tmp->next; tmp = tmp->next) | |
369 | ; | |
370 | } else { | |
371 | return -EBUSY; | |
372 | } | |
373 | } | |
374 | return 0; | |
375 | } | |
376 | ||
377 | static void append_irq_action(int pil, struct irqaction *action) | |
378 | { | |
379 | struct irqaction **pp = irq_action + pil; | |
380 | ||
381 | while (*pp) | |
382 | pp = &((*pp)->next); | |
383 | *pp = action; | |
384 | } | |
385 | ||
386 | static struct irqaction *get_action_slot(struct ino_bucket *bucket) | |
387 | { | |
388 | struct irq_desc *desc = bucket->irq_info; | |
389 | int max_irq, i; | |
390 | ||
391 | max_irq = 1; | |
392 | if (bucket->flags & IBF_PCI) | |
393 | max_irq = MAX_IRQ_DESC_ACTION; | |
394 | for (i = 0; i < max_irq; i++) { | |
395 | struct irqaction *p = &desc->action[i]; | |
396 | u32 mask = (1 << i); | |
397 | ||
398 | if (desc->action_active_mask & mask) | |
399 | continue; | |
400 | ||
401 | desc->action_active_mask |= mask; | |
402 | return p; | |
403 | } | |
404 | return NULL; | |
405 | } | |
406 | ||
1da177e4 LT |
407 | int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), |
408 | unsigned long irqflags, const char *name, void *dev_id) | |
409 | { | |
088dd1f8 | 410 | struct irqaction *action; |
1da177e4 LT |
411 | struct ino_bucket *bucket = __bucket(irq); |
412 | unsigned long flags; | |
413 | int pending = 0; | |
414 | ||
088dd1f8 | 415 | if (unlikely(!handler)) |
1da177e4 | 416 | return -EINVAL; |
088dd1f8 DM |
417 | |
418 | if (unlikely(!bucket->irq_info)) | |
419 | return -ENODEV; | |
1da177e4 LT |
420 | |
421 | if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) { | |
422 | /* | |
423 | * This function might sleep, we want to call it first, | |
424 | * outside of the atomic block. In SA_STATIC_ALLOC case, | |
425 | * random driver's kmalloc will fail, but it is safe. | |
426 | * If already initialized, random driver will not reinit. | |
427 | * Yes, this might clear the entropy pool if the wrong | |
428 | * driver is attempted to be loaded, without actually | |
429 | * installing a new handler, but is this really a problem, | |
430 | * only the sysadmin is able to do this. | |
431 | */ | |
432 | rand_initialize_irq(irq); | |
433 | } | |
434 | ||
435 | spin_lock_irqsave(&irq_action_lock, flags); | |
436 | ||
088dd1f8 DM |
437 | if (check_irq_sharing(bucket->pil, irqflags)) { |
438 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
439 | return -EBUSY; | |
1da177e4 LT |
440 | } |
441 | ||
088dd1f8 | 442 | action = get_action_slot(bucket); |
1da177e4 LT |
443 | if (!action) { |
444 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
445 | return -ENOMEM; | |
446 | } | |
447 | ||
088dd1f8 DM |
448 | bucket->flags |= IBF_ACTIVE; |
449 | pending = 0; | |
450 | if (bucket != &pil0_dummy_bucket) { | |
1da177e4 LT |
451 | pending = bucket->pending; |
452 | if (pending) | |
453 | bucket->pending = 0; | |
454 | } | |
455 | ||
456 | action->handler = handler; | |
457 | action->flags = irqflags; | |
458 | action->name = name; | |
459 | action->next = NULL; | |
460 | action->dev_id = dev_id; | |
461 | put_ino_in_irqaction(action, irq); | |
462 | put_smpaff_in_irqaction(action, CPU_MASK_NONE); | |
463 | ||
088dd1f8 | 464 | append_irq_action(bucket->pil, action); |
1da177e4 LT |
465 | |
466 | enable_irq(irq); | |
467 | ||
468 | /* We ate the IVEC already, this makes sure it does not get lost. */ | |
469 | if (pending) { | |
470 | atomic_bucket_insert(bucket); | |
471 | set_softint(1 << bucket->pil); | |
472 | } | |
088dd1f8 | 473 | |
1da177e4 | 474 | spin_unlock_irqrestore(&irq_action_lock, flags); |
088dd1f8 DM |
475 | |
476 | if (bucket != &pil0_dummy_bucket) | |
1da177e4 LT |
477 | register_irq_proc(__irq_ino(irq)); |
478 | ||
479 | #ifdef CONFIG_SMP | |
480 | distribute_irqs(); | |
481 | #endif | |
482 | return 0; | |
1da177e4 LT |
483 | } |
484 | ||
485 | EXPORT_SYMBOL(request_irq); | |
486 | ||
088dd1f8 | 487 | static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id) |
1da177e4 | 488 | { |
088dd1f8 DM |
489 | struct ino_bucket *bucket = __bucket(irq); |
490 | struct irqaction *action, **pp; | |
1da177e4 | 491 | |
088dd1f8 DM |
492 | pp = irq_action + bucket->pil; |
493 | action = *pp; | |
494 | if (unlikely(!action)) | |
495 | return NULL; | |
1da177e4 | 496 | |
088dd1f8 | 497 | if (unlikely(!action->handler)) { |
1da177e4 | 498 | printk("Freeing free IRQ %d\n", bucket->pil); |
088dd1f8 | 499 | return NULL; |
1da177e4 LT |
500 | } |
501 | ||
088dd1f8 DM |
502 | while (action && action->dev_id != dev_id) { |
503 | pp = &action->next; | |
504 | action = *pp; | |
1da177e4 LT |
505 | } |
506 | ||
088dd1f8 DM |
507 | if (likely(action)) |
508 | *pp = action->next; | |
509 | ||
510 | return action; | |
511 | } | |
512 | ||
513 | void free_irq(unsigned int irq, void *dev_id) | |
514 | { | |
515 | struct irqaction *action; | |
516 | struct ino_bucket *bucket; | |
517 | unsigned long flags; | |
518 | ||
519 | spin_lock_irqsave(&irq_action_lock, flags); | |
520 | ||
521 | action = unlink_irq_action(irq, dev_id); | |
1da177e4 LT |
522 | |
523 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
524 | ||
088dd1f8 DM |
525 | if (unlikely(!action)) |
526 | return; | |
527 | ||
1da177e4 LT |
528 | synchronize_irq(irq); |
529 | ||
530 | spin_lock_irqsave(&irq_action_lock, flags); | |
531 | ||
088dd1f8 | 532 | bucket = __bucket(irq); |
1da177e4 | 533 | if (bucket != &pil0_dummy_bucket) { |
088dd1f8 | 534 | struct irq_desc *desc = bucket->irq_info; |
1da177e4 | 535 | unsigned long imap = bucket->imap; |
088dd1f8 | 536 | int ent, i; |
1da177e4 | 537 | |
088dd1f8 DM |
538 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { |
539 | struct irqaction *p = &desc->action[i]; | |
540 | ||
541 | if (p == action) { | |
542 | desc->action_active_mask &= ~(1 << i); | |
543 | break; | |
1da177e4 | 544 | } |
1da177e4 LT |
545 | } |
546 | ||
088dd1f8 DM |
547 | if (!desc->action_active_mask) { |
548 | /* This unique interrupt source is now inactive. */ | |
549 | bucket->flags &= ~IBF_ACTIVE; | |
1da177e4 | 550 | |
088dd1f8 DM |
551 | /* See if any other buckets share this bucket's IMAP |
552 | * and are still active. | |
553 | */ | |
554 | for (ent = 0; ent < NUM_IVECS; ent++) { | |
555 | struct ino_bucket *bp = &ivector_table[ent]; | |
556 | if (bp != bucket && | |
557 | bp->imap == imap && | |
558 | (bp->flags & IBF_ACTIVE) != 0) | |
559 | break; | |
560 | } | |
1da177e4 | 561 | |
088dd1f8 DM |
562 | /* Only disable when no other sub-irq levels of |
563 | * the same IMAP are active. | |
564 | */ | |
565 | if (ent == NUM_IVECS) | |
566 | disable_irq(irq); | |
567 | } | |
1da177e4 LT |
568 | } |
569 | ||
1da177e4 LT |
570 | spin_unlock_irqrestore(&irq_action_lock, flags); |
571 | } | |
572 | ||
573 | EXPORT_SYMBOL(free_irq); | |
574 | ||
575 | #ifdef CONFIG_SMP | |
576 | void synchronize_irq(unsigned int irq) | |
577 | { | |
578 | struct ino_bucket *bucket = __bucket(irq); | |
579 | ||
580 | #if 0 | |
581 | /* The following is how I wish I could implement this. | |
582 | * Unfortunately the ICLR registers are read-only, you can | |
583 | * only write ICLR_foo values to them. To get the current | |
584 | * IRQ status you would need to get at the IRQ diag registers | |
585 | * in the PCI/SBUS controller and the layout of those vary | |
586 | * from one controller to the next, sigh... -DaveM | |
587 | */ | |
588 | unsigned long iclr = bucket->iclr; | |
589 | ||
590 | while (1) { | |
591 | u32 tmp = upa_readl(iclr); | |
592 | ||
593 | if (tmp == ICLR_TRANSMIT || | |
594 | tmp == ICLR_PENDING) { | |
595 | cpu_relax(); | |
596 | continue; | |
597 | } | |
598 | break; | |
599 | } | |
600 | #else | |
601 | /* So we have to do this with a INPROGRESS bit just like x86. */ | |
602 | while (bucket->flags & IBF_INPROGRESS) | |
603 | cpu_relax(); | |
604 | #endif | |
605 | } | |
606 | #endif /* CONFIG_SMP */ | |
607 | ||
088dd1f8 | 608 | static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs) |
1da177e4 | 609 | { |
088dd1f8 DM |
610 | struct irq_desc *desc = bp->irq_info; |
611 | unsigned char flags = bp->flags; | |
612 | u32 action_mask, i; | |
613 | int random; | |
1da177e4 | 614 | |
088dd1f8 | 615 | bp->flags |= IBF_INPROGRESS; |
1da177e4 | 616 | |
088dd1f8 DM |
617 | if (unlikely(!(flags & IBF_ACTIVE))) { |
618 | bp->pending = 1; | |
1da177e4 | 619 | goto out; |
1da177e4 LT |
620 | } |
621 | ||
088dd1f8 DM |
622 | if (desc->pre_handler) |
623 | desc->pre_handler(bp, | |
624 | desc->pre_handler_arg1, | |
625 | desc->pre_handler_arg2); | |
1da177e4 | 626 | |
088dd1f8 DM |
627 | action_mask = desc->action_active_mask; |
628 | random = 0; | |
629 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { | |
630 | struct irqaction *p = &desc->action[i]; | |
631 | u32 mask = (1 << i); | |
1da177e4 | 632 | |
088dd1f8 DM |
633 | if (!(action_mask & mask)) |
634 | continue; | |
1da177e4 | 635 | |
088dd1f8 | 636 | action_mask &= ~mask; |
1da177e4 | 637 | |
088dd1f8 DM |
638 | if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED) |
639 | random |= p->flags; | |
640 | ||
641 | if (!action_mask) | |
642 | break; | |
643 | } | |
644 | if (bp->pil != 0) { | |
10951ee6 DM |
645 | if (tlb_type == hypervisor) { |
646 | unsigned int irq = __irq(bp); | |
647 | ||
648 | sun4v_intr_setstate(irq, HV_INTR_STATE_IDLE); | |
649 | } else { | |
650 | upa_writel(ICLR_IDLE, bp->iclr); | |
651 | /* Test and add entropy */ | |
652 | if (random & SA_SAMPLE_RANDOM) | |
653 | add_interrupt_randomness(irq); | |
654 | } | |
088dd1f8 | 655 | } |
1da177e4 | 656 | out: |
088dd1f8 | 657 | bp->flags &= ~IBF_INPROGRESS; |
1da177e4 LT |
658 | } |
659 | ||
1da177e4 LT |
660 | void handler_irq(int irq, struct pt_regs *regs) |
661 | { | |
088dd1f8 | 662 | struct ino_bucket *bp; |
1da177e4 LT |
663 | int cpu = smp_processor_id(); |
664 | ||
665 | #ifndef CONFIG_SMP | |
666 | /* | |
667 | * Check for TICK_INT on level 14 softint. | |
668 | */ | |
669 | { | |
670 | unsigned long clr_mask = 1 << irq; | |
671 | unsigned long tick_mask = tick_ops->softint_mask; | |
672 | ||
673 | if ((irq == 14) && (get_softint() & tick_mask)) { | |
674 | irq = 0; | |
675 | clr_mask = tick_mask; | |
676 | } | |
677 | clear_softint(clr_mask); | |
678 | } | |
679 | #else | |
1da177e4 LT |
680 | clear_softint(1 << irq); |
681 | #endif | |
682 | ||
683 | irq_enter(); | |
684 | kstat_this_cpu.irqs[irq]++; | |
685 | ||
686 | /* Sliiiick... */ | |
687 | #ifndef CONFIG_SMP | |
688 | bp = ((irq != 0) ? | |
689 | __bucket(xchg32(irq_work(cpu, irq), 0)) : | |
690 | &pil0_dummy_bucket); | |
691 | #else | |
692 | bp = __bucket(xchg32(irq_work(cpu, irq), 0)); | |
693 | #endif | |
088dd1f8 DM |
694 | while (bp) { |
695 | struct ino_bucket *nbp = __bucket(bp->irq_chain); | |
1da177e4 | 696 | |
1da177e4 | 697 | bp->irq_chain = 0; |
088dd1f8 DM |
698 | process_bucket(irq, bp, regs); |
699 | bp = nbp; | |
1da177e4 LT |
700 | } |
701 | irq_exit(); | |
702 | } | |
703 | ||
704 | #ifdef CONFIG_BLK_DEV_FD | |
63b61452 | 705 | extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);; |
1da177e4 | 706 | |
63b61452 DM |
707 | /* XXX No easy way to include asm/floppy.h XXX */ |
708 | extern unsigned char *pdma_vaddr; | |
709 | extern unsigned long pdma_size; | |
710 | extern volatile int doing_pdma; | |
711 | extern unsigned long fdc_status; | |
1da177e4 | 712 | |
63b61452 | 713 | irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs) |
1da177e4 | 714 | { |
63b61452 DM |
715 | if (likely(doing_pdma)) { |
716 | void __iomem *stat = (void __iomem *) fdc_status; | |
717 | unsigned char *vaddr = pdma_vaddr; | |
718 | unsigned long size = pdma_size; | |
719 | u8 val; | |
720 | ||
721 | while (size) { | |
722 | val = readb(stat); | |
723 | if (unlikely(!(val & 0x80))) { | |
724 | pdma_vaddr = vaddr; | |
725 | pdma_size = size; | |
726 | return IRQ_HANDLED; | |
727 | } | |
728 | if (unlikely(!(val & 0x20))) { | |
729 | pdma_vaddr = vaddr; | |
730 | pdma_size = size; | |
731 | doing_pdma = 0; | |
732 | goto main_interrupt; | |
733 | } | |
734 | if (val & 0x40) { | |
735 | /* read */ | |
736 | *vaddr++ = readb(stat + 1); | |
737 | } else { | |
738 | unsigned char data = *vaddr++; | |
1da177e4 | 739 | |
63b61452 DM |
740 | /* write */ |
741 | writeb(data, stat + 1); | |
742 | } | |
743 | size--; | |
744 | } | |
1da177e4 | 745 | |
63b61452 DM |
746 | pdma_vaddr = vaddr; |
747 | pdma_size = size; | |
1da177e4 | 748 | |
63b61452 DM |
749 | /* Send Terminal Count pulse to floppy controller. */ |
750 | val = readb(auxio_register); | |
751 | val |= AUXIO_AUX1_FTCNT; | |
752 | writeb(val, auxio_register); | |
94bbc176 | 753 | val &= ~AUXIO_AUX1_FTCNT; |
63b61452 | 754 | writeb(val, auxio_register); |
1da177e4 | 755 | |
63b61452 | 756 | doing_pdma = 0; |
1da177e4 | 757 | } |
1da177e4 | 758 | |
63b61452 DM |
759 | main_interrupt: |
760 | return floppy_interrupt(irq, dev_cookie, regs); | |
1da177e4 | 761 | } |
63b61452 DM |
762 | EXPORT_SYMBOL(sparc_floppy_irq); |
763 | #endif | |
1da177e4 LT |
764 | |
765 | /* We really don't need these at all on the Sparc. We only have | |
766 | * stubs here because they are exported to modules. | |
767 | */ | |
768 | unsigned long probe_irq_on(void) | |
769 | { | |
770 | return 0; | |
771 | } | |
772 | ||
773 | EXPORT_SYMBOL(probe_irq_on); | |
774 | ||
775 | int probe_irq_off(unsigned long mask) | |
776 | { | |
777 | return 0; | |
778 | } | |
779 | ||
780 | EXPORT_SYMBOL(probe_irq_off); | |
781 | ||
782 | #ifdef CONFIG_SMP | |
783 | static int retarget_one_irq(struct irqaction *p, int goal_cpu) | |
784 | { | |
785 | struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table; | |
786 | unsigned long imap = bucket->imap; | |
1da177e4 LT |
787 | |
788 | while (!cpu_online(goal_cpu)) { | |
789 | if (++goal_cpu >= NR_CPUS) | |
790 | goal_cpu = 0; | |
791 | } | |
792 | ||
10951ee6 DM |
793 | if (tlb_type == hypervisor) { |
794 | unsigned int irq = __irq(bucket); | |
795 | ||
796 | sun4v_intr_settarget(irq, goal_cpu); | |
797 | sun4v_intr_setenabled(irq, HV_INTR_ENABLED); | |
1da177e4 | 798 | } else { |
10951ee6 DM |
799 | unsigned int tid; |
800 | ||
801 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
802 | tid = goal_cpu << 26; | |
803 | tid &= IMAP_AID_SAFARI; | |
804 | } else if (this_is_starfire == 0) { | |
805 | tid = goal_cpu << 26; | |
806 | tid &= IMAP_TID_UPA; | |
807 | } else { | |
808 | tid = (starfire_translate(imap, goal_cpu) << 26); | |
809 | tid &= IMAP_TID_UPA; | |
810 | } | |
811 | upa_writel(tid | IMAP_VALID, imap); | |
1da177e4 | 812 | } |
1da177e4 | 813 | |
cee2824f | 814 | do { |
1da177e4 LT |
815 | if (++goal_cpu >= NR_CPUS) |
816 | goal_cpu = 0; | |
cee2824f | 817 | } while (!cpu_online(goal_cpu)); |
1da177e4 LT |
818 | |
819 | return goal_cpu; | |
820 | } | |
821 | ||
822 | /* Called from request_irq. */ | |
823 | static void distribute_irqs(void) | |
824 | { | |
825 | unsigned long flags; | |
826 | int cpu, level; | |
827 | ||
828 | spin_lock_irqsave(&irq_action_lock, flags); | |
829 | cpu = 0; | |
830 | ||
831 | /* | |
832 | * Skip the timer at [0], and very rare error/power intrs at [15]. | |
833 | * Also level [12], it causes problems on Ex000 systems. | |
834 | */ | |
835 | for (level = 1; level < NR_IRQS; level++) { | |
836 | struct irqaction *p = irq_action[level]; | |
088dd1f8 DM |
837 | |
838 | if (level == 12) | |
839 | continue; | |
840 | ||
1da177e4 LT |
841 | while(p) { |
842 | cpu = retarget_one_irq(p, cpu); | |
843 | p = p->next; | |
844 | } | |
845 | } | |
846 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
847 | } | |
848 | #endif | |
849 | ||
cdd5186f DM |
850 | struct sun5_timer { |
851 | u64 count0; | |
852 | u64 limit0; | |
853 | u64 count1; | |
854 | u64 limit1; | |
855 | }; | |
1da177e4 | 856 | |
cdd5186f | 857 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
858 | static u64 prom_limit0, prom_limit1; |
859 | ||
860 | static void map_prom_timers(void) | |
861 | { | |
862 | unsigned int addr[3]; | |
863 | int tnode, err; | |
864 | ||
865 | /* PROM timer node hangs out in the top level of device siblings... */ | |
866 | tnode = prom_finddevice("/counter-timer"); | |
867 | ||
868 | /* Assume if node is not present, PROM uses different tick mechanism | |
869 | * which we should not care about. | |
870 | */ | |
871 | if (tnode == 0 || tnode == -1) { | |
872 | prom_timers = (struct sun5_timer *) 0; | |
873 | return; | |
874 | } | |
875 | ||
876 | /* If PROM is really using this, it must be mapped by him. */ | |
877 | err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr)); | |
878 | if (err == -1) { | |
879 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); | |
880 | prom_timers = (struct sun5_timer *) 0; | |
881 | return; | |
882 | } | |
883 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
884 | } | |
885 | ||
886 | static void kill_prom_timer(void) | |
887 | { | |
888 | if (!prom_timers) | |
889 | return; | |
890 | ||
891 | /* Save them away for later. */ | |
892 | prom_limit0 = prom_timers->limit0; | |
893 | prom_limit1 = prom_timers->limit1; | |
894 | ||
895 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
896 | * We turn both off here just to be paranoid. | |
897 | */ | |
898 | prom_timers->limit0 = 0; | |
899 | prom_timers->limit1 = 0; | |
900 | ||
901 | /* Wheee, eat the interrupt packet too... */ | |
902 | __asm__ __volatile__( | |
903 | " mov 0x40, %%g2\n" | |
904 | " ldxa [%%g0] %0, %%g1\n" | |
905 | " ldxa [%%g2] %1, %%g1\n" | |
906 | " stxa %%g0, [%%g0] %0\n" | |
907 | " membar #Sync\n" | |
908 | : /* no outputs */ | |
909 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
910 | : "g1", "g2"); | |
911 | } | |
912 | ||
1da177e4 LT |
913 | void init_irqwork_curcpu(void) |
914 | { | |
1da177e4 LT |
915 | int cpu = hard_smp_processor_id(); |
916 | ||
56fb4df6 | 917 | memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct)); |
1da177e4 LT |
918 | } |
919 | ||
b5a37e96 | 920 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type) |
ac29c11d | 921 | { |
164c220f DM |
922 | register unsigned long func __asm__("%o5"); |
923 | register unsigned long arg0 __asm__("%o0"); | |
924 | register unsigned long arg1 __asm__("%o1"); | |
925 | register unsigned long arg2 __asm__("%o2"); | |
ac29c11d DM |
926 | |
927 | func = HV_FAST_CPU_QCONF; | |
928 | arg0 = type; | |
b5a37e96 | 929 | arg1 = paddr; |
ac29c11d DM |
930 | arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */ |
931 | __asm__ __volatile__("ta %8" | |
932 | : "=&r" (func), "=&r" (arg0), | |
933 | "=&r" (arg1), "=&r" (arg2) | |
934 | : "0" (func), "1" (arg0), | |
935 | "2" (arg1), "3" (arg2), | |
936 | "i" (HV_FAST_TRAP)); | |
937 | ||
b5a37e96 | 938 | if (arg0 != HV_EOK) { |
ac29c11d DM |
939 | prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n", |
940 | type, func); | |
941 | prom_halt(); | |
942 | } | |
943 | } | |
944 | ||
b5a37e96 | 945 | static void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 946 | { |
b5a37e96 DM |
947 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
948 | ||
949 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO); | |
950 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO); | |
951 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR); | |
952 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR); | |
953 | } | |
954 | ||
955 | static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem) | |
956 | { | |
957 | void *page; | |
958 | ||
959 | if (use_bootmem) | |
960 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
961 | else | |
962 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
963 | ||
964 | if (!page) { | |
965 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); | |
966 | prom_halt(); | |
967 | } | |
968 | ||
969 | *pa_ptr = __pa(page); | |
970 | } | |
971 | ||
972 | static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem) | |
973 | { | |
974 | void *page; | |
975 | ||
976 | if (use_bootmem) | |
977 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
978 | else | |
979 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
5b0c0572 DM |
980 | |
981 | if (!page) { | |
982 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); | |
983 | prom_halt(); | |
984 | } | |
985 | ||
986 | *pa_ptr = __pa(page); | |
987 | } | |
988 | ||
b5a37e96 | 989 | static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem) |
1d2f1f90 DM |
990 | { |
991 | #ifdef CONFIG_SMP | |
b5a37e96 | 992 | void *page; |
1d2f1f90 DM |
993 | |
994 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
995 | ||
b5a37e96 DM |
996 | if (use_bootmem) |
997 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
998 | else | |
999 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
1000 | ||
1d2f1f90 DM |
1001 | if (!page) { |
1002 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
1003 | prom_halt(); | |
1004 | } | |
1005 | ||
1006 | tb->cpu_mondo_block_pa = __pa(page); | |
1007 | tb->cpu_list_pa = __pa(page + 64); | |
1008 | #endif | |
1009 | } | |
1010 | ||
b5a37e96 DM |
1011 | /* Allocate and register the mondo and error queues for this cpu. */ |
1012 | void __cpuinit sun4v_init_mondo_queues(int use_bootmem) | |
ac29c11d DM |
1013 | { |
1014 | int cpu = hard_smp_processor_id(); | |
1015 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1016 | ||
b5a37e96 DM |
1017 | alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem); |
1018 | alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem); | |
1019 | alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem); | |
1020 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem); | |
1021 | alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem); | |
1022 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem); | |
1d2f1f90 | 1023 | |
b5a37e96 | 1024 | init_cpu_send_mondo_info(tb, use_bootmem); |
1d2f1f90 | 1025 | |
b5a37e96 | 1026 | sun4v_register_mondo_queues(cpu); |
ac29c11d DM |
1027 | } |
1028 | ||
1da177e4 LT |
1029 | /* Only invoked on boot processor. */ |
1030 | void __init init_IRQ(void) | |
1031 | { | |
1032 | map_prom_timers(); | |
1033 | kill_prom_timer(); | |
1034 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
1035 | ||
ac29c11d | 1036 | if (tlb_type == hypervisor) |
b5a37e96 | 1037 | sun4v_init_mondo_queues(1); |
ac29c11d | 1038 | |
1da177e4 LT |
1039 | /* We need to clear any IRQ's pending in the soft interrupt |
1040 | * registers, a spurious one could be left around from the | |
1041 | * PROM timer which we just disabled. | |
1042 | */ | |
1043 | clear_softint(get_softint()); | |
1044 | ||
1045 | /* Now that ivector table is initialized, it is safe | |
1046 | * to receive IRQ vector traps. We will normally take | |
1047 | * one or two right now, in case some device PROM used | |
1048 | * to boot us wants to speak to us. We just ignore them. | |
1049 | */ | |
1050 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
1051 | "or %%g1, %0, %%g1\n\t" | |
1052 | "wrpr %%g1, 0x0, %%pstate" | |
1053 | : /* No outputs */ | |
1054 | : "i" (PSTATE_IE) | |
1055 | : "g1"); | |
1056 | } | |
1057 | ||
1058 | static struct proc_dir_entry * root_irq_dir; | |
1059 | static struct proc_dir_entry * irq_dir [NUM_IVECS]; | |
1060 | ||
1061 | #ifdef CONFIG_SMP | |
1062 | ||
1063 | static int irq_affinity_read_proc (char *page, char **start, off_t off, | |
1064 | int count, int *eof, void *data) | |
1065 | { | |
1066 | struct ino_bucket *bp = ivector_table + (long)data; | |
12cf649f ED |
1067 | struct irq_desc *desc = bp->irq_info; |
1068 | struct irqaction *ap = desc->action; | |
1da177e4 LT |
1069 | cpumask_t mask; |
1070 | int len; | |
1071 | ||
1072 | mask = get_smpaff_in_irqaction(ap); | |
1073 | if (cpus_empty(mask)) | |
1074 | mask = cpu_online_map; | |
1075 | ||
1076 | len = cpumask_scnprintf(page, count, mask); | |
1077 | if (count - len < 2) | |
1078 | return -EINVAL; | |
1079 | len += sprintf(page + len, "\n"); | |
1080 | return len; | |
1081 | } | |
1082 | ||
1083 | static inline void set_intr_affinity(int irq, cpumask_t hw_aff) | |
1084 | { | |
1085 | struct ino_bucket *bp = ivector_table + irq; | |
12cf649f ED |
1086 | struct irq_desc *desc = bp->irq_info; |
1087 | struct irqaction *ap = desc->action; | |
1da177e4 LT |
1088 | |
1089 | /* Users specify affinity in terms of hw cpu ids. | |
1090 | * As soon as we do this, handler_irq() might see and take action. | |
1091 | */ | |
12cf649f | 1092 | put_smpaff_in_irqaction(ap, hw_aff); |
1da177e4 LT |
1093 | |
1094 | /* Migration is simply done by the next cpu to service this | |
1095 | * interrupt. | |
1096 | */ | |
1097 | } | |
1098 | ||
1099 | static int irq_affinity_write_proc (struct file *file, const char __user *buffer, | |
1100 | unsigned long count, void *data) | |
1101 | { | |
1102 | int irq = (long) data, full_count = count, err; | |
1103 | cpumask_t new_value; | |
1104 | ||
1105 | err = cpumask_parse(buffer, count, new_value); | |
1106 | ||
1107 | /* | |
1108 | * Do not allow disabling IRQs completely - it's a too easy | |
1109 | * way to make the system unusable accidentally :-) At least | |
1110 | * one online CPU still has to be targeted. | |
1111 | */ | |
1112 | cpus_and(new_value, new_value, cpu_online_map); | |
1113 | if (cpus_empty(new_value)) | |
1114 | return -EINVAL; | |
1115 | ||
1116 | set_intr_affinity(irq, new_value); | |
1117 | ||
1118 | return full_count; | |
1119 | } | |
1120 | ||
1121 | #endif | |
1122 | ||
1123 | #define MAX_NAMELEN 10 | |
1124 | ||
1125 | static void register_irq_proc (unsigned int irq) | |
1126 | { | |
1127 | char name [MAX_NAMELEN]; | |
1128 | ||
1129 | if (!root_irq_dir || irq_dir[irq]) | |
1130 | return; | |
1131 | ||
1132 | memset(name, 0, MAX_NAMELEN); | |
1133 | sprintf(name, "%x", irq); | |
1134 | ||
1135 | /* create /proc/irq/1234 */ | |
1136 | irq_dir[irq] = proc_mkdir(name, root_irq_dir); | |
1137 | ||
1138 | #ifdef CONFIG_SMP | |
1139 | /* XXX SMP affinity not supported on starfire yet. */ | |
1140 | if (this_is_starfire == 0) { | |
1141 | struct proc_dir_entry *entry; | |
1142 | ||
1143 | /* create /proc/irq/1234/smp_affinity */ | |
1144 | entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); | |
1145 | ||
1146 | if (entry) { | |
1147 | entry->nlink = 1; | |
1148 | entry->data = (void *)(long)irq; | |
1149 | entry->read_proc = irq_affinity_read_proc; | |
1150 | entry->write_proc = irq_affinity_write_proc; | |
1151 | } | |
1152 | } | |
1153 | #endif | |
1154 | } | |
1155 | ||
1156 | void init_irq_proc (void) | |
1157 | { | |
1158 | /* create /proc/irq */ | |
1159 | root_irq_dir = proc_mkdir("irq", NULL); | |
1160 | } | |
1161 |