Commit | Line | Data |
---|---|---|
4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
4a907dec | 3 | * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/sched.h> | |
10 | #include <linux/ptrace.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/signal.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/random.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/proc_fs.h> | |
21 | #include <linux/seq_file.h> | |
b5a37e96 | 22 | #include <linux/bootmem.h> |
e18e2a00 | 23 | #include <linux/irq.h> |
1da177e4 LT |
24 | |
25 | #include <asm/ptrace.h> | |
26 | #include <asm/processor.h> | |
27 | #include <asm/atomic.h> | |
28 | #include <asm/system.h> | |
29 | #include <asm/irq.h> | |
2e457ef6 | 30 | #include <asm/io.h> |
1da177e4 LT |
31 | #include <asm/sbus.h> |
32 | #include <asm/iommu.h> | |
33 | #include <asm/upa.h> | |
34 | #include <asm/oplib.h> | |
25c7581b | 35 | #include <asm/prom.h> |
1da177e4 LT |
36 | #include <asm/timer.h> |
37 | #include <asm/smp.h> | |
38 | #include <asm/starfire.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/cache.h> | |
41 | #include <asm/cpudata.h> | |
63b61452 | 42 | #include <asm/auxio.h> |
92704a1c | 43 | #include <asm/head.h> |
4a907dec | 44 | #include <asm/hypervisor.h> |
42d5f99b | 45 | #include <asm/cacheflush.h> |
1da177e4 | 46 | |
d91aa123 | 47 | #include "entry.h" |
e18e2a00 DM |
48 | |
49 | #define NUM_IVECS (IMAP_INR + 1) | |
d91aa123 | 50 | |
10397e40 | 51 | struct ino_bucket *ivector_table; |
eb2d8d60 | 52 | unsigned long ivector_table_pa; |
1da177e4 | 53 | |
42d5f99b DM |
54 | /* On several sun4u processors, it is illegal to mix bypass and |
55 | * non-bypass accesses. Therefore we access all INO buckets | |
56 | * using bypass accesses only. | |
57 | */ | |
58 | static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) | |
59 | { | |
60 | unsigned long ret; | |
61 | ||
62 | __asm__ __volatile__("ldxa [%1] %2, %0" | |
63 | : "=&r" (ret) | |
64 | : "r" (bucket_pa + | |
65 | offsetof(struct ino_bucket, | |
66 | __irq_chain_pa)), | |
67 | "i" (ASI_PHYS_USE_EC)); | |
68 | ||
69 | return ret; | |
70 | } | |
71 | ||
72 | static void bucket_clear_chain_pa(unsigned long bucket_pa) | |
73 | { | |
74 | __asm__ __volatile__("stxa %%g0, [%0] %1" | |
75 | : /* no outputs */ | |
76 | : "r" (bucket_pa + | |
77 | offsetof(struct ino_bucket, | |
78 | __irq_chain_pa)), | |
79 | "i" (ASI_PHYS_USE_EC)); | |
80 | } | |
81 | ||
82 | static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) | |
83 | { | |
84 | unsigned int ret; | |
85 | ||
86 | __asm__ __volatile__("lduwa [%1] %2, %0" | |
87 | : "=&r" (ret) | |
88 | : "r" (bucket_pa + | |
89 | offsetof(struct ino_bucket, | |
90 | __virt_irq)), | |
91 | "i" (ASI_PHYS_USE_EC)); | |
92 | ||
93 | return ret; | |
94 | } | |
95 | ||
96 | static void bucket_set_virt_irq(unsigned long bucket_pa, | |
97 | unsigned int virt_irq) | |
98 | { | |
99 | __asm__ __volatile__("stwa %0, [%1] %2" | |
100 | : /* no outputs */ | |
101 | : "r" (virt_irq), | |
102 | "r" (bucket_pa + | |
103 | offsetof(struct ino_bucket, | |
104 | __virt_irq)), | |
105 | "i" (ASI_PHYS_USE_EC)); | |
106 | } | |
107 | ||
eb2d8d60 | 108 | #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) |
1da177e4 | 109 | |
93b3238e | 110 | static struct { |
93b3238e DM |
111 | unsigned int dev_handle; |
112 | unsigned int dev_ino; | |
256c1df3 | 113 | unsigned int in_use; |
45b3f4cc | 114 | } virt_irq_table[NR_IRQS]; |
759f89e0 | 115 | static DEFINE_SPINLOCK(virt_irq_alloc_lock); |
8047e247 | 116 | |
256c1df3 | 117 | unsigned char virt_irq_alloc(unsigned int dev_handle, |
bb74b734 | 118 | unsigned int dev_ino) |
8047e247 | 119 | { |
759f89e0 | 120 | unsigned long flags; |
8047e247 DM |
121 | unsigned char ent; |
122 | ||
123 | BUILD_BUG_ON(NR_IRQS >= 256); | |
124 | ||
759f89e0 DM |
125 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
126 | ||
35a17eb6 | 127 | for (ent = 1; ent < NR_IRQS; ent++) { |
45b3f4cc | 128 | if (!virt_irq_table[ent].in_use) |
35a17eb6 DM |
129 | break; |
130 | } | |
8047e247 DM |
131 | if (ent >= NR_IRQS) { |
132 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
759f89e0 DM |
133 | ent = 0; |
134 | } else { | |
45b3f4cc DM |
135 | virt_irq_table[ent].dev_handle = dev_handle; |
136 | virt_irq_table[ent].dev_ino = dev_ino; | |
137 | virt_irq_table[ent].in_use = 1; | |
8047e247 DM |
138 | } |
139 | ||
759f89e0 | 140 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 DM |
141 | |
142 | return ent; | |
143 | } | |
144 | ||
5746c99d | 145 | #ifdef CONFIG_PCI_MSI |
759f89e0 | 146 | void virt_irq_free(unsigned int virt_irq) |
8047e247 | 147 | { |
759f89e0 | 148 | unsigned long flags; |
8047e247 | 149 | |
35a17eb6 DM |
150 | if (virt_irq >= NR_IRQS) |
151 | return; | |
152 | ||
759f89e0 DM |
153 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
154 | ||
45b3f4cc | 155 | virt_irq_table[virt_irq].in_use = 0; |
35a17eb6 | 156 | |
759f89e0 | 157 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 | 158 | } |
5746c99d | 159 | #endif |
8047e247 | 160 | |
1da177e4 | 161 | /* |
e18e2a00 | 162 | * /proc/interrupts printing: |
1da177e4 | 163 | */ |
1da177e4 LT |
164 | |
165 | int show_interrupts(struct seq_file *p, void *v) | |
166 | { | |
e18e2a00 DM |
167 | int i = *(loff_t *) v, j; |
168 | struct irqaction * action; | |
1da177e4 | 169 | unsigned long flags; |
1da177e4 | 170 | |
e18e2a00 DM |
171 | if (i == 0) { |
172 | seq_printf(p, " "); | |
173 | for_each_online_cpu(j) | |
174 | seq_printf(p, "CPU%d ",j); | |
175 | seq_putc(p, '\n'); | |
176 | } | |
177 | ||
178 | if (i < NR_IRQS) { | |
179 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
180 | action = irq_desc[i].action; | |
181 | if (!action) | |
182 | goto skip; | |
183 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
184 | #ifndef CONFIG_SMP |
185 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
186 | #else | |
e18e2a00 DM |
187 | for_each_online_cpu(j) |
188 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 189 | #endif |
d1bef4ed | 190 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
191 | seq_printf(p, " %s", action->name); |
192 | ||
193 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 194 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 195 | |
1da177e4 | 196 | seq_putc(p, '\n'); |
e18e2a00 DM |
197 | skip: |
198 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 199 | } |
1da177e4 LT |
200 | return 0; |
201 | } | |
202 | ||
ebd8c56c DM |
203 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
204 | { | |
205 | unsigned int tid; | |
206 | ||
207 | if (this_is_starfire) { | |
208 | tid = starfire_translate(imap, cpuid); | |
209 | tid <<= IMAP_TID_SHIFT; | |
210 | tid &= IMAP_TID_UPA; | |
211 | } else { | |
212 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
213 | unsigned long ver; | |
214 | ||
215 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
216 | if ((ver >> 32UL) == __JALAPENO_ID || | |
217 | (ver >> 32UL) == __SERRANO_ID) { | |
218 | tid = cpuid << IMAP_TID_SHIFT; | |
219 | tid &= IMAP_TID_JBUS; | |
220 | } else { | |
221 | unsigned int a = cpuid & 0x1f; | |
222 | unsigned int n = (cpuid >> 5) & 0x1f; | |
223 | ||
224 | tid = ((a << IMAP_AID_SHIFT) | | |
225 | (n << IMAP_NID_SHIFT)); | |
226 | tid &= (IMAP_AID_SAFARI | | |
227 | IMAP_NID_SAFARI);; | |
228 | } | |
229 | } else { | |
230 | tid = cpuid << IMAP_TID_SHIFT; | |
231 | tid &= IMAP_TID_UPA; | |
232 | } | |
233 | } | |
234 | ||
235 | return tid; | |
236 | } | |
237 | ||
e18e2a00 DM |
238 | struct irq_handler_data { |
239 | unsigned long iclr; | |
240 | unsigned long imap; | |
8047e247 | 241 | |
e18e2a00 | 242 | void (*pre_handler)(unsigned int, void *, void *); |
8d57d3ad DM |
243 | void *arg1; |
244 | void *arg2; | |
e18e2a00 | 245 | }; |
1da177e4 | 246 | |
e18e2a00 DM |
247 | #ifdef CONFIG_SMP |
248 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 249 | { |
a53da52f | 250 | cpumask_t mask = irq_desc[virt_irq].affinity; |
e18e2a00 | 251 | int cpuid; |
088dd1f8 | 252 | |
e18e2a00 DM |
253 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
254 | static int irq_rover; | |
255 | static DEFINE_SPINLOCK(irq_rover_lock); | |
256 | unsigned long flags; | |
1da177e4 | 257 | |
e18e2a00 DM |
258 | /* Round-robin distribution... */ |
259 | do_round_robin: | |
260 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 261 | |
e18e2a00 DM |
262 | while (!cpu_online(irq_rover)) { |
263 | if (++irq_rover >= NR_CPUS) | |
264 | irq_rover = 0; | |
265 | } | |
266 | cpuid = irq_rover; | |
267 | do { | |
268 | if (++irq_rover >= NR_CPUS) | |
269 | irq_rover = 0; | |
270 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 271 | |
e18e2a00 DM |
272 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
273 | } else { | |
274 | cpumask_t tmp; | |
088dd1f8 | 275 | |
e18e2a00 | 276 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 277 | |
e18e2a00 DM |
278 | if (cpus_empty(tmp)) |
279 | goto do_round_robin; | |
088dd1f8 | 280 | |
e18e2a00 | 281 | cpuid = first_cpu(tmp); |
1da177e4 | 282 | } |
088dd1f8 | 283 | |
e18e2a00 DM |
284 | return cpuid; |
285 | } | |
286 | #else | |
287 | static int irq_choose_cpu(unsigned int virt_irq) | |
288 | { | |
289 | return real_hard_smp_processor_id(); | |
1da177e4 | 290 | } |
e18e2a00 | 291 | #endif |
1da177e4 | 292 | |
e18e2a00 | 293 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 294 | { |
68c92186 | 295 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 296 | |
e18e2a00 | 297 | if (likely(data)) { |
861fe906 | 298 | unsigned long cpuid, imap, val; |
e18e2a00 | 299 | unsigned int tid; |
e3999574 | 300 | |
e18e2a00 DM |
301 | cpuid = irq_choose_cpu(virt_irq); |
302 | imap = data->imap; | |
e3999574 | 303 | |
e18e2a00 | 304 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 305 | |
861fe906 DM |
306 | val = upa_readq(imap); |
307 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
308 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
309 | val |= tid | IMAP_VALID; | |
310 | upa_writeq(val, imap); | |
e3999574 | 311 | } |
e3999574 DM |
312 | } |
313 | ||
b53bcb67 DM |
314 | static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask) |
315 | { | |
316 | sun4u_irq_enable(virt_irq); | |
317 | } | |
318 | ||
e18e2a00 | 319 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 320 | { |
68c92186 | 321 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 322 | |
e18e2a00 DM |
323 | if (likely(data)) { |
324 | unsigned long imap = data->imap; | |
6e69d606 | 325 | unsigned long tmp = upa_readq(imap); |
1da177e4 | 326 | |
e18e2a00 | 327 | tmp &= ~IMAP_VALID; |
861fe906 | 328 | upa_writeq(tmp, imap); |
088dd1f8 | 329 | } |
088dd1f8 DM |
330 | } |
331 | ||
8d57d3ad | 332 | static void sun4u_irq_eoi(unsigned int virt_irq) |
088dd1f8 | 333 | { |
68c92186 | 334 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
5a606b72 DM |
335 | struct irq_desc *desc = irq_desc + virt_irq; |
336 | ||
337 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
338 | return; | |
088dd1f8 | 339 | |
e18e2a00 | 340 | if (likely(data)) |
861fe906 | 341 | upa_writeq(ICLR_IDLE, data->iclr); |
088dd1f8 DM |
342 | } |
343 | ||
e18e2a00 | 344 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 345 | { |
45b3f4cc | 346 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 DM |
347 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
348 | int err; | |
349 | ||
350 | err = sun4v_intr_settarget(ino, cpuid); | |
351 | if (err != HV_EOK) | |
352 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
353 | "err(%d)\n", ino, cpuid, err); | |
354 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); | |
355 | if (err != HV_EOK) | |
356 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
357 | "err(%d)\n", ino, err); | |
358 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
359 | if (err != HV_EOK) | |
360 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", | |
361 | ino, err); | |
088dd1f8 DM |
362 | } |
363 | ||
b53bcb67 DM |
364 | static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask) |
365 | { | |
45b3f4cc | 366 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 DM |
367 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
368 | int err; | |
369 | ||
370 | err = sun4v_intr_settarget(ino, cpuid); | |
371 | if (err != HV_EOK) | |
372 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
373 | "err(%d)\n", ino, cpuid, err); | |
b53bcb67 DM |
374 | } |
375 | ||
e18e2a00 | 376 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 377 | { |
45b3f4cc | 378 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 | 379 | int err; |
1da177e4 | 380 | |
77182300 DM |
381 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
382 | if (err != HV_EOK) | |
383 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " | |
384 | "err(%d)\n", ino, err); | |
e18e2a00 | 385 | } |
1da177e4 | 386 | |
8d57d3ad | 387 | static void sun4v_irq_eoi(unsigned int virt_irq) |
e18e2a00 | 388 | { |
45b3f4cc | 389 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
5a606b72 | 390 | struct irq_desc *desc = irq_desc + virt_irq; |
77182300 | 391 | int err; |
5a606b72 DM |
392 | |
393 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
394 | return; | |
1da177e4 | 395 | |
77182300 DM |
396 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
397 | if (err != HV_EOK) | |
398 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
399 | "err(%d)\n", ino, err); | |
1da177e4 LT |
400 | } |
401 | ||
4a907dec DM |
402 | static void sun4v_virq_enable(unsigned int virt_irq) |
403 | { | |
77182300 DM |
404 | unsigned long cpuid, dev_handle, dev_ino; |
405 | int err; | |
406 | ||
407 | cpuid = irq_choose_cpu(virt_irq); | |
408 | ||
45b3f4cc DM |
409 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
410 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
77182300 DM |
411 | |
412 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
413 | if (err != HV_EOK) | |
414 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
415 | "err(%d)\n", | |
416 | dev_handle, dev_ino, cpuid, err); | |
417 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
418 | HV_INTR_STATE_IDLE); | |
419 | if (err != HV_EOK) | |
420 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
421 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
422 | dev_handle, dev_ino, err); | |
423 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
424 | HV_INTR_ENABLED); | |
425 | if (err != HV_EOK) | |
426 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
427 | "HV_INTR_ENABLED): err(%d)\n", | |
428 | dev_handle, dev_ino, err); | |
4a907dec DM |
429 | } |
430 | ||
b53bcb67 DM |
431 | static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask) |
432 | { | |
77182300 DM |
433 | unsigned long cpuid, dev_handle, dev_ino; |
434 | int err; | |
b53bcb67 | 435 | |
77182300 | 436 | cpuid = irq_choose_cpu(virt_irq); |
b53bcb67 | 437 | |
45b3f4cc DM |
438 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
439 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
b53bcb67 | 440 | |
77182300 DM |
441 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); |
442 | if (err != HV_EOK) | |
443 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
444 | "err(%d)\n", | |
445 | dev_handle, dev_ino, cpuid, err); | |
b53bcb67 DM |
446 | } |
447 | ||
4a907dec DM |
448 | static void sun4v_virq_disable(unsigned int virt_irq) |
449 | { | |
77182300 DM |
450 | unsigned long dev_handle, dev_ino; |
451 | int err; | |
452 | ||
45b3f4cc DM |
453 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
454 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
77182300 DM |
455 | |
456 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
457 | HV_INTR_DISABLED); | |
458 | if (err != HV_EOK) | |
459 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
460 | "HV_INTR_DISABLED): err(%d)\n", | |
461 | dev_handle, dev_ino, err); | |
4a907dec DM |
462 | } |
463 | ||
8d57d3ad | 464 | static void sun4v_virq_eoi(unsigned int virt_irq) |
4a907dec | 465 | { |
5a606b72 | 466 | struct irq_desc *desc = irq_desc + virt_irq; |
77182300 DM |
467 | unsigned long dev_handle, dev_ino; |
468 | int err; | |
5a606b72 DM |
469 | |
470 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
471 | return; | |
4a907dec | 472 | |
45b3f4cc DM |
473 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
474 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
4a907dec | 475 | |
77182300 DM |
476 | err = sun4v_vintr_set_state(dev_handle, dev_ino, |
477 | HV_INTR_STATE_IDLE); | |
478 | if (err != HV_EOK) | |
479 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
480 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
481 | dev_handle, dev_ino, err); | |
4a907dec DM |
482 | } |
483 | ||
729e7d7e | 484 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
485 | .typename = "sun4u", |
486 | .enable = sun4u_irq_enable, | |
487 | .disable = sun4u_irq_disable, | |
8d57d3ad | 488 | .eoi = sun4u_irq_eoi, |
b53bcb67 | 489 | .set_affinity = sun4u_set_affinity, |
e18e2a00 | 490 | }; |
088dd1f8 | 491 | |
729e7d7e | 492 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
493 | .typename = "sun4v", |
494 | .enable = sun4v_irq_enable, | |
495 | .disable = sun4v_irq_disable, | |
8d57d3ad | 496 | .eoi = sun4v_irq_eoi, |
b53bcb67 | 497 | .set_affinity = sun4v_set_affinity, |
e18e2a00 | 498 | }; |
1da177e4 | 499 | |
4a907dec DM |
500 | static struct irq_chip sun4v_virq = { |
501 | .typename = "vsun4v", | |
502 | .enable = sun4v_virq_enable, | |
503 | .disable = sun4v_virq_disable, | |
8d57d3ad | 504 | .eoi = sun4v_virq_eoi, |
b53bcb67 | 505 | .set_affinity = sun4v_virt_set_affinity, |
4a907dec DM |
506 | }; |
507 | ||
edde08f2 | 508 | static void pre_flow_handler(unsigned int virt_irq, |
8d57d3ad DM |
509 | struct irq_desc *desc) |
510 | { | |
511 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); | |
512 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; | |
513 | ||
514 | data->pre_handler(ino, data->arg1, data->arg2); | |
515 | ||
516 | handle_fasteoi_irq(virt_irq, desc); | |
517 | } | |
518 | ||
e18e2a00 DM |
519 | void irq_install_pre_handler(int virt_irq, |
520 | void (*func)(unsigned int, void *, void *), | |
521 | void *arg1, void *arg2) | |
522 | { | |
68c92186 | 523 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
8d57d3ad | 524 | struct irq_desc *desc = irq_desc + virt_irq; |
088dd1f8 | 525 | |
e18e2a00 | 526 | data->pre_handler = func; |
8d57d3ad DM |
527 | data->arg1 = arg1; |
528 | data->arg2 = arg2; | |
24ac26d4 | 529 | |
8d57d3ad | 530 | desc->handle_irq = pre_flow_handler; |
e18e2a00 | 531 | } |
1da177e4 | 532 | |
e18e2a00 DM |
533 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
534 | { | |
535 | struct ino_bucket *bucket; | |
536 | struct irq_handler_data *data; | |
42d5f99b | 537 | unsigned int virt_irq; |
e18e2a00 | 538 | int ino; |
1da177e4 | 539 | |
e18e2a00 | 540 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 541 | |
861fe906 | 542 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 | 543 | bucket = &ivector_table[ino]; |
42d5f99b DM |
544 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
545 | if (!virt_irq) { | |
256c1df3 | 546 | virt_irq = virt_irq_alloc(0, ino); |
42d5f99b | 547 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
548 | set_irq_chip_and_handler_name(virt_irq, |
549 | &sun4u_irq, | |
550 | handle_fasteoi_irq, | |
551 | "IVEC"); | |
fd0504c3 | 552 | } |
1da177e4 | 553 | |
42d5f99b | 554 | data = get_irq_chip_data(virt_irq); |
68c92186 | 555 | if (unlikely(data)) |
e18e2a00 | 556 | goto out; |
fd0504c3 | 557 | |
e18e2a00 DM |
558 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
559 | if (unlikely(!data)) { | |
560 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
561 | prom_halt(); | |
1da177e4 | 562 | } |
42d5f99b | 563 | set_irq_chip_data(virt_irq, data); |
1da177e4 | 564 | |
e18e2a00 DM |
565 | data->imap = imap; |
566 | data->iclr = iclr; | |
1da177e4 | 567 | |
e18e2a00 | 568 | out: |
42d5f99b | 569 | return virt_irq; |
e18e2a00 | 570 | } |
1da177e4 | 571 | |
4a907dec DM |
572 | static unsigned int sun4v_build_common(unsigned long sysino, |
573 | struct irq_chip *chip) | |
1da177e4 | 574 | { |
8047e247 | 575 | struct ino_bucket *bucket; |
e18e2a00 | 576 | struct irq_handler_data *data; |
42d5f99b | 577 | unsigned int virt_irq; |
8047e247 | 578 | |
e18e2a00 | 579 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 580 | |
e18e2a00 | 581 | bucket = &ivector_table[sysino]; |
42d5f99b DM |
582 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
583 | if (!virt_irq) { | |
256c1df3 | 584 | virt_irq = virt_irq_alloc(0, sysino); |
42d5f99b | 585 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
586 | set_irq_chip_and_handler_name(virt_irq, chip, |
587 | handle_fasteoi_irq, | |
588 | "IVEC"); | |
1da177e4 | 589 | } |
1da177e4 | 590 | |
42d5f99b | 591 | data = get_irq_chip_data(virt_irq); |
68c92186 | 592 | if (unlikely(data)) |
1da177e4 | 593 | goto out; |
1da177e4 | 594 | |
e18e2a00 DM |
595 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
596 | if (unlikely(!data)) { | |
597 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
598 | prom_halt(); | |
599 | } | |
42d5f99b | 600 | set_irq_chip_data(virt_irq, data); |
1da177e4 | 601 | |
e18e2a00 DM |
602 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
603 | * is done by hypervisor calls on sun4v platforms, not by direct | |
604 | * register accesses. | |
605 | */ | |
606 | data->imap = ~0UL; | |
607 | data->iclr = ~0UL; | |
1da177e4 | 608 | |
e18e2a00 | 609 | out: |
42d5f99b | 610 | return virt_irq; |
e18e2a00 | 611 | } |
1da177e4 | 612 | |
4a907dec DM |
613 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
614 | { | |
615 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
616 | ||
617 | return sun4v_build_common(sysino, &sun4v_irq); | |
618 | } | |
619 | ||
620 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
621 | { | |
b80e6998 DM |
622 | struct irq_handler_data *data; |
623 | struct ino_bucket *bucket; | |
624 | unsigned long hv_err, cookie; | |
42d5f99b | 625 | unsigned int virt_irq; |
b80e6998 DM |
626 | |
627 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); | |
628 | if (unlikely(!bucket)) | |
629 | return 0; | |
42d5f99b DM |
630 | __flush_dcache_range((unsigned long) bucket, |
631 | ((unsigned long) bucket + | |
632 | sizeof(struct ino_bucket))); | |
b80e6998 | 633 | |
256c1df3 | 634 | virt_irq = virt_irq_alloc(devhandle, devino); |
42d5f99b | 635 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
636 | |
637 | set_irq_chip_and_handler_name(virt_irq, &sun4v_virq, | |
638 | handle_fasteoi_irq, | |
639 | "IVEC"); | |
4a907dec | 640 | |
b80e6998 DM |
641 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
642 | if (unlikely(!data)) | |
643 | return 0; | |
4a907dec | 644 | |
42d5f99b | 645 | set_irq_chip_data(virt_irq, data); |
4a907dec | 646 | |
b80e6998 DM |
647 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
648 | * is done by hypervisor calls on sun4v platforms, not by direct | |
649 | * register accesses. | |
650 | */ | |
651 | data->imap = ~0UL; | |
652 | data->iclr = ~0UL; | |
653 | ||
654 | cookie = ~__pa(bucket); | |
655 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); | |
4a907dec DM |
656 | if (hv_err) { |
657 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
658 | "err=%lu\n", devhandle, devino, hv_err); | |
659 | prom_halt(); | |
660 | } | |
661 | ||
42d5f99b | 662 | return virt_irq; |
4a907dec DM |
663 | } |
664 | ||
e18e2a00 DM |
665 | void ack_bad_irq(unsigned int virt_irq) |
666 | { | |
45b3f4cc | 667 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
ab66a50e | 668 | |
77182300 DM |
669 | if (!ino) |
670 | ino = 0xdeadbeef; | |
6a76267f | 671 | |
e18e2a00 DM |
672 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
673 | ino, virt_irq); | |
1da177e4 LT |
674 | } |
675 | ||
1da177e4 LT |
676 | void handler_irq(int irq, struct pt_regs *regs) |
677 | { | |
eb2d8d60 | 678 | unsigned long pstate, bucket_pa; |
6d24c8dc | 679 | struct pt_regs *old_regs; |
1da177e4 | 680 | |
1da177e4 | 681 | clear_softint(1 << irq); |
1da177e4 | 682 | |
6d24c8dc | 683 | old_regs = set_irq_regs(regs); |
1da177e4 | 684 | irq_enter(); |
1da177e4 | 685 | |
a650d383 DM |
686 | /* Grab an atomic snapshot of the pending IVECs. */ |
687 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
688 | "wrpr %0, %3, %%pstate\n\t" | |
689 | "ldx [%2], %1\n\t" | |
690 | "stx %%g0, [%2]\n\t" | |
691 | "wrpr %0, 0x0, %%pstate\n\t" | |
eb2d8d60 DM |
692 | : "=&r" (pstate), "=&r" (bucket_pa) |
693 | : "r" (irq_work_pa(smp_processor_id())), | |
a650d383 DM |
694 | "i" (PSTATE_IE) |
695 | : "memory"); | |
696 | ||
eb2d8d60 | 697 | while (bucket_pa) { |
8d57d3ad | 698 | struct irq_desc *desc; |
eb2d8d60 DM |
699 | unsigned long next_pa; |
700 | unsigned int virt_irq; | |
1da177e4 | 701 | |
42d5f99b DM |
702 | next_pa = bucket_get_chain_pa(bucket_pa); |
703 | virt_irq = bucket_get_virt_irq(bucket_pa); | |
704 | bucket_clear_chain_pa(bucket_pa); | |
fd0504c3 | 705 | |
8d57d3ad DM |
706 | desc = irq_desc + virt_irq; |
707 | ||
708 | desc->handle_irq(virt_irq, desc); | |
eb2d8d60 DM |
709 | |
710 | bucket_pa = next_pa; | |
1da177e4 | 711 | } |
e18e2a00 | 712 | |
1da177e4 | 713 | irq_exit(); |
6d24c8dc | 714 | set_irq_regs(old_regs); |
1da177e4 LT |
715 | } |
716 | ||
e0204409 DM |
717 | #ifdef CONFIG_HOTPLUG_CPU |
718 | void fixup_irqs(void) | |
719 | { | |
720 | unsigned int irq; | |
721 | ||
722 | for (irq = 0; irq < NR_IRQS; irq++) { | |
723 | unsigned long flags; | |
724 | ||
725 | spin_lock_irqsave(&irq_desc[irq].lock, flags); | |
726 | if (irq_desc[irq].action && | |
727 | !(irq_desc[irq].status & IRQ_PER_CPU)) { | |
728 | if (irq_desc[irq].chip->set_affinity) | |
729 | irq_desc[irq].chip->set_affinity(irq, | |
730 | irq_desc[irq].affinity); | |
731 | } | |
732 | spin_unlock_irqrestore(&irq_desc[irq].lock, flags); | |
733 | } | |
734 | } | |
735 | #endif | |
736 | ||
cdd5186f DM |
737 | struct sun5_timer { |
738 | u64 count0; | |
739 | u64 limit0; | |
740 | u64 count1; | |
741 | u64 limit1; | |
742 | }; | |
1da177e4 | 743 | |
cdd5186f | 744 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
745 | static u64 prom_limit0, prom_limit1; |
746 | ||
747 | static void map_prom_timers(void) | |
748 | { | |
25c7581b | 749 | struct device_node *dp; |
6a23acf3 | 750 | const unsigned int *addr; |
1da177e4 LT |
751 | |
752 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
753 | dp = of_find_node_by_path("/"); |
754 | dp = dp->child; | |
755 | while (dp) { | |
756 | if (!strcmp(dp->name, "counter-timer")) | |
757 | break; | |
758 | dp = dp->sibling; | |
759 | } | |
1da177e4 LT |
760 | |
761 | /* Assume if node is not present, PROM uses different tick mechanism | |
762 | * which we should not care about. | |
763 | */ | |
25c7581b | 764 | if (!dp) { |
1da177e4 LT |
765 | prom_timers = (struct sun5_timer *) 0; |
766 | return; | |
767 | } | |
768 | ||
769 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
770 | addr = of_get_property(dp, "address", NULL); |
771 | if (!addr) { | |
1da177e4 LT |
772 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
773 | prom_timers = (struct sun5_timer *) 0; | |
774 | return; | |
775 | } | |
776 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
777 | } | |
778 | ||
779 | static void kill_prom_timer(void) | |
780 | { | |
781 | if (!prom_timers) | |
782 | return; | |
783 | ||
784 | /* Save them away for later. */ | |
785 | prom_limit0 = prom_timers->limit0; | |
786 | prom_limit1 = prom_timers->limit1; | |
787 | ||
788 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
789 | * We turn both off here just to be paranoid. | |
790 | */ | |
791 | prom_timers->limit0 = 0; | |
792 | prom_timers->limit1 = 0; | |
793 | ||
794 | /* Wheee, eat the interrupt packet too... */ | |
795 | __asm__ __volatile__( | |
796 | " mov 0x40, %%g2\n" | |
797 | " ldxa [%%g0] %0, %%g1\n" | |
798 | " ldxa [%%g2] %1, %%g1\n" | |
799 | " stxa %%g0, [%%g0] %0\n" | |
800 | " membar #Sync\n" | |
801 | : /* no outputs */ | |
802 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
803 | : "g1", "g2"); | |
804 | } | |
805 | ||
1da177e4 LT |
806 | void init_irqwork_curcpu(void) |
807 | { | |
1da177e4 LT |
808 | int cpu = hard_smp_processor_id(); |
809 | ||
eb2d8d60 | 810 | trap_block[cpu].irq_worklist_pa = 0UL; |
1da177e4 LT |
811 | } |
812 | ||
5cbc3073 DM |
813 | /* Please be very careful with register_one_mondo() and |
814 | * sun4v_register_mondo_queues(). | |
815 | * | |
816 | * On SMP this gets invoked from the CPU trampoline before | |
817 | * the cpu has fully taken over the trap table from OBP, | |
818 | * and it's kernel stack + %g6 thread register state is | |
819 | * not fully cooked yet. | |
820 | * | |
821 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
822 | * from these two routines. | |
823 | */ | |
824 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) | |
ac29c11d | 825 | { |
5cbc3073 | 826 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
827 | unsigned long status; |
828 | ||
829 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
830 | if (status != HV_EOK) { | |
831 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
832 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
833 | prom_halt(); |
834 | } | |
835 | } | |
836 | ||
b434e719 | 837 | void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 838 | { |
b5a37e96 DM |
839 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
840 | ||
5cbc3073 DM |
841 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
842 | tb->cpu_mondo_qmask); | |
843 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
844 | tb->dev_mondo_qmask); | |
845 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
846 | tb->resum_qmask); | |
847 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
848 | tb->nonresum_qmask); | |
b5a37e96 DM |
849 | } |
850 | ||
b434e719 | 851 | static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 852 | { |
5cbc3073 | 853 | unsigned long size = PAGE_ALIGN(qmask + 1); |
719023fb | 854 | void *p = __alloc_bootmem(size, size, 0); |
5cbc3073 | 855 | if (!p) { |
b5a37e96 DM |
856 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
857 | prom_halt(); | |
858 | } | |
859 | ||
5cbc3073 | 860 | *pa_ptr = __pa(p); |
b5a37e96 DM |
861 | } |
862 | ||
b434e719 | 863 | static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 864 | { |
5cbc3073 | 865 | unsigned long size = PAGE_ALIGN(qmask + 1); |
719023fb | 866 | void *p = __alloc_bootmem(size, size, 0); |
5b0c0572 | 867 | |
5cbc3073 | 868 | if (!p) { |
5b0c0572 DM |
869 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
870 | prom_halt(); | |
871 | } | |
872 | ||
5cbc3073 | 873 | *pa_ptr = __pa(p); |
5b0c0572 DM |
874 | } |
875 | ||
b434e719 | 876 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
1d2f1f90 DM |
877 | { |
878 | #ifdef CONFIG_SMP | |
b5a37e96 | 879 | void *page; |
1d2f1f90 DM |
880 | |
881 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
882 | ||
719023fb | 883 | page = alloc_bootmem_pages(PAGE_SIZE); |
1d2f1f90 DM |
884 | if (!page) { |
885 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
886 | prom_halt(); | |
887 | } | |
888 | ||
889 | tb->cpu_mondo_block_pa = __pa(page); | |
890 | tb->cpu_list_pa = __pa(page + 64); | |
891 | #endif | |
892 | } | |
893 | ||
b434e719 DM |
894 | /* Allocate mondo and error queues for all possible cpus. */ |
895 | static void __init sun4v_init_mondo_queues(void) | |
ac29c11d | 896 | { |
b434e719 | 897 | int cpu; |
ac29c11d | 898 | |
b434e719 DM |
899 | for_each_possible_cpu(cpu) { |
900 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 901 | |
b434e719 DM |
902 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
903 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); | |
904 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); | |
905 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); | |
906 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); | |
907 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, | |
908 | tb->nonresum_qmask); | |
1d2f1f90 | 909 | |
b434e719 | 910 | init_cpu_send_mondo_info(tb); |
72aff53f | 911 | } |
b434e719 DM |
912 | |
913 | /* Load up the boot cpu's entries. */ | |
914 | sun4v_register_mondo_queues(hard_smp_processor_id()); | |
ac29c11d DM |
915 | } |
916 | ||
e18e2a00 DM |
917 | static struct irqaction timer_irq_action = { |
918 | .name = "timer", | |
919 | }; | |
920 | ||
1da177e4 LT |
921 | /* Only invoked on boot processor. */ |
922 | void __init init_IRQ(void) | |
923 | { | |
10397e40 DM |
924 | unsigned long size; |
925 | ||
1da177e4 LT |
926 | map_prom_timers(); |
927 | kill_prom_timer(); | |
1da177e4 | 928 | |
10397e40 | 929 | size = sizeof(struct ino_bucket) * NUM_IVECS; |
719023fb | 930 | ivector_table = alloc_bootmem(size); |
10397e40 DM |
931 | if (!ivector_table) { |
932 | prom_printf("Fatal error, cannot allocate ivector_table\n"); | |
933 | prom_halt(); | |
934 | } | |
42d5f99b DM |
935 | __flush_dcache_range((unsigned long) ivector_table, |
936 | ((unsigned long) ivector_table) + size); | |
10397e40 DM |
937 | |
938 | ivector_table_pa = __pa(ivector_table); | |
eb2d8d60 | 939 | |
ac29c11d | 940 | if (tlb_type == hypervisor) |
b434e719 | 941 | sun4v_init_mondo_queues(); |
ac29c11d | 942 | |
1da177e4 LT |
943 | /* We need to clear any IRQ's pending in the soft interrupt |
944 | * registers, a spurious one could be left around from the | |
945 | * PROM timer which we just disabled. | |
946 | */ | |
947 | clear_softint(get_softint()); | |
948 | ||
949 | /* Now that ivector table is initialized, it is safe | |
950 | * to receive IRQ vector traps. We will normally take | |
951 | * one or two right now, in case some device PROM used | |
952 | * to boot us wants to speak to us. We just ignore them. | |
953 | */ | |
954 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
955 | "or %%g1, %0, %%g1\n\t" | |
956 | "wrpr %%g1, 0x0, %%pstate" | |
957 | : /* No outputs */ | |
958 | : "i" (PSTATE_IE) | |
959 | : "g1"); | |
1da177e4 | 960 | |
e18e2a00 | 961 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 962 | } |