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1da177e4 LT |
1 | /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $ |
2 | * irq.c: UltraSparc IRQ handling/init/registry. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/ptrace.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/signal.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/random.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/proc_fs.h> | |
23 | #include <linux/seq_file.h> | |
b5a37e96 | 24 | #include <linux/bootmem.h> |
e18e2a00 | 25 | #include <linux/irq.h> |
1da177e4 LT |
26 | |
27 | #include <asm/ptrace.h> | |
28 | #include <asm/processor.h> | |
29 | #include <asm/atomic.h> | |
30 | #include <asm/system.h> | |
31 | #include <asm/irq.h> | |
2e457ef6 | 32 | #include <asm/io.h> |
1da177e4 LT |
33 | #include <asm/sbus.h> |
34 | #include <asm/iommu.h> | |
35 | #include <asm/upa.h> | |
36 | #include <asm/oplib.h> | |
25c7581b | 37 | #include <asm/prom.h> |
1da177e4 LT |
38 | #include <asm/timer.h> |
39 | #include <asm/smp.h> | |
40 | #include <asm/starfire.h> | |
41 | #include <asm/uaccess.h> | |
42 | #include <asm/cache.h> | |
43 | #include <asm/cpudata.h> | |
63b61452 | 44 | #include <asm/auxio.h> |
92704a1c | 45 | #include <asm/head.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /* UPA nodes send interrupt packet to UltraSparc with first data reg |
48 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
49 | * delivered. We must translate this into a non-vector IRQ so we can | |
50 | * set the softint on this cpu. | |
51 | * | |
52 | * To make processing these packets efficient and race free we use | |
53 | * an array of irq buckets below. The interrupt vector handler in | |
54 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
55 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
56 | * code uses CAS to get an atomic snapshot of the list and clear it | |
57 | * at the same time. | |
e18e2a00 DM |
58 | * |
59 | * If you make changes to ino_bucket, please update hand coded assembler | |
60 | * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S | |
1da177e4 | 61 | */ |
e18e2a00 DM |
62 | struct ino_bucket { |
63 | /* Next handler in per-CPU IRQ worklist. We know that | |
64 | * bucket pointers have the high 32-bits clear, so to | |
65 | * save space we only store the bits we need. | |
66 | */ | |
67 | /*0x00*/unsigned int irq_chain; | |
1da177e4 | 68 | |
e18e2a00 DM |
69 | /* Virtual interrupt number assigned to this INO. */ |
70 | /*0x04*/unsigned int virt_irq; | |
71 | }; | |
72 | ||
73 | #define NUM_IVECS (IMAP_INR + 1) | |
1da177e4 LT |
74 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); |
75 | ||
e18e2a00 DM |
76 | #define __irq_ino(irq) \ |
77 | (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0]) | |
78 | #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq)) | |
79 | #define __irq(bucket) ((unsigned int)(unsigned long)(bucket)) | |
80 | ||
1da177e4 LT |
81 | /* This has to be in the main kernel image, it cannot be |
82 | * turned into per-cpu data. The reason is that the main | |
83 | * kernel image is locked into the TLB and this structure | |
84 | * is accessed from the vectored interrupt trap handler. If | |
85 | * access to this structure takes a TLB miss it could cause | |
86 | * the 5-level sparc v9 trap stack to overflow. | |
87 | */ | |
fd0504c3 | 88 | #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist) |
1da177e4 | 89 | |
8047e247 DM |
90 | static unsigned int virt_to_real_irq_table[NR_IRQS]; |
91 | static unsigned char virt_irq_cur = 1; | |
92 | ||
93 | static unsigned char virt_irq_alloc(unsigned int real_irq) | |
94 | { | |
95 | unsigned char ent; | |
96 | ||
97 | BUILD_BUG_ON(NR_IRQS >= 256); | |
98 | ||
99 | ent = virt_irq_cur; | |
100 | if (ent >= NR_IRQS) { | |
101 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
102 | return 0; | |
103 | } | |
104 | ||
105 | virt_irq_cur = ent + 1; | |
106 | virt_to_real_irq_table[ent] = real_irq; | |
107 | ||
108 | return ent; | |
109 | } | |
110 | ||
111 | #if 0 /* Currently unused. */ | |
112 | static unsigned char real_to_virt_irq(unsigned int real_irq) | |
113 | { | |
114 | struct ino_bucket *bucket = __bucket(real_irq); | |
115 | ||
116 | return bucket->virt_irq; | |
117 | } | |
118 | #endif | |
119 | ||
120 | static unsigned int virt_to_real_irq(unsigned char virt_irq) | |
121 | { | |
122 | return virt_to_real_irq_table[virt_irq]; | |
123 | } | |
124 | ||
1da177e4 | 125 | /* |
e18e2a00 | 126 | * /proc/interrupts printing: |
1da177e4 | 127 | */ |
1da177e4 LT |
128 | |
129 | int show_interrupts(struct seq_file *p, void *v) | |
130 | { | |
e18e2a00 DM |
131 | int i = *(loff_t *) v, j; |
132 | struct irqaction * action; | |
1da177e4 | 133 | unsigned long flags; |
1da177e4 | 134 | |
e18e2a00 DM |
135 | if (i == 0) { |
136 | seq_printf(p, " "); | |
137 | for_each_online_cpu(j) | |
138 | seq_printf(p, "CPU%d ",j); | |
139 | seq_putc(p, '\n'); | |
140 | } | |
141 | ||
142 | if (i < NR_IRQS) { | |
143 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
144 | action = irq_desc[i].action; | |
145 | if (!action) | |
146 | goto skip; | |
147 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
148 | #ifndef CONFIG_SMP |
149 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
150 | #else | |
e18e2a00 DM |
151 | for_each_online_cpu(j) |
152 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 153 | #endif |
e18e2a00 DM |
154 | seq_printf(p, " %9s", irq_desc[i].handler->typename); |
155 | seq_printf(p, " %s", action->name); | |
156 | ||
157 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 158 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 159 | |
1da177e4 | 160 | seq_putc(p, '\n'); |
e18e2a00 DM |
161 | skip: |
162 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 163 | } |
1da177e4 LT |
164 | return 0; |
165 | } | |
166 | ||
ebd8c56c DM |
167 | extern unsigned long real_hard_smp_processor_id(void); |
168 | ||
169 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) | |
170 | { | |
171 | unsigned int tid; | |
172 | ||
173 | if (this_is_starfire) { | |
174 | tid = starfire_translate(imap, cpuid); | |
175 | tid <<= IMAP_TID_SHIFT; | |
176 | tid &= IMAP_TID_UPA; | |
177 | } else { | |
178 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
179 | unsigned long ver; | |
180 | ||
181 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
182 | if ((ver >> 32UL) == __JALAPENO_ID || | |
183 | (ver >> 32UL) == __SERRANO_ID) { | |
184 | tid = cpuid << IMAP_TID_SHIFT; | |
185 | tid &= IMAP_TID_JBUS; | |
186 | } else { | |
187 | unsigned int a = cpuid & 0x1f; | |
188 | unsigned int n = (cpuid >> 5) & 0x1f; | |
189 | ||
190 | tid = ((a << IMAP_AID_SHIFT) | | |
191 | (n << IMAP_NID_SHIFT)); | |
192 | tid &= (IMAP_AID_SAFARI | | |
193 | IMAP_NID_SAFARI);; | |
194 | } | |
195 | } else { | |
196 | tid = cpuid << IMAP_TID_SHIFT; | |
197 | tid &= IMAP_TID_UPA; | |
198 | } | |
199 | } | |
200 | ||
201 | return tid; | |
202 | } | |
203 | ||
e18e2a00 DM |
204 | struct irq_handler_data { |
205 | unsigned long iclr; | |
206 | unsigned long imap; | |
8047e247 | 207 | |
e18e2a00 DM |
208 | void (*pre_handler)(unsigned int, void *, void *); |
209 | void *pre_handler_arg1; | |
210 | void *pre_handler_arg2; | |
211 | }; | |
1da177e4 | 212 | |
e18e2a00 | 213 | static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq) |
1da177e4 | 214 | { |
8047e247 | 215 | unsigned int real_irq = virt_to_real_irq(virt_irq); |
e18e2a00 | 216 | struct ino_bucket *bucket = NULL; |
1da177e4 | 217 | |
e18e2a00 DM |
218 | if (likely(real_irq)) |
219 | bucket = __bucket(real_irq); | |
8047e247 | 220 | |
e18e2a00 | 221 | return bucket; |
1da177e4 LT |
222 | } |
223 | ||
e18e2a00 DM |
224 | #ifdef CONFIG_SMP |
225 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 226 | { |
e18e2a00 DM |
227 | cpumask_t mask = irq_affinity[virt_irq]; |
228 | int cpuid; | |
088dd1f8 | 229 | |
e18e2a00 DM |
230 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
231 | static int irq_rover; | |
232 | static DEFINE_SPINLOCK(irq_rover_lock); | |
233 | unsigned long flags; | |
1da177e4 | 234 | |
e18e2a00 DM |
235 | /* Round-robin distribution... */ |
236 | do_round_robin: | |
237 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 238 | |
e18e2a00 DM |
239 | while (!cpu_online(irq_rover)) { |
240 | if (++irq_rover >= NR_CPUS) | |
241 | irq_rover = 0; | |
242 | } | |
243 | cpuid = irq_rover; | |
244 | do { | |
245 | if (++irq_rover >= NR_CPUS) | |
246 | irq_rover = 0; | |
247 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 248 | |
e18e2a00 DM |
249 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
250 | } else { | |
251 | cpumask_t tmp; | |
088dd1f8 | 252 | |
e18e2a00 | 253 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 254 | |
e18e2a00 DM |
255 | if (cpus_empty(tmp)) |
256 | goto do_round_robin; | |
088dd1f8 | 257 | |
e18e2a00 | 258 | cpuid = first_cpu(tmp); |
1da177e4 | 259 | } |
088dd1f8 | 260 | |
e18e2a00 DM |
261 | return cpuid; |
262 | } | |
263 | #else | |
264 | static int irq_choose_cpu(unsigned int virt_irq) | |
265 | { | |
266 | return real_hard_smp_processor_id(); | |
1da177e4 | 267 | } |
e18e2a00 | 268 | #endif |
1da177e4 | 269 | |
e18e2a00 | 270 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 271 | { |
e18e2a00 DM |
272 | irq_desc_t *desc = irq_desc + virt_irq; |
273 | struct irq_handler_data *data = desc->handler_data; | |
e3999574 | 274 | |
e18e2a00 DM |
275 | if (likely(data)) { |
276 | unsigned long cpuid, imap; | |
277 | unsigned int tid; | |
e3999574 | 278 | |
e18e2a00 DM |
279 | cpuid = irq_choose_cpu(virt_irq); |
280 | imap = data->imap; | |
e3999574 | 281 | |
e18e2a00 | 282 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 283 | |
e18e2a00 | 284 | upa_writel(tid | IMAP_VALID, imap); |
e3999574 | 285 | } |
e3999574 DM |
286 | } |
287 | ||
e18e2a00 | 288 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 289 | { |
e18e2a00 DM |
290 | irq_desc_t *desc = irq_desc + virt_irq; |
291 | struct irq_handler_data *data = desc->handler_data; | |
1da177e4 | 292 | |
e18e2a00 DM |
293 | if (likely(data)) { |
294 | unsigned long imap = data->imap; | |
295 | u32 tmp = upa_readl(imap); | |
1da177e4 | 296 | |
e18e2a00 DM |
297 | tmp &= ~IMAP_VALID; |
298 | upa_writel(tmp, imap); | |
088dd1f8 | 299 | } |
088dd1f8 DM |
300 | } |
301 | ||
e18e2a00 | 302 | static void sun4u_irq_end(unsigned int virt_irq) |
088dd1f8 | 303 | { |
e18e2a00 DM |
304 | irq_desc_t *desc = irq_desc + virt_irq; |
305 | struct irq_handler_data *data = desc->handler_data; | |
088dd1f8 | 306 | |
e18e2a00 DM |
307 | if (likely(data)) |
308 | upa_writel(ICLR_IDLE, data->iclr); | |
088dd1f8 DM |
309 | } |
310 | ||
e18e2a00 | 311 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 312 | { |
e18e2a00 DM |
313 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
314 | unsigned int ino = bucket - &ivector_table[0]; | |
088dd1f8 | 315 | |
e18e2a00 DM |
316 | if (likely(bucket)) { |
317 | unsigned long cpuid; | |
318 | int err; | |
088dd1f8 | 319 | |
e18e2a00 | 320 | cpuid = irq_choose_cpu(virt_irq); |
088dd1f8 | 321 | |
e18e2a00 DM |
322 | err = sun4v_intr_settarget(ino, cpuid); |
323 | if (err != HV_EOK) | |
324 | printk("sun4v_intr_settarget(%x,%lu): err(%d)\n", | |
325 | ino, cpuid, err); | |
326 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
327 | if (err != HV_EOK) | |
328 | printk("sun4v_intr_setenabled(%x): err(%d)\n", | |
329 | ino, err); | |
088dd1f8 | 330 | } |
088dd1f8 DM |
331 | } |
332 | ||
e18e2a00 | 333 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 334 | { |
e18e2a00 DM |
335 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
336 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 337 | |
e18e2a00 DM |
338 | if (likely(bucket)) { |
339 | int err; | |
1da177e4 | 340 | |
e18e2a00 DM |
341 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
342 | if (err != HV_EOK) | |
343 | printk("sun4v_intr_setenabled(%x): " | |
344 | "err(%d)\n", ino, err); | |
1da177e4 | 345 | } |
e18e2a00 | 346 | } |
1da177e4 | 347 | |
e18e2a00 DM |
348 | static void sun4v_irq_end(unsigned int virt_irq) |
349 | { | |
350 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
351 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 352 | |
e18e2a00 DM |
353 | if (likely(bucket)) { |
354 | int err; | |
1da177e4 | 355 | |
e18e2a00 DM |
356 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
357 | if (err != HV_EOK) | |
358 | printk("sun4v_intr_setstate(%x): " | |
359 | "err(%d)\n", ino, err); | |
1da177e4 | 360 | } |
1da177e4 LT |
361 | } |
362 | ||
e18e2a00 | 363 | static void run_pre_handler(unsigned int virt_irq) |
1da177e4 | 364 | { |
e18e2a00 DM |
365 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
366 | irq_desc_t *desc = irq_desc + virt_irq; | |
367 | struct irq_handler_data *data = desc->handler_data; | |
1da177e4 | 368 | |
e18e2a00 DM |
369 | if (likely(data->pre_handler)) { |
370 | data->pre_handler(__irq_ino(__irq(bucket)), | |
371 | data->pre_handler_arg1, | |
372 | data->pre_handler_arg2); | |
1da177e4 | 373 | } |
088dd1f8 DM |
374 | } |
375 | ||
e18e2a00 DM |
376 | static struct hw_interrupt_type sun4u_irq = { |
377 | .typename = "sun4u", | |
378 | .enable = sun4u_irq_enable, | |
379 | .disable = sun4u_irq_disable, | |
380 | .end = sun4u_irq_end, | |
381 | }; | |
8047e247 | 382 | |
e18e2a00 DM |
383 | static struct hw_interrupt_type sun4u_irq_ack = { |
384 | .typename = "sun4u+ack", | |
385 | .enable = sun4u_irq_enable, | |
386 | .disable = sun4u_irq_disable, | |
387 | .ack = run_pre_handler, | |
388 | .end = sun4u_irq_end, | |
389 | }; | |
088dd1f8 | 390 | |
e18e2a00 DM |
391 | static struct hw_interrupt_type sun4v_irq = { |
392 | .typename = "sun4v", | |
393 | .enable = sun4v_irq_enable, | |
394 | .disable = sun4v_irq_disable, | |
395 | .end = sun4v_irq_end, | |
396 | }; | |
1da177e4 | 397 | |
e18e2a00 DM |
398 | static struct hw_interrupt_type sun4v_irq_ack = { |
399 | .typename = "sun4v+ack", | |
400 | .enable = sun4v_irq_enable, | |
401 | .disable = sun4v_irq_disable, | |
402 | .ack = run_pre_handler, | |
403 | .end = sun4v_irq_end, | |
404 | }; | |
1da177e4 | 405 | |
e18e2a00 DM |
406 | void irq_install_pre_handler(int virt_irq, |
407 | void (*func)(unsigned int, void *, void *), | |
408 | void *arg1, void *arg2) | |
409 | { | |
410 | irq_desc_t *desc = irq_desc + virt_irq; | |
411 | struct irq_handler_data *data = desc->handler_data; | |
088dd1f8 | 412 | |
e18e2a00 DM |
413 | data->pre_handler = func; |
414 | data->pre_handler_arg1 = arg1; | |
415 | data->pre_handler_arg2 = arg2; | |
1da177e4 | 416 | |
e18e2a00 DM |
417 | desc->handler = (desc->handler == &sun4u_irq ? |
418 | &sun4u_irq_ack : &sun4v_irq_ack); | |
419 | } | |
1da177e4 | 420 | |
e18e2a00 DM |
421 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
422 | { | |
423 | struct ino_bucket *bucket; | |
424 | struct irq_handler_data *data; | |
425 | irq_desc_t *desc; | |
426 | int ino; | |
1da177e4 | 427 | |
e18e2a00 | 428 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 429 | |
e18e2a00 DM |
430 | ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
431 | bucket = &ivector_table[ino]; | |
432 | if (!bucket->virt_irq) { | |
433 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
434 | irq_desc[bucket->virt_irq].handler = &sun4u_irq; | |
fd0504c3 | 435 | } |
1da177e4 | 436 | |
e18e2a00 DM |
437 | desc = irq_desc + bucket->virt_irq; |
438 | if (unlikely(desc->handler_data)) | |
439 | goto out; | |
fd0504c3 | 440 | |
e18e2a00 DM |
441 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
442 | if (unlikely(!data)) { | |
443 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
444 | prom_halt(); | |
1da177e4 | 445 | } |
e18e2a00 | 446 | desc->handler_data = data; |
1da177e4 | 447 | |
e18e2a00 DM |
448 | data->imap = imap; |
449 | data->iclr = iclr; | |
1da177e4 | 450 | |
e18e2a00 DM |
451 | out: |
452 | return bucket->virt_irq; | |
453 | } | |
1da177e4 | 454 | |
e18e2a00 | 455 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
1da177e4 | 456 | { |
8047e247 | 457 | struct ino_bucket *bucket; |
e18e2a00 DM |
458 | struct irq_handler_data *data; |
459 | unsigned long sysino; | |
460 | irq_desc_t *desc; | |
8047e247 | 461 | |
e18e2a00 | 462 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 463 | |
e18e2a00 DM |
464 | sysino = sun4v_devino_to_sysino(devhandle, devino); |
465 | bucket = &ivector_table[sysino]; | |
466 | if (!bucket->virt_irq) { | |
467 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
468 | irq_desc[bucket->virt_irq].handler = &sun4v_irq; | |
1da177e4 | 469 | } |
1da177e4 | 470 | |
e18e2a00 DM |
471 | desc = irq_desc + bucket->virt_irq; |
472 | if (unlikely(desc->handler_data)) | |
1da177e4 | 473 | goto out; |
1da177e4 | 474 | |
e18e2a00 DM |
475 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
476 | if (unlikely(!data)) { | |
477 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
478 | prom_halt(); | |
479 | } | |
480 | desc->handler_data = data; | |
1da177e4 | 481 | |
e18e2a00 DM |
482 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
483 | * is done by hypervisor calls on sun4v platforms, not by direct | |
484 | * register accesses. | |
485 | */ | |
486 | data->imap = ~0UL; | |
487 | data->iclr = ~0UL; | |
1da177e4 | 488 | |
e18e2a00 DM |
489 | out: |
490 | return bucket->virt_irq; | |
491 | } | |
1da177e4 | 492 | |
e18e2a00 DM |
493 | void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq) |
494 | { | |
495 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
496 | unsigned long pstate; | |
497 | unsigned int *ent; | |
088dd1f8 | 498 | |
e18e2a00 DM |
499 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); |
500 | __asm__ __volatile__("wrpr %0, %1, %%pstate" | |
501 | : : "r" (pstate), "i" (PSTATE_IE)); | |
502 | ent = irq_work(smp_processor_id()); | |
503 | bucket->irq_chain = *ent; | |
504 | *ent = __irq(bucket); | |
505 | set_softint(1 << PIL_DEVICE_IRQ); | |
506 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate)); | |
507 | } | |
10951ee6 | 508 | |
e18e2a00 DM |
509 | void ack_bad_irq(unsigned int virt_irq) |
510 | { | |
511 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
512 | unsigned int ino = 0xdeadbeef; | |
ab66a50e | 513 | |
e18e2a00 DM |
514 | if (bucket) |
515 | ino = bucket - &ivector_table[0]; | |
6a76267f | 516 | |
e18e2a00 DM |
517 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
518 | ino, virt_irq); | |
1da177e4 LT |
519 | } |
520 | ||
fd0504c3 DM |
521 | #ifndef CONFIG_SMP |
522 | extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *); | |
523 | ||
524 | void timer_irq(int irq, struct pt_regs *regs) | |
525 | { | |
526 | unsigned long clr_mask = 1 << irq; | |
527 | unsigned long tick_mask = tick_ops->softint_mask; | |
528 | ||
529 | if (get_softint() & tick_mask) { | |
530 | irq = 0; | |
531 | clr_mask = tick_mask; | |
532 | } | |
533 | clear_softint(clr_mask); | |
534 | ||
535 | irq_enter(); | |
e18e2a00 | 536 | |
8047e247 | 537 | kstat_this_cpu.irqs[0]++; |
fd0504c3 | 538 | timer_interrupt(irq, NULL, regs); |
e18e2a00 | 539 | |
fd0504c3 DM |
540 | irq_exit(); |
541 | } | |
542 | #endif | |
543 | ||
1da177e4 LT |
544 | void handler_irq(int irq, struct pt_regs *regs) |
545 | { | |
e18e2a00 | 546 | struct ino_bucket *bucket; |
1da177e4 | 547 | |
1da177e4 | 548 | clear_softint(1 << irq); |
1da177e4 LT |
549 | |
550 | irq_enter(); | |
1da177e4 LT |
551 | |
552 | /* Sliiiick... */ | |
e18e2a00 DM |
553 | bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0)); |
554 | while (bucket) { | |
555 | struct ino_bucket *next = __bucket(bucket->irq_chain); | |
1da177e4 | 556 | |
e18e2a00 DM |
557 | bucket->irq_chain = 0; |
558 | __do_IRQ(bucket->virt_irq, regs); | |
fd0504c3 | 559 | |
e18e2a00 | 560 | bucket = next; |
1da177e4 | 561 | } |
e18e2a00 | 562 | |
1da177e4 LT |
563 | irq_exit(); |
564 | } | |
565 | ||
cdd5186f DM |
566 | struct sun5_timer { |
567 | u64 count0; | |
568 | u64 limit0; | |
569 | u64 count1; | |
570 | u64 limit1; | |
571 | }; | |
1da177e4 | 572 | |
cdd5186f | 573 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
574 | static u64 prom_limit0, prom_limit1; |
575 | ||
576 | static void map_prom_timers(void) | |
577 | { | |
25c7581b DM |
578 | struct device_node *dp; |
579 | unsigned int *addr; | |
1da177e4 LT |
580 | |
581 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
582 | dp = of_find_node_by_path("/"); |
583 | dp = dp->child; | |
584 | while (dp) { | |
585 | if (!strcmp(dp->name, "counter-timer")) | |
586 | break; | |
587 | dp = dp->sibling; | |
588 | } | |
1da177e4 LT |
589 | |
590 | /* Assume if node is not present, PROM uses different tick mechanism | |
591 | * which we should not care about. | |
592 | */ | |
25c7581b | 593 | if (!dp) { |
1da177e4 LT |
594 | prom_timers = (struct sun5_timer *) 0; |
595 | return; | |
596 | } | |
597 | ||
598 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
599 | addr = of_get_property(dp, "address", NULL); |
600 | if (!addr) { | |
1da177e4 LT |
601 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
602 | prom_timers = (struct sun5_timer *) 0; | |
603 | return; | |
604 | } | |
605 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
606 | } | |
607 | ||
608 | static void kill_prom_timer(void) | |
609 | { | |
610 | if (!prom_timers) | |
611 | return; | |
612 | ||
613 | /* Save them away for later. */ | |
614 | prom_limit0 = prom_timers->limit0; | |
615 | prom_limit1 = prom_timers->limit1; | |
616 | ||
617 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
618 | * We turn both off here just to be paranoid. | |
619 | */ | |
620 | prom_timers->limit0 = 0; | |
621 | prom_timers->limit1 = 0; | |
622 | ||
623 | /* Wheee, eat the interrupt packet too... */ | |
624 | __asm__ __volatile__( | |
625 | " mov 0x40, %%g2\n" | |
626 | " ldxa [%%g0] %0, %%g1\n" | |
627 | " ldxa [%%g2] %1, %%g1\n" | |
628 | " stxa %%g0, [%%g0] %0\n" | |
629 | " membar #Sync\n" | |
630 | : /* no outputs */ | |
631 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
632 | : "g1", "g2"); | |
633 | } | |
634 | ||
1da177e4 LT |
635 | void init_irqwork_curcpu(void) |
636 | { | |
1da177e4 LT |
637 | int cpu = hard_smp_processor_id(); |
638 | ||
fd0504c3 | 639 | trap_block[cpu].irq_worklist = 0; |
1da177e4 LT |
640 | } |
641 | ||
b5a37e96 | 642 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type) |
ac29c11d | 643 | { |
94f8762d DM |
644 | unsigned long num_entries = 128; |
645 | unsigned long status; | |
646 | ||
647 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
648 | if (status != HV_EOK) { | |
649 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
650 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
651 | prom_halt(); |
652 | } | |
653 | } | |
654 | ||
b5a37e96 | 655 | static void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 656 | { |
b5a37e96 DM |
657 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
658 | ||
659 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO); | |
660 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO); | |
661 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR); | |
662 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR); | |
663 | } | |
664 | ||
665 | static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem) | |
666 | { | |
667 | void *page; | |
668 | ||
669 | if (use_bootmem) | |
670 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
671 | else | |
672 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
673 | ||
674 | if (!page) { | |
675 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); | |
676 | prom_halt(); | |
677 | } | |
678 | ||
679 | *pa_ptr = __pa(page); | |
680 | } | |
681 | ||
682 | static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem) | |
683 | { | |
684 | void *page; | |
685 | ||
686 | if (use_bootmem) | |
687 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
688 | else | |
689 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
5b0c0572 DM |
690 | |
691 | if (!page) { | |
692 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); | |
693 | prom_halt(); | |
694 | } | |
695 | ||
696 | *pa_ptr = __pa(page); | |
697 | } | |
698 | ||
b5a37e96 | 699 | static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem) |
1d2f1f90 DM |
700 | { |
701 | #ifdef CONFIG_SMP | |
b5a37e96 | 702 | void *page; |
1d2f1f90 DM |
703 | |
704 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
705 | ||
b5a37e96 DM |
706 | if (use_bootmem) |
707 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
708 | else | |
709 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
710 | ||
1d2f1f90 DM |
711 | if (!page) { |
712 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
713 | prom_halt(); | |
714 | } | |
715 | ||
716 | tb->cpu_mondo_block_pa = __pa(page); | |
717 | tb->cpu_list_pa = __pa(page + 64); | |
718 | #endif | |
719 | } | |
720 | ||
b5a37e96 | 721 | /* Allocate and register the mondo and error queues for this cpu. */ |
72aff53f | 722 | void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load) |
ac29c11d | 723 | { |
ac29c11d DM |
724 | struct trap_per_cpu *tb = &trap_block[cpu]; |
725 | ||
72aff53f DM |
726 | if (alloc) { |
727 | alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem); | |
728 | alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem); | |
729 | alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem); | |
730 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem); | |
731 | alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem); | |
732 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem); | |
1d2f1f90 | 733 | |
72aff53f DM |
734 | init_cpu_send_mondo_info(tb, use_bootmem); |
735 | } | |
1d2f1f90 | 736 | |
72aff53f DM |
737 | if (load) { |
738 | if (cpu != hard_smp_processor_id()) { | |
739 | prom_printf("SUN4V: init mondo on cpu %d not %d\n", | |
740 | cpu, hard_smp_processor_id()); | |
741 | prom_halt(); | |
742 | } | |
743 | sun4v_register_mondo_queues(cpu); | |
744 | } | |
ac29c11d DM |
745 | } |
746 | ||
e18e2a00 DM |
747 | static struct irqaction timer_irq_action = { |
748 | .name = "timer", | |
749 | }; | |
750 | ||
1da177e4 LT |
751 | /* Only invoked on boot processor. */ |
752 | void __init init_IRQ(void) | |
753 | { | |
754 | map_prom_timers(); | |
755 | kill_prom_timer(); | |
756 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
757 | ||
ac29c11d | 758 | if (tlb_type == hypervisor) |
72aff53f | 759 | sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1); |
ac29c11d | 760 | |
1da177e4 LT |
761 | /* We need to clear any IRQ's pending in the soft interrupt |
762 | * registers, a spurious one could be left around from the | |
763 | * PROM timer which we just disabled. | |
764 | */ | |
765 | clear_softint(get_softint()); | |
766 | ||
767 | /* Now that ivector table is initialized, it is safe | |
768 | * to receive IRQ vector traps. We will normally take | |
769 | * one or two right now, in case some device PROM used | |
770 | * to boot us wants to speak to us. We just ignore them. | |
771 | */ | |
772 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
773 | "or %%g1, %0, %%g1\n\t" | |
774 | "wrpr %%g1, 0x0, %%pstate" | |
775 | : /* No outputs */ | |
776 | : "i" (PSTATE_IE) | |
777 | : "g1"); | |
1da177e4 | 778 | |
e18e2a00 | 779 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 780 | } |