[deliverable/linux.git] / arch / sparc64 / kernel / itlb_base.S

/* $Id: itlb_base.S,v 1.12 2002/02/09 19:49:30 davem Exp $
 * itlb_base.S:	Front end to ITLB miss replacement strategy.
 *              This is included directly into the trap table.
 *
 * Copyright (C) 1996,1998 David S. Miller (davem@redhat.com)
 * Copyright (C) 1997,1998 Jakub Jelinek   (jj@ultra.linux.cz)
 */

#if PAGE_SHIFT == 13
/*
 * To compute vpte offset, we need to do ((addr >> 13) << 3),
 * which can be optimized to (addr >> 10) if bits 10/11/12 can
 * be guaranteed to be 0 ... mmu_context.h does guarantee this
 * by only using 10 bits in the hwcontext value.
 */
#define CREATE_VPTE_OFFSET1(r1, r2) \
				srax	r1, 10, r2
#define CREATE_VPTE_OFFSET2(r1, r2) nop
#else /* PAGE_SHIFT */
#define CREATE_VPTE_OFFSET1(r1, r2) \
				srax	r1, PAGE_SHIFT, r2
#define CREATE_VPTE_OFFSET2(r1, r2) \
				sllx	r2, 3, r2
#endif /* PAGE_SHIFT */


/* Ways we can get here:
 *
 * 1) Nucleus instruction misses from module code.
 * 2) All user instruction misses.
 *
 * All real page faults merge their code paths to the
 * sparc64_realfault_common label below.
 */

/* ITLB ** ICACHE line 1: Quick user TLB misses		*/
	mov		TLB_SFSR, %g1
	ldxa		[%g1 + %g1] ASI_IMMU, %g4	! Get TAG_ACCESS
	CREATE_VPTE_OFFSET1(%g4, %g6)			! Create VPTE offset
	CREATE_VPTE_OFFSET2(%g4, %g6)			! Create VPTE offset
	ldxa		[%g3 + %g6] ASI_P, %g5		! Load VPTE
1:	brgez,pn	%g5, 3f				! Not valid, branch out
	 sethi		%hi(_PAGE_EXEC), %g4		! Delay-slot
	andcc		%g5, %g4, %g0			! Executable?

/* ITLB ** ICACHE line 2: Real faults			*/
	be,pn		%xcc, 3f			! Nope, branch.
	 nop						! Delay-slot
2:	stxa		%g5, [%g0] ASI_ITLB_DATA_IN	! Load PTE into TLB
	retry						! Trap return
3:	rdpr		%pstate, %g4			! Move into alt-globals
	wrpr		%g4, PSTATE_AG|PSTATE_MG, %pstate
	rdpr		%tpc, %g5			! And load faulting VA
	mov		FAULT_CODE_ITLB, %g4		! It was read from ITLB

/* ITLB ** ICACHE line 3: Finish faults	*/
sparc64_realfault_common:				! Called by dtlb_miss
	stb		%g4, [%g6 + TI_FAULT_CODE]
	stx		%g5, [%g6 + TI_FAULT_ADDR]
	ba,pt		%xcc, etrap			! Save state
1:	 rd		%pc, %g7			! ...
	call		do_sparc64_fault		! Call fault handler
	 add		%sp, PTREGS_OFF, %o0! Compute pt_regs arg
	ba,pt		%xcc, rtrap_clr_l6		! Restore cpu state
	 nop

/* ITLB ** ICACHE line 4: Window fixups */
winfix_trampoline:
	rdpr		%tpc, %g3			! Prepare winfixup TNPC
	or		%g3, 0x7c, %g3			! Compute branch offset
	wrpr		%g3, %tnpc			! Write it into TNPC
	done						! Do it to it
	nop
	nop
	nop
	nop

#undef CREATE_VPTE_OFFSET1
#undef CREATE_VPTE_OFFSET2
Commit	Line	Data
1da177e4 LT	1	/* $Id: itlb_base.S,v 1.12 2002/02/09 19:49:30 davem Exp $
	2	* itlb_base.S: Front end to ITLB miss replacement strategy.
	3	* This is included directly into the trap table.
	4	*
	5	* Copyright (C) 1996,1998 David S. Miller (davem@redhat.com)
	6	* Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz)
	7	*/
	8
	9	#if PAGE_SHIFT == 13
	10	/*
	11	* To compute vpte offset, we need to do ((addr >> 13) << 3),
	12	* which can be optimized to (addr >> 10) if bits 10/11/12 can
	13	* be guaranteed to be 0 ... mmu_context.h does guarantee this
	14	* by only using 10 bits in the hwcontext value.
	15	*/
	16	#define CREATE_VPTE_OFFSET1(r1, r2) \
	17	srax r1, 10, r2
c9c10830	18	#define CREATE_VPTE_OFFSET2(r1, r2) nop
1da177e4 LT	19	#else /* PAGE_SHIFT */
	20	#define CREATE_VPTE_OFFSET1(r1, r2) \
	21	srax r1, PAGE_SHIFT, r2
	22	#define CREATE_VPTE_OFFSET2(r1, r2) \
	23	sllx r2, 3, r2
1da177e4 LT	24	#endif /* PAGE_SHIFT */
	25
	26
	27	/* Ways we can get here:
	28	*
	29	* 1) Nucleus instruction misses from module code.
	30	* 2) All user instruction misses.
	31	*
	32	* All real page faults merge their code paths to the
	33	* sparc64_realfault_common label below.
	34	*/
	35
	36	/* ITLB ** ICACHE line 1: Quick user TLB misses */
c9c10830	37	mov TLB_SFSR, %g1
1da177e4 LT	38	ldxa [%g1 + %g1] ASI_IMMU, %g4 ! Get TAG_ACCESS
	39	CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset
	40	CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset
	41	ldxa [%g3 + %g6] ASI_P, %g5 ! Load VPTE
	42	1: brgez,pn %g5, 3f ! Not valid, branch out
	43	sethi %hi(_PAGE_EXEC), %g4 ! Delay-slot
	44	andcc %g5, %g4, %g0 ! Executable?
c9c10830 DM	45
c9c10830 DM	46	/* ITLB ** ICACHE line 2: Real faults */
1da177e4 LT	47	be,pn %xcc, 3f ! Nope, branch.
	48	nop ! Delay-slot
	49	2: stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load PTE into TLB
	50	retry ! Trap return
c9c10830	51	3: rdpr %pstate, %g4 ! Move into alt-globals
1da177e4 LT	52	wrpr %g4, PSTATE_AG\|PSTATE_MG, %pstate
	53	rdpr %tpc, %g5 ! And load faulting VA
	54	mov FAULT_CODE_ITLB, %g4 ! It was read from ITLB
c9c10830 DM	55
	56	/* ITLB ** ICACHE line 3: Finish faults */
	57	sparc64_realfault_common: ! Called by dtlb_miss
1da177e4 LT	58	stb %g4, [%g6 + TI_FAULT_CODE]
	59	stx %g5, [%g6 + TI_FAULT_ADDR]
	60	ba,pt %xcc, etrap ! Save state
	61	1: rd %pc, %g7 ! ...
1da177e4 LT	62	call do_sparc64_fault ! Call fault handler
	63	add %sp, PTREGS_OFF, %o0! Compute pt_regs arg
	64	ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
	65	nop
c9c10830 DM	66
c9c10830 DM	67	/* ITLB ** ICACHE line 4: Window fixups */
1da177e4 LT	68	winfix_trampoline:
1da177e4 LT	69	rdpr %tpc, %g3 ! Prepare winfixup TNPC
c9c10830	70	or %g3, 0x7c, %g3 ! Compute branch offset
1da177e4 LT	71	wrpr %g3, %tnpc ! Write it into TNPC
1da177e4 LT	72	done ! Do it to it
1da177e4 LT	73	nop
	74	nop
	75	nop
	76	nop
1da177e4 LT	77
	78	#undef CREATE_VPTE_OFFSET1
	79	#undef CREATE_VPTE_OFFSET2