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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[deliverable/linux.git] / arch / sparc64 / kernel / pci.c
CommitLineData
a2fb23af 1/* pci.c: UltraSparc PCI controller support.
1da177e4
LT		 2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
a2fb23af
DM		 6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
c57c2ffb 17#include <linux/pci.h>
35a17eb6
DM		 18#include <linux/msi.h>
19#include <linux/irq.h>
1da177e4
LT		 20#include <linux/init.h>
21
22#include <asm/uaccess.h>
1da177e4
LT		 23#include <asm/pgtable.h>
24#include <asm/irq.h>
25#include <asm/ebus.h>
e87dc350 26#include <asm/prom.h>
01f94c4a 27#include <asm/apb.h>
1da177e4 28
1e8a8cc5
DM		 29#include "pci_impl.h"
30
1da177e4
LT		 31#ifndef CONFIG_PCI
32/* A "nop" PCI implementation. */
33asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
34 unsigned long off, unsigned long len,
35 unsigned char *buf)
36{
37 return 0;
38}
39asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
40 unsigned long off, unsigned long len,
41 unsigned char *buf)
42{
43 return 0;
44}
45#else
46
47/* List of all PCI controllers found in the system. */
34768bc8 48struct pci_pbm_info *pci_pbm_root = NULL;
1da177e4 49
6c108f12
DM		 50/* Each PBM found gets a unique index. */
51int pci_num_pbms = 0;
1da177e4 52
1da177e4
LT		 53volatile int pci_poke_in_progress;
54volatile int pci_poke_cpu = -1;
55volatile int pci_poke_faulted;
56
57static DEFINE_SPINLOCK(pci_poke_lock);
58
59void pci_config_read8(u8 *addr, u8 *ret)
60{
61 unsigned long flags;
62 u8 byte;
63
64 spin_lock_irqsave(&pci_poke_lock, flags);
65 pci_poke_cpu = smp_processor_id();
66 pci_poke_in_progress = 1;
67 pci_poke_faulted = 0;
68 __asm__ __volatile__("membar #Sync\n\t"
69 "lduba [%1] %2, %0\n\t"
70 "membar #Sync"
71 : "=r" (byte)
72 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
73 : "memory");
74 pci_poke_in_progress = 0;
75 pci_poke_cpu = -1;
76 if (!pci_poke_faulted)
77 *ret = byte;
78 spin_unlock_irqrestore(&pci_poke_lock, flags);
79}
80
81void pci_config_read16(u16 *addr, u16 *ret)
82{
83 unsigned long flags;
84 u16 word;
85
86 spin_lock_irqsave(&pci_poke_lock, flags);
87 pci_poke_cpu = smp_processor_id();
88 pci_poke_in_progress = 1;
89 pci_poke_faulted = 0;
90 __asm__ __volatile__("membar #Sync\n\t"
91 "lduha [%1] %2, %0\n\t"
92 "membar #Sync"
93 : "=r" (word)
94 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
95 : "memory");
96 pci_poke_in_progress = 0;
97 pci_poke_cpu = -1;
98 if (!pci_poke_faulted)
99 *ret = word;
100 spin_unlock_irqrestore(&pci_poke_lock, flags);
101}
102
103void pci_config_read32(u32 *addr, u32 *ret)
104{
105 unsigned long flags;
106 u32 dword;
107
108 spin_lock_irqsave(&pci_poke_lock, flags);
109 pci_poke_cpu = smp_processor_id();
110 pci_poke_in_progress = 1;
111 pci_poke_faulted = 0;
112 __asm__ __volatile__("membar #Sync\n\t"
113 "lduwa [%1] %2, %0\n\t"
114 "membar #Sync"
115 : "=r" (dword)
116 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
117 : "memory");
118 pci_poke_in_progress = 0;
119 pci_poke_cpu = -1;
120 if (!pci_poke_faulted)
121 *ret = dword;
122 spin_unlock_irqrestore(&pci_poke_lock, flags);
123}
124
125void pci_config_write8(u8 *addr, u8 val)
126{
127 unsigned long flags;
128
129 spin_lock_irqsave(&pci_poke_lock, flags);
130 pci_poke_cpu = smp_processor_id();
131 pci_poke_in_progress = 1;
132 pci_poke_faulted = 0;
133 __asm__ __volatile__("membar #Sync\n\t"
134 "stba %0, [%1] %2\n\t"
135 "membar #Sync"
136 : /* no outputs */
137 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
138 : "memory");
139 pci_poke_in_progress = 0;
140 pci_poke_cpu = -1;
141 spin_unlock_irqrestore(&pci_poke_lock, flags);
142}
143
144void pci_config_write16(u16 *addr, u16 val)
145{
146 unsigned long flags;
147
148 spin_lock_irqsave(&pci_poke_lock, flags);
149 pci_poke_cpu = smp_processor_id();
150 pci_poke_in_progress = 1;
151 pci_poke_faulted = 0;
152 __asm__ __volatile__("membar #Sync\n\t"
153 "stha %0, [%1] %2\n\t"
154 "membar #Sync"
155 : /* no outputs */
156 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
157 : "memory");
158 pci_poke_in_progress = 0;
159 pci_poke_cpu = -1;
160 spin_unlock_irqrestore(&pci_poke_lock, flags);
161}
162
163void pci_config_write32(u32 *addr, u32 val)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&pci_poke_lock, flags);
168 pci_poke_cpu = smp_processor_id();
169 pci_poke_in_progress = 1;
170 pci_poke_faulted = 0;
171 __asm__ __volatile__("membar #Sync\n\t"
172 "stwa %0, [%1] %2\n\t"
173 "membar #Sync"
174 : /* no outputs */
175 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
176 : "memory");
177 pci_poke_in_progress = 0;
178 pci_poke_cpu = -1;
179 spin_unlock_irqrestore(&pci_poke_lock, flags);
180}
181
182/* Probe for all PCI controllers in the system. */
e87dc350
DM		 183extern void sabre_init(struct device_node *, const char *);
184extern void psycho_init(struct device_node *, const char *);
185extern void schizo_init(struct device_node *, const char *);
186extern void schizo_plus_init(struct device_node *, const char *);
187extern void tomatillo_init(struct device_node *, const char *);
188extern void sun4v_pci_init(struct device_node *, const char *);
861fe906 189extern void fire_pci_init(struct device_node *, const char *);
1da177e4
LT		 190
191static struct {
192 char *model_name;
e87dc350 193 void (*init)(struct device_node *, const char *);
1da177e4
LT		 194} pci_controller_table[] __initdata = {
195 { "SUNW,sabre", sabre_init },
196 { "pci108e,a000", sabre_init },
197 { "pci108e,a001", sabre_init },
198 { "SUNW,psycho", psycho_init },
199 { "pci108e,8000", psycho_init },
200 { "SUNW,schizo", schizo_init },
201 { "pci108e,8001", schizo_init },
202 { "SUNW,schizo+", schizo_plus_init },
203 { "pci108e,8002", schizo_plus_init },
204 { "SUNW,tomatillo", tomatillo_init },
205 { "pci108e,a801", tomatillo_init },
8f6a93a1 206 { "SUNW,sun4v-pci", sun4v_pci_init },
861fe906 207 { "pciex108e,80f0", fire_pci_init },
1da177e4 208};
29f139ce 209#define PCI_NUM_CONTROLLER_TYPES ARRAY_SIZE(pci_controller_table)
1da177e4 210
e87dc350 211static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 212{
213 int i;
214
215 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
216 if (!strncmp(model_name,
217 pci_controller_table[i].model_name,
218 namelen)) {
e87dc350 219 pci_controller_table[i].init(dp, model_name);
1da177e4
LT		 220 return 1;
221 }
222 }
1da177e4
LT		 223
224 return 0;
225}
226
e87dc350 227static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
1da177e4 228{
e87dc350 229 struct device_node *dp;
1da177e4
LT		 230 int count = 0;
231
e87dc350
DM		 232 for_each_node_by_name(dp, "pci") {
233 struct property *prop;
1da177e4
LT		 234 int len;
235
e87dc350
DM		 236 prop = of_find_property(dp, "model", &len);
237 if (!prop)
238 prop = of_find_property(dp, "compatible", &len);
239
240 if (prop) {
241 const char *model = prop->value;
1da177e4
LT		 242 int item_len = 0;
243
244 /* Our value may be a multi-valued string in the
245 * case of some compatible properties. For sanity,
e87dc350
DM		 246 * only try the first one.
247 */
248 while (model[item_len] && len) {
1da177e4
LT		 249 len--;
250 item_len++;
251 }
252
e87dc350 253 if (handler(model, item_len, dp))
1da177e4
LT		 254 count++;
255 }
1da177e4
LT		 256 }
257
258 return count;
259}
260
1da177e4
LT		 261/* Find each controller in the system, attach and initialize
262 * software state structure for each and link into the
34768bc8 263 * pci_pbm_root. Setup the controller enough such
1da177e4
LT		 264 * that bus scanning can be done.
265 */
266static void __init pci_controller_probe(void)
267{
268 printk("PCI: Probing for controllers.\n");
269
270 pci_controller_scan(pci_controller_init);
271}
272
5840fc66
DM		 273static int ofpci_verbose;
274
275static int __init ofpci_debug(char *str)
276{
277 int val = 0;
278
279 get_option(&str, &val);
280 if (val)
281 ofpci_verbose = 1;
282 return 1;
283}
284
285__setup("ofpci_debug=", ofpci_debug);
286
a2fb23af
DM		 287static unsigned long pci_parse_of_flags(u32 addr0)
288{
289 unsigned long flags = 0;
290
291 if (addr0 & 0x02000000) {
292 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
293 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
294 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
295 if (addr0 & 0x40000000)
296 flags |= IORESOURCE_PREFETCH
297 | PCI_BASE_ADDRESS_MEM_PREFETCH;
298 } else if (addr0 & 0x01000000)
299 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
300 return flags;
301}
302
303/* The of_device layer has translated all of the assigned-address properties
304 * into physical address resources, we only have to figure out the register
305 * mapping.
306 */
307static void pci_parse_of_addrs(struct of_device *op,
308 struct device_node *node,
309 struct pci_dev *dev)
310{
311 struct resource *op_res;
312 const u32 *addrs;
313 int proplen;
314
315 addrs = of_get_property(node, "assigned-addresses", &proplen);
316 if (!addrs)
317 return;
5840fc66
DM		 318 if (ofpci_verbose)
319 printk(" parse addresses (%d bytes) @ %p\n",
320 proplen, addrs);
a2fb23af
DM		 321 op_res = &op->resource[0];
322 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
323 struct resource *res;
324 unsigned long flags;
325 int i;
326
327 flags = pci_parse_of_flags(addrs[0]);
328 if (!flags)
329 continue;
330 i = addrs[0] & 0xff;
5840fc66
DM		 331 if (ofpci_verbose)
332 printk(" start: %lx, end: %lx, i: %x\n",
333 op_res->start, op_res->end, i);
a2fb23af
DM		 334
335 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
336 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
337 } else if (i == dev->rom_base_reg) {
338 res = &dev->resource[PCI_ROM_RESOURCE];
339 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
340 } else {
341 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
342 continue;
343 }
344 res->start = op_res->start;
345 res->end = op_res->end;
346 res->flags = flags;
347 res->name = pci_name(dev);
348 }
349}
350
351struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
352 struct device_node *node,
97b3cf05
DM		 353 struct pci_bus *bus, int devfn,
354 int host_controller)
a2fb23af
DM		 355{
356 struct dev_archdata *sd;
357 struct pci_dev *dev;
358 const char *type;
01f94c4a 359 u32 class;
a2fb23af 360
26e6385f 361 dev = alloc_pci_dev();
a2fb23af
DM		 362 if (!dev)
363 return NULL;
364
365 sd = &dev->dev.archdata;
366 sd->iommu = pbm->iommu;
367 sd->stc = &pbm->stc;
368 sd->host_controller = pbm;
369 sd->prom_node = node;
370 sd->op = of_find_device_by_node(node);
c1b1a5f1 371 sd->numa_node = pbm->numa_node;
a2fb23af 372
ad7ad57c
DM		 373 sd = &sd->op->dev.archdata;
374 sd->iommu = pbm->iommu;
375 sd->stc = &pbm->stc;
c1b1a5f1 376 sd->numa_node = pbm->numa_node;
ad7ad57c 377
a2fb23af
DM		 378 type = of_get_property(node, "device_type", NULL);
379 if (type == NULL)
380 type = "";
381
5840fc66
DM		 382 if (ofpci_verbose)
383 printk(" create device, devfn: %x, type: %s\n",
384 devfn, type);
a2fb23af
DM		 385
386 dev->bus = bus;
387 dev->sysdata = node;
388 dev->dev.parent = bus->bridge;
389 dev->dev.bus = &pci_bus_type;
390 dev->devfn = devfn;
391 dev->multifunction = 0; /* maybe a lie? */
392
97b3cf05 393 if (host_controller) {
a2d6ea01
DM		 394 if (tlb_type != hypervisor) {
395 pci_read_config_word(dev, PCI_VENDOR_ID,
396 &dev->vendor);
397 pci_read_config_word(dev, PCI_DEVICE_ID,
398 &dev->device);
399 } else {
400 dev->vendor = PCI_VENDOR_ID_SUN;
401 dev->device = 0x80f0;
402 }
97b3cf05 403 dev->cfg_size = 256;
28f57e77
DM		 404 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
405 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
406 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
97b3cf05
DM		 407 } else {
408 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
409 dev->device = of_getintprop_default(node, "device-id", 0xffff);
410 dev->subsystem_vendor =
411 of_getintprop_default(node, "subsystem-vendor-id", 0);
412 dev->subsystem_device =
413 of_getintprop_default(node, "subsystem-id", 0);
414
415 dev->cfg_size = pci_cfg_space_size(dev);
01f94c4a 416
97b3cf05
DM		 417 /* We can't actually use the firmware value, we have
418 * to read what is in the register right now. One
419 * reason is that in the case of IDE interfaces the
420 * firmware can sample the value before the the IDE
421 * interface is programmed into native mode.
422 */
423 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
424 dev->class = class >> 8;
b8a3a521 425 dev->revision = class & 0xff;
28f57e77
DM		 426
427 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
428 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
97b3cf05 429 }
5840fc66
DM		 430 if (ofpci_verbose)
431 printk(" class: 0x%x device name: %s\n",
432 dev->class, pci_name(dev));
a2fb23af 433
861fe906
DM		 434 /* I have seen IDE devices which will not respond to
435 * the bmdma simplex check reads if bus mastering is
436 * disabled.
437 */
438 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
439 pci_set_master(dev);
440
a2fb23af
DM		 441 dev->current_state = 4; /* unknown power state */
442 dev->error_state = pci_channel_io_normal;
443
97b3cf05 444 if (host_controller) {
a2fb23af
DM		 445 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
446 dev->rom_base_reg = PCI_ROM_ADDRESS1;
97b3cf05 447 dev->irq = PCI_IRQ_NONE;
a2fb23af 448 } else {
97b3cf05
DM		 449 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
450 /* a PCI-PCI bridge */
451 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
452 dev->rom_base_reg = PCI_ROM_ADDRESS1;
453 } else if (!strcmp(type, "cardbus")) {
454 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
455 } else {
456 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
457 dev->rom_base_reg = PCI_ROM_ADDRESS;
a2fb23af 458
97b3cf05
DM		 459 dev->irq = sd->op->irqs[0];
460 if (dev->irq == 0xffffffff)
461 dev->irq = PCI_IRQ_NONE;
462 }
a2fb23af 463 }
a2fb23af
DM		 464 pci_parse_of_addrs(sd->op, node, dev);
465
5840fc66
DM		 466 if (ofpci_verbose)
467 printk(" adding to system ...\n");
a2fb23af
DM		 468
469 pci_device_add(dev, bus);
470
471 return dev;
472}
473
a6009dda 474static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
01f94c4a
DM		 475{
476 u32 idx, first, last;
477
478 first = 8;
479 last = 0;
480 for (idx = 0; idx < 8; idx++) {
481 if ((map & (1 << idx)) != 0) {
482 if (first > idx)
483 first = idx;
484 if (last < idx)
485 last = idx;
486 }
487 }
488
489 *first_p = first;
490 *last_p = last;
491}
492
f16537ba
DM		 493static void pci_resource_adjust(struct resource *res,
494 struct resource *root)
0bae5f81
DM		 495{
496 res->start += root->start;
497 res->end += root->start;
498}
499
8c2786cf
DM		 500/* For PCI bus devices which lack a 'ranges' property we interrogate
501 * the config space values to set the resources, just like the generic
502 * Linux PCI probing code does.
503 */
504static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
505 struct pci_bus *bus,
506 struct pci_pbm_info *pbm)
507{
508 struct resource *res;
509 u8 io_base_lo, io_limit_lo;
510 u16 mem_base_lo, mem_limit_lo;
511 unsigned long base, limit;
512
513 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
514 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
515 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
516 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
517
518 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
519 u16 io_base_hi, io_limit_hi;
520
521 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
522 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
523 base |= (io_base_hi << 16);
524 limit |= (io_limit_hi << 16);
525 }
526
527 res = bus->resource[0];
528 if (base <= limit) {
529 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
530 if (!res->start)
531 res->start = base;
532 if (!res->end)
533 res->end = limit + 0xfff;
534 pci_resource_adjust(res, &pbm->io_space);
535 }
536
537 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
538 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
539 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
540 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
541
542 res = bus->resource[1];
543 if (base <= limit) {
544 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
545 IORESOURCE_MEM);
546 res->start = base;
547 res->end = limit + 0xfffff;
548 pci_resource_adjust(res, &pbm->mem_space);
549 }
550
551 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
552 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
553 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
554 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
555
556 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
557 u32 mem_base_hi, mem_limit_hi;
558
559 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
560 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
561
562 /*
563 * Some bridges set the base > limit by default, and some
564 * (broken) BIOSes do not initialize them. If we find
565 * this, just assume they are not being used.
566 */
567 if (mem_base_hi <= mem_limit_hi) {
568 base |= ((long) mem_base_hi) << 32;
569 limit |= ((long) mem_limit_hi) << 32;
570 }
571 }
572
573 res = bus->resource[2];
574 if (base <= limit) {
575 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
576 IORESOURCE_MEM | IORESOURCE_PREFETCH);
577 res->start = base;
578 res->end = limit + 0xfffff;
579 pci_resource_adjust(res, &pbm->mem_space);
580 }
581}
582
01f94c4a
DM		 583/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
584 * a proper 'ranges' property.
585 */
a6009dda
DM		 586static void __devinit apb_fake_ranges(struct pci_dev *dev,
587 struct pci_bus *bus,
588 struct pci_pbm_info *pbm)
01f94c4a
DM		 589{
590 struct resource *res;
591 u32 first, last;
592 u8 map;
593
594 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
595 apb_calc_first_last(map, &first, &last);
596 res = bus->resource[0];
597 res->start = (first << 21);
598 res->end = (last << 21) + ((1 << 21) - 1);
599 res->flags = IORESOURCE_IO;
0bae5f81 600 pci_resource_adjust(res, &pbm->io_space);
01f94c4a
DM		 601
602 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
603 apb_calc_first_last(map, &first, &last);
604 res = bus->resource[1];
605 res->start = (first << 21);
606 res->end = (last << 21) + ((1 << 21) - 1);
607 res->flags = IORESOURCE_MEM;
0bae5f81 608 pci_resource_adjust(res, &pbm->mem_space);
01f94c4a
DM		 609}
610
a6009dda
DM		 611static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
612 struct device_node *node,
613 struct pci_bus *bus);
a2fb23af
DM		 614
615#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
616
a6009dda
DM		 617static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
618 struct device_node *node,
619 struct pci_dev *dev)
a2fb23af
DM		 620{
621 struct pci_bus *bus;
622 const u32 *busrange, *ranges;
01f94c4a 623 int len, i, simba;
a2fb23af
DM		 624 struct resource *res;
625 unsigned int flags;
626 u64 size;
627
5840fc66
DM		 628 if (ofpci_verbose)
629 printk("of_scan_pci_bridge(%s)\n", node->full_name);
a2fb23af
DM		 630
631 /* parse bus-range property */
632 busrange = of_get_property(node, "bus-range", &len);
633 if (busrange == NULL || len != 8) {
634 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
635 node->full_name);
636 return;
637 }
638 ranges = of_get_property(node, "ranges", &len);
01f94c4a 639 simba = 0;
a2fb23af 640 if (ranges == NULL) {
a165b420 641 const char *model = of_get_property(node, "model", NULL);
8c2786cf 642 if (model && !strcmp(model, "SUNW,simba"))
01f94c4a 643 simba = 1;
a2fb23af
DM		 644 }
645
646 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
647 if (!bus) {
648 printk(KERN_ERR "Failed to create pci bus for %s\n",
649 node->full_name);
650 return;
651 }
652
653 bus->primary = dev->bus->number;
654 bus->subordinate = busrange[1];
655 bus->bridge_ctl = 0;
656
01f94c4a 657 /* parse ranges property, or cook one up by hand for Simba */
a2fb23af
DM		 658 /* PCI #address-cells == 3 and #size-cells == 2 always */
659 res = &dev->resource[PCI_BRIDGE_RESOURCES];
660 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
661 res->flags = 0;
662 bus->resource[i] = res;
663 ++res;
664 }
01f94c4a
DM		 665 if (simba) {
666 apb_fake_ranges(dev, bus, pbm);
8c2786cf
DM		 667 goto after_ranges;
668 } else if (ranges == NULL) {
669 pci_cfg_fake_ranges(dev, bus, pbm);
670 goto after_ranges;
01f94c4a 671 }
a2fb23af
DM		 672 i = 1;
673 for (; len >= 32; len -= 32, ranges += 8) {
674 struct resource *root;
675
676 flags = pci_parse_of_flags(ranges[0]);
677 size = GET_64BIT(ranges, 6);
678 if (flags == 0 || size == 0)
679 continue;
680 if (flags & IORESOURCE_IO) {
681 res = bus->resource[0];
682 if (res->flags) {
683 printk(KERN_ERR "PCI: ignoring extra I/O range"
684 " for bridge %s\n", node->full_name);
685 continue;
686 }
687 root = &pbm->io_space;
688 } else {
689 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
690 printk(KERN_ERR "PCI: too many memory ranges"
691 " for bridge %s\n", node->full_name);
692 continue;
693 }
694 res = bus->resource[i];
695 ++i;
696 root = &pbm->mem_space;
697 }
698
699 res->start = GET_64BIT(ranges, 1);
700 res->end = res->start + size - 1;
701 res->flags = flags;
702
703 /* Another way to implement this would be to add an of_device
704 * layer routine that can calculate a resource for a given
705 * range property value in a PCI device.
706 */
0bae5f81 707 pci_resource_adjust(res, root);
a2fb23af 708 }
8c2786cf 709after_ranges:
a2fb23af
DM		 710 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
711 bus->number);
5840fc66
DM		 712 if (ofpci_verbose)
713 printk(" bus name: %s\n", bus->name);
a2fb23af
DM		 714
715 pci_of_scan_bus(pbm, node, bus);
716}
717
a6009dda
DM		 718static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
719 struct device_node *node,
720 struct pci_bus *bus)
a2fb23af
DM		 721{
722 struct device_node *child;
723 const u32 *reg;
2cc7345f 724 int reglen, devfn, prev_devfn;
a2fb23af
DM		 725 struct pci_dev *dev;
726
5840fc66
DM		 727 if (ofpci_verbose)
728 printk("PCI: scan_bus[%s] bus no %d\n",
729 node->full_name, bus->number);
a2fb23af
DM		 730
731 child = NULL;
2cc7345f 732 prev_devfn = -1;
a2fb23af 733 while ((child = of_get_next_child(node, child)) != NULL) {
5840fc66
DM		 734 if (ofpci_verbose)
735 printk(" * %s\n", child->full_name);
a2fb23af
DM		 736 reg = of_get_property(child, "reg", &reglen);
737 if (reg == NULL || reglen < 20)
738 continue;
2cc7345f 739
a2fb23af
DM		 740 devfn = (reg[0] >> 8) & 0xff;
741
2cc7345f
DM		 742 /* This is a workaround for some device trees
743 * which list PCI devices twice. On the V100
744 * for example, device number 3 is listed twice.
745 * Once as "pm" and once again as "lomp".
746 */
747 if (devfn == prev_devfn)
748 continue;
749 prev_devfn = devfn;
750
a2fb23af 751 /* create a new pci_dev for this device */
97b3cf05 752 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
a2fb23af
DM		 753 if (!dev)
754 continue;
5840fc66
DM		 755 if (ofpci_verbose)
756 printk("PCI: dev header type: %x\n",
757 dev->hdr_type);
a2fb23af
DM		 758
759 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
760 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
761 of_scan_pci_bridge(pbm, child, dev);
762 }
763}
764
765static ssize_t
766show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
767{
768 struct pci_dev *pdev;
769 struct device_node *dp;
770
771 pdev = to_pci_dev(dev);
772 dp = pdev->dev.archdata.prom_node;
773
774 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
775}
776
777static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
778
779static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
780{
781 struct pci_dev *dev;
a378fd0e 782 struct pci_bus *child_bus;
a2fb23af
DM		 783 int err;
784
785 list_for_each_entry(dev, &bus->devices, bus_list) {
786 /* we don't really care if we can create this file or
787 * not, but we need to assign the result of the call
788 * or the world will fall under alien invasion and
789 * everybody will be frozen on a spaceship ready to be
790 * eaten on alpha centauri by some green and jelly
791 * humanoid.
792 */
793 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
794 }
a378fd0e
DM		 795 list_for_each_entry(child_bus, &bus->children, node)
796 pci_bus_register_of_sysfs(child_bus);
a2fb23af
DM		 797}
798
97b3cf05
DM		 799int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
800 unsigned int devfn,
801 int where, int size,
802 u32 *value)
803{
804 static u8 fake_pci_config[] = {
805 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
a2d6ea01 806 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
97b3cf05
DM		 807 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
808 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
809 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
810 0x00, /* Cacheline: 0x00 */
811 0x40, /* Latency: 0x40 */
812 0x00, /* Header-Type: 0x00 normal */
813 };
814
815 *value = 0;
816 if (where >= 0 && where < sizeof(fake_pci_config) &&
817 (where + size) >= 0 &&
818 (where + size) < sizeof(fake_pci_config) &&
819 size <= sizeof(u32)) {
820 while (size--) {
821 *value <<= 8;
822 *value |= fake_pci_config[where + size];
823 }
824 }
825
826 return PCIBIOS_SUCCESSFUL;
827}
828
829int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
830 unsigned int devfn,
831 int where, int size,
832 u32 value)
833{
834 return PCIBIOS_SUCCESSFUL;
835}
836
a6009dda 837struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
a2fb23af 838{
a2fb23af 839 struct device_node *node = pbm->prom_node;
97b3cf05 840 struct pci_dev *host_pdev;
a2fb23af
DM		 841 struct pci_bus *bus;
842
843 printk("PCI: Scanning PBM %s\n", node->full_name);
844
845 /* XXX parent device? XXX */
f1cd8de2 846 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
a2fb23af
DM		 847 if (!bus) {
848 printk(KERN_ERR "Failed to create bus for %s\n",
849 node->full_name);
850 return NULL;
851 }
852 bus->secondary = pbm->pci_first_busno;
853 bus->subordinate = pbm->pci_last_busno;
854
855 bus->resource[0] = &pbm->io_space;
856 bus->resource[1] = &pbm->mem_space;
857
97b3cf05
DM		 858 /* Create the dummy host bridge and link it in. */
859 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
860 bus->self = host_pdev;
861
a2fb23af
DM		 862 pci_of_scan_bus(pbm, node, bus);
863 pci_bus_add_devices(bus);
864 pci_bus_register_of_sysfs(bus);
865
866 return bus;
867}
868
1da177e4
LT		 869static void __init pci_scan_each_controller_bus(void)
870{
34768bc8 871 struct pci_pbm_info *pbm;
1da177e4 872
34768bc8
DM		 873 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
874 pbm->scan_bus(pbm);
1da177e4
LT		 875}
876
1da177e4
LT		 877extern void power_init(void);
878
879static int __init pcibios_init(void)
880{
881 pci_controller_probe();
34768bc8 882 if (pci_pbm_root == NULL)
1da177e4
LT		 883 return 0;
884
885 pci_scan_each_controller_bus();
886
1da177e4 887 ebus_init();
1da177e4
LT		 888 power_init();
889
890 return 0;
891}
892
893subsys_initcall(pcibios_init);
894
f6b45da1 895void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
1da177e4
LT		 896{
897 struct pci_pbm_info *pbm = pbus->sysdata;
898
899 /* Generic PCI bus probing sets these to point at
900 * &io{port,mem}_resouce which is wrong for us.
901 */
902 pbus->resource[0] = &pbm->io_space;
903 pbus->resource[1] = &pbm->mem_space;
904}
905
085ae41f 906struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
1da177e4
LT		 907{
908 struct pci_pbm_info *pbm = pdev->bus->sysdata;
085ae41f 909 struct resource *root = NULL;
1da177e4 910
085ae41f 911 if (r->flags & IORESOURCE_IO)
1da177e4 912 root = &pbm->io_space;
085ae41f 913 if (r->flags & IORESOURCE_MEM)
1da177e4
LT		 914 root = &pbm->mem_space;
915
085ae41f 916 return root;
1da177e4
LT		 917}
918
919void pcibios_update_irq(struct pci_dev *pdev, int irq)
920{
921}
922
923void pcibios_align_resource(void *data, struct resource *res,
e31dd6e4 924 resource_size_t size, resource_size_t align)
1da177e4
LT		 925{
926}
927
a2fb23af 928int pcibios_enable_device(struct pci_dev *dev, int mask)
1da177e4 929{
a2fb23af
DM		 930 u16 cmd, oldcmd;
931 int i;
932
933 pci_read_config_word(dev, PCI_COMMAND, &cmd);
934 oldcmd = cmd;
935
936 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
937 struct resource *res = &dev->resource[i];
938
939 /* Only set up the requested stuff */
940 if (!(mask & (1<<i)))
941 continue;
942
943 if (res->flags & IORESOURCE_IO)
944 cmd |= PCI_COMMAND_IO;
945 if (res->flags & IORESOURCE_MEM)
946 cmd |= PCI_COMMAND_MEMORY;
947 }
948
949 if (cmd != oldcmd) {
950 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
951 pci_name(dev), cmd);
952 /* Enable the appropriate bits in the PCI command register. */
953 pci_write_config_word(dev, PCI_COMMAND, cmd);
954 }
1da177e4
LT		 955 return 0;
956}
957
958void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
959 struct resource *res)
960{
961 struct pci_pbm_info *pbm = pdev->bus->sysdata;
962 struct resource zero_res, *root;
963
964 zero_res.start = 0;
965 zero_res.end = 0;
966 zero_res.flags = res->flags;
967
968 if (res->flags & IORESOURCE_IO)
969 root = &pbm->io_space;
970 else
971 root = &pbm->mem_space;
972
0bae5f81 973 pci_resource_adjust(&zero_res, root);
1da177e4
LT		 974
975 region->start = res->start - zero_res.start;
976 region->end = res->end - zero_res.start;
977}
5fdfd42e 978EXPORT_SYMBOL(pcibios_resource_to_bus);
1da177e4
LT		 979
980void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
981 struct pci_bus_region *region)
982{
983 struct pci_pbm_info *pbm = pdev->bus->sysdata;
984 struct resource *root;
985
986 res->start = region->start;
987 res->end = region->end;
988
989 if (res->flags & IORESOURCE_IO)
990 root = &pbm->io_space;
991 else
992 root = &pbm->mem_space;
993
0bae5f81 994 pci_resource_adjust(res, root);
1da177e4 995}
41290c14 996EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 997
f6b45da1 998char * __devinit pcibios_setup(char *str)
1da177e4 999{
1da177e4
LT		 1000 return str;
1001}
1002
1003/* Platform support for /proc/bus/pci/X/Y mmap()s. */
1004
1005/* If the user uses a host-bridge as the PCI device, he may use
1006 * this to perform a raw mmap() of the I/O or MEM space behind
1007 * that controller.
1008 *
1009 * This can be useful for execution of x86 PCI bios initialization code
1010 * on a PCI card, like the xfree86 int10 stuff does.
1011 */
1012static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1013 enum pci_mmap_state mmap_state)
1014{
a2fb23af 1015 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1da177e4
LT		 1016 unsigned long space_size, user_offset, user_size;
1017
3875c5c0
DM		 1018 if (mmap_state == pci_mmap_io) {
1019 space_size = (pbm->io_space.end -
1020 pbm->io_space.start) + 1;
1da177e4 1021 } else {
3875c5c0
DM		 1022 space_size = (pbm->mem_space.end -
1023 pbm->mem_space.start) + 1;
1da177e4
LT		 1024 }
1025
1026 /* Make sure the request is in range. */
1027 user_offset = vma->vm_pgoff << PAGE_SHIFT;
1028 user_size = vma->vm_end - vma->vm_start;
1029
1030 if (user_offset >= space_size ||
1031 (user_offset + user_size) > space_size)
1032 return -EINVAL;
1033
3875c5c0
DM		 1034 if (mmap_state == pci_mmap_io) {
1035 vma->vm_pgoff = (pbm->io_space.start +
1036 user_offset) >> PAGE_SHIFT;
1da177e4 1037 } else {
3875c5c0
DM		 1038 vma->vm_pgoff = (pbm->mem_space.start +
1039 user_offset) >> PAGE_SHIFT;
1da177e4
LT		 1040 }
1041
1042 return 0;
1043}
1044
bbe0b5eb
DM		 1045/* Adjust vm_pgoff of VMA such that it is the physical page offset
1046 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
1da177e4
LT		 1047 *
1048 * Basically, the user finds the base address for his device which he wishes
1049 * to mmap. They read the 32-bit value from the config space base register,
1050 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1051 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1052 *
1053 * Returns negative error code on failure, zero on success.
1054 */
bbe0b5eb
DM		 1055static int __pci_mmap_make_offset(struct pci_dev *pdev,
1056 struct vm_area_struct *vma,
1da177e4
LT		 1057 enum pci_mmap_state mmap_state)
1058{
bbe0b5eb
DM		 1059 unsigned long user_paddr, user_size;
1060 int i, err;
1da177e4 1061
bbe0b5eb
DM		 1062 /* First compute the physical address in vma->vm_pgoff,
1063 * making sure the user offset is within range in the
1064 * appropriate PCI space.
1065 */
1066 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
1067 if (err)
1068 return err;
1069
1070 /* If this is a mapping on a host bridge, any address
1071 * is OK.
1072 */
1073 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1074 return err;
1075
1076 /* Otherwise make sure it's in the range for one of the
1077 * device's resources.
1078 */
1079 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
1080 user_size = vma->vm_end - vma->vm_start;
1da177e4 1081
1da177e4 1082 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
bbe0b5eb 1083 struct resource *rp = &pdev->resource[i];
1da177e4
LT		 1084
1085 /* Active? */
1086 if (!rp->flags)
1087 continue;
1088
1089 /* Same type? */
1090 if (i == PCI_ROM_RESOURCE) {
1091 if (mmap_state != pci_mmap_mem)
1092 continue;
1093 } else {
1094 if ((mmap_state == pci_mmap_io &&
1095 (rp->flags & IORESOURCE_IO) == 0) ||
1096 (mmap_state == pci_mmap_mem &&
1097 (rp->flags & IORESOURCE_MEM) == 0))
1098 continue;
1099 }
1100
bbe0b5eb
DM		 1101 if ((rp->start <= user_paddr) &&
1102 (user_paddr + user_size) <= (rp->end + 1UL))
1103 break;
1da177e4
LT		 1104 }
1105
bbe0b5eb 1106 if (i > PCI_ROM_RESOURCE)
1da177e4
LT		 1107 return -EINVAL;
1108
1da177e4
LT		 1109 return 0;
1110}
1111
1112/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1113 * mapping.
1114 */
1115static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1116 enum pci_mmap_state mmap_state)
1117{
1118 vma->vm_flags |= (VM_IO | VM_RESERVED);
1119}
1120
1121/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1122 * device mapping.
1123 */
1124static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1125 enum pci_mmap_state mmap_state)
1126{
a7a6cac2 1127 /* Our io_remap_pfn_range takes care of this, do nothing. */
1da177e4
LT		 1128}
1129
1130/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1131 * for this architecture. The region in the process to map is described by vm_start
1132 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1133 * The pci device structure is provided so that architectures may make mapping
1134 * decisions on a per-device or per-bus basis.
1135 *
1136 * Returns a negative error code on failure, zero on success.
1137 */
1138int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1139 enum pci_mmap_state mmap_state,
1140 int write_combine)
1141{
1142 int ret;
1143
1144 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1145 if (ret < 0)
1146 return ret;
1147
1148 __pci_mmap_set_flags(dev, vma, mmap_state);
1149 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1150
14778d90 1151 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4
LT		 1152 ret = io_remap_pfn_range(vma, vma->vm_start,
1153 vma->vm_pgoff,
1154 vma->vm_end - vma->vm_start,
1155 vma->vm_page_prot);
1156 if (ret)
1157 return ret;
1158
1da177e4
LT		 1159 return 0;
1160}
1161
c1b1a5f1
DM		 1162#ifdef CONFIG_NUMA
1163int pcibus_to_node(struct pci_bus *pbus)
1164{
1165 struct pci_pbm_info *pbm = pbus->sysdata;
1166
1167 return pbm->numa_node;
1168}
1169EXPORT_SYMBOL(pcibus_to_node);
1170#endif
1171
1da177e4
LT		 1172/* Return the domain nuber for this pci bus */
1173
1174int pci_domain_nr(struct pci_bus *pbus)
1175{
1176 struct pci_pbm_info *pbm = pbus->sysdata;
1177 int ret;
1178
1179 if (pbm == NULL || pbm->parent == NULL) {
1180 ret = -ENXIO;
1181 } else {
6c108f12 1182 ret = pbm->index;
1da177e4
LT		 1183 }
1184
1185 return ret;
1186}
1187EXPORT_SYMBOL(pci_domain_nr);
1188
35a17eb6
DM		 1189#ifdef CONFIG_PCI_MSI
1190int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1191{
a2fb23af 1192 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
e9870c4c 1193 int virt_irq;
35a17eb6 1194
e9870c4c 1195 if (!pbm->setup_msi_irq)
35a17eb6
DM		 1196 return -EINVAL;
1197
e9870c4c 1198 return pbm->setup_msi_irq(&virt_irq, pdev, desc);
35a17eb6
DM		 1199}
1200
1201void arch_teardown_msi_irq(unsigned int virt_irq)
1202{
abfd336c 1203 struct msi_desc *entry = get_irq_msi(virt_irq);
35a17eb6 1204 struct pci_dev *pdev = entry->dev;
a2fb23af 1205 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6 1206
e9870c4c 1207 if (!pbm->teardown_msi_irq)
35a17eb6
DM		 1208 return;
1209
e9870c4c 1210 return pbm->teardown_msi_irq(virt_irq, pdev);
35a17eb6
DM		 1211}
1212#endif /* !(CONFIG_PCI_MSI) */
1213
f6d0f9ea
DM		 1214struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1215{
a2fb23af 1216 return pdev->dev.archdata.prom_node;
f6d0f9ea
DM		 1217}
1218EXPORT_SYMBOL(pci_device_to_OF_node);
1219
ad7ad57c
DM		 1220static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
1221{
1222 struct pci_dev *ali_isa_bridge;
1223 u8 val;
1224
1225 /* ALI sound chips generate 31-bits of DMA, a special register
1226 * determines what bit 31 is emitted as.
1227 */
1228 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
1229 PCI_DEVICE_ID_AL_M1533,
1230 NULL);
1231
1232 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
1233 if (set_bit)
1234 val |= 0x01;
1235 else
1236 val &= ~0x01;
1237 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
1238 pci_dev_put(ali_isa_bridge);
1239}
1240
1241int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
1242{
1243 u64 dma_addr_mask;
1244
1245 if (pdev == NULL) {
1246 dma_addr_mask = 0xffffffff;
1247 } else {
1248 struct iommu *iommu = pdev->dev.archdata.iommu;
1249
1250 dma_addr_mask = iommu->dma_addr_mask;
1251
1252 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1253 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1254 device_mask == 0x7fffffff) {
1255 ali_sound_dma_hack(pdev,
1256 (dma_addr_mask & 0x80000000) != 0);
1257 return 1;
1258 }
1259 }
1260
1261 if (device_mask >= (1UL << 32UL))
1262 return 0;
1263
1264 return (device_mask & dma_addr_mask) == dma_addr_mask;
1265}
1266
bcea1db1
DM		 1267void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1268 const struct resource *rp, resource_size_t *start,
1269 resource_size_t *end)
1270{
1271 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1272 unsigned long offset;
1273
1274 if (rp->flags & IORESOURCE_IO)
1275 offset = pbm->io_space.start;
1276 else
1277 offset = pbm->mem_space.start;
1278
1279 *start = rp->start - offset;
1280 *end = rp->end - offset;
1281}
1282
1da177e4 1283#endif /* !(CONFIG_PCI) */
Linux kernel - Deliverables
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