Commit | Line | Data |
---|---|---|
a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
c57c2ffb | 17 | #include <linux/pci.h> |
35a17eb6 DM |
18 | #include <linux/msi.h> |
19 | #include <linux/irq.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | ||
22 | #include <asm/uaccess.h> | |
1da177e4 LT |
23 | #include <asm/pgtable.h> |
24 | #include <asm/irq.h> | |
25 | #include <asm/ebus.h> | |
26 | #include <asm/isa.h> | |
e87dc350 | 27 | #include <asm/prom.h> |
01f94c4a | 28 | #include <asm/apb.h> |
1da177e4 | 29 | |
1e8a8cc5 DM |
30 | #include "pci_impl.h" |
31 | ||
1da177e4 LT |
32 | unsigned long pci_memspace_mask = 0xffffffffUL; |
33 | ||
34 | #ifndef CONFIG_PCI | |
35 | /* A "nop" PCI implementation. */ | |
36 | asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn, | |
37 | unsigned long off, unsigned long len, | |
38 | unsigned char *buf) | |
39 | { | |
40 | return 0; | |
41 | } | |
42 | asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, | |
43 | unsigned long off, unsigned long len, | |
44 | unsigned char *buf) | |
45 | { | |
46 | return 0; | |
47 | } | |
48 | #else | |
49 | ||
50 | /* List of all PCI controllers found in the system. */ | |
34768bc8 | 51 | struct pci_pbm_info *pci_pbm_root = NULL; |
1da177e4 | 52 | |
6c108f12 DM |
53 | /* Each PBM found gets a unique index. */ |
54 | int pci_num_pbms = 0; | |
1da177e4 | 55 | |
1da177e4 LT |
56 | volatile int pci_poke_in_progress; |
57 | volatile int pci_poke_cpu = -1; | |
58 | volatile int pci_poke_faulted; | |
59 | ||
60 | static DEFINE_SPINLOCK(pci_poke_lock); | |
61 | ||
62 | void pci_config_read8(u8 *addr, u8 *ret) | |
63 | { | |
64 | unsigned long flags; | |
65 | u8 byte; | |
66 | ||
67 | spin_lock_irqsave(&pci_poke_lock, flags); | |
68 | pci_poke_cpu = smp_processor_id(); | |
69 | pci_poke_in_progress = 1; | |
70 | pci_poke_faulted = 0; | |
71 | __asm__ __volatile__("membar #Sync\n\t" | |
72 | "lduba [%1] %2, %0\n\t" | |
73 | "membar #Sync" | |
74 | : "=r" (byte) | |
75 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
76 | : "memory"); | |
77 | pci_poke_in_progress = 0; | |
78 | pci_poke_cpu = -1; | |
79 | if (!pci_poke_faulted) | |
80 | *ret = byte; | |
81 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
82 | } | |
83 | ||
84 | void pci_config_read16(u16 *addr, u16 *ret) | |
85 | { | |
86 | unsigned long flags; | |
87 | u16 word; | |
88 | ||
89 | spin_lock_irqsave(&pci_poke_lock, flags); | |
90 | pci_poke_cpu = smp_processor_id(); | |
91 | pci_poke_in_progress = 1; | |
92 | pci_poke_faulted = 0; | |
93 | __asm__ __volatile__("membar #Sync\n\t" | |
94 | "lduha [%1] %2, %0\n\t" | |
95 | "membar #Sync" | |
96 | : "=r" (word) | |
97 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
98 | : "memory"); | |
99 | pci_poke_in_progress = 0; | |
100 | pci_poke_cpu = -1; | |
101 | if (!pci_poke_faulted) | |
102 | *ret = word; | |
103 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
104 | } | |
105 | ||
106 | void pci_config_read32(u32 *addr, u32 *ret) | |
107 | { | |
108 | unsigned long flags; | |
109 | u32 dword; | |
110 | ||
111 | spin_lock_irqsave(&pci_poke_lock, flags); | |
112 | pci_poke_cpu = smp_processor_id(); | |
113 | pci_poke_in_progress = 1; | |
114 | pci_poke_faulted = 0; | |
115 | __asm__ __volatile__("membar #Sync\n\t" | |
116 | "lduwa [%1] %2, %0\n\t" | |
117 | "membar #Sync" | |
118 | : "=r" (dword) | |
119 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
120 | : "memory"); | |
121 | pci_poke_in_progress = 0; | |
122 | pci_poke_cpu = -1; | |
123 | if (!pci_poke_faulted) | |
124 | *ret = dword; | |
125 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
126 | } | |
127 | ||
128 | void pci_config_write8(u8 *addr, u8 val) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&pci_poke_lock, flags); | |
133 | pci_poke_cpu = smp_processor_id(); | |
134 | pci_poke_in_progress = 1; | |
135 | pci_poke_faulted = 0; | |
136 | __asm__ __volatile__("membar #Sync\n\t" | |
137 | "stba %0, [%1] %2\n\t" | |
138 | "membar #Sync" | |
139 | : /* no outputs */ | |
140 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
141 | : "memory"); | |
142 | pci_poke_in_progress = 0; | |
143 | pci_poke_cpu = -1; | |
144 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
145 | } | |
146 | ||
147 | void pci_config_write16(u16 *addr, u16 val) | |
148 | { | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&pci_poke_lock, flags); | |
152 | pci_poke_cpu = smp_processor_id(); | |
153 | pci_poke_in_progress = 1; | |
154 | pci_poke_faulted = 0; | |
155 | __asm__ __volatile__("membar #Sync\n\t" | |
156 | "stha %0, [%1] %2\n\t" | |
157 | "membar #Sync" | |
158 | : /* no outputs */ | |
159 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
160 | : "memory"); | |
161 | pci_poke_in_progress = 0; | |
162 | pci_poke_cpu = -1; | |
163 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
164 | } | |
165 | ||
166 | void pci_config_write32(u32 *addr, u32 val) | |
167 | { | |
168 | unsigned long flags; | |
169 | ||
170 | spin_lock_irqsave(&pci_poke_lock, flags); | |
171 | pci_poke_cpu = smp_processor_id(); | |
172 | pci_poke_in_progress = 1; | |
173 | pci_poke_faulted = 0; | |
174 | __asm__ __volatile__("membar #Sync\n\t" | |
175 | "stwa %0, [%1] %2\n\t" | |
176 | "membar #Sync" | |
177 | : /* no outputs */ | |
178 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
179 | : "memory"); | |
180 | pci_poke_in_progress = 0; | |
181 | pci_poke_cpu = -1; | |
182 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
183 | } | |
184 | ||
185 | /* Probe for all PCI controllers in the system. */ | |
e87dc350 DM |
186 | extern void sabre_init(struct device_node *, const char *); |
187 | extern void psycho_init(struct device_node *, const char *); | |
188 | extern void schizo_init(struct device_node *, const char *); | |
189 | extern void schizo_plus_init(struct device_node *, const char *); | |
190 | extern void tomatillo_init(struct device_node *, const char *); | |
191 | extern void sun4v_pci_init(struct device_node *, const char *); | |
861fe906 | 192 | extern void fire_pci_init(struct device_node *, const char *); |
1da177e4 LT |
193 | |
194 | static struct { | |
195 | char *model_name; | |
e87dc350 | 196 | void (*init)(struct device_node *, const char *); |
1da177e4 LT |
197 | } pci_controller_table[] __initdata = { |
198 | { "SUNW,sabre", sabre_init }, | |
199 | { "pci108e,a000", sabre_init }, | |
200 | { "pci108e,a001", sabre_init }, | |
201 | { "SUNW,psycho", psycho_init }, | |
202 | { "pci108e,8000", psycho_init }, | |
203 | { "SUNW,schizo", schizo_init }, | |
204 | { "pci108e,8001", schizo_init }, | |
205 | { "SUNW,schizo+", schizo_plus_init }, | |
206 | { "pci108e,8002", schizo_plus_init }, | |
207 | { "SUNW,tomatillo", tomatillo_init }, | |
208 | { "pci108e,a801", tomatillo_init }, | |
8f6a93a1 | 209 | { "SUNW,sun4v-pci", sun4v_pci_init }, |
861fe906 | 210 | { "pciex108e,80f0", fire_pci_init }, |
1da177e4 LT |
211 | }; |
212 | #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \ | |
213 | sizeof(pci_controller_table[0])) | |
214 | ||
e87dc350 | 215 | static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
216 | { |
217 | int i; | |
218 | ||
219 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
220 | if (!strncmp(model_name, | |
221 | pci_controller_table[i].model_name, | |
222 | namelen)) { | |
e87dc350 | 223 | pci_controller_table[i].init(dp, model_name); |
1da177e4 LT |
224 | return 1; |
225 | } | |
226 | } | |
1da177e4 LT |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
e87dc350 | 231 | static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
232 | { |
233 | int i; | |
234 | ||
235 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
236 | if (!strncmp(model_name, | |
237 | pci_controller_table[i].model_name, | |
238 | namelen)) { | |
239 | return 1; | |
240 | } | |
241 | } | |
242 | return 0; | |
243 | } | |
244 | ||
e87dc350 | 245 | static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *)) |
1da177e4 | 246 | { |
e87dc350 | 247 | struct device_node *dp; |
1da177e4 LT |
248 | int count = 0; |
249 | ||
e87dc350 DM |
250 | for_each_node_by_name(dp, "pci") { |
251 | struct property *prop; | |
1da177e4 LT |
252 | int len; |
253 | ||
e87dc350 DM |
254 | prop = of_find_property(dp, "model", &len); |
255 | if (!prop) | |
256 | prop = of_find_property(dp, "compatible", &len); | |
257 | ||
258 | if (prop) { | |
259 | const char *model = prop->value; | |
1da177e4 LT |
260 | int item_len = 0; |
261 | ||
262 | /* Our value may be a multi-valued string in the | |
263 | * case of some compatible properties. For sanity, | |
e87dc350 DM |
264 | * only try the first one. |
265 | */ | |
266 | while (model[item_len] && len) { | |
1da177e4 LT |
267 | len--; |
268 | item_len++; | |
269 | } | |
270 | ||
e87dc350 | 271 | if (handler(model, item_len, dp)) |
1da177e4 LT |
272 | count++; |
273 | } | |
1da177e4 LT |
274 | } |
275 | ||
276 | return count; | |
277 | } | |
278 | ||
279 | ||
280 | /* Is there some PCI controller in the system? */ | |
281 | int __init pcic_present(void) | |
282 | { | |
283 | return pci_controller_scan(pci_is_controller); | |
284 | } | |
285 | ||
c6e87566 | 286 | const struct pci_iommu_ops *pci_iommu_ops; |
8f6a93a1 DM |
287 | EXPORT_SYMBOL(pci_iommu_ops); |
288 | ||
c6e87566 | 289 | extern const struct pci_iommu_ops pci_sun4u_iommu_ops, |
8f6a93a1 DM |
290 | pci_sun4v_iommu_ops; |
291 | ||
1da177e4 LT |
292 | /* Find each controller in the system, attach and initialize |
293 | * software state structure for each and link into the | |
34768bc8 | 294 | * pci_pbm_root. Setup the controller enough such |
1da177e4 LT |
295 | * that bus scanning can be done. |
296 | */ | |
297 | static void __init pci_controller_probe(void) | |
298 | { | |
8f6a93a1 DM |
299 | if (tlb_type == hypervisor) |
300 | pci_iommu_ops = &pci_sun4v_iommu_ops; | |
301 | else | |
302 | pci_iommu_ops = &pci_sun4u_iommu_ops; | |
303 | ||
1da177e4 LT |
304 | printk("PCI: Probing for controllers.\n"); |
305 | ||
306 | pci_controller_scan(pci_controller_init); | |
307 | } | |
308 | ||
5840fc66 DM |
309 | static int ofpci_verbose; |
310 | ||
311 | static int __init ofpci_debug(char *str) | |
312 | { | |
313 | int val = 0; | |
314 | ||
315 | get_option(&str, &val); | |
316 | if (val) | |
317 | ofpci_verbose = 1; | |
318 | return 1; | |
319 | } | |
320 | ||
321 | __setup("ofpci_debug=", ofpci_debug); | |
322 | ||
a2fb23af DM |
323 | static unsigned long pci_parse_of_flags(u32 addr0) |
324 | { | |
325 | unsigned long flags = 0; | |
326 | ||
327 | if (addr0 & 0x02000000) { | |
328 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
329 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
330 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
331 | if (addr0 & 0x40000000) | |
332 | flags |= IORESOURCE_PREFETCH | |
333 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
334 | } else if (addr0 & 0x01000000) | |
335 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
336 | return flags; | |
337 | } | |
338 | ||
339 | /* The of_device layer has translated all of the assigned-address properties | |
340 | * into physical address resources, we only have to figure out the register | |
341 | * mapping. | |
342 | */ | |
343 | static void pci_parse_of_addrs(struct of_device *op, | |
344 | struct device_node *node, | |
345 | struct pci_dev *dev) | |
346 | { | |
347 | struct resource *op_res; | |
348 | const u32 *addrs; | |
349 | int proplen; | |
350 | ||
351 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
352 | if (!addrs) | |
353 | return; | |
5840fc66 DM |
354 | if (ofpci_verbose) |
355 | printk(" parse addresses (%d bytes) @ %p\n", | |
356 | proplen, addrs); | |
a2fb23af DM |
357 | op_res = &op->resource[0]; |
358 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
359 | struct resource *res; | |
360 | unsigned long flags; | |
361 | int i; | |
362 | ||
363 | flags = pci_parse_of_flags(addrs[0]); | |
364 | if (!flags) | |
365 | continue; | |
366 | i = addrs[0] & 0xff; | |
5840fc66 DM |
367 | if (ofpci_verbose) |
368 | printk(" start: %lx, end: %lx, i: %x\n", | |
369 | op_res->start, op_res->end, i); | |
a2fb23af DM |
370 | |
371 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
372 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
373 | } else if (i == dev->rom_base_reg) { | |
374 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
375 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
376 | } else { | |
377 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
378 | continue; | |
379 | } | |
380 | res->start = op_res->start; | |
381 | res->end = op_res->end; | |
382 | res->flags = flags; | |
383 | res->name = pci_name(dev); | |
384 | } | |
385 | } | |
386 | ||
387 | struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, | |
388 | struct device_node *node, | |
97b3cf05 DM |
389 | struct pci_bus *bus, int devfn, |
390 | int host_controller) | |
a2fb23af DM |
391 | { |
392 | struct dev_archdata *sd; | |
393 | struct pci_dev *dev; | |
394 | const char *type; | |
01f94c4a | 395 | u32 class; |
a2fb23af | 396 | |
26e6385f | 397 | dev = alloc_pci_dev(); |
a2fb23af DM |
398 | if (!dev) |
399 | return NULL; | |
400 | ||
401 | sd = &dev->dev.archdata; | |
402 | sd->iommu = pbm->iommu; | |
403 | sd->stc = &pbm->stc; | |
404 | sd->host_controller = pbm; | |
405 | sd->prom_node = node; | |
406 | sd->op = of_find_device_by_node(node); | |
407 | sd->msi_num = 0xffffffff; | |
408 | ||
409 | type = of_get_property(node, "device_type", NULL); | |
410 | if (type == NULL) | |
411 | type = ""; | |
412 | ||
5840fc66 DM |
413 | if (ofpci_verbose) |
414 | printk(" create device, devfn: %x, type: %s\n", | |
415 | devfn, type); | |
a2fb23af DM |
416 | |
417 | dev->bus = bus; | |
418 | dev->sysdata = node; | |
419 | dev->dev.parent = bus->bridge; | |
420 | dev->dev.bus = &pci_bus_type; | |
421 | dev->devfn = devfn; | |
422 | dev->multifunction = 0; /* maybe a lie? */ | |
423 | ||
97b3cf05 DM |
424 | if (host_controller) { |
425 | dev->vendor = 0x108e; | |
426 | dev->device = 0x8000; | |
427 | dev->subsystem_vendor = 0x0000; | |
428 | dev->subsystem_device = 0x0000; | |
429 | dev->cfg_size = 256; | |
28f57e77 DM |
430 | dev->class = PCI_CLASS_BRIDGE_HOST << 8; |
431 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
432 | 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 DM |
433 | } else { |
434 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); | |
435 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
436 | dev->subsystem_vendor = | |
437 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
438 | dev->subsystem_device = | |
439 | of_getintprop_default(node, "subsystem-id", 0); | |
440 | ||
441 | dev->cfg_size = pci_cfg_space_size(dev); | |
01f94c4a | 442 | |
97b3cf05 DM |
443 | /* We can't actually use the firmware value, we have |
444 | * to read what is in the register right now. One | |
445 | * reason is that in the case of IDE interfaces the | |
446 | * firmware can sample the value before the the IDE | |
447 | * interface is programmed into native mode. | |
448 | */ | |
449 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
450 | dev->class = class >> 8; | |
28f57e77 DM |
451 | |
452 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
453 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 | 454 | } |
5840fc66 DM |
455 | if (ofpci_verbose) |
456 | printk(" class: 0x%x device name: %s\n", | |
457 | dev->class, pci_name(dev)); | |
a2fb23af | 458 | |
861fe906 DM |
459 | /* I have seen IDE devices which will not respond to |
460 | * the bmdma simplex check reads if bus mastering is | |
461 | * disabled. | |
462 | */ | |
463 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
464 | pci_set_master(dev); | |
465 | ||
a2fb23af DM |
466 | dev->current_state = 4; /* unknown power state */ |
467 | dev->error_state = pci_channel_io_normal; | |
468 | ||
97b3cf05 | 469 | if (host_controller) { |
a2fb23af DM |
470 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
471 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
97b3cf05 | 472 | dev->irq = PCI_IRQ_NONE; |
a2fb23af | 473 | } else { |
97b3cf05 DM |
474 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
475 | /* a PCI-PCI bridge */ | |
476 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
477 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
478 | } else if (!strcmp(type, "cardbus")) { | |
479 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
480 | } else { | |
481 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
482 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 483 | |
97b3cf05 DM |
484 | dev->irq = sd->op->irqs[0]; |
485 | if (dev->irq == 0xffffffff) | |
486 | dev->irq = PCI_IRQ_NONE; | |
487 | } | |
a2fb23af | 488 | } |
a2fb23af DM |
489 | pci_parse_of_addrs(sd->op, node, dev); |
490 | ||
5840fc66 DM |
491 | if (ofpci_verbose) |
492 | printk(" adding to system ...\n"); | |
a2fb23af DM |
493 | |
494 | pci_device_add(dev, bus); | |
495 | ||
496 | return dev; | |
497 | } | |
498 | ||
a6009dda | 499 | static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
01f94c4a DM |
500 | { |
501 | u32 idx, first, last; | |
502 | ||
503 | first = 8; | |
504 | last = 0; | |
505 | for (idx = 0; idx < 8; idx++) { | |
506 | if ((map & (1 << idx)) != 0) { | |
507 | if (first > idx) | |
508 | first = idx; | |
509 | if (last < idx) | |
510 | last = idx; | |
511 | } | |
512 | } | |
513 | ||
514 | *first_p = first; | |
515 | *last_p = last; | |
516 | } | |
517 | ||
f16537ba DM |
518 | static void pci_resource_adjust(struct resource *res, |
519 | struct resource *root) | |
0bae5f81 DM |
520 | { |
521 | res->start += root->start; | |
522 | res->end += root->start; | |
523 | } | |
524 | ||
01f94c4a DM |
525 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
526 | * a proper 'ranges' property. | |
527 | */ | |
a6009dda DM |
528 | static void __devinit apb_fake_ranges(struct pci_dev *dev, |
529 | struct pci_bus *bus, | |
530 | struct pci_pbm_info *pbm) | |
01f94c4a DM |
531 | { |
532 | struct resource *res; | |
533 | u32 first, last; | |
534 | u8 map; | |
535 | ||
536 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
537 | apb_calc_first_last(map, &first, &last); | |
538 | res = bus->resource[0]; | |
539 | res->start = (first << 21); | |
540 | res->end = (last << 21) + ((1 << 21) - 1); | |
541 | res->flags = IORESOURCE_IO; | |
0bae5f81 | 542 | pci_resource_adjust(res, &pbm->io_space); |
01f94c4a DM |
543 | |
544 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
545 | apb_calc_first_last(map, &first, &last); | |
546 | res = bus->resource[1]; | |
547 | res->start = (first << 21); | |
548 | res->end = (last << 21) + ((1 << 21) - 1); | |
549 | res->flags = IORESOURCE_MEM; | |
0bae5f81 | 550 | pci_resource_adjust(res, &pbm->mem_space); |
01f94c4a DM |
551 | } |
552 | ||
a6009dda DM |
553 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
554 | struct device_node *node, | |
555 | struct pci_bus *bus); | |
a2fb23af DM |
556 | |
557 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
558 | ||
a6009dda DM |
559 | static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, |
560 | struct device_node *node, | |
561 | struct pci_dev *dev) | |
a2fb23af DM |
562 | { |
563 | struct pci_bus *bus; | |
564 | const u32 *busrange, *ranges; | |
01f94c4a | 565 | int len, i, simba; |
a2fb23af DM |
566 | struct resource *res; |
567 | unsigned int flags; | |
568 | u64 size; | |
569 | ||
5840fc66 DM |
570 | if (ofpci_verbose) |
571 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
a2fb23af DM |
572 | |
573 | /* parse bus-range property */ | |
574 | busrange = of_get_property(node, "bus-range", &len); | |
575 | if (busrange == NULL || len != 8) { | |
576 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
577 | node->full_name); | |
578 | return; | |
579 | } | |
580 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 581 | simba = 0; |
a2fb23af | 582 | if (ranges == NULL) { |
a165b420 | 583 | const char *model = of_get_property(node, "model", NULL); |
01f94c4a DM |
584 | if (model && !strcmp(model, "SUNW,simba")) { |
585 | simba = 1; | |
586 | } else { | |
587 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", | |
588 | node->full_name); | |
589 | return; | |
590 | } | |
a2fb23af DM |
591 | } |
592 | ||
593 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
594 | if (!bus) { | |
595 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
596 | node->full_name); | |
597 | return; | |
598 | } | |
599 | ||
600 | bus->primary = dev->bus->number; | |
601 | bus->subordinate = busrange[1]; | |
602 | bus->bridge_ctl = 0; | |
603 | ||
01f94c4a | 604 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
605 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
606 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
607 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
608 | res->flags = 0; | |
609 | bus->resource[i] = res; | |
610 | ++res; | |
611 | } | |
01f94c4a DM |
612 | if (simba) { |
613 | apb_fake_ranges(dev, bus, pbm); | |
614 | goto simba_cont; | |
615 | } | |
a2fb23af DM |
616 | i = 1; |
617 | for (; len >= 32; len -= 32, ranges += 8) { | |
618 | struct resource *root; | |
619 | ||
620 | flags = pci_parse_of_flags(ranges[0]); | |
621 | size = GET_64BIT(ranges, 6); | |
622 | if (flags == 0 || size == 0) | |
623 | continue; | |
624 | if (flags & IORESOURCE_IO) { | |
625 | res = bus->resource[0]; | |
626 | if (res->flags) { | |
627 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
628 | " for bridge %s\n", node->full_name); | |
629 | continue; | |
630 | } | |
631 | root = &pbm->io_space; | |
632 | } else { | |
633 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
634 | printk(KERN_ERR "PCI: too many memory ranges" | |
635 | " for bridge %s\n", node->full_name); | |
636 | continue; | |
637 | } | |
638 | res = bus->resource[i]; | |
639 | ++i; | |
640 | root = &pbm->mem_space; | |
641 | } | |
642 | ||
643 | res->start = GET_64BIT(ranges, 1); | |
644 | res->end = res->start + size - 1; | |
645 | res->flags = flags; | |
646 | ||
647 | /* Another way to implement this would be to add an of_device | |
648 | * layer routine that can calculate a resource for a given | |
649 | * range property value in a PCI device. | |
650 | */ | |
0bae5f81 | 651 | pci_resource_adjust(res, root); |
a2fb23af | 652 | } |
01f94c4a | 653 | simba_cont: |
a2fb23af DM |
654 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
655 | bus->number); | |
5840fc66 DM |
656 | if (ofpci_verbose) |
657 | printk(" bus name: %s\n", bus->name); | |
a2fb23af DM |
658 | |
659 | pci_of_scan_bus(pbm, node, bus); | |
660 | } | |
661 | ||
a6009dda DM |
662 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
663 | struct device_node *node, | |
664 | struct pci_bus *bus) | |
a2fb23af DM |
665 | { |
666 | struct device_node *child; | |
667 | const u32 *reg; | |
668 | int reglen, devfn; | |
669 | struct pci_dev *dev; | |
670 | ||
5840fc66 DM |
671 | if (ofpci_verbose) |
672 | printk("PCI: scan_bus[%s] bus no %d\n", | |
673 | node->full_name, bus->number); | |
a2fb23af DM |
674 | |
675 | child = NULL; | |
676 | while ((child = of_get_next_child(node, child)) != NULL) { | |
5840fc66 DM |
677 | if (ofpci_verbose) |
678 | printk(" * %s\n", child->full_name); | |
a2fb23af DM |
679 | reg = of_get_property(child, "reg", ®len); |
680 | if (reg == NULL || reglen < 20) | |
681 | continue; | |
682 | devfn = (reg[0] >> 8) & 0xff; | |
683 | ||
684 | /* create a new pci_dev for this device */ | |
97b3cf05 | 685 | dev = of_create_pci_dev(pbm, child, bus, devfn, 0); |
a2fb23af DM |
686 | if (!dev) |
687 | continue; | |
5840fc66 DM |
688 | if (ofpci_verbose) |
689 | printk("PCI: dev header type: %x\n", | |
690 | dev->hdr_type); | |
a2fb23af DM |
691 | |
692 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
693 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
694 | of_scan_pci_bridge(pbm, child, dev); | |
695 | } | |
696 | } | |
697 | ||
698 | static ssize_t | |
699 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
700 | { | |
701 | struct pci_dev *pdev; | |
702 | struct device_node *dp; | |
703 | ||
704 | pdev = to_pci_dev(dev); | |
705 | dp = pdev->dev.archdata.prom_node; | |
706 | ||
707 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
708 | } | |
709 | ||
710 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
711 | ||
712 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
713 | { | |
714 | struct pci_dev *dev; | |
a378fd0e | 715 | struct pci_bus *child_bus; |
a2fb23af DM |
716 | int err; |
717 | ||
718 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
719 | /* we don't really care if we can create this file or | |
720 | * not, but we need to assign the result of the call | |
721 | * or the world will fall under alien invasion and | |
722 | * everybody will be frozen on a spaceship ready to be | |
723 | * eaten on alpha centauri by some green and jelly | |
724 | * humanoid. | |
725 | */ | |
726 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
727 | } | |
a378fd0e DM |
728 | list_for_each_entry(child_bus, &bus->children, node) |
729 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
730 | } |
731 | ||
97b3cf05 DM |
732 | int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev, |
733 | unsigned int devfn, | |
734 | int where, int size, | |
735 | u32 *value) | |
736 | { | |
737 | static u8 fake_pci_config[] = { | |
738 | 0x8e, 0x10, /* Vendor: 0x108e (Sun) */ | |
739 | 0x00, 0x80, /* Device: 0x8000 (PBM) */ | |
740 | 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */ | |
741 | 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */ | |
742 | 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */ | |
743 | 0x00, /* Cacheline: 0x00 */ | |
744 | 0x40, /* Latency: 0x40 */ | |
745 | 0x00, /* Header-Type: 0x00 normal */ | |
746 | }; | |
747 | ||
748 | *value = 0; | |
749 | if (where >= 0 && where < sizeof(fake_pci_config) && | |
750 | (where + size) >= 0 && | |
751 | (where + size) < sizeof(fake_pci_config) && | |
752 | size <= sizeof(u32)) { | |
753 | while (size--) { | |
754 | *value <<= 8; | |
755 | *value |= fake_pci_config[where + size]; | |
756 | } | |
757 | } | |
758 | ||
759 | return PCIBIOS_SUCCESSFUL; | |
760 | } | |
761 | ||
762 | int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev, | |
763 | unsigned int devfn, | |
764 | int where, int size, | |
765 | u32 value) | |
766 | { | |
767 | return PCIBIOS_SUCCESSFUL; | |
768 | } | |
769 | ||
a6009dda | 770 | struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm) |
a2fb23af | 771 | { |
a2fb23af | 772 | struct device_node *node = pbm->prom_node; |
97b3cf05 | 773 | struct pci_dev *host_pdev; |
a2fb23af DM |
774 | struct pci_bus *bus; |
775 | ||
776 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
777 | ||
778 | /* XXX parent device? XXX */ | |
f1cd8de2 | 779 | bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm); |
a2fb23af DM |
780 | if (!bus) { |
781 | printk(KERN_ERR "Failed to create bus for %s\n", | |
782 | node->full_name); | |
783 | return NULL; | |
784 | } | |
785 | bus->secondary = pbm->pci_first_busno; | |
786 | bus->subordinate = pbm->pci_last_busno; | |
787 | ||
788 | bus->resource[0] = &pbm->io_space; | |
789 | bus->resource[1] = &pbm->mem_space; | |
790 | ||
97b3cf05 DM |
791 | /* Create the dummy host bridge and link it in. */ |
792 | host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1); | |
793 | bus->self = host_pdev; | |
794 | ||
a2fb23af DM |
795 | pci_of_scan_bus(pbm, node, bus); |
796 | pci_bus_add_devices(bus); | |
797 | pci_bus_register_of_sysfs(bus); | |
798 | ||
799 | return bus; | |
800 | } | |
801 | ||
1da177e4 LT |
802 | static void __init pci_scan_each_controller_bus(void) |
803 | { | |
34768bc8 | 804 | struct pci_pbm_info *pbm; |
1da177e4 | 805 | |
34768bc8 DM |
806 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) |
807 | pbm->scan_bus(pbm); | |
1da177e4 LT |
808 | } |
809 | ||
1da177e4 LT |
810 | extern void power_init(void); |
811 | ||
812 | static int __init pcibios_init(void) | |
813 | { | |
814 | pci_controller_probe(); | |
34768bc8 | 815 | if (pci_pbm_root == NULL) |
1da177e4 LT |
816 | return 0; |
817 | ||
818 | pci_scan_each_controller_bus(); | |
819 | ||
1da177e4 LT |
820 | isa_init(); |
821 | ebus_init(); | |
1da177e4 LT |
822 | power_init(); |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | subsys_initcall(pcibios_init); | |
828 | ||
f6b45da1 | 829 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 LT |
830 | { |
831 | struct pci_pbm_info *pbm = pbus->sysdata; | |
832 | ||
833 | /* Generic PCI bus probing sets these to point at | |
834 | * &io{port,mem}_resouce which is wrong for us. | |
835 | */ | |
836 | pbus->resource[0] = &pbm->io_space; | |
837 | pbus->resource[1] = &pbm->mem_space; | |
838 | } | |
839 | ||
085ae41f | 840 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
841 | { |
842 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 843 | struct resource *root = NULL; |
1da177e4 | 844 | |
085ae41f | 845 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 846 | root = &pbm->io_space; |
085ae41f | 847 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
848 | root = &pbm->mem_space; |
849 | ||
085ae41f | 850 | return root; |
1da177e4 LT |
851 | } |
852 | ||
853 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
854 | { | |
855 | } | |
856 | ||
857 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 858 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
859 | { |
860 | } | |
861 | ||
a2fb23af | 862 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 863 | { |
a2fb23af DM |
864 | u16 cmd, oldcmd; |
865 | int i; | |
866 | ||
867 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
868 | oldcmd = cmd; | |
869 | ||
870 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
871 | struct resource *res = &dev->resource[i]; | |
872 | ||
873 | /* Only set up the requested stuff */ | |
874 | if (!(mask & (1<<i))) | |
875 | continue; | |
876 | ||
877 | if (res->flags & IORESOURCE_IO) | |
878 | cmd |= PCI_COMMAND_IO; | |
879 | if (res->flags & IORESOURCE_MEM) | |
880 | cmd |= PCI_COMMAND_MEMORY; | |
881 | } | |
882 | ||
883 | if (cmd != oldcmd) { | |
884 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
885 | pci_name(dev), cmd); | |
886 | /* Enable the appropriate bits in the PCI command register. */ | |
887 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
888 | } | |
1da177e4 LT |
889 | return 0; |
890 | } | |
891 | ||
892 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
893 | struct resource *res) | |
894 | { | |
895 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
896 | struct resource zero_res, *root; | |
897 | ||
898 | zero_res.start = 0; | |
899 | zero_res.end = 0; | |
900 | zero_res.flags = res->flags; | |
901 | ||
902 | if (res->flags & IORESOURCE_IO) | |
903 | root = &pbm->io_space; | |
904 | else | |
905 | root = &pbm->mem_space; | |
906 | ||
0bae5f81 | 907 | pci_resource_adjust(&zero_res, root); |
1da177e4 LT |
908 | |
909 | region->start = res->start - zero_res.start; | |
910 | region->end = res->end - zero_res.start; | |
911 | } | |
5fdfd42e | 912 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
1da177e4 LT |
913 | |
914 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
915 | struct pci_bus_region *region) | |
916 | { | |
917 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
918 | struct resource *root; | |
919 | ||
920 | res->start = region->start; | |
921 | res->end = region->end; | |
922 | ||
923 | if (res->flags & IORESOURCE_IO) | |
924 | root = &pbm->io_space; | |
925 | else | |
926 | root = &pbm->mem_space; | |
927 | ||
0bae5f81 | 928 | pci_resource_adjust(res, root); |
1da177e4 | 929 | } |
41290c14 | 930 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 931 | |
f6b45da1 | 932 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 933 | { |
1da177e4 LT |
934 | return str; |
935 | } | |
936 | ||
937 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
938 | ||
939 | /* If the user uses a host-bridge as the PCI device, he may use | |
940 | * this to perform a raw mmap() of the I/O or MEM space behind | |
941 | * that controller. | |
942 | * | |
943 | * This can be useful for execution of x86 PCI bios initialization code | |
944 | * on a PCI card, like the xfree86 int10 stuff does. | |
945 | */ | |
946 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
947 | enum pci_mmap_state mmap_state) | |
948 | { | |
a2fb23af | 949 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
950 | unsigned long space_size, user_offset, user_size; |
951 | ||
3875c5c0 DM |
952 | if (mmap_state == pci_mmap_io) { |
953 | space_size = (pbm->io_space.end - | |
954 | pbm->io_space.start) + 1; | |
1da177e4 | 955 | } else { |
3875c5c0 DM |
956 | space_size = (pbm->mem_space.end - |
957 | pbm->mem_space.start) + 1; | |
1da177e4 LT |
958 | } |
959 | ||
960 | /* Make sure the request is in range. */ | |
961 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
962 | user_size = vma->vm_end - vma->vm_start; | |
963 | ||
964 | if (user_offset >= space_size || | |
965 | (user_offset + user_size) > space_size) | |
966 | return -EINVAL; | |
967 | ||
3875c5c0 DM |
968 | if (mmap_state == pci_mmap_io) { |
969 | vma->vm_pgoff = (pbm->io_space.start + | |
970 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 971 | } else { |
3875c5c0 DM |
972 | vma->vm_pgoff = (pbm->mem_space.start + |
973 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
974 | } |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
979 | /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding | |
980 | * to the 32-bit pci bus offset for DEV requested by the user. | |
981 | * | |
982 | * Basically, the user finds the base address for his device which he wishes | |
983 | * to mmap. They read the 32-bit value from the config space base register, | |
984 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
985 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
986 | * | |
987 | * Returns negative error code on failure, zero on success. | |
988 | */ | |
989 | static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, | |
990 | enum pci_mmap_state mmap_state) | |
991 | { | |
992 | unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
993 | unsigned long user32 = user_offset & pci_memspace_mask; | |
994 | unsigned long largest_base, this_base, addr32; | |
995 | int i; | |
996 | ||
997 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
998 | return __pci_mmap_make_offset_bus(dev, vma, mmap_state); | |
999 | ||
1000 | /* Figure out which base address this is for. */ | |
1001 | largest_base = 0UL; | |
1002 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
1003 | struct resource *rp = &dev->resource[i]; | |
1004 | ||
1005 | /* Active? */ | |
1006 | if (!rp->flags) | |
1007 | continue; | |
1008 | ||
1009 | /* Same type? */ | |
1010 | if (i == PCI_ROM_RESOURCE) { | |
1011 | if (mmap_state != pci_mmap_mem) | |
1012 | continue; | |
1013 | } else { | |
1014 | if ((mmap_state == pci_mmap_io && | |
1015 | (rp->flags & IORESOURCE_IO) == 0) || | |
1016 | (mmap_state == pci_mmap_mem && | |
1017 | (rp->flags & IORESOURCE_MEM) == 0)) | |
1018 | continue; | |
1019 | } | |
1020 | ||
1021 | this_base = rp->start; | |
1022 | ||
1023 | addr32 = (this_base & PAGE_MASK) & pci_memspace_mask; | |
1024 | ||
1025 | if (mmap_state == pci_mmap_io) | |
1026 | addr32 &= 0xffffff; | |
1027 | ||
1028 | if (addr32 <= user32 && this_base > largest_base) | |
1029 | largest_base = this_base; | |
1030 | } | |
1031 | ||
1032 | if (largest_base == 0UL) | |
1033 | return -EINVAL; | |
1034 | ||
1035 | /* Now construct the final physical address. */ | |
1036 | if (mmap_state == pci_mmap_io) | |
1037 | vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT); | |
1038 | else | |
1039 | vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT); | |
1040 | ||
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
1045 | * mapping. | |
1046 | */ | |
1047 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
1048 | enum pci_mmap_state mmap_state) | |
1049 | { | |
1050 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
1051 | } | |
1052 | ||
1053 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
1054 | * device mapping. | |
1055 | */ | |
1056 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
1057 | enum pci_mmap_state mmap_state) | |
1058 | { | |
a7a6cac2 | 1059 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
1060 | } |
1061 | ||
1062 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
1063 | * for this architecture. The region in the process to map is described by vm_start | |
1064 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
1065 | * The pci device structure is provided so that architectures may make mapping | |
1066 | * decisions on a per-device or per-bus basis. | |
1067 | * | |
1068 | * Returns a negative error code on failure, zero on success. | |
1069 | */ | |
1070 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1071 | enum pci_mmap_state mmap_state, | |
1072 | int write_combine) | |
1073 | { | |
1074 | int ret; | |
1075 | ||
1076 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
1077 | if (ret < 0) | |
1078 | return ret; | |
1079 | ||
1080 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
1081 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
1082 | ||
14778d90 | 1083 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
1084 | ret = io_remap_pfn_range(vma, vma->vm_start, |
1085 | vma->vm_pgoff, | |
1086 | vma->vm_end - vma->vm_start, | |
1087 | vma->vm_page_prot); | |
1088 | if (ret) | |
1089 | return ret; | |
1090 | ||
1da177e4 LT |
1091 | return 0; |
1092 | } | |
1093 | ||
1094 | /* Return the domain nuber for this pci bus */ | |
1095 | ||
1096 | int pci_domain_nr(struct pci_bus *pbus) | |
1097 | { | |
1098 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1099 | int ret; | |
1100 | ||
1101 | if (pbm == NULL || pbm->parent == NULL) { | |
1102 | ret = -ENXIO; | |
1103 | } else { | |
6c108f12 | 1104 | ret = pbm->index; |
1da177e4 LT |
1105 | } |
1106 | ||
1107 | return ret; | |
1108 | } | |
1109 | EXPORT_SYMBOL(pci_domain_nr); | |
1110 | ||
35a17eb6 DM |
1111 | #ifdef CONFIG_PCI_MSI |
1112 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1113 | { | |
a2fb23af | 1114 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
e9870c4c | 1115 | int virt_irq; |
35a17eb6 | 1116 | |
e9870c4c | 1117 | if (!pbm->setup_msi_irq) |
35a17eb6 DM |
1118 | return -EINVAL; |
1119 | ||
e9870c4c | 1120 | return pbm->setup_msi_irq(&virt_irq, pdev, desc); |
35a17eb6 DM |
1121 | } |
1122 | ||
1123 | void arch_teardown_msi_irq(unsigned int virt_irq) | |
1124 | { | |
abfd336c | 1125 | struct msi_desc *entry = get_irq_msi(virt_irq); |
35a17eb6 | 1126 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 1127 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 | 1128 | |
e9870c4c | 1129 | if (!pbm->teardown_msi_irq) |
35a17eb6 DM |
1130 | return; |
1131 | ||
e9870c4c | 1132 | return pbm->teardown_msi_irq(virt_irq, pdev); |
35a17eb6 DM |
1133 | } |
1134 | #endif /* !(CONFIG_PCI_MSI) */ | |
1135 | ||
f6d0f9ea DM |
1136 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1137 | { | |
a2fb23af | 1138 | return pdev->dev.archdata.prom_node; |
f6d0f9ea DM |
1139 | } |
1140 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
1141 | ||
1da177e4 | 1142 | #endif /* !(CONFIG_PCI) */ |