Commit | Line | Data |
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9fd8b647 | 1 | /* pci_common.c: PCI controller common support. |
1da177e4 | 2 | * |
9fd8b647 | 3 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
6 | #include <linux/string.h> | |
7 | #include <linux/slab.h> | |
8 | #include <linux/init.h> | |
cf69eab2 FMDN |
9 | #include <linux/pci.h> |
10 | #include <linux/device.h> | |
1da177e4 | 11 | |
de8d28b1 | 12 | #include <asm/prom.h> |
2b1e5978 | 13 | #include <asm/of_device.h> |
c57c2ffb | 14 | #include <asm/oplib.h> |
de8d28b1 DM |
15 | |
16 | #include "pci_impl.h" | |
ca3dd88e DM |
17 | #include "pci_sun4v.h" |
18 | ||
19 | static int config_out_of_range(struct pci_pbm_info *pbm, | |
20 | unsigned long bus, | |
21 | unsigned long devfn, | |
22 | unsigned long reg) | |
23 | { | |
24 | if (bus < pbm->pci_first_busno || | |
25 | bus > pbm->pci_last_busno) | |
26 | return 1; | |
27 | return 0; | |
28 | } | |
29 | ||
30 | static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm, | |
31 | unsigned long bus, | |
32 | unsigned long devfn, | |
33 | unsigned long reg) | |
34 | { | |
35 | unsigned long rbits = pbm->config_space_reg_bits; | |
36 | ||
37 | if (config_out_of_range(pbm, bus, devfn, reg)) | |
38 | return NULL; | |
39 | ||
40 | reg = (reg & ((1 << rbits) - 1)); | |
41 | devfn <<= rbits; | |
42 | bus <<= rbits + 8; | |
43 | ||
44 | return (void *) (pbm->config_space | bus | devfn | reg); | |
45 | } | |
46 | ||
47 | static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
48 | int where, int size, u32 *value) | |
49 | { | |
50 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
51 | unsigned char bus = bus_dev->number; | |
52 | u32 *addr; | |
53 | u16 tmp16; | |
54 | u8 tmp8; | |
55 | ||
56 | if (bus_dev == pbm->pci_bus && devfn == 0x00) | |
57 | return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where, | |
58 | size, value); | |
59 | ||
60 | switch (size) { | |
61 | case 1: | |
62 | *value = 0xff; | |
63 | break; | |
64 | case 2: | |
65 | *value = 0xffff; | |
66 | break; | |
67 | case 4: | |
68 | *value = 0xffffffff; | |
69 | break; | |
70 | } | |
71 | ||
72 | addr = sun4u_config_mkaddr(pbm, bus, devfn, where); | |
73 | if (!addr) | |
74 | return PCIBIOS_SUCCESSFUL; | |
75 | ||
76 | switch (size) { | |
77 | case 1: | |
78 | pci_config_read8((u8 *)addr, &tmp8); | |
79 | *value = (u32) tmp8; | |
80 | break; | |
81 | ||
82 | case 2: | |
83 | if (where & 0x01) { | |
84 | printk("pci_read_config_word: misaligned reg [%x]\n", | |
85 | where); | |
86 | return PCIBIOS_SUCCESSFUL; | |
87 | } | |
88 | pci_config_read16((u16 *)addr, &tmp16); | |
89 | *value = (u32) tmp16; | |
90 | break; | |
91 | ||
92 | case 4: | |
93 | if (where & 0x03) { | |
94 | printk("pci_read_config_dword: misaligned reg [%x]\n", | |
95 | where); | |
96 | return PCIBIOS_SUCCESSFUL; | |
97 | } | |
98 | pci_config_read32(addr, value); | |
99 | break; | |
100 | } | |
101 | return PCIBIOS_SUCCESSFUL; | |
102 | } | |
103 | ||
104 | static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
105 | int where, int size, u32 value) | |
106 | { | |
107 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
108 | unsigned char bus = bus_dev->number; | |
109 | u32 *addr; | |
110 | ||
111 | if (bus_dev == pbm->pci_bus && devfn == 0x00) | |
112 | return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where, | |
113 | size, value); | |
114 | addr = sun4u_config_mkaddr(pbm, bus, devfn, where); | |
115 | if (!addr) | |
116 | return PCIBIOS_SUCCESSFUL; | |
117 | ||
118 | switch (size) { | |
119 | case 1: | |
120 | pci_config_write8((u8 *)addr, value); | |
121 | break; | |
122 | ||
123 | case 2: | |
124 | if (where & 0x01) { | |
125 | printk("pci_write_config_word: misaligned reg [%x]\n", | |
126 | where); | |
127 | return PCIBIOS_SUCCESSFUL; | |
128 | } | |
129 | pci_config_write16((u16 *)addr, value); | |
130 | break; | |
131 | ||
132 | case 4: | |
133 | if (where & 0x03) { | |
134 | printk("pci_write_config_dword: misaligned reg [%x]\n", | |
135 | where); | |
136 | return PCIBIOS_SUCCESSFUL; | |
137 | } | |
138 | pci_config_write32(addr, value); | |
139 | } | |
140 | return PCIBIOS_SUCCESSFUL; | |
141 | } | |
142 | ||
143 | struct pci_ops sun4u_pci_ops = { | |
144 | .read = sun4u_read_pci_cfg, | |
145 | .write = sun4u_write_pci_cfg, | |
146 | }; | |
147 | ||
148 | static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
149 | int where, int size, u32 *value) | |
150 | { | |
151 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
152 | u32 devhandle = pbm->devhandle; | |
153 | unsigned int bus = bus_dev->number; | |
154 | unsigned int device = PCI_SLOT(devfn); | |
155 | unsigned int func = PCI_FUNC(devfn); | |
156 | unsigned long ret; | |
157 | ||
158 | if (bus_dev == pbm->pci_bus && devfn == 0x00) | |
159 | return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where, | |
160 | size, value); | |
161 | if (config_out_of_range(pbm, bus, devfn, where)) { | |
162 | ret = ~0UL; | |
163 | } else { | |
164 | ret = pci_sun4v_config_get(devhandle, | |
165 | HV_PCI_DEVICE_BUILD(bus, device, func), | |
166 | where, size); | |
167 | } | |
168 | switch (size) { | |
169 | case 1: | |
170 | *value = ret & 0xff; | |
171 | break; | |
172 | case 2: | |
173 | *value = ret & 0xffff; | |
174 | break; | |
175 | case 4: | |
176 | *value = ret & 0xffffffff; | |
177 | break; | |
178 | }; | |
179 | ||
180 | ||
181 | return PCIBIOS_SUCCESSFUL; | |
182 | } | |
183 | ||
184 | static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
185 | int where, int size, u32 value) | |
186 | { | |
187 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
188 | u32 devhandle = pbm->devhandle; | |
189 | unsigned int bus = bus_dev->number; | |
190 | unsigned int device = PCI_SLOT(devfn); | |
191 | unsigned int func = PCI_FUNC(devfn); | |
192 | unsigned long ret; | |
193 | ||
194 | if (bus_dev == pbm->pci_bus && devfn == 0x00) | |
195 | return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where, | |
196 | size, value); | |
197 | if (config_out_of_range(pbm, bus, devfn, where)) { | |
198 | /* Do nothing. */ | |
199 | } else { | |
200 | ret = pci_sun4v_config_put(devhandle, | |
201 | HV_PCI_DEVICE_BUILD(bus, device, func), | |
202 | where, size, value); | |
203 | } | |
204 | return PCIBIOS_SUCCESSFUL; | |
205 | } | |
206 | ||
207 | struct pci_ops sun4v_pci_ops = { | |
208 | .read = sun4v_read_pci_cfg, | |
209 | .write = sun4v_write_pci_cfg, | |
210 | }; | |
1da177e4 | 211 | |
cfa0652c DM |
212 | void pci_get_pbm_props(struct pci_pbm_info *pbm) |
213 | { | |
214 | const u32 *val = of_get_property(pbm->prom_node, "bus-range", NULL); | |
215 | ||
216 | pbm->pci_first_busno = val[0]; | |
217 | pbm->pci_last_busno = val[1]; | |
218 | ||
219 | val = of_get_property(pbm->prom_node, "ino-bitmap", NULL); | |
220 | if (val) { | |
221 | pbm->ino_bitmap = (((u64)val[1] << 32UL) | | |
222 | ((u64)val[0] << 0UL)); | |
223 | } | |
224 | } | |
225 | ||
9fd8b647 DM |
226 | static void pci_register_legacy_regions(struct resource *io_res, |
227 | struct resource *mem_res) | |
1da177e4 LT |
228 | { |
229 | struct resource *p; | |
230 | ||
231 | /* VGA Video RAM. */ | |
9132983a | 232 | p = kzalloc(sizeof(*p), GFP_KERNEL); |
1da177e4 LT |
233 | if (!p) |
234 | return; | |
235 | ||
1da177e4 LT |
236 | p->name = "Video RAM area"; |
237 | p->start = mem_res->start + 0xa0000UL; | |
238 | p->end = p->start + 0x1ffffUL; | |
239 | p->flags = IORESOURCE_BUSY; | |
240 | request_resource(mem_res, p); | |
241 | ||
9132983a | 242 | p = kzalloc(sizeof(*p), GFP_KERNEL); |
1da177e4 LT |
243 | if (!p) |
244 | return; | |
245 | ||
1da177e4 LT |
246 | p->name = "System ROM"; |
247 | p->start = mem_res->start + 0xf0000UL; | |
248 | p->end = p->start + 0xffffUL; | |
249 | p->flags = IORESOURCE_BUSY; | |
250 | request_resource(mem_res, p); | |
251 | ||
9132983a | 252 | p = kzalloc(sizeof(*p), GFP_KERNEL); |
1da177e4 LT |
253 | if (!p) |
254 | return; | |
255 | ||
1da177e4 LT |
256 | p->name = "Video ROM"; |
257 | p->start = mem_res->start + 0xc0000UL; | |
258 | p->end = p->start + 0x7fffUL; | |
259 | p->flags = IORESOURCE_BUSY; | |
260 | request_resource(mem_res, p); | |
261 | } | |
262 | ||
9fd8b647 DM |
263 | static void pci_register_iommu_region(struct pci_pbm_info *pbm) |
264 | { | |
a165b420 | 265 | const u32 *vdma = of_get_property(pbm->prom_node, "virtual-dma", NULL); |
9fd8b647 DM |
266 | |
267 | if (vdma) { | |
268 | struct resource *rp = kmalloc(sizeof(*rp), GFP_KERNEL); | |
269 | ||
270 | if (!rp) { | |
271 | prom_printf("Cannot allocate IOMMU resource.\n"); | |
272 | prom_halt(); | |
273 | } | |
274 | rp->name = "IOMMU"; | |
275 | rp->start = pbm->mem_space.start + (unsigned long) vdma[0]; | |
276 | rp->end = rp->start + (unsigned long) vdma[1] - 1UL; | |
277 | rp->flags = IORESOURCE_BUSY; | |
278 | request_resource(&pbm->mem_space, rp); | |
279 | } | |
280 | } | |
281 | ||
282 | void pci_determine_mem_io_space(struct pci_pbm_info *pbm) | |
283 | { | |
a165b420 | 284 | const struct linux_prom_pci_ranges *pbm_ranges; |
9fd8b647 | 285 | int i, saw_mem, saw_io; |
3487a1f9 | 286 | int num_pbm_ranges; |
9fd8b647 DM |
287 | |
288 | saw_mem = saw_io = 0; | |
3487a1f9 DM |
289 | pbm_ranges = of_get_property(pbm->prom_node, "ranges", &i); |
290 | num_pbm_ranges = i / sizeof(*pbm_ranges); | |
291 | ||
292 | for (i = 0; i < num_pbm_ranges; i++) { | |
a165b420 | 293 | const struct linux_prom_pci_ranges *pr = &pbm_ranges[i]; |
9fd8b647 | 294 | unsigned long a; |
3487a1f9 | 295 | u32 parent_phys_hi, parent_phys_lo; |
9fd8b647 DM |
296 | int type; |
297 | ||
3487a1f9 DM |
298 | parent_phys_hi = pr->parent_phys_hi; |
299 | parent_phys_lo = pr->parent_phys_lo; | |
300 | if (tlb_type == hypervisor) | |
301 | parent_phys_hi &= 0x0fffffff; | |
302 | ||
9fd8b647 | 303 | type = (pr->child_phys_hi >> 24) & 0x3; |
3487a1f9 DM |
304 | a = (((unsigned long)parent_phys_hi << 32UL) | |
305 | ((unsigned long)parent_phys_lo << 0UL)); | |
9fd8b647 DM |
306 | |
307 | switch (type) { | |
308 | case 0: | |
309 | /* PCI config space, 16MB */ | |
310 | pbm->config_space = a; | |
311 | break; | |
312 | ||
313 | case 1: | |
314 | /* 16-bit IO space, 16MB */ | |
315 | pbm->io_space.start = a; | |
316 | pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL); | |
317 | pbm->io_space.flags = IORESOURCE_IO; | |
318 | saw_io = 1; | |
319 | break; | |
320 | ||
321 | case 2: | |
322 | /* 32-bit MEM space, 2GB */ | |
323 | pbm->mem_space.start = a; | |
324 | pbm->mem_space.end = a + (0x80000000UL - 1UL); | |
325 | pbm->mem_space.flags = IORESOURCE_MEM; | |
326 | saw_mem = 1; | |
327 | break; | |
328 | ||
329 | case 3: | |
330 | /* XXX 64-bit MEM handling XXX */ | |
331 | ||
332 | default: | |
333 | break; | |
334 | }; | |
335 | } | |
336 | ||
337 | if (!saw_io || !saw_mem) { | |
338 | prom_printf("%s: Fatal error, missing %s PBM range.\n", | |
339 | pbm->name, | |
340 | (!saw_io ? "IO" : "MEM")); | |
341 | prom_halt(); | |
342 | } | |
343 | ||
344 | printk("%s: PCI IO[%lx] MEM[%lx]\n", | |
345 | pbm->name, | |
346 | pbm->io_space.start, | |
347 | pbm->mem_space.start); | |
348 | ||
349 | pbm->io_space.name = pbm->mem_space.name = pbm->name; | |
350 | ||
351 | request_resource(&ioport_resource, &pbm->io_space); | |
352 | request_resource(&iomem_resource, &pbm->mem_space); | |
353 | ||
354 | pci_register_legacy_regions(&pbm->io_space, | |
355 | &pbm->mem_space); | |
356 | pci_register_iommu_region(pbm); | |
357 | } | |
358 | ||
1da177e4 | 359 | /* Generic helper routines for PCI error reporting. */ |
6c108f12 | 360 | void pci_scan_for_target_abort(struct pci_pbm_info *pbm, |
1da177e4 LT |
361 | struct pci_bus *pbus) |
362 | { | |
363 | struct pci_dev *pdev; | |
364 | struct pci_bus *bus; | |
365 | ||
366 | list_for_each_entry(pdev, &pbus->devices, bus_list) { | |
367 | u16 status, error_bits; | |
368 | ||
369 | pci_read_config_word(pdev, PCI_STATUS, &status); | |
370 | error_bits = | |
371 | (status & (PCI_STATUS_SIG_TARGET_ABORT | | |
372 | PCI_STATUS_REC_TARGET_ABORT)); | |
373 | if (error_bits) { | |
374 | pci_write_config_word(pdev, PCI_STATUS, error_bits); | |
6c108f12 DM |
375 | printk("%s: Device %s saw Target Abort [%016x]\n", |
376 | pbm->name, pci_name(pdev), status); | |
1da177e4 LT |
377 | } |
378 | } | |
379 | ||
380 | list_for_each_entry(bus, &pbus->children, node) | |
6c108f12 | 381 | pci_scan_for_target_abort(pbm, bus); |
1da177e4 LT |
382 | } |
383 | ||
6c108f12 | 384 | void pci_scan_for_master_abort(struct pci_pbm_info *pbm, |
1da177e4 LT |
385 | struct pci_bus *pbus) |
386 | { | |
387 | struct pci_dev *pdev; | |
388 | struct pci_bus *bus; | |
389 | ||
390 | list_for_each_entry(pdev, &pbus->devices, bus_list) { | |
391 | u16 status, error_bits; | |
392 | ||
393 | pci_read_config_word(pdev, PCI_STATUS, &status); | |
394 | error_bits = | |
395 | (status & (PCI_STATUS_REC_MASTER_ABORT)); | |
396 | if (error_bits) { | |
397 | pci_write_config_word(pdev, PCI_STATUS, error_bits); | |
6c108f12 DM |
398 | printk("%s: Device %s received Master Abort [%016x]\n", |
399 | pbm->name, pci_name(pdev), status); | |
1da177e4 LT |
400 | } |
401 | } | |
402 | ||
403 | list_for_each_entry(bus, &pbus->children, node) | |
6c108f12 | 404 | pci_scan_for_master_abort(pbm, bus); |
1da177e4 LT |
405 | } |
406 | ||
6c108f12 | 407 | void pci_scan_for_parity_error(struct pci_pbm_info *pbm, |
1da177e4 LT |
408 | struct pci_bus *pbus) |
409 | { | |
410 | struct pci_dev *pdev; | |
411 | struct pci_bus *bus; | |
412 | ||
413 | list_for_each_entry(pdev, &pbus->devices, bus_list) { | |
414 | u16 status, error_bits; | |
415 | ||
416 | pci_read_config_word(pdev, PCI_STATUS, &status); | |
417 | error_bits = | |
418 | (status & (PCI_STATUS_PARITY | | |
419 | PCI_STATUS_DETECTED_PARITY)); | |
420 | if (error_bits) { | |
421 | pci_write_config_word(pdev, PCI_STATUS, error_bits); | |
6c108f12 DM |
422 | printk("%s: Device %s saw Parity Error [%016x]\n", |
423 | pbm->name, pci_name(pdev), status); | |
1da177e4 LT |
424 | } |
425 | } | |
426 | ||
427 | list_for_each_entry(bus, &pbus->children, node) | |
6c108f12 | 428 | pci_scan_for_parity_error(pbm, bus); |
1da177e4 | 429 | } |