[deliverable/linux.git] / arch / sparc64 / kernel / pci_fire.c

/* pci_fire.c: Sun4u platform PCI-E controller support.
 *
 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
 */
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/irq.h>
#include <linux/of_device.h>

#include <asm/prom.h>
#include <asm/irq.h>

#include "pci_impl.h"

#define DRIVER_NAME	"fire"
#define PFX		DRIVER_NAME ": "

#define fire_read(__reg) \
({	u64 __ret; \
	__asm__ __volatile__("ldxa [%1] %2, %0" \
			     : "=r" (__ret) \
			     : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
			     : "memory"); \
	__ret; \
})
#define fire_write(__reg, __val) \
	__asm__ __volatile__("stxa %0, [%1] %2" \
			     : /* no outputs */ \
			     : "r" (__val), "r" (__reg), \
			       "i" (ASI_PHYS_BYPASS_EC_E) \
			     : "memory")

#define FIRE_IOMMU_CONTROL	0x40000UL
#define FIRE_IOMMU_TSBBASE	0x40008UL
#define FIRE_IOMMU_FLUSH	0x40100UL
#define FIRE_IOMMU_FLUSHINV	0x40108UL

static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
{
	struct iommu *iommu = pbm->iommu;
	u32 vdma[2], dma_mask;
	u64 control;
	int tsbsize, err;

	/* No virtual-dma property on these guys, use largest size.  */
	vdma[0] = 0xc0000000; /* base */
	vdma[1] = 0x40000000; /* size */
	dma_mask = 0xffffffff;
	tsbsize = 128;

	/* Register addresses. */
	iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
	iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
	iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
	iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;

	/* We use the main control/status register of FIRE as the write
	 * completion register.
	 */
	iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;

	/*
	 * Invalidate TLB Entries.
	 */
	fire_write(iommu->iommu_flushinv, ~(u64)0);

	err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
			       pbm->numa_node);
	if (err)
		return err;

	fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);

	control = fire_read(iommu->iommu_control);
	control |= (0x00000400 /* TSB cache snoop enable */	|
		    0x00000300 /* Cache mode */			|
		    0x00000002 /* Bypass enable */		|
		    0x00000001 /* Translation enable */);
	fire_write(iommu->iommu_control, control);

	return 0;
}

#ifdef CONFIG_PCI_MSI
struct pci_msiq_entry {
	u64		word0;
#define MSIQ_WORD0_RESV			0x8000000000000000UL
#define MSIQ_WORD0_FMT_TYPE		0x7f00000000000000UL
#define MSIQ_WORD0_FMT_TYPE_SHIFT	56
#define MSIQ_WORD0_LEN			0x00ffc00000000000UL
#define MSIQ_WORD0_LEN_SHIFT		46
#define MSIQ_WORD0_ADDR0		0x00003fff00000000UL
#define MSIQ_WORD0_ADDR0_SHIFT		32
#define MSIQ_WORD0_RID			0x00000000ffff0000UL
#define MSIQ_WORD0_RID_SHIFT		16
#define MSIQ_WORD0_DATA0		0x000000000000ffffUL
#define MSIQ_WORD0_DATA0_SHIFT		0

#define MSIQ_TYPE_MSG			0x6
#define MSIQ_TYPE_MSI32			0xb
#define MSIQ_TYPE_MSI64			0xf

	u64		word1;
#define MSIQ_WORD1_ADDR1		0xffffffffffff0000UL
#define MSIQ_WORD1_ADDR1_SHIFT		16
#define MSIQ_WORD1_DATA1		0x000000000000ffffUL
#define MSIQ_WORD1_DATA1_SHIFT		0

	u64		resv[6];
};

/* All MSI registers are offset from pbm->pbm_regs */
#define EVENT_QUEUE_BASE_ADDR_REG	0x010000UL
#define  EVENT_QUEUE_BASE_ADDR_ALL_ONES	0xfffc000000000000UL

#define EVENT_QUEUE_CONTROL_SET(EQ)	(0x011000UL + (EQ) * 0x8UL)
#define  EVENT_QUEUE_CONTROL_SET_OFLOW	0x0200000000000000UL
#define  EVENT_QUEUE_CONTROL_SET_EN	0x0000100000000000UL

#define EVENT_QUEUE_CONTROL_CLEAR(EQ)	(0x011200UL + (EQ) * 0x8UL)
#define  EVENT_QUEUE_CONTROL_CLEAR_OF	0x0200000000000000UL
#define  EVENT_QUEUE_CONTROL_CLEAR_E2I	0x0000800000000000UL
#define  EVENT_QUEUE_CONTROL_CLEAR_DIS	0x0000100000000000UL

#define EVENT_QUEUE_STATE(EQ)		(0x011400UL + (EQ) * 0x8UL)
#define  EVENT_QUEUE_STATE_MASK		0x0000000000000007UL
#define  EVENT_QUEUE_STATE_IDLE		0x0000000000000001UL
#define  EVENT_QUEUE_STATE_ACTIVE	0x0000000000000002UL
#define  EVENT_QUEUE_STATE_ERROR	0x0000000000000004UL

#define EVENT_QUEUE_TAIL(EQ)		(0x011600UL + (EQ) * 0x8UL)
#define  EVENT_QUEUE_TAIL_OFLOW		0x0200000000000000UL
#define  EVENT_QUEUE_TAIL_VAL		0x000000000000007fUL

#define EVENT_QUEUE_HEAD(EQ)		(0x011800UL + (EQ) * 0x8UL)
#define  EVENT_QUEUE_HEAD_VAL		0x000000000000007fUL

#define MSI_MAP(MSI)			(0x020000UL + (MSI) * 0x8UL)
#define  MSI_MAP_VALID			0x8000000000000000UL
#define  MSI_MAP_EQWR_N			0x4000000000000000UL
#define  MSI_MAP_EQNUM			0x000000000000003fUL

#define MSI_CLEAR(MSI)			(0x028000UL + (MSI) * 0x8UL)
#define  MSI_CLEAR_EQWR_N		0x4000000000000000UL

#define IMONDO_DATA0			0x02C000UL
#define  IMONDO_DATA0_DATA		0xffffffffffffffc0UL

#define IMONDO_DATA1			0x02C008UL
#define  IMONDO_DATA1_DATA		0xffffffffffffffffUL

#define MSI_32BIT_ADDR			0x034000UL
#define  MSI_32BIT_ADDR_VAL		0x00000000ffff0000UL

#define MSI_64BIT_ADDR			0x034008UL
#define  MSI_64BIT_ADDR_VAL		0xffffffffffff0000UL

static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
			     unsigned long *head)
{
	*head = fire_read(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
	return 0;
}

static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
				unsigned long *head, unsigned long *msi)
{
	unsigned long type_fmt, type, msi_num;
	struct pci_msiq_entry *base, *ep;

	base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
	ep = &base[*head];

	if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
		return 0;

	type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
		    MSIQ_WORD0_FMT_TYPE_SHIFT);
	type = (type_fmt >> 3);
	if (unlikely(type != MSIQ_TYPE_MSI32 &&
		     type != MSIQ_TYPE_MSI64))
		return -EINVAL;

	*msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
			  MSIQ_WORD0_DATA0_SHIFT);

	fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num),
		   MSI_CLEAR_EQWR_N);

	/* Clear the entry.  */
	ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;

	/* Go to next entry in ring.  */
	(*head)++;
	if (*head >= pbm->msiq_ent_count)
		*head = 0;

	return 1;
}

static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
			     unsigned long head)
{
	fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid), head);
	return 0;
}

static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
			      unsigned long msi, int is_msi64)
{
	u64 val;

	val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
	val &= ~(MSI_MAP_EQNUM);
	val |= msiqid;
	fire_write(pbm->pbm_regs + MSI_MAP(msi), val);

	fire_write(pbm->pbm_regs + MSI_CLEAR(msi),
		   MSI_CLEAR_EQWR_N);

	val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
	val |= MSI_MAP_VALID;
	fire_write(pbm->pbm_regs + MSI_MAP(msi), val);

	return 0;
}

static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
{
	unsigned long msiqid;
	u64 val;

	val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
	msiqid = (val & MSI_MAP_EQNUM);

	val &= ~MSI_MAP_VALID;

	fire_write(pbm->pbm_regs + MSI_MAP(msi), val);

	return 0;
}

static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
{
	unsigned long pages, order, i;

	order = get_order(512 * 1024);
	pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
	if (pages == 0UL) {
		printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
		       order);
		return -ENOMEM;
	}
	memset((char *)pages, 0, PAGE_SIZE << order);
	pbm->msi_queues = (void *) pages;

	fire_write(pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG,
		   (EVENT_QUEUE_BASE_ADDR_ALL_ONES |
		    __pa(pbm->msi_queues)));

	fire_write(pbm->pbm_regs + IMONDO_DATA0,
		   pbm->portid << 6);
	fire_write(pbm->pbm_regs + IMONDO_DATA1, 0);

	fire_write(pbm->pbm_regs + MSI_32BIT_ADDR,
		   pbm->msi32_start);
	fire_write(pbm->pbm_regs + MSI_64BIT_ADDR,
		   pbm->msi64_start);

	for (i = 0; i < pbm->msiq_num; i++) {
		fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(i), 0);
		fire_write(pbm->pbm_regs + EVENT_QUEUE_TAIL(i), 0);
	}

	return 0;
}

static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
{
	unsigned long pages, order;

	order = get_order(512 * 1024);
	pages = (unsigned long) pbm->msi_queues;

	free_pages(pages, order);

	pbm->msi_queues = NULL;
}

static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
				   unsigned long msiqid,
				   unsigned long devino)
{
	unsigned long cregs = (unsigned long) pbm->pbm_regs;
	unsigned long imap_reg, iclr_reg, int_ctrlr;
	unsigned int virt_irq;
	int fixup;
	u64 val;

	imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
	iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));

	/* XXX iterate amongst the 4 IRQ controllers XXX */
	int_ctrlr = (1UL << 6);

	val = fire_read(imap_reg);
	val |= (1UL << 63) | int_ctrlr;
	fire_write(imap_reg, val);

	fixup = ((pbm->portid << 6) | devino) - int_ctrlr;

	virt_irq = build_irq(fixup, iclr_reg, imap_reg);
	if (!virt_irq)
		return -ENOMEM;

	fire_write(pbm->pbm_regs +
		   EVENT_QUEUE_CONTROL_SET(msiqid),
		   EVENT_QUEUE_CONTROL_SET_EN);

	return virt_irq;
}

static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
	.get_head	=	pci_fire_get_head,
	.dequeue_msi	=	pci_fire_dequeue_msi,
	.set_head	=	pci_fire_set_head,
	.msi_setup	=	pci_fire_msi_setup,
	.msi_teardown	=	pci_fire_msi_teardown,
	.msiq_alloc	=	pci_fire_msiq_alloc,
	.msiq_free	=	pci_fire_msiq_free,
	.msiq_build_irq	=	pci_fire_msiq_build_irq,
};

static void pci_fire_msi_init(struct pci_pbm_info *pbm)
{
	sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
}
#else /* CONFIG_PCI_MSI */
static void pci_fire_msi_init(struct pci_pbm_info *pbm)
{
}
#endif /* !(CONFIG_PCI_MSI) */

/* Based at pbm->controller_regs */
#define FIRE_PARITY_CONTROL	0x470010UL
#define  FIRE_PARITY_ENAB	0x8000000000000000UL
#define FIRE_FATAL_RESET_CTL	0x471028UL
#define  FIRE_FATAL_RESET_SPARE	0x0000000004000000UL
#define  FIRE_FATAL_RESET_MB	0x0000000002000000UL
#define  FIRE_FATAL_RESET_CPE	0x0000000000008000UL
#define  FIRE_FATAL_RESET_APE	0x0000000000004000UL
#define  FIRE_FATAL_RESET_PIO	0x0000000000000040UL
#define  FIRE_FATAL_RESET_JW	0x0000000000000004UL
#define  FIRE_FATAL_RESET_JI	0x0000000000000002UL
#define  FIRE_FATAL_RESET_JR	0x0000000000000001UL
#define FIRE_CORE_INTR_ENABLE	0x471800UL

/* Based at pbm->pbm_regs */
#define FIRE_TLU_CTRL		0x80000UL
#define  FIRE_TLU_CTRL_TIM	0x00000000da000000UL
#define  FIRE_TLU_CTRL_QDET	0x0000000000000100UL
#define  FIRE_TLU_CTRL_CFG	0x0000000000000001UL
#define FIRE_TLU_DEV_CTRL	0x90008UL
#define FIRE_TLU_LINK_CTRL	0x90020UL
#define FIRE_TLU_LINK_CTRL_CLK	0x0000000000000040UL
#define FIRE_LPU_RESET		0xe2008UL
#define FIRE_LPU_LLCFG		0xe2200UL
#define  FIRE_LPU_LLCFG_VC0	0x0000000000000100UL
#define FIRE_LPU_FCTRL_UCTRL	0xe2240UL
#define  FIRE_LPU_FCTRL_UCTRL_N	0x0000000000000002UL
#define  FIRE_LPU_FCTRL_UCTRL_P	0x0000000000000001UL
#define FIRE_LPU_TXL_FIFOP	0xe2430UL
#define FIRE_LPU_LTSSM_CFG2	0xe2788UL
#define FIRE_LPU_LTSSM_CFG3	0xe2790UL
#define FIRE_LPU_LTSSM_CFG4	0xe2798UL
#define FIRE_LPU_LTSSM_CFG5	0xe27a0UL
#define FIRE_DMC_IENAB		0x31800UL
#define FIRE_DMC_DBG_SEL_A	0x53000UL
#define FIRE_DMC_DBG_SEL_B	0x53008UL
#define FIRE_PEC_IENAB		0x51800UL

static void pci_fire_hw_init(struct pci_pbm_info *pbm)
{
	u64 val;

	fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
		   FIRE_PARITY_ENAB);

	fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
		   (FIRE_FATAL_RESET_SPARE |
		    FIRE_FATAL_RESET_MB |
		    FIRE_FATAL_RESET_CPE |
		    FIRE_FATAL_RESET_APE |
		    FIRE_FATAL_RESET_PIO |
		    FIRE_FATAL_RESET_JW |
		    FIRE_FATAL_RESET_JI |
		    FIRE_FATAL_RESET_JR));

	fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);

	val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
	val |= (FIRE_TLU_CTRL_TIM |
		FIRE_TLU_CTRL_QDET |
		FIRE_TLU_CTRL_CFG);
	fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
	fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
	fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
		   FIRE_TLU_LINK_CTRL_CLK);

	fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
	fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
		   FIRE_LPU_LLCFG_VC0);
	fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
		   (FIRE_LPU_FCTRL_UCTRL_N |
		    FIRE_LPU_FCTRL_UCTRL_P));
	fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
		   ((0xffff << 16) | (0x0000 << 0)));
	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
		   (2 << 16) | (140 << 8));
	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);

	fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
	fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
	fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);

	fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
}

static int __init pci_fire_pbm_init(struct pci_controller_info *p,
				    struct of_device *op, u32 portid)
{
	const struct linux_prom64_registers *regs;
	struct device_node *dp = op->node;
	struct pci_pbm_info *pbm;
	int err;

	if ((portid & 1) == 0)
		pbm = &p->pbm_A;
	else
		pbm = &p->pbm_B;

	pbm->next = pci_pbm_root;
	pci_pbm_root = pbm;

	pbm->numa_node = -1;

	pbm->pci_ops = &sun4u_pci_ops;
	pbm->config_space_reg_bits = 12;

	pbm->index = pci_num_pbms++;

	pbm->portid = portid;
	pbm->parent = p;
	pbm->prom_node = dp;
	pbm->name = dp->full_name;

	regs = of_get_property(dp, "reg", NULL);
	pbm->pbm_regs = regs[0].phys_addr;
	pbm->controller_regs = regs[1].phys_addr - 0x410000UL;

	printk("%s: SUN4U PCIE Bus Module\n", pbm->name);

	pci_determine_mem_io_space(pbm);

	pci_get_pbm_props(pbm);

	pci_fire_hw_init(pbm);

	err = pci_fire_pbm_iommu_init(pbm);
	if (err)
		return err;

	pci_fire_msi_init(pbm);

	pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);

	/* XXX register error interrupt handlers XXX */

	return 0;
}

static inline int portid_compare(u32 x, u32 y)
{
	if (x == (y ^ 1))
		return 1;
	return 0;
}

static int __devinit fire_probe(struct of_device *op,
				const struct of_device_id *match)
{
	struct device_node *dp = op->node;
	struct pci_controller_info *p;
	struct pci_pbm_info *pbm;
	struct iommu *iommu;
	u32 portid;
	int err;

	portid = of_getintprop_default(dp, "portid", 0xff);
	for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
		if (portid_compare(pbm->portid, portid))
			return pci_fire_pbm_init(pbm->parent, op, portid);
	}

	err = -ENOMEM;
	p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
	if (!p) {
		printk(KERN_ERR PFX "Cannot allocate controller info.\n");
		goto out_err;
	}

	iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
	if (!iommu) {
		printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
		goto out_free_controller;
	}

	p->pbm_A.iommu = iommu;

	iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
	if (!iommu) {
		printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
		goto out_free_iommu_A;
	}

	p->pbm_B.iommu = iommu;

	return pci_fire_pbm_init(p, op, portid);

out_free_iommu_A:
	kfree(p->pbm_A.iommu);
			
out_free_controller:
	kfree(p);

out_err:
	return err;
}

static struct of_device_id __initdata fire_match[] = {
	{
		.name = "pci",
		.compatible = "pciex108e,80f0",
	},
	{},
};

static struct of_platform_driver fire_driver = {
	.name		= DRIVER_NAME,
	.match_table	= fire_match,
	.probe		= fire_probe,
};

static int __init fire_init(void)
{
	return of_register_driver(&fire_driver, &of_bus_type);
}

subsys_initcall(fire_init);
Commit	Line	Data
861fe906 DM	1	/* pci_fire.c: Sun4u platform PCI-E controller support.
	2	*
	3	* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
	4	*/
	5	#include <linux/kernel.h>
	6	#include <linux/pci.h>
	7	#include <linux/slab.h>
	8	#include <linux/init.h>
9bb3c227 DM	9	#include <linux/msi.h>
9bb3c227 DM	10	#include <linux/irq.h>
c8049966	11	#include <linux/of_device.h>
861fe906	12
861fe906	13	#include <asm/prom.h>
9bb3c227	14	#include <asm/irq.h>
861fe906 DM	15
	16	#include "pci_impl.h"
	17
c8049966 DM	18	#define DRIVER_NAME "fire"
	19	#define PFX DRIVER_NAME ": "
	20
861fe906 DM	21	#define fire_read(__reg) \
	22	({ u64 __ret; \
	23	__asm__ __volatile__("ldxa [%1] %2, %0" \
	24	: "=r" (__ret) \
	25	: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
	26	: "memory"); \
	27	__ret; \
	28	})
	29	#define fire_write(__reg, __val) \
	30	__asm__ __volatile__("stxa %0, [%1] %2" \
	31	: /* no outputs */ \
	32	: "r" (__val), "r" (__reg), \
	33	"i" (ASI_PHYS_BYPASS_EC_E) \
	34	: "memory")
	35
861fe906 DM	36	#define FIRE_IOMMU_CONTROL 0x40000UL
	37	#define FIRE_IOMMU_TSBBASE 0x40008UL
	38	#define FIRE_IOMMU_FLUSH 0x40100UL
95d71e66	39	#define FIRE_IOMMU_FLUSHINV 0x40108UL
861fe906	40
ad7ad57c	41	static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
861fe906 DM	42	{
	43	struct iommu *iommu = pbm->iommu;
	44	u32 vdma[2], dma_mask;
	45	u64 control;
ad7ad57c	46	int tsbsize, err;
861fe906 DM	47
	48	/* No virtual-dma property on these guys, use largest size. */
	49	vdma[0] = 0xc0000000; /* base */
	50	vdma[1] = 0x40000000; /* size */
	51	dma_mask = 0xffffffff;
	52	tsbsize = 128;
	53
	54	/* Register addresses. */
	55	iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
	56	iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
	57	iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
	58	iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
	59
	60	/* We use the main control/status register of FIRE as the write
	61	* completion register.
	62	*/
	63	iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
	64
	65	/*
	66	* Invalidate TLB Entries.
	67	*/
	68	fire_write(iommu->iommu_flushinv, ~(u64)0);
	69
c1b1a5f1 DM	70	err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
c1b1a5f1 DM	71	pbm->numa_node);
ad7ad57c DM	72	if (err)
ad7ad57c DM	73	return err;
861fe906 DM	74
	75	fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) \| 0x7UL);
	76
	77	control = fire_read(iommu->iommu_control);
	78	control \|= (0x00000400 /* TSB cache snoop enable */ \|
	79	0x00000300 /* Cache mode */ \|
	80	0x00000002 /* Bypass enable */ \|
	81	0x00000001 /* Translation enable */);
	82	fire_write(iommu->iommu_control, control);
ad7ad57c DM	83
ad7ad57c DM	84	return 0;
861fe906 DM	85	}
861fe906 DM	86
9bb3c227 DM	87	#ifdef CONFIG_PCI_MSI
	88	struct pci_msiq_entry {
	89	u64 word0;
	90	#define MSIQ_WORD0_RESV 0x8000000000000000UL
	91	#define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL
	92	#define MSIQ_WORD0_FMT_TYPE_SHIFT 56
	93	#define MSIQ_WORD0_LEN 0x00ffc00000000000UL
	94	#define MSIQ_WORD0_LEN_SHIFT 46
	95	#define MSIQ_WORD0_ADDR0 0x00003fff00000000UL
	96	#define MSIQ_WORD0_ADDR0_SHIFT 32
	97	#define MSIQ_WORD0_RID 0x00000000ffff0000UL
	98	#define MSIQ_WORD0_RID_SHIFT 16
	99	#define MSIQ_WORD0_DATA0 0x000000000000ffffUL
	100	#define MSIQ_WORD0_DATA0_SHIFT 0
	101
	102	#define MSIQ_TYPE_MSG 0x6
	103	#define MSIQ_TYPE_MSI32 0xb
	104	#define MSIQ_TYPE_MSI64 0xf
	105
	106	u64 word1;
	107	#define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL
	108	#define MSIQ_WORD1_ADDR1_SHIFT 16
	109	#define MSIQ_WORD1_DATA1 0x000000000000ffffUL
	110	#define MSIQ_WORD1_DATA1_SHIFT 0
	111
	112	u64 resv[6];
	113	};
	114
	115	/* All MSI registers are offset from pbm->pbm_regs */
	116	#define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL
	117	#define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
	118
	119	#define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL)
	120	#define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL
	121	#define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL
	122
	123	#define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL)
	124	#define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL
	125	#define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL
	126	#define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL
	127
	128	#define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL)
	129	#define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL
	130	#define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL
	131	#define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL
	132	#define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL
	133
	134	#define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL)
	135	#define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL
	136	#define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL
	137
	138	#define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL)
	139	#define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL
	140
	141	#define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL)
	142	#define MSI_MAP_VALID 0x8000000000000000UL
	143	#define MSI_MAP_EQWR_N 0x4000000000000000UL
	144	#define MSI_MAP_EQNUM 0x000000000000003fUL
	145
	146	#define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL)
	147	#define MSI_CLEAR_EQWR_N 0x4000000000000000UL
	148
	149	#define IMONDO_DATA0 0x02C000UL
	150	#define IMONDO_DATA0_DATA 0xffffffffffffffc0UL
151
152	#define IMONDO_DATA1 0x02C008UL
153	#define IMONDO_DATA1_DATA 0xffffffffffffffffUL
154
155	#define MSI_32BIT_ADDR 0x034000UL
156	#define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL
157
158	#define MSI_64BIT_ADDR 0x034008UL
159	#define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL
160
759f89e0 DM	161	static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
	162	unsigned long *head)
	163	{
	164	*head = fire_read(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
	165	return 0;
	166	}
	167
	168	static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
	169	unsigned long head, unsigned long msi)
9bb3c227	170	{
759f89e0	171	unsigned long type_fmt, type, msi_num;
9bb3c227 DM	172	struct pci_msiq_entry base, ep;
9bb3c227 DM	173
759f89e0 DM	174	base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
759f89e0 DM	175	ep = &base[*head];
9bb3c227	176
759f89e0 DM	177	if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
759f89e0 DM	178	return 0;
9bb3c227	179
759f89e0 DM	180	type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
	181	MSIQ_WORD0_FMT_TYPE_SHIFT);
	182	type = (type_fmt >> 3);
	183	if (unlikely(type != MSIQ_TYPE_MSI32 &&
	184	type != MSIQ_TYPE_MSI64))
	185	return -EINVAL;
9bb3c227	186
759f89e0 DM	187	*msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
759f89e0 DM	188	MSIQ_WORD0_DATA0_SHIFT);
9bb3c227	189
759f89e0 DM	190	fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num),
	191	MSI_CLEAR_EQWR_N);
	192
	193	/* Clear the entry. */
	194	ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
	195
	196	/* Go to next entry in ring. */
	197	(*head)++;
	198	if (*head >= pbm->msiq_ent_count)
	199	*head = 0;
	200
	201	return 1;
9bb3c227 DM	202	}
9bb3c227 DM	203
759f89e0 DM	204	static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
759f89e0 DM	205	unsigned long head)
9bb3c227	206	{
759f89e0 DM	207	fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid), head);
	208	return 0;
	209	}
9bb3c227	210
759f89e0 DM	211	static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
	212	unsigned long msi, int is_msi64)
	213	{
	214	u64 val;
9bb3c227	215
759f89e0 DM	216	val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
	217	val &= ~(MSI_MAP_EQNUM);
	218	val \|= msiqid;
	219	fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
	220
	221	fire_write(pbm->pbm_regs + MSI_CLEAR(msi),
	222	MSI_CLEAR_EQWR_N);
	223
	224	val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
	225	val \|= MSI_MAP_VALID;
	226	fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
9bb3c227 DM	227
	228	return 0;
	229	}
	230
759f89e0	231	static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
9bb3c227	232	{
759f89e0 DM	233	unsigned long msiqid;
	234	u64 val;
	235
	236	val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
	237	msiqid = (val & MSI_MAP_EQNUM);
	238
	239	val &= ~MSI_MAP_VALID;
	240
	241	fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
	242
	243	return 0;
9bb3c227 DM	244	}
9bb3c227 DM	245
759f89e0	246	static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
9bb3c227 DM	247	{
	248	unsigned long pages, order, i;
	249
	250	order = get_order(512 * 1024);
	251	pages = __get_free_pages(GFP_KERNEL \| __GFP_COMP, order);
	252	if (pages == 0UL) {
	253	printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
	254	order);
	255	return -ENOMEM;
	256	}
	257	memset((char *)pages, 0, PAGE_SIZE << order);
	258	pbm->msi_queues = (void *) pages;
	259
	260	fire_write(pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG,
	261	(EVENT_QUEUE_BASE_ADDR_ALL_ONES \|
	262	__pa(pbm->msi_queues)));
	263
	264	fire_write(pbm->pbm_regs + IMONDO_DATA0,
	265	pbm->portid << 6);
	266	fire_write(pbm->pbm_regs + IMONDO_DATA1, 0);
	267
	268	fire_write(pbm->pbm_regs + MSI_32BIT_ADDR,
	269	pbm->msi32_start);
	270	fire_write(pbm->pbm_regs + MSI_64BIT_ADDR,
	271	pbm->msi64_start);
	272
	273	for (i = 0; i < pbm->msiq_num; i++) {
	274	fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(i), 0);
	275	fire_write(pbm->pbm_regs + EVENT_QUEUE_TAIL(i), 0);
	276	}
	277
	278	return 0;
	279	}
	280
759f89e0	281	static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
9bb3c227	282	{
759f89e0	283	unsigned long pages, order;
9bb3c227	284
759f89e0 DM	285	order = get_order(512 * 1024);
759f89e0 DM	286	pages = (unsigned long) pbm->msi_queues;
9bb3c227	287
759f89e0	288	free_pages(pages, order);
9bb3c227	289
759f89e0	290	pbm->msi_queues = NULL;
9bb3c227 DM	291	}
9bb3c227 DM	292
759f89e0 DM	293	static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
	294	unsigned long msiqid,
	295	unsigned long devino)
9bb3c227	296	{
759f89e0 DM	297	unsigned long cregs = (unsigned long) pbm->pbm_regs;
	298	unsigned long imap_reg, iclr_reg, int_ctrlr;
	299	unsigned int virt_irq;
	300	int fixup;
9bb3c227 DM	301	u64 val;
9bb3c227 DM	302
759f89e0 DM	303	imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
759f89e0 DM	304	iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
9bb3c227	305
759f89e0 DM	306	/* XXX iterate amongst the 4 IRQ controllers XXX */
759f89e0 DM	307	int_ctrlr = (1UL << 6);
9bb3c227	308
759f89e0 DM	309	val = fire_read(imap_reg);
	310	val \|= (1UL << 63) \| int_ctrlr;
	311	fire_write(imap_reg, val);
9bb3c227	312
759f89e0	313	fixup = ((pbm->portid << 6) \| devino) - int_ctrlr;
9bb3c227	314
759f89e0 DM	315	virt_irq = build_irq(fixup, iclr_reg, imap_reg);
	316	if (!virt_irq)
	317	return -ENOMEM;
9bb3c227 DM	318
	319	fire_write(pbm->pbm_regs +
	320	EVENT_QUEUE_CONTROL_SET(msiqid),
	321	EVENT_QUEUE_CONTROL_SET_EN);
	322
759f89e0	323	return virt_irq;
9bb3c227 DM	324	}
9bb3c227 DM	325
759f89e0 DM	326	static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
	327	.get_head = pci_fire_get_head,
	328	.dequeue_msi = pci_fire_dequeue_msi,
	329	.set_head = pci_fire_set_head,
	330	.msi_setup = pci_fire_msi_setup,
	331	.msi_teardown = pci_fire_msi_teardown,
	332	.msiq_alloc = pci_fire_msiq_alloc,
	333	.msiq_free = pci_fire_msiq_free,
	334	.msiq_build_irq = pci_fire_msiq_build_irq,
	335	};
9bb3c227 DM	336
	337	static void pci_fire_msi_init(struct pci_pbm_info *pbm)
	338	{
759f89e0	339	sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
9bb3c227 DM	340	}
	341	#else /* CONFIG_PCI_MSI */
	342	static void pci_fire_msi_init(struct pci_pbm_info *pbm)
	343	{
	344	}
	345	#endif /* !(CONFIG_PCI_MSI) */
	346
861fe906 DM	347	/* Based at pbm->controller_regs */
	348	#define FIRE_PARITY_CONTROL 0x470010UL
	349	#define FIRE_PARITY_ENAB 0x8000000000000000UL
	350	#define FIRE_FATAL_RESET_CTL 0x471028UL
	351	#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
	352	#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
	353	#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
	354	#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
	355	#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
	356	#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
	357	#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
	358	#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
	359	#define FIRE_CORE_INTR_ENABLE 0x471800UL
	360
	361	/* Based at pbm->pbm_regs */
	362	#define FIRE_TLU_CTRL 0x80000UL
	363	#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
	364	#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
	365	#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
	366	#define FIRE_TLU_DEV_CTRL 0x90008UL
	367	#define FIRE_TLU_LINK_CTRL 0x90020UL
	368	#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
	369	#define FIRE_LPU_RESET 0xe2008UL
	370	#define FIRE_LPU_LLCFG 0xe2200UL
	371	#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
	372	#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
	373	#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
	374	#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
	375	#define FIRE_LPU_TXL_FIFOP 0xe2430UL
	376	#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
	377	#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
	378	#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
	379	#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
	380	#define FIRE_DMC_IENAB 0x31800UL
	381	#define FIRE_DMC_DBG_SEL_A 0x53000UL
	382	#define FIRE_DMC_DBG_SEL_B 0x53008UL
	383	#define FIRE_PEC_IENAB 0x51800UL
	384
	385	static void pci_fire_hw_init(struct pci_pbm_info *pbm)
	386	{
	387	u64 val;
	388
	389	fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
	390	FIRE_PARITY_ENAB);
	391
	392	fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
	393	(FIRE_FATAL_RESET_SPARE \|
	394	FIRE_FATAL_RESET_MB \|
	395	FIRE_FATAL_RESET_CPE \|
	396	FIRE_FATAL_RESET_APE \|
	397	FIRE_FATAL_RESET_PIO \|
	398	FIRE_FATAL_RESET_JW \|
	399	FIRE_FATAL_RESET_JI \|
	400	FIRE_FATAL_RESET_JR));
	401
	402	fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
	403
	404	val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
	405	val \|= (FIRE_TLU_CTRL_TIM \|
	406	FIRE_TLU_CTRL_QDET \|
	407	FIRE_TLU_CTRL_CFG);
	408	fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
	409	fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
	410	fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
411	FIRE_TLU_LINK_CTRL_CLK);
412
413	fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
414	fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
415	FIRE_LPU_LLCFG_VC0);
416	fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
417	(FIRE_LPU_FCTRL_UCTRL_N \|
418	FIRE_LPU_FCTRL_UCTRL_P));
419	fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
420	((0xffff << 16) \| (0x0000 << 0)));
421	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
422	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
423	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
424	(2 << 16) \| (140 << 8));
425	fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
426
427	fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
428	fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
429	fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
430
431	fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
432	}
433
a1f35ba3	434	static int __init pci_fire_pbm_init(struct pci_controller_info *p,
e822358a	435	struct of_device *op, u32 portid)
861fe906 DM	436	{
861fe906 DM	437	const struct linux_prom64_registers *regs;
e822358a	438	struct device_node *dp = op->node;
861fe906	439	struct pci_pbm_info *pbm;
9bb3c227	440	int err;
861fe906 DM	441
	442	if ((portid & 1) == 0)
	443	pbm = &p->pbm_A;
	444	else
	445	pbm = &p->pbm_B;
	446
34768bc8 DM	447	pbm->next = pci_pbm_root;
	448	pci_pbm_root = pbm;
	449
c1b1a5f1 DM	450	pbm->numa_node = -1;
c1b1a5f1 DM	451
ca3dd88e DM	452	pbm->pci_ops = &sun4u_pci_ops;
ca3dd88e DM	453	pbm->config_space_reg_bits = 12;
34768bc8	454
6c108f12 DM	455	pbm->index = pci_num_pbms++;
6c108f12 DM	456
861fe906 DM	457	pbm->portid = portid;
	458	pbm->parent = p;
	459	pbm->prom_node = dp;
	460	pbm->name = dp->full_name;
	461
	462	regs = of_get_property(dp, "reg", NULL);
	463	pbm->pbm_regs = regs[0].phys_addr;
	464	pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
	465
	466	printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
	467
	468	pci_determine_mem_io_space(pbm);
	469
cfa0652c	470	pci_get_pbm_props(pbm);
861fe906 DM	471
861fe906 DM	472	pci_fire_hw_init(pbm);
ad7ad57c	473
9bb3c227 DM	474	err = pci_fire_pbm_iommu_init(pbm);
	475	if (err)
	476	return err;
	477
	478	pci_fire_msi_init(pbm);
	479
e822358a DM	480	pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
	481
	482	/* XXX register error interrupt handlers XXX */
c8049966	483
9bb3c227	484	return 0;
861fe906 DM	485	}
	486
	487	static inline int portid_compare(u32 x, u32 y)
	488	{
	489	if (x == (y ^ 1))
	490	return 1;
	491	return 0;
	492	}
	493
c8049966 DM	494	static int __devinit fire_probe(struct of_device *op,
c8049966 DM	495	const struct of_device_id *match)
861fe906	496	{
c8049966	497	struct device_node *dp = op->node;
861fe906	498	struct pci_controller_info *p;
34768bc8	499	struct pci_pbm_info *pbm;
c8049966 DM	500	struct iommu *iommu;
	501	u32 portid;
	502	int err;
861fe906	503
c8049966	504	portid = of_getintprop_default(dp, "portid", 0xff);
34768bc8	505	for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
c8049966	506	if (portid_compare(pbm->portid, portid))
e822358a	507	return pci_fire_pbm_init(pbm->parent, op, portid);
861fe906 DM	508	}
861fe906 DM	509
c8049966	510	err = -ENOMEM;
861fe906	511	p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
c8049966 DM	512	if (!p) {
c8049966 DM	513	printk(KERN_ERR PFX "Cannot allocate controller info.\n");
d7472c38	514	goto out_err;
c8049966	515	}
861fe906 DM	516
861fe906 DM	517	iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
c8049966 DM	518	if (!iommu) {
c8049966 DM	519	printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
d7472c38	520	goto out_free_controller;
c8049966	521	}
861fe906 DM	522
	523	p->pbm_A.iommu = iommu;
	524
	525	iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
c8049966 DM	526	if (!iommu) {
c8049966 DM	527	printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
d7472c38	528	goto out_free_iommu_A;
c8049966	529	}
861fe906 DM	530
	531	p->pbm_B.iommu = iommu;
	532
e822358a	533	return pci_fire_pbm_init(p, op, portid);
ad7ad57c	534
d7472c38 DM	535	out_free_iommu_A:
	536	kfree(p->pbm_A.iommu);
	537
	538	out_free_controller:
	539	kfree(p);
	540
	541	out_err:
c8049966 DM	542	return err;
	543	}
	544
fd098316	545	static struct of_device_id __initdata fire_match[] = {
c8049966 DM	546	{
	547	.name = "pci",
	548	.compatible = "pciex108e,80f0",
	549	},
	550	{},
	551	};
861fe906	552
c8049966 DM	553	static struct of_platform_driver fire_driver = {
	554	.name = DRIVER_NAME,
	555	.match_table = fire_match,
	556	.probe = fire_probe,
	557	};
	558
	559	static int __init fire_init(void)
	560	{
	561	return of_register_driver(&fire_driver, &of_bus_type);
861fe906	562	}
c8049966 DM	563
c8049966 DM	564	subsys_initcall(fire_init);