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sparc: Annotate of_device_id arrays with const or __initdata.
[deliverable/linux.git] / arch / sparc64 / kernel / pci_fire.c
CommitLineData
861fe906
DM		 1/* pci_fire.c: Sun4u platform PCI-E controller support.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5#include <linux/kernel.h>
6#include <linux/pci.h>
7#include <linux/slab.h>
8#include <linux/init.h>
9bb3c227
DM		 9#include <linux/msi.h>
10#include <linux/irq.h>
c8049966 11#include <linux/of_device.h>
861fe906 12
861fe906 13#include <asm/prom.h>
9bb3c227 14#include <asm/irq.h>
861fe906
DM		 15
16#include "pci_impl.h"
17
c8049966
DM		 18#define DRIVER_NAME "fire"
19#define PFX DRIVER_NAME ": "
20
861fe906
DM		 21#define fire_read(__reg) \
22({ u64 __ret; \
23 __asm__ __volatile__("ldxa [%1] %2, %0" \
24 : "=r" (__ret) \
25 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
26 : "memory"); \
27 __ret; \
28})
29#define fire_write(__reg, __val) \
30 __asm__ __volatile__("stxa %0, [%1] %2" \
31 : /* no outputs */ \
32 : "r" (__val), "r" (__reg), \
33 "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory")
35
a1f35ba3 36static void __init pci_fire_scan_bus(struct pci_pbm_info *pbm)
861fe906
DM		 37{
38 pbm->pci_bus = pci_scan_one_pbm(pbm);
861fe906
DM		 39
40 /* XXX register error interrupt handlers XXX */
41}
42
43#define FIRE_IOMMU_CONTROL 0x40000UL
44#define FIRE_IOMMU_TSBBASE 0x40008UL
45#define FIRE_IOMMU_FLUSH 0x40100UL
95d71e66 46#define FIRE_IOMMU_FLUSHINV 0x40108UL
861fe906 47
ad7ad57c 48static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
861fe906
DM		 49{
50 struct iommu *iommu = pbm->iommu;
51 u32 vdma[2], dma_mask;
52 u64 control;
ad7ad57c 53 int tsbsize, err;
861fe906
DM		 54
55 /* No virtual-dma property on these guys, use largest size. */
56 vdma[0] = 0xc0000000; /* base */
57 vdma[1] = 0x40000000; /* size */
58 dma_mask = 0xffffffff;
59 tsbsize = 128;
60
61 /* Register addresses. */
62 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
63 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
64 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
65 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
66
67 /* We use the main control/status register of FIRE as the write
68 * completion register.
69 */
70 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
71
72 /*
73 * Invalidate TLB Entries.
74 */
75 fire_write(iommu->iommu_flushinv, ~(u64)0);
76
c1b1a5f1
DM		 77 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
78 pbm->numa_node);
ad7ad57c
DM		 79 if (err)
80 return err;
861fe906
DM		 81
82 fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
83
84 control = fire_read(iommu->iommu_control);
85 control |= (0x00000400 /* TSB cache snoop enable */ |
86 0x00000300 /* Cache mode */ |
87 0x00000002 /* Bypass enable */ |
88 0x00000001 /* Translation enable */);
89 fire_write(iommu->iommu_control, control);
ad7ad57c
DM		 90
91 return 0;
861fe906
DM		 92}
93
9bb3c227
DM		 94#ifdef CONFIG_PCI_MSI
95struct pci_msiq_entry {
96 u64 word0;
97#define MSIQ_WORD0_RESV 0x8000000000000000UL
98#define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL
99#define MSIQ_WORD0_FMT_TYPE_SHIFT 56
100#define MSIQ_WORD0_LEN 0x00ffc00000000000UL
101#define MSIQ_WORD0_LEN_SHIFT 46
102#define MSIQ_WORD0_ADDR0 0x00003fff00000000UL
103#define MSIQ_WORD0_ADDR0_SHIFT 32
104#define MSIQ_WORD0_RID 0x00000000ffff0000UL
105#define MSIQ_WORD0_RID_SHIFT 16
106#define MSIQ_WORD0_DATA0 0x000000000000ffffUL
107#define MSIQ_WORD0_DATA0_SHIFT 0
108
109#define MSIQ_TYPE_MSG 0x6
110#define MSIQ_TYPE_MSI32 0xb
111#define MSIQ_TYPE_MSI64 0xf
112
113 u64 word1;
114#define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL
115#define MSIQ_WORD1_ADDR1_SHIFT 16
116#define MSIQ_WORD1_DATA1 0x000000000000ffffUL
117#define MSIQ_WORD1_DATA1_SHIFT 0
118
119 u64 resv[6];
120};
121
122/* All MSI registers are offset from pbm->pbm_regs */
123#define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL
124#define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
125
126#define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL)
127#define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL
128#define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL
129
130#define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL)
131#define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL
132#define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL
133#define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL
134
135#define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL)
136#define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL
137#define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL
138#define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL
139#define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL
140
141#define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL)
142#define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL
143#define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL
144
145#define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL)
146#define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL
147
148#define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL)
149#define MSI_MAP_VALID 0x8000000000000000UL
150#define MSI_MAP_EQWR_N 0x4000000000000000UL
151#define MSI_MAP_EQNUM 0x000000000000003fUL
152
153#define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL)
154#define MSI_CLEAR_EQWR_N 0x4000000000000000UL
155
156#define IMONDO_DATA0 0x02C000UL
157#define IMONDO_DATA0_DATA 0xffffffffffffffc0UL
158
159#define IMONDO_DATA1 0x02C008UL
160#define IMONDO_DATA1_DATA 0xffffffffffffffffUL
161
162#define MSI_32BIT_ADDR 0x034000UL
163#define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL
164
165#define MSI_64BIT_ADDR 0x034008UL
166#define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL
167
759f89e0
DM		 168static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
169 unsigned long *head)
170{
171 *head = fire_read(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
172 return 0;
173}
174
175static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
176 unsigned long *head, unsigned long *msi)
9bb3c227 177{
759f89e0 178 unsigned long type_fmt, type, msi_num;
9bb3c227
DM		 179 struct pci_msiq_entry *base, *ep;
180
759f89e0
DM		 181 base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
182 ep = &base[*head];
9bb3c227 183
759f89e0
DM		 184 if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
185 return 0;
9bb3c227 186
759f89e0
DM		 187 type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
188 MSIQ_WORD0_FMT_TYPE_SHIFT);
189 type = (type_fmt >> 3);
190 if (unlikely(type != MSIQ_TYPE_MSI32 &&
191 type != MSIQ_TYPE_MSI64))
192 return -EINVAL;
9bb3c227 193
759f89e0
DM		 194 *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
195 MSIQ_WORD0_DATA0_SHIFT);
9bb3c227 196
759f89e0
DM		 197 fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num),
198 MSI_CLEAR_EQWR_N);
199
200 /* Clear the entry. */
201 ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
202
203 /* Go to next entry in ring. */
204 (*head)++;
205 if (*head >= pbm->msiq_ent_count)
206 *head = 0;
207
208 return 1;
9bb3c227
DM		 209}
210
759f89e0
DM		 211static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
212 unsigned long head)
9bb3c227 213{
759f89e0
DM		 214 fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid), head);
215 return 0;
216}
9bb3c227 217
759f89e0
DM		 218static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
219 unsigned long msi, int is_msi64)
220{
221 u64 val;
9bb3c227 222
759f89e0
DM		 223 val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
224 val &= ~(MSI_MAP_EQNUM);
225 val |= msiqid;
226 fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
227
228 fire_write(pbm->pbm_regs + MSI_CLEAR(msi),
229 MSI_CLEAR_EQWR_N);
230
231 val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
232 val |= MSI_MAP_VALID;
233 fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
9bb3c227
DM		 234
235 return 0;
236}
237
759f89e0 238static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
9bb3c227 239{
759f89e0
DM		 240 unsigned long msiqid;
241 u64 val;
242
243 val = fire_read(pbm->pbm_regs + MSI_MAP(msi));
244 msiqid = (val & MSI_MAP_EQNUM);
245
246 val &= ~MSI_MAP_VALID;
247
248 fire_write(pbm->pbm_regs + MSI_MAP(msi), val);
249
250 return 0;
9bb3c227
DM		 251}
252
759f89e0 253static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
9bb3c227
DM		 254{
255 unsigned long pages, order, i;
256
257 order = get_order(512 * 1024);
258 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
259 if (pages == 0UL) {
260 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
261 order);
262 return -ENOMEM;
263 }
264 memset((char *)pages, 0, PAGE_SIZE << order);
265 pbm->msi_queues = (void *) pages;
266
267 fire_write(pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG,
268 (EVENT_QUEUE_BASE_ADDR_ALL_ONES |
269 __pa(pbm->msi_queues)));
270
271 fire_write(pbm->pbm_regs + IMONDO_DATA0,
272 pbm->portid << 6);
273 fire_write(pbm->pbm_regs + IMONDO_DATA1, 0);
274
275 fire_write(pbm->pbm_regs + MSI_32BIT_ADDR,
276 pbm->msi32_start);
277 fire_write(pbm->pbm_regs + MSI_64BIT_ADDR,
278 pbm->msi64_start);
279
280 for (i = 0; i < pbm->msiq_num; i++) {
281 fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(i), 0);
282 fire_write(pbm->pbm_regs + EVENT_QUEUE_TAIL(i), 0);
283 }
284
285 return 0;
286}
287
759f89e0 288static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
9bb3c227 289{
759f89e0 290 unsigned long pages, order;
9bb3c227 291
759f89e0
DM		 292 order = get_order(512 * 1024);
293 pages = (unsigned long) pbm->msi_queues;
9bb3c227 294
759f89e0 295 free_pages(pages, order);
9bb3c227 296
759f89e0 297 pbm->msi_queues = NULL;
9bb3c227
DM		 298}
299
759f89e0
DM		 300static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
301 unsigned long msiqid,
302 unsigned long devino)
9bb3c227 303{
759f89e0
DM		 304 unsigned long cregs = (unsigned long) pbm->pbm_regs;
305 unsigned long imap_reg, iclr_reg, int_ctrlr;
306 unsigned int virt_irq;
307 int fixup;
9bb3c227
DM		 308 u64 val;
309
759f89e0
DM		 310 imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
311 iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
9bb3c227 312
759f89e0
DM		 313 /* XXX iterate amongst the 4 IRQ controllers XXX */
314 int_ctrlr = (1UL << 6);
9bb3c227 315
759f89e0
DM		 316 val = fire_read(imap_reg);
317 val |= (1UL << 63) | int_ctrlr;
318 fire_write(imap_reg, val);
9bb3c227 319
759f89e0 320 fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
9bb3c227 321
759f89e0
DM		 322 virt_irq = build_irq(fixup, iclr_reg, imap_reg);
323 if (!virt_irq)
324 return -ENOMEM;
9bb3c227
DM		 325
326 fire_write(pbm->pbm_regs +
327 EVENT_QUEUE_CONTROL_SET(msiqid),
328 EVENT_QUEUE_CONTROL_SET_EN);
329
759f89e0 330 return virt_irq;
9bb3c227
DM		 331}
332
759f89e0
DM		 333static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
334 .get_head = pci_fire_get_head,
335 .dequeue_msi = pci_fire_dequeue_msi,
336 .set_head = pci_fire_set_head,
337 .msi_setup = pci_fire_msi_setup,
338 .msi_teardown = pci_fire_msi_teardown,
339 .msiq_alloc = pci_fire_msiq_alloc,
340 .msiq_free = pci_fire_msiq_free,
341 .msiq_build_irq = pci_fire_msiq_build_irq,
342};
9bb3c227
DM		 343
344static void pci_fire_msi_init(struct pci_pbm_info *pbm)
345{
759f89e0 346 sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
9bb3c227
DM		 347}
348#else /* CONFIG_PCI_MSI */
349static void pci_fire_msi_init(struct pci_pbm_info *pbm)
350{
351}
352#endif /* !(CONFIG_PCI_MSI) */
353
861fe906
DM		 354/* Based at pbm->controller_regs */
355#define FIRE_PARITY_CONTROL 0x470010UL
356#define FIRE_PARITY_ENAB 0x8000000000000000UL
357#define FIRE_FATAL_RESET_CTL 0x471028UL
358#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
359#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
360#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
361#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
362#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
363#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
364#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
365#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
366#define FIRE_CORE_INTR_ENABLE 0x471800UL
367
368/* Based at pbm->pbm_regs */
369#define FIRE_TLU_CTRL 0x80000UL
370#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
371#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
372#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
373#define FIRE_TLU_DEV_CTRL 0x90008UL
374#define FIRE_TLU_LINK_CTRL 0x90020UL
375#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
376#define FIRE_LPU_RESET 0xe2008UL
377#define FIRE_LPU_LLCFG 0xe2200UL
378#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
379#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
380#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
381#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
382#define FIRE_LPU_TXL_FIFOP 0xe2430UL
383#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
384#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
385#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
386#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
387#define FIRE_DMC_IENAB 0x31800UL
388#define FIRE_DMC_DBG_SEL_A 0x53000UL
389#define FIRE_DMC_DBG_SEL_B 0x53008UL
390#define FIRE_PEC_IENAB 0x51800UL
391
392static void pci_fire_hw_init(struct pci_pbm_info *pbm)
393{
394 u64 val;
395
396 fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
397 FIRE_PARITY_ENAB);
398
399 fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
400 (FIRE_FATAL_RESET_SPARE |
401 FIRE_FATAL_RESET_MB |
402 FIRE_FATAL_RESET_CPE |
403 FIRE_FATAL_RESET_APE |
404 FIRE_FATAL_RESET_PIO |
405 FIRE_FATAL_RESET_JW |
406 FIRE_FATAL_RESET_JI |
407 FIRE_FATAL_RESET_JR));
408
409 fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
410
411 val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
412 val |= (FIRE_TLU_CTRL_TIM |
413 FIRE_TLU_CTRL_QDET |
414 FIRE_TLU_CTRL_CFG);
415 fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
416 fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
417 fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
418 FIRE_TLU_LINK_CTRL_CLK);
419
420 fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
421 fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
422 FIRE_LPU_LLCFG_VC0);
423 fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
424 (FIRE_LPU_FCTRL_UCTRL_N |
425 FIRE_LPU_FCTRL_UCTRL_P));
426 fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
427 ((0xffff << 16) | (0x0000 << 0)));
428 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
429 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
430 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
431 (2 << 16) | (140 << 8));
432 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
433
434 fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
435 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
436 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
437
438 fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
439}
440
a1f35ba3
SR		 441static int __init pci_fire_pbm_init(struct pci_controller_info *p,
442 struct device_node *dp, u32 portid)
861fe906
DM		 443{
444 const struct linux_prom64_registers *regs;
445 struct pci_pbm_info *pbm;
9bb3c227 446 int err;
861fe906
DM		 447
448 if ((portid & 1) == 0)
449 pbm = &p->pbm_A;
450 else
451 pbm = &p->pbm_B;
452
34768bc8
DM		 453 pbm->next = pci_pbm_root;
454 pci_pbm_root = pbm;
455
c1b1a5f1
DM		 456 pbm->numa_node = -1;
457
ca3dd88e
DM		 458 pbm->pci_ops = &sun4u_pci_ops;
459 pbm->config_space_reg_bits = 12;
34768bc8 460
6c108f12
DM		 461 pbm->index = pci_num_pbms++;
462
861fe906
DM		 463 pbm->portid = portid;
464 pbm->parent = p;
465 pbm->prom_node = dp;
466 pbm->name = dp->full_name;
467
468 regs = of_get_property(dp, "reg", NULL);
469 pbm->pbm_regs = regs[0].phys_addr;
470 pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
471
472 printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
473
474 pci_determine_mem_io_space(pbm);
475
cfa0652c 476 pci_get_pbm_props(pbm);
861fe906
DM		 477
478 pci_fire_hw_init(pbm);
ad7ad57c 479
9bb3c227
DM		 480 err = pci_fire_pbm_iommu_init(pbm);
481 if (err)
482 return err;
483
484 pci_fire_msi_init(pbm);
485
c8049966
DM		 486 pci_fire_scan_bus(pbm);
487
9bb3c227 488 return 0;
861fe906
DM		 489}
490
491static inline int portid_compare(u32 x, u32 y)
492{
493 if (x == (y ^ 1))
494 return 1;
495 return 0;
496}
497
c8049966
DM		 498static int __devinit fire_probe(struct of_device *op,
499 const struct of_device_id *match)
861fe906 500{
c8049966 501 struct device_node *dp = op->node;
861fe906 502 struct pci_controller_info *p;
34768bc8 503 struct pci_pbm_info *pbm;
c8049966
DM		 504 struct iommu *iommu;
505 u32 portid;
506 int err;
861fe906 507
c8049966 508 portid = of_getintprop_default(dp, "portid", 0xff);
34768bc8 509 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
c8049966
DM		 510 if (portid_compare(pbm->portid, portid))
511 return pci_fire_pbm_init(pbm->parent, dp, portid);
861fe906
DM		 512 }
513
c8049966 514 err = -ENOMEM;
861fe906 515 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
c8049966
DM		 516 if (!p) {
517 printk(KERN_ERR PFX "Cannot allocate controller info.\n");
518 goto out_free;
519 }
861fe906
DM		 520
521 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
c8049966
DM		 522 if (!iommu) {
523 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
524 goto out_free;
525 }
861fe906
DM		 526
527 p->pbm_A.iommu = iommu;
528
529 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
c8049966
DM		 530 if (!iommu) {
531 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
532 goto out_free;
533 }
861fe906
DM		 534
535 p->pbm_B.iommu = iommu;
536
c8049966 537 return pci_fire_pbm_init(p, dp, portid);
ad7ad57c 538
c8049966
DM		 539out_free:
540 if (p) {
541 if (p->pbm_A.iommu)
542 kfree(p->pbm_A.iommu);
543 if (p->pbm_B.iommu)
544 kfree(p->pbm_B.iommu);
545 kfree(p);
546 }
547 return err;
548}
549
fd098316 550static struct of_device_id __initdata fire_match[] = {
c8049966
DM		 551 {
552 .name = "pci",
553 .compatible = "pciex108e,80f0",
554 },
555 {},
556};
861fe906 557
c8049966
DM		 558static struct of_platform_driver fire_driver = {
559 .name = DRIVER_NAME,
560 .match_table = fire_match,
561 .probe = fire_probe,
562};
563
564static int __init fire_init(void)
565{
566 return of_register_driver(&fire_driver, &of_bus_type);
861fe906 567}
c8049966
DM		 568
569subsys_initcall(fire_init);
Linux kernel - Deliverables
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