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9fd8b647 | 1 | /* pci_impl.h: Helper definitions for PCI controller support. |
1da177e4 | 2 | * |
9fd8b647 | 3 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
6 | #ifndef PCI_IMPL_H | |
7 | #define PCI_IMPL_H | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <linux/spinlock.h> | |
c57c2ffb DM |
11 | #include <linux/pci.h> |
12 | #include <linux/msi.h> | |
1da177e4 | 13 | #include <asm/io.h> |
de8d28b1 | 14 | #include <asm/prom.h> |
c57c2ffb DM |
15 | #include <asm/iommu.h> |
16 | ||
17 | /* The abstraction used here is that there are PCI controllers, | |
18 | * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules | |
19 | * underneath. Each PCI bus module uses an IOMMU (shared by both | |
20 | * PBMs of a controller, or per-PBM), and if a streaming buffer | |
21 | * is present, each PCI bus module has it's own. (ie. the IOMMU | |
22 | * might be shared between PBMs, the STC is never shared) | |
23 | * Furthermore, each PCI bus module controls it's own autonomous | |
24 | * PCI bus. | |
25 | */ | |
26 | ||
27 | #define PCI_STC_FLUSHFLAG_INIT(STC) \ | |
28 | (*((STC)->strbuf_flushflag) = 0UL) | |
29 | #define PCI_STC_FLUSHFLAG_SET(STC) \ | |
30 | (*((STC)->strbuf_flushflag) != 0UL) | |
31 | ||
759f89e0 DM |
32 | #ifdef CONFIG_PCI_MSI |
33 | struct pci_pbm_info; | |
34 | struct sparc64_msiq_ops { | |
35 | int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
36 | unsigned long *head); | |
37 | int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
38 | unsigned long *head, unsigned long *msi); | |
39 | int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
40 | unsigned long head); | |
41 | int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
42 | unsigned long msi, int is_msi64); | |
43 | int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi); | |
44 | int (*msiq_alloc)(struct pci_pbm_info *pbm); | |
45 | void (*msiq_free)(struct pci_pbm_info *pbm); | |
46 | int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
47 | unsigned long devino); | |
48 | }; | |
49 | ||
50 | extern void sparc64_pbm_msi_init(struct pci_pbm_info *pbm, | |
51 | const struct sparc64_msiq_ops *ops); | |
52 | ||
53 | struct sparc64_msiq_cookie { | |
54 | struct pci_pbm_info *pbm; | |
55 | unsigned long msiqid; | |
56 | }; | |
57 | #endif | |
58 | ||
c57c2ffb DM |
59 | struct pci_controller_info; |
60 | ||
61 | struct pci_pbm_info { | |
62 | struct pci_pbm_info *next; | |
63 | int index; | |
64 | ||
65 | /* PCI controller we sit under. */ | |
66 | struct pci_controller_info *parent; | |
67 | ||
68 | /* Physical address base of controller registers. */ | |
69 | unsigned long controller_regs; | |
70 | ||
71 | /* Physical address base of PBM registers. */ | |
72 | unsigned long pbm_regs; | |
73 | ||
74 | /* Physical address of DMA sync register, if any. */ | |
75 | unsigned long sync_reg; | |
76 | ||
77 | /* Opaque 32-bit system bus Port ID. */ | |
78 | u32 portid; | |
79 | ||
80 | /* Opaque 32-bit handle used for hypervisor calls. */ | |
81 | u32 devhandle; | |
82 | ||
83 | /* Chipset version information. */ | |
84 | int chip_type; | |
85 | #define PBM_CHIP_TYPE_SABRE 1 | |
86 | #define PBM_CHIP_TYPE_PSYCHO 2 | |
87 | #define PBM_CHIP_TYPE_SCHIZO 3 | |
88 | #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 | |
89 | #define PBM_CHIP_TYPE_TOMATILLO 5 | |
90 | int chip_version; | |
91 | int chip_revision; | |
92 | ||
93 | /* Name used for top-level resources. */ | |
94 | char *name; | |
95 | ||
96 | /* OBP specific information. */ | |
97 | struct device_node *prom_node; | |
98 | u64 ino_bitmap; | |
99 | ||
100 | /* PBM I/O and Memory space resources. */ | |
101 | struct resource io_space; | |
102 | struct resource mem_space; | |
103 | ||
104 | /* Base of PCI Config space, can be per-PBM or shared. */ | |
105 | unsigned long config_space; | |
106 | ||
ca3dd88e DM |
107 | /* This will be 12 on PCI-E controllers, 8 elsewhere. */ |
108 | unsigned long config_space_reg_bits; | |
109 | ||
c57c2ffb DM |
110 | /* State of 66MHz capabilities on this PBM. */ |
111 | int is_66mhz_capable; | |
112 | int all_devs_66mhz; | |
113 | ||
114 | #ifdef CONFIG_PCI_MSI | |
115 | /* MSI info. */ | |
116 | u32 msiq_num; | |
117 | u32 msiq_ent_count; | |
118 | u32 msiq_first; | |
119 | u32 msiq_first_devino; | |
759f89e0 DM |
120 | u32 msiq_rotor; |
121 | struct sparc64_msiq_cookie *msiq_irq_cookies; | |
c57c2ffb DM |
122 | u32 msi_num; |
123 | u32 msi_first; | |
124 | u32 msi_data_mask; | |
125 | u32 msix_data_width; | |
126 | u64 msi32_start; | |
127 | u64 msi64_start; | |
128 | u32 msi32_len; | |
129 | u32 msi64_len; | |
130 | void *msi_queues; | |
131 | unsigned long *msi_bitmap; | |
759f89e0 | 132 | unsigned int *msi_irq_table; |
c57c2ffb DM |
133 | int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev, |
134 | struct msi_desc *entry); | |
135 | void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev); | |
759f89e0 | 136 | const struct sparc64_msiq_ops *msi_ops; |
c57c2ffb DM |
137 | #endif /* !(CONFIG_PCI_MSI) */ |
138 | ||
139 | /* This PBM's streaming buffer. */ | |
140 | struct strbuf stc; | |
141 | ||
142 | /* IOMMU state, potentially shared by both PBM segments. */ | |
143 | struct iommu *iommu; | |
144 | ||
145 | /* Now things for the actual PCI bus probes. */ | |
146 | unsigned int pci_first_busno; | |
147 | unsigned int pci_last_busno; | |
148 | struct pci_bus *pci_bus; | |
149 | void (*scan_bus)(struct pci_pbm_info *); | |
150 | struct pci_ops *pci_ops; | |
c1b1a5f1 DM |
151 | |
152 | int numa_node; | |
c57c2ffb DM |
153 | }; |
154 | ||
155 | struct pci_controller_info { | |
156 | /* The PCI bus modules controlled by us. */ | |
157 | struct pci_pbm_info pbm_A; | |
158 | struct pci_pbm_info pbm_B; | |
159 | }; | |
1da177e4 | 160 | |
34768bc8 | 161 | extern struct pci_pbm_info *pci_pbm_root; |
1da177e4 | 162 | |
6c108f12 | 163 | extern int pci_num_pbms; |
1da177e4 LT |
164 | |
165 | /* PCI bus scanning and fixup support. */ | |
cfa0652c | 166 | extern void pci_get_pbm_props(struct pci_pbm_info *pbm); |
a2fb23af | 167 | extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm); |
9fd8b647 | 168 | extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm); |
1da177e4 LT |
169 | |
170 | /* Error reporting support. */ | |
6c108f12 DM |
171 | extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *); |
172 | extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *); | |
173 | extern void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *); | |
1da177e4 LT |
174 | |
175 | /* Configuration space access. */ | |
176 | extern void pci_config_read8(u8 *addr, u8 *ret); | |
177 | extern void pci_config_read16(u16 *addr, u16 *ret); | |
178 | extern void pci_config_read32(u32 *addr, u32 *ret); | |
179 | extern void pci_config_write8(u8 *addr, u8 val); | |
180 | extern void pci_config_write16(u16 *addr, u16 val); | |
181 | extern void pci_config_write32(u32 *addr, u32 val); | |
182 | ||
ca3dd88e DM |
183 | extern struct pci_ops sun4u_pci_ops; |
184 | extern struct pci_ops sun4v_pci_ops; | |
185 | ||
1da177e4 | 186 | #endif /* !(PCI_IMPL_H) */ |