Commit | Line | Data |
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1da177e4 LT |
1 | /* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $ |
2 | * pci_iommu.c: UltraSparc PCI controller IOM/STC support. | |
3 | * | |
4 | * Copyright (C) 1999 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com) | |
6 | */ | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/mm.h> | |
4dbc30fb | 11 | #include <linux/delay.h> |
1da177e4 LT |
12 | |
13 | #include <asm/pbm.h> | |
14 | ||
15 | #include "iommu_common.h" | |
16 | ||
17 | #define PCI_STC_CTXMATCH_ADDR(STC, CTX) \ | |
18 | ((STC)->strbuf_ctxmatch_base + ((CTX) << 3)) | |
19 | ||
20 | /* Accessing IOMMU and Streaming Buffer registers. | |
21 | * REG parameter is a physical address. All registers | |
22 | * are 64-bits in size. | |
23 | */ | |
24 | #define pci_iommu_read(__reg) \ | |
25 | ({ u64 __ret; \ | |
26 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
27 | : "=r" (__ret) \ | |
28 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
29 | : "memory"); \ | |
30 | __ret; \ | |
31 | }) | |
32 | #define pci_iommu_write(__reg, __val) \ | |
33 | __asm__ __volatile__("stxa %0, [%1] %2" \ | |
34 | : /* no outputs */ \ | |
35 | : "r" (__val), "r" (__reg), \ | |
36 | "i" (ASI_PHYS_BYPASS_EC_E)) | |
37 | ||
38 | /* Must be invoked under the IOMMU lock. */ | |
39 | static void __iommu_flushall(struct pci_iommu *iommu) | |
40 | { | |
41 | unsigned long tag; | |
42 | int entry; | |
43 | ||
44 | tag = iommu->iommu_flush + (0xa580UL - 0x0210UL); | |
45 | for (entry = 0; entry < 16; entry++) { | |
46 | pci_iommu_write(tag, 0); | |
47 | tag += 8; | |
48 | } | |
49 | ||
50 | /* Ensure completion of previous PIO writes. */ | |
51 | (void) pci_iommu_read(iommu->write_complete_reg); | |
1da177e4 LT |
52 | } |
53 | ||
54 | #define IOPTE_CONSISTENT(CTX) \ | |
55 | (IOPTE_VALID | IOPTE_CACHE | \ | |
56 | (((CTX) << 47) & IOPTE_CONTEXT)) | |
57 | ||
58 | #define IOPTE_STREAMING(CTX) \ | |
59 | (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF) | |
60 | ||
61 | /* Existing mappings are never marked invalid, instead they | |
62 | * are pointed to a dummy page. | |
63 | */ | |
64 | #define IOPTE_IS_DUMMY(iommu, iopte) \ | |
65 | ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa) | |
66 | ||
24fc6f00 | 67 | static inline void iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte) |
1da177e4 LT |
68 | { |
69 | unsigned long val = iopte_val(*iopte); | |
70 | ||
71 | val &= ~IOPTE_PAGE; | |
72 | val |= iommu->dummy_page_pa; | |
73 | ||
74 | iopte_val(*iopte) = val; | |
75 | } | |
76 | ||
688cb30b DM |
77 | /* Based largely upon the ppc64 iommu allocator. */ |
78 | static long pci_arena_alloc(struct pci_iommu *iommu, unsigned long npages) | |
79 | { | |
80 | struct pci_iommu_arena *arena = &iommu->arena; | |
81 | unsigned long n, i, start, end, limit; | |
82 | int pass; | |
83 | ||
84 | limit = arena->limit; | |
85 | start = arena->hint; | |
86 | pass = 0; | |
87 | ||
88 | again: | |
89 | n = find_next_zero_bit(arena->map, limit, start); | |
90 | end = n + npages; | |
91 | if (unlikely(end >= limit)) { | |
92 | if (likely(pass < 1)) { | |
93 | limit = start; | |
94 | start = 0; | |
95 | __iommu_flushall(iommu); | |
96 | pass++; | |
97 | goto again; | |
98 | } else { | |
99 | /* Scanned the whole thing, give up. */ | |
100 | return -1; | |
101 | } | |
102 | } | |
103 | ||
104 | for (i = n; i < end; i++) { | |
105 | if (test_bit(i, arena->map)) { | |
106 | start = i + 1; | |
107 | goto again; | |
108 | } | |
109 | } | |
110 | ||
111 | for (i = n; i < end; i++) | |
112 | __set_bit(i, arena->map); | |
113 | ||
114 | arena->hint = end; | |
115 | ||
116 | return n; | |
117 | } | |
118 | ||
119 | static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages) | |
120 | { | |
121 | unsigned long i; | |
122 | ||
123 | for (i = base; i < (base + npages); i++) | |
124 | __clear_bit(i, arena->map); | |
125 | } | |
126 | ||
51e85136 | 127 | void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask) |
1da177e4 | 128 | { |
688cb30b DM |
129 | unsigned long i, tsbbase, order, sz, num_tsb_entries; |
130 | ||
131 | num_tsb_entries = tsbsize / sizeof(iopte_t); | |
51e85136 DM |
132 | |
133 | /* Setup initial software IOMMU state. */ | |
134 | spin_lock_init(&iommu->lock); | |
135 | iommu->ctx_lowest_free = 1; | |
136 | iommu->page_table_map_base = dma_offset; | |
137 | iommu->dma_addr_mask = dma_addr_mask; | |
138 | ||
688cb30b DM |
139 | /* Allocate and initialize the free area map. */ |
140 | sz = num_tsb_entries / 8; | |
141 | sz = (sz + 7UL) & ~7UL; | |
9132983a | 142 | iommu->arena.map = kzalloc(sz, GFP_KERNEL); |
688cb30b DM |
143 | if (!iommu->arena.map) { |
144 | prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n"); | |
51e85136 | 145 | prom_halt(); |
51e85136 | 146 | } |
688cb30b | 147 | iommu->arena.limit = num_tsb_entries; |
1da177e4 | 148 | |
51e85136 DM |
149 | /* Allocate and initialize the dummy page which we |
150 | * set inactive IO PTEs to point to. | |
151 | */ | |
152 | iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); | |
153 | if (!iommu->dummy_page) { | |
154 | prom_printf("PCI_IOMMU: Error, gfp(dummy_page) failed.\n"); | |
155 | prom_halt(); | |
156 | } | |
157 | memset((void *)iommu->dummy_page, 0, PAGE_SIZE); | |
158 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); | |
159 | ||
160 | /* Now allocate and setup the IOMMU page table itself. */ | |
161 | order = get_order(tsbsize); | |
162 | tsbbase = __get_free_pages(GFP_KERNEL, order); | |
163 | if (!tsbbase) { | |
164 | prom_printf("PCI_IOMMU: Error, gfp(tsb) failed.\n"); | |
165 | prom_halt(); | |
166 | } | |
167 | iommu->page_table = (iopte_t *)tsbbase; | |
1da177e4 | 168 | |
688cb30b | 169 | for (i = 0; i < num_tsb_entries; i++) |
1da177e4 LT |
170 | iopte_make_dummy(iommu, &iommu->page_table[i]); |
171 | } | |
172 | ||
688cb30b | 173 | static inline iopte_t *alloc_npages(struct pci_iommu *iommu, unsigned long npages) |
1da177e4 | 174 | { |
688cb30b | 175 | long entry; |
1da177e4 | 176 | |
688cb30b DM |
177 | entry = pci_arena_alloc(iommu, npages); |
178 | if (unlikely(entry < 0)) | |
179 | return NULL; | |
1da177e4 | 180 | |
688cb30b | 181 | return iommu->page_table + entry; |
1da177e4 LT |
182 | } |
183 | ||
688cb30b | 184 | static inline void free_npages(struct pci_iommu *iommu, dma_addr_t base, unsigned long npages) |
1da177e4 | 185 | { |
688cb30b | 186 | pci_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages); |
1da177e4 LT |
187 | } |
188 | ||
7c963ad1 DM |
189 | static int iommu_alloc_ctx(struct pci_iommu *iommu) |
190 | { | |
191 | int lowest = iommu->ctx_lowest_free; | |
192 | int sz = IOMMU_NUM_CTXS - lowest; | |
193 | int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest); | |
194 | ||
195 | if (unlikely(n == sz)) { | |
196 | n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1); | |
197 | if (unlikely(n == lowest)) { | |
198 | printk(KERN_WARNING "IOMMU: Ran out of contexts.\n"); | |
199 | n = 0; | |
200 | } | |
201 | } | |
202 | if (n) | |
203 | __set_bit(n, iommu->ctx_bitmap); | |
204 | ||
205 | return n; | |
206 | } | |
207 | ||
208 | static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx) | |
209 | { | |
210 | if (likely(ctx)) { | |
211 | __clear_bit(ctx, iommu->ctx_bitmap); | |
212 | if (ctx < iommu->ctx_lowest_free) | |
213 | iommu->ctx_lowest_free = ctx; | |
214 | } | |
215 | } | |
216 | ||
1da177e4 LT |
217 | /* Allocate and map kernel buffer of size SIZE using consistent mode |
218 | * DMA for PCI device PDEV. Return non-NULL cpu-side address if | |
219 | * successful and set *DMA_ADDRP to the PCI side dma address. | |
220 | */ | |
42f14237 | 221 | static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp) |
1da177e4 | 222 | { |
1da177e4 LT |
223 | struct pci_iommu *iommu; |
224 | iopte_t *iopte; | |
688cb30b | 225 | unsigned long flags, order, first_page; |
1da177e4 LT |
226 | void *ret; |
227 | int npages; | |
228 | ||
229 | size = IO_PAGE_ALIGN(size); | |
230 | order = get_order(size); | |
231 | if (order >= 10) | |
232 | return NULL; | |
233 | ||
42f14237 | 234 | first_page = __get_free_pages(gfp, order); |
1da177e4 LT |
235 | if (first_page == 0UL) |
236 | return NULL; | |
237 | memset((char *)first_page, 0, PAGE_SIZE << order); | |
238 | ||
a2fb23af | 239 | iommu = pdev->dev.archdata.iommu; |
1da177e4 LT |
240 | |
241 | spin_lock_irqsave(&iommu->lock, flags); | |
688cb30b DM |
242 | iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT); |
243 | spin_unlock_irqrestore(&iommu->lock, flags); | |
244 | ||
245 | if (unlikely(iopte == NULL)) { | |
1da177e4 LT |
246 | free_pages(first_page, order); |
247 | return NULL; | |
248 | } | |
249 | ||
250 | *dma_addrp = (iommu->page_table_map_base + | |
251 | ((iopte - iommu->page_table) << IO_PAGE_SHIFT)); | |
252 | ret = (void *) first_page; | |
253 | npages = size >> IO_PAGE_SHIFT; | |
1da177e4 LT |
254 | first_page = __pa(first_page); |
255 | while (npages--) { | |
688cb30b | 256 | iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) | |
1da177e4 LT |
257 | IOPTE_WRITE | |
258 | (first_page & IOPTE_PAGE)); | |
259 | iopte++; | |
260 | first_page += IO_PAGE_SIZE; | |
261 | } | |
262 | ||
1da177e4 LT |
263 | return ret; |
264 | } | |
265 | ||
266 | /* Free and unmap a consistent DMA translation. */ | |
8f6a93a1 | 267 | static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma) |
1da177e4 | 268 | { |
1da177e4 LT |
269 | struct pci_iommu *iommu; |
270 | iopte_t *iopte; | |
688cb30b | 271 | unsigned long flags, order, npages; |
1da177e4 LT |
272 | |
273 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
a2fb23af | 274 | iommu = pdev->dev.archdata.iommu; |
1da177e4 LT |
275 | iopte = iommu->page_table + |
276 | ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
277 | ||
278 | spin_lock_irqsave(&iommu->lock, flags); | |
279 | ||
012d64ff | 280 | free_npages(iommu, dvma - iommu->page_table_map_base, npages); |
7c963ad1 | 281 | |
1da177e4 LT |
282 | spin_unlock_irqrestore(&iommu->lock, flags); |
283 | ||
284 | order = get_order(size); | |
285 | if (order < 10) | |
286 | free_pages((unsigned long)cpu, order); | |
287 | } | |
288 | ||
289 | /* Map a single buffer at PTR of SZ bytes for PCI DMA | |
290 | * in streaming mode. | |
291 | */ | |
8f6a93a1 | 292 | static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction) |
1da177e4 | 293 | { |
1da177e4 LT |
294 | struct pci_iommu *iommu; |
295 | struct pci_strbuf *strbuf; | |
296 | iopte_t *base; | |
297 | unsigned long flags, npages, oaddr; | |
298 | unsigned long i, base_paddr, ctx; | |
299 | u32 bus_addr, ret; | |
300 | unsigned long iopte_protection; | |
301 | ||
a2fb23af DM |
302 | iommu = pdev->dev.archdata.iommu; |
303 | strbuf = pdev->dev.archdata.stc; | |
1da177e4 | 304 | |
688cb30b DM |
305 | if (unlikely(direction == PCI_DMA_NONE)) |
306 | goto bad_no_ctx; | |
1da177e4 LT |
307 | |
308 | oaddr = (unsigned long)ptr; | |
309 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); | |
310 | npages >>= IO_PAGE_SHIFT; | |
311 | ||
312 | spin_lock_irqsave(&iommu->lock, flags); | |
688cb30b DM |
313 | base = alloc_npages(iommu, npages); |
314 | ctx = 0; | |
315 | if (iommu->iommu_ctxflush) | |
316 | ctx = iommu_alloc_ctx(iommu); | |
317 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 318 | |
688cb30b | 319 | if (unlikely(!base)) |
1da177e4 | 320 | goto bad; |
688cb30b | 321 | |
1da177e4 LT |
322 | bus_addr = (iommu->page_table_map_base + |
323 | ((base - iommu->page_table) << IO_PAGE_SHIFT)); | |
324 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
325 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
1da177e4 LT |
326 | if (strbuf->strbuf_enabled) |
327 | iopte_protection = IOPTE_STREAMING(ctx); | |
328 | else | |
329 | iopte_protection = IOPTE_CONSISTENT(ctx); | |
330 | if (direction != PCI_DMA_TODEVICE) | |
331 | iopte_protection |= IOPTE_WRITE; | |
332 | ||
333 | for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) | |
334 | iopte_val(*base) = iopte_protection | base_paddr; | |
335 | ||
1da177e4 LT |
336 | return ret; |
337 | ||
338 | bad: | |
688cb30b DM |
339 | iommu_free_ctx(iommu, ctx); |
340 | bad_no_ctx: | |
341 | if (printk_ratelimit()) | |
342 | WARN_ON(1); | |
1da177e4 LT |
343 | return PCI_DMA_ERROR_CODE; |
344 | } | |
345 | ||
7c963ad1 | 346 | static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction) |
4dbc30fb DM |
347 | { |
348 | int limit; | |
349 | ||
4dbc30fb DM |
350 | if (strbuf->strbuf_ctxflush && |
351 | iommu->iommu_ctxflush) { | |
352 | unsigned long matchreg, flushreg; | |
7c963ad1 | 353 | u64 val; |
4dbc30fb DM |
354 | |
355 | flushreg = strbuf->strbuf_ctxflush; | |
356 | matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx); | |
357 | ||
a228dfd5 | 358 | pci_iommu_write(flushreg, ctx); |
88314ee7 DM |
359 | val = pci_iommu_read(matchreg); |
360 | val &= 0xffff; | |
361 | if (!val) | |
7c963ad1 DM |
362 | goto do_flush_sync; |
363 | ||
7c963ad1 DM |
364 | while (val) { |
365 | if (val & 0x1) | |
366 | pci_iommu_write(flushreg, ctx); | |
367 | val >>= 1; | |
a228dfd5 | 368 | } |
7c963ad1 DM |
369 | val = pci_iommu_read(matchreg); |
370 | if (unlikely(val)) { | |
4dbc30fb | 371 | printk(KERN_WARNING "pci_strbuf_flush: ctx flush " |
7c963ad1 DM |
372 | "timeout matchreg[%lx] ctx[%lx]\n", |
373 | val, ctx); | |
374 | goto do_page_flush; | |
375 | } | |
4dbc30fb DM |
376 | } else { |
377 | unsigned long i; | |
378 | ||
7c963ad1 | 379 | do_page_flush: |
4dbc30fb DM |
380 | for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE) |
381 | pci_iommu_write(strbuf->strbuf_pflush, vaddr); | |
382 | } | |
383 | ||
7c963ad1 DM |
384 | do_flush_sync: |
385 | /* If the device could not have possibly put dirty data into | |
386 | * the streaming cache, no flush-flag synchronization needs | |
387 | * to be performed. | |
388 | */ | |
389 | if (direction == PCI_DMA_TODEVICE) | |
390 | return; | |
391 | ||
392 | PCI_STC_FLUSHFLAG_INIT(strbuf); | |
4dbc30fb DM |
393 | pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa); |
394 | (void) pci_iommu_read(iommu->write_complete_reg); | |
395 | ||
a228dfd5 | 396 | limit = 100000; |
4dbc30fb DM |
397 | while (!PCI_STC_FLUSHFLAG_SET(strbuf)) { |
398 | limit--; | |
399 | if (!limit) | |
400 | break; | |
a228dfd5 | 401 | udelay(1); |
4f07118f | 402 | rmb(); |
4dbc30fb DM |
403 | } |
404 | if (!limit) | |
405 | printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout " | |
406 | "vaddr[%08x] ctx[%lx] npages[%ld]\n", | |
407 | vaddr, ctx, npages); | |
408 | } | |
409 | ||
1da177e4 | 410 | /* Unmap a single streaming mode DMA translation. */ |
8f6a93a1 | 411 | static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction) |
1da177e4 | 412 | { |
1da177e4 LT |
413 | struct pci_iommu *iommu; |
414 | struct pci_strbuf *strbuf; | |
415 | iopte_t *base; | |
688cb30b | 416 | unsigned long flags, npages, ctx, i; |
1da177e4 | 417 | |
688cb30b DM |
418 | if (unlikely(direction == PCI_DMA_NONE)) { |
419 | if (printk_ratelimit()) | |
420 | WARN_ON(1); | |
421 | return; | |
422 | } | |
1da177e4 | 423 | |
a2fb23af DM |
424 | iommu = pdev->dev.archdata.iommu; |
425 | strbuf = pdev->dev.archdata.stc; | |
1da177e4 LT |
426 | |
427 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
428 | npages >>= IO_PAGE_SHIFT; | |
429 | base = iommu->page_table + | |
430 | ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
431 | #ifdef DEBUG_PCI_IOMMU | |
432 | if (IOPTE_IS_DUMMY(iommu, base)) | |
433 | printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n", | |
434 | bus_addr, sz, __builtin_return_address(0)); | |
435 | #endif | |
436 | bus_addr &= IO_PAGE_MASK; | |
437 | ||
438 | spin_lock_irqsave(&iommu->lock, flags); | |
439 | ||
440 | /* Record the context, if any. */ | |
441 | ctx = 0; | |
442 | if (iommu->iommu_ctxflush) | |
443 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
444 | ||
445 | /* Step 1: Kick data out of streaming buffers if necessary. */ | |
4dbc30fb | 446 | if (strbuf->strbuf_enabled) |
688cb30b DM |
447 | pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, |
448 | npages, direction); | |
1da177e4 | 449 | |
688cb30b DM |
450 | /* Step 2: Clear out TSB entries. */ |
451 | for (i = 0; i < npages; i++) | |
452 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 453 | |
688cb30b | 454 | free_npages(iommu, bus_addr - iommu->page_table_map_base, npages); |
1da177e4 | 455 | |
7c963ad1 DM |
456 | iommu_free_ctx(iommu, ctx); |
457 | ||
1da177e4 LT |
458 | spin_unlock_irqrestore(&iommu->lock, flags); |
459 | } | |
460 | ||
461 | #define SG_ENT_PHYS_ADDRESS(SG) \ | |
462 | (__pa(page_address((SG)->page)) + (SG)->offset) | |
463 | ||
464 | static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, | |
465 | int nused, int nelems, unsigned long iopte_protection) | |
466 | { | |
467 | struct scatterlist *dma_sg = sg; | |
468 | struct scatterlist *sg_end = sg + nelems; | |
469 | int i; | |
470 | ||
471 | for (i = 0; i < nused; i++) { | |
472 | unsigned long pteval = ~0UL; | |
473 | u32 dma_npages; | |
474 | ||
475 | dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) + | |
476 | dma_sg->dma_length + | |
477 | ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT; | |
478 | do { | |
479 | unsigned long offset; | |
480 | signed int len; | |
481 | ||
482 | /* If we are here, we know we have at least one | |
483 | * more page to map. So walk forward until we | |
484 | * hit a page crossing, and begin creating new | |
485 | * mappings from that spot. | |
486 | */ | |
487 | for (;;) { | |
488 | unsigned long tmp; | |
489 | ||
490 | tmp = SG_ENT_PHYS_ADDRESS(sg); | |
491 | len = sg->length; | |
492 | if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) { | |
493 | pteval = tmp & IO_PAGE_MASK; | |
494 | offset = tmp & (IO_PAGE_SIZE - 1UL); | |
495 | break; | |
496 | } | |
497 | if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) { | |
498 | pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK; | |
499 | offset = 0UL; | |
500 | len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL))); | |
501 | break; | |
502 | } | |
503 | sg++; | |
504 | } | |
505 | ||
506 | pteval = iopte_protection | (pteval & IOPTE_PAGE); | |
507 | while (len > 0) { | |
508 | *iopte++ = __iopte(pteval); | |
509 | pteval += IO_PAGE_SIZE; | |
510 | len -= (IO_PAGE_SIZE - offset); | |
511 | offset = 0; | |
512 | dma_npages--; | |
513 | } | |
514 | ||
515 | pteval = (pteval & IOPTE_PAGE) + len; | |
516 | sg++; | |
517 | ||
518 | /* Skip over any tail mappings we've fully mapped, | |
519 | * adjusting pteval along the way. Stop when we | |
520 | * detect a page crossing event. | |
521 | */ | |
522 | while (sg < sg_end && | |
523 | (pteval << (64 - IO_PAGE_SHIFT)) != 0UL && | |
524 | (pteval == SG_ENT_PHYS_ADDRESS(sg)) && | |
525 | ((pteval ^ | |
526 | (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) { | |
527 | pteval += sg->length; | |
528 | sg++; | |
529 | } | |
530 | if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL) | |
531 | pteval = ~0UL; | |
532 | } while (dma_npages != 0); | |
533 | dma_sg++; | |
534 | } | |
535 | } | |
536 | ||
537 | /* Map a set of buffers described by SGLIST with NELEMS array | |
538 | * elements in streaming mode for PCI DMA. | |
539 | * When making changes here, inspect the assembly output. I was having | |
540 | * hard time to kepp this routine out of using stack slots for holding variables. | |
541 | */ | |
8f6a93a1 | 542 | static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) |
1da177e4 | 543 | { |
1da177e4 LT |
544 | struct pci_iommu *iommu; |
545 | struct pci_strbuf *strbuf; | |
546 | unsigned long flags, ctx, npages, iopte_protection; | |
547 | iopte_t *base; | |
548 | u32 dma_base; | |
549 | struct scatterlist *sgtmp; | |
550 | int used; | |
551 | ||
552 | /* Fast path single entry scatterlists. */ | |
553 | if (nelems == 1) { | |
554 | sglist->dma_address = | |
18397944 DM |
555 | pci_4u_map_single(pdev, |
556 | (page_address(sglist->page) + sglist->offset), | |
557 | sglist->length, direction); | |
688cb30b DM |
558 | if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE)) |
559 | return 0; | |
1da177e4 LT |
560 | sglist->dma_length = sglist->length; |
561 | return 1; | |
562 | } | |
563 | ||
a2fb23af DM |
564 | iommu = pdev->dev.archdata.iommu; |
565 | strbuf = pdev->dev.archdata.stc; | |
1da177e4 | 566 | |
688cb30b DM |
567 | if (unlikely(direction == PCI_DMA_NONE)) |
568 | goto bad_no_ctx; | |
1da177e4 LT |
569 | |
570 | /* Step 1: Prepare scatter list. */ | |
571 | ||
572 | npages = prepare_sg(sglist, nelems); | |
573 | ||
688cb30b | 574 | /* Step 2: Allocate a cluster and context, if necessary. */ |
1da177e4 LT |
575 | |
576 | spin_lock_irqsave(&iommu->lock, flags); | |
577 | ||
688cb30b DM |
578 | base = alloc_npages(iommu, npages); |
579 | ctx = 0; | |
580 | if (iommu->iommu_ctxflush) | |
581 | ctx = iommu_alloc_ctx(iommu); | |
582 | ||
583 | spin_unlock_irqrestore(&iommu->lock, flags); | |
584 | ||
1da177e4 LT |
585 | if (base == NULL) |
586 | goto bad; | |
688cb30b DM |
587 | |
588 | dma_base = iommu->page_table_map_base + | |
589 | ((base - iommu->page_table) << IO_PAGE_SHIFT); | |
1da177e4 LT |
590 | |
591 | /* Step 3: Normalize DMA addresses. */ | |
592 | used = nelems; | |
593 | ||
594 | sgtmp = sglist; | |
595 | while (used && sgtmp->dma_length) { | |
596 | sgtmp->dma_address += dma_base; | |
597 | sgtmp++; | |
598 | used--; | |
599 | } | |
600 | used = nelems - used; | |
601 | ||
688cb30b | 602 | /* Step 4: Create the mappings. */ |
1da177e4 LT |
603 | if (strbuf->strbuf_enabled) |
604 | iopte_protection = IOPTE_STREAMING(ctx); | |
605 | else | |
606 | iopte_protection = IOPTE_CONSISTENT(ctx); | |
607 | if (direction != PCI_DMA_TODEVICE) | |
608 | iopte_protection |= IOPTE_WRITE; | |
688cb30b DM |
609 | |
610 | fill_sg(base, sglist, used, nelems, iopte_protection); | |
611 | ||
1da177e4 LT |
612 | #ifdef VERIFY_SG |
613 | verify_sglist(sglist, nelems, base, npages); | |
614 | #endif | |
615 | ||
1da177e4 LT |
616 | return used; |
617 | ||
618 | bad: | |
688cb30b DM |
619 | iommu_free_ctx(iommu, ctx); |
620 | bad_no_ctx: | |
621 | if (printk_ratelimit()) | |
622 | WARN_ON(1); | |
623 | return 0; | |
1da177e4 LT |
624 | } |
625 | ||
626 | /* Unmap a set of streaming mode DMA translations. */ | |
8f6a93a1 | 627 | static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) |
1da177e4 | 628 | { |
1da177e4 LT |
629 | struct pci_iommu *iommu; |
630 | struct pci_strbuf *strbuf; | |
631 | iopte_t *base; | |
632 | unsigned long flags, ctx, i, npages; | |
633 | u32 bus_addr; | |
634 | ||
688cb30b DM |
635 | if (unlikely(direction == PCI_DMA_NONE)) { |
636 | if (printk_ratelimit()) | |
637 | WARN_ON(1); | |
638 | } | |
1da177e4 | 639 | |
a2fb23af DM |
640 | iommu = pdev->dev.archdata.iommu; |
641 | strbuf = pdev->dev.archdata.stc; | |
1da177e4 LT |
642 | |
643 | bus_addr = sglist->dma_address & IO_PAGE_MASK; | |
644 | ||
645 | for (i = 1; i < nelems; i++) | |
646 | if (sglist[i].dma_length == 0) | |
647 | break; | |
648 | i--; | |
688cb30b DM |
649 | npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - |
650 | bus_addr) >> IO_PAGE_SHIFT; | |
1da177e4 LT |
651 | |
652 | base = iommu->page_table + | |
653 | ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
654 | ||
655 | #ifdef DEBUG_PCI_IOMMU | |
656 | if (IOPTE_IS_DUMMY(iommu, base)) | |
657 | printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0)); | |
658 | #endif | |
659 | ||
660 | spin_lock_irqsave(&iommu->lock, flags); | |
661 | ||
662 | /* Record the context, if any. */ | |
663 | ctx = 0; | |
664 | if (iommu->iommu_ctxflush) | |
665 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
666 | ||
667 | /* Step 1: Kick data out of streaming buffers if necessary. */ | |
4dbc30fb | 668 | if (strbuf->strbuf_enabled) |
7c963ad1 | 669 | pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 | 670 | |
688cb30b DM |
671 | /* Step 2: Clear out the TSB entries. */ |
672 | for (i = 0; i < npages; i++) | |
673 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 674 | |
688cb30b | 675 | free_npages(iommu, bus_addr - iommu->page_table_map_base, npages); |
1da177e4 | 676 | |
7c963ad1 DM |
677 | iommu_free_ctx(iommu, ctx); |
678 | ||
1da177e4 LT |
679 | spin_unlock_irqrestore(&iommu->lock, flags); |
680 | } | |
681 | ||
682 | /* Make physical memory consistent for a single | |
683 | * streaming mode DMA translation after a transfer. | |
684 | */ | |
8f6a93a1 | 685 | static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction) |
1da177e4 | 686 | { |
1da177e4 LT |
687 | struct pci_iommu *iommu; |
688 | struct pci_strbuf *strbuf; | |
689 | unsigned long flags, ctx, npages; | |
690 | ||
a2fb23af DM |
691 | iommu = pdev->dev.archdata.iommu; |
692 | strbuf = pdev->dev.archdata.stc; | |
1da177e4 LT |
693 | |
694 | if (!strbuf->strbuf_enabled) | |
695 | return; | |
696 | ||
697 | spin_lock_irqsave(&iommu->lock, flags); | |
698 | ||
699 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
700 | npages >>= IO_PAGE_SHIFT; | |
701 | bus_addr &= IO_PAGE_MASK; | |
702 | ||
703 | /* Step 1: Record the context, if any. */ | |
704 | ctx = 0; | |
705 | if (iommu->iommu_ctxflush && | |
706 | strbuf->strbuf_ctxflush) { | |
707 | iopte_t *iopte; | |
708 | ||
709 | iopte = iommu->page_table + | |
710 | ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT); | |
711 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; | |
712 | } | |
713 | ||
714 | /* Step 2: Kick data out of streaming buffers. */ | |
7c963ad1 | 715 | pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
716 | |
717 | spin_unlock_irqrestore(&iommu->lock, flags); | |
718 | } | |
719 | ||
720 | /* Make physical memory consistent for a set of streaming | |
721 | * mode DMA translations after a transfer. | |
722 | */ | |
8f6a93a1 | 723 | static void pci_4u_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction) |
1da177e4 | 724 | { |
1da177e4 LT |
725 | struct pci_iommu *iommu; |
726 | struct pci_strbuf *strbuf; | |
4dbc30fb DM |
727 | unsigned long flags, ctx, npages, i; |
728 | u32 bus_addr; | |
1da177e4 | 729 | |
a2fb23af DM |
730 | iommu = pdev->dev.archdata.iommu; |
731 | strbuf = pdev->dev.archdata.stc; | |
1da177e4 LT |
732 | |
733 | if (!strbuf->strbuf_enabled) | |
734 | return; | |
735 | ||
736 | spin_lock_irqsave(&iommu->lock, flags); | |
737 | ||
738 | /* Step 1: Record the context, if any. */ | |
739 | ctx = 0; | |
740 | if (iommu->iommu_ctxflush && | |
741 | strbuf->strbuf_ctxflush) { | |
742 | iopte_t *iopte; | |
743 | ||
744 | iopte = iommu->page_table + | |
745 | ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
746 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; | |
747 | } | |
748 | ||
749 | /* Step 2: Kick data out of streaming buffers. */ | |
4dbc30fb DM |
750 | bus_addr = sglist[0].dma_address & IO_PAGE_MASK; |
751 | for(i = 1; i < nelems; i++) | |
752 | if (!sglist[i].dma_length) | |
753 | break; | |
754 | i--; | |
755 | npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) | |
756 | - bus_addr) >> IO_PAGE_SHIFT; | |
7c963ad1 | 757 | pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
758 | |
759 | spin_unlock_irqrestore(&iommu->lock, flags); | |
760 | } | |
761 | ||
c6e87566 | 762 | const struct pci_iommu_ops pci_sun4u_iommu_ops = { |
8f6a93a1 DM |
763 | .alloc_consistent = pci_4u_alloc_consistent, |
764 | .free_consistent = pci_4u_free_consistent, | |
765 | .map_single = pci_4u_map_single, | |
766 | .unmap_single = pci_4u_unmap_single, | |
767 | .map_sg = pci_4u_map_sg, | |
768 | .unmap_sg = pci_4u_unmap_sg, | |
769 | .dma_sync_single_for_cpu = pci_4u_dma_sync_single_for_cpu, | |
770 | .dma_sync_sg_for_cpu = pci_4u_dma_sync_sg_for_cpu, | |
771 | }; | |
772 | ||
1da177e4 LT |
773 | static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) |
774 | { | |
775 | struct pci_dev *ali_isa_bridge; | |
776 | u8 val; | |
777 | ||
778 | /* ALI sound chips generate 31-bits of DMA, a special register | |
779 | * determines what bit 31 is emitted as. | |
780 | */ | |
781 | ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, | |
782 | PCI_DEVICE_ID_AL_M1533, | |
783 | NULL); | |
784 | ||
785 | pci_read_config_byte(ali_isa_bridge, 0x7e, &val); | |
786 | if (set_bit) | |
787 | val |= 0x01; | |
788 | else | |
789 | val &= ~0x01; | |
790 | pci_write_config_byte(ali_isa_bridge, 0x7e, val); | |
791 | pci_dev_put(ali_isa_bridge); | |
792 | } | |
793 | ||
794 | int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) | |
795 | { | |
1da177e4 LT |
796 | u64 dma_addr_mask; |
797 | ||
798 | if (pdev == NULL) { | |
799 | dma_addr_mask = 0xffffffff; | |
800 | } else { | |
a2fb23af | 801 | struct pci_iommu *iommu = pdev->dev.archdata.iommu; |
1da177e4 LT |
802 | |
803 | dma_addr_mask = iommu->dma_addr_mask; | |
804 | ||
805 | if (pdev->vendor == PCI_VENDOR_ID_AL && | |
806 | pdev->device == PCI_DEVICE_ID_AL_M5451 && | |
807 | device_mask == 0x7fffffff) { | |
808 | ali_sound_dma_hack(pdev, | |
809 | (dma_addr_mask & 0x80000000) != 0); | |
810 | return 1; | |
811 | } | |
812 | } | |
813 | ||
814 | if (device_mask >= (1UL << 32UL)) | |
815 | return 0; | |
816 | ||
817 | return (device_mask & dma_addr_mask) == dma_addr_mask; | |
818 | } |