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[SPARC64]: Kill ino_bucket->pil
[deliverable/linux.git] / arch / sparc64 / kernel / pci_psycho.c
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1da177e4
LT		 1/* $Id: pci_psycho.c,v 1.33 2002/02/01 00:58:33 davem Exp $
2 * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
7 */
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/init.h>
13#include <linux/slab.h>
14#include <linux/interrupt.h>
15
16#include <asm/pbm.h>
17#include <asm/iommu.h>
18#include <asm/irq.h>
19#include <asm/starfire.h>
20
21#include "pci_impl.h"
22#include "iommu_common.h"
23
24/* All PSYCHO registers are 64-bits. The following accessor
25 * routines are how they are accessed. The REG parameter
26 * is a physical address.
27 */
28#define psycho_read(__reg) \
29({ u64 __ret; \
30 __asm__ __volatile__("ldxa [%1] %2, %0" \
31 : "=r" (__ret) \
32 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
33 : "memory"); \
34 __ret; \
35})
36#define psycho_write(__reg, __val) \
37 __asm__ __volatile__("stxa %0, [%1] %2" \
38 : /* no outputs */ \
39 : "r" (__val), "r" (__reg), \
40 "i" (ASI_PHYS_BYPASS_EC_E) \
41 : "memory")
42
43/* Misc. PSYCHO PCI controller register offsets and definitions. */
44#define PSYCHO_CONTROL 0x0010UL
45#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
46#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
47#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
48#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
49#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
50#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
51#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
52#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
53#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
54#define PSYCHO_PCIA_CTRL 0x2000UL
55#define PSYCHO_PCIB_CTRL 0x4000UL
56#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
57#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
58#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
59#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
60#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
61#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
62#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
63#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
64#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
65#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
66#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
67#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
68
69/* U2P Programmer's Manual, page 13-55, configuration space
70 * address format:
71 *
72 * 32 24 23 16 15 11 10 8 7 2 1 0
73 * ---------------------------------------------------------
74 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
75 * ---------------------------------------------------------
76 */
77#define PSYCHO_CONFIG_BASE(PBM) \
78 ((PBM)->config_space | (1UL << 24))
79#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
80 (((unsigned long)(BUS) << 16) | \
81 ((unsigned long)(DEVFN) << 8) | \
82 ((unsigned long)(REG)))
83
84static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
85 unsigned char bus,
86 unsigned int devfn,
87 int where)
88{
89 if (!pbm)
90 return NULL;
91 return (void *)
92 (PSYCHO_CONFIG_BASE(pbm) |
93 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
94}
95
96static int psycho_out_of_range(struct pci_pbm_info *pbm,
97 unsigned char bus,
98 unsigned char devfn)
99{
100 return ((pbm->parent == 0) ||
101 ((pbm == &pbm->parent->pbm_B) &&
102 (bus == pbm->pci_first_busno) &&
103 PCI_SLOT(devfn) > 8) ||
104 ((pbm == &pbm->parent->pbm_A) &&
105 (bus == pbm->pci_first_busno) &&
106 PCI_SLOT(devfn) > 8));
107}
108
109/* PSYCHO PCI configuration space accessors. */
110
111static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
112 int where, int size, u32 *value)
113{
114 struct pci_pbm_info *pbm = bus_dev->sysdata;
115 unsigned char bus = bus_dev->number;
116 u32 *addr;
117 u16 tmp16;
118 u8 tmp8;
119
120 switch (size) {
121 case 1:
122 *value = 0xff;
123 break;
124 case 2:
125 *value = 0xffff;
126 break;
127 case 4:
128 *value = 0xffffffff;
129 break;
130 }
131
132 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
133 if (!addr)
134 return PCIBIOS_SUCCESSFUL;
135
136 if (psycho_out_of_range(pbm, bus, devfn))
137 return PCIBIOS_SUCCESSFUL;
138 switch (size) {
139 case 1:
140 pci_config_read8((u8 *)addr, &tmp8);
141 *value = (u32) tmp8;
142 break;
143
144 case 2:
145 if (where & 0x01) {
146 printk("pci_read_config_word: misaligned reg [%x]\n",
147 where);
148 return PCIBIOS_SUCCESSFUL;
149 }
150 pci_config_read16((u16 *)addr, &tmp16);
151 *value = (u32) tmp16;
152 break;
153
154 case 4:
155 if (where & 0x03) {
156 printk("pci_read_config_dword: misaligned reg [%x]\n",
157 where);
158 return PCIBIOS_SUCCESSFUL;
159 }
160 pci_config_read32(addr, value);
161 break;
162 }
163 return PCIBIOS_SUCCESSFUL;
164}
165
166static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
167 int where, int size, u32 value)
168{
169 struct pci_pbm_info *pbm = bus_dev->sysdata;
170 unsigned char bus = bus_dev->number;
171 u32 *addr;
172
173 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
174 if (!addr)
175 return PCIBIOS_SUCCESSFUL;
176
177 if (psycho_out_of_range(pbm, bus, devfn))
178 return PCIBIOS_SUCCESSFUL;
179
180 switch (size) {
181 case 1:
182 pci_config_write8((u8 *)addr, value);
183 break;
184
185 case 2:
186 if (where & 0x01) {
187 printk("pci_write_config_word: misaligned reg [%x]\n",
188 where);
189 return PCIBIOS_SUCCESSFUL;
190 }
191 pci_config_write16((u16 *)addr, value);
192 break;
193
194 case 4:
195 if (where & 0x03) {
196 printk("pci_write_config_dword: misaligned reg [%x]\n",
197 where);
198 return PCIBIOS_SUCCESSFUL;
199 }
200 pci_config_write32(addr, value);
201 }
202 return PCIBIOS_SUCCESSFUL;
203}
204
205static struct pci_ops psycho_ops = {
206 .read = psycho_read_pci_cfg,
207 .write = psycho_write_pci_cfg,
208};
209
210/* PSYCHO interrupt mapping support. */
211#define PSYCHO_IMAP_A_SLOT0 0x0c00UL
212#define PSYCHO_IMAP_B_SLOT0 0x0c20UL
213static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
214{
215 unsigned int bus = (ino & 0x10) >> 4;
216 unsigned int slot = (ino & 0x0c) >> 2;
217
218 if (bus == 0)
219 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
220 else
221 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
222}
223
224#define PSYCHO_IMAP_SCSI 0x1000UL
225#define PSYCHO_IMAP_ETH 0x1008UL
226#define PSYCHO_IMAP_BPP 0x1010UL
227#define PSYCHO_IMAP_AU_REC 0x1018UL
228#define PSYCHO_IMAP_AU_PLAY 0x1020UL
229#define PSYCHO_IMAP_PFAIL 0x1028UL
230#define PSYCHO_IMAP_KMS 0x1030UL
231#define PSYCHO_IMAP_FLPY 0x1038UL
232#define PSYCHO_IMAP_SHW 0x1040UL
233#define PSYCHO_IMAP_KBD 0x1048UL
234#define PSYCHO_IMAP_MS 0x1050UL
235#define PSYCHO_IMAP_SER 0x1058UL
236#define PSYCHO_IMAP_TIM0 0x1060UL
237#define PSYCHO_IMAP_TIM1 0x1068UL
238#define PSYCHO_IMAP_UE 0x1070UL
239#define PSYCHO_IMAP_CE 0x1078UL
240#define PSYCHO_IMAP_A_ERR 0x1080UL
241#define PSYCHO_IMAP_B_ERR 0x1088UL
242#define PSYCHO_IMAP_PMGMT 0x1090UL
243#define PSYCHO_IMAP_GFX 0x1098UL
244#define PSYCHO_IMAP_EUPA 0x10a0UL
245
246static unsigned long __onboard_imap_off[] = {
247/*0x20*/ PSYCHO_IMAP_SCSI,
248/*0x21*/ PSYCHO_IMAP_ETH,
249/*0x22*/ PSYCHO_IMAP_BPP,
250/*0x23*/ PSYCHO_IMAP_AU_REC,
251/*0x24*/ PSYCHO_IMAP_AU_PLAY,
252/*0x25*/ PSYCHO_IMAP_PFAIL,
253/*0x26*/ PSYCHO_IMAP_KMS,
254/*0x27*/ PSYCHO_IMAP_FLPY,
255/*0x28*/ PSYCHO_IMAP_SHW,
256/*0x29*/ PSYCHO_IMAP_KBD,
257/*0x2a*/ PSYCHO_IMAP_MS,
258/*0x2b*/ PSYCHO_IMAP_SER,
259/*0x2c*/ PSYCHO_IMAP_TIM0,
260/*0x2d*/ PSYCHO_IMAP_TIM1,
261/*0x2e*/ PSYCHO_IMAP_UE,
262/*0x2f*/ PSYCHO_IMAP_CE,
263/*0x30*/ PSYCHO_IMAP_A_ERR,
264/*0x31*/ PSYCHO_IMAP_B_ERR,
265/*0x32*/ PSYCHO_IMAP_PMGMT
266};
267#define PSYCHO_ONBOARD_IRQ_BASE 0x20
268#define PSYCHO_ONBOARD_IRQ_LAST 0x32
269#define psycho_onboard_imap_offset(__ino) \
270 __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
271
272#define PSYCHO_ICLR_A_SLOT0 0x1400UL
273#define PSYCHO_ICLR_SCSI 0x1800UL
274
275#define psycho_iclr_offset(ino) \
276 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
277 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
278
085ae41f
DM		 279static unsigned int psycho_irq_build(struct pci_pbm_info *pbm,
280 struct pci_dev *pdev,
281 unsigned int ino)
1da177e4
LT		 282{
283 struct ino_bucket *bucket;
284 unsigned long imap, iclr;
285 unsigned long imap_off, iclr_off;
37cdcd9e 286 int inofixup = 0;
1da177e4
LT		 287
288 ino &= PCI_IRQ_INO;
289 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
290 /* PCI slot */
291 imap_off = psycho_pcislot_imap_offset(ino);
292 } else {
293 /* Onboard device */
294 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
295 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
296 prom_halt();
297 }
298 imap_off = psycho_onboard_imap_offset(ino);
299 }
300
301 /* Now build the IRQ bucket. */
1da177e4
LT		 302 imap = pbm->controller_regs + imap_off;
303 imap += 4;
304
305 iclr_off = psycho_iclr_offset(ino);
306 iclr = pbm->controller_regs + iclr_off;
307 iclr += 4;
308
309 if ((ino & 0x20) == 0)
310 inofixup = ino & 0x03;
311
37cdcd9e 312 bucket = __bucket(build_irq(inofixup, iclr, imap));
1da177e4
LT		 313 bucket->flags |= IBF_PCI;
314
315 return __irq(bucket);
316}
317
318/* PSYCHO error handling support. */
319enum psycho_error_type {
320 UE_ERR, CE_ERR, PCI_ERR
321};
322
323/* Helper function of IOMMU error checking, which checks out
324 * the state of the streaming buffers. The IOMMU lock is
325 * held when this is called.
326 *
327 * For the PCI error case we know which PBM (and thus which
328 * streaming buffer) caused the error, but for the uncorrectable
329 * error case we do not. So we always check both streaming caches.
330 */
331#define PSYCHO_STRBUF_CONTROL_A 0x2800UL
332#define PSYCHO_STRBUF_CONTROL_B 0x4800UL
333#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
334#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
335#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
336#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
337#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
338#define PSYCHO_STRBUF_FLUSH_A 0x2808UL
339#define PSYCHO_STRBUF_FLUSH_B 0x4808UL
340#define PSYCHO_STRBUF_FSYNC_A 0x2810UL
341#define PSYCHO_STRBUF_FSYNC_B 0x4810UL
342#define PSYCHO_STC_DATA_A 0xb000UL
343#define PSYCHO_STC_DATA_B 0xc000UL
344#define PSYCHO_STC_ERR_A 0xb400UL
345#define PSYCHO_STC_ERR_B 0xc400UL
346#define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
347#define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
348#define PSYCHO_STC_TAG_A 0xb800UL
349#define PSYCHO_STC_TAG_B 0xc800UL
350#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
351#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
352#define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
353#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
354#define PSYCHO_STC_LINE_A 0xb900UL
355#define PSYCHO_STC_LINE_B 0xc900UL
356#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
357#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
358#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
359#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
360#define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
361#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
362
363static DEFINE_SPINLOCK(stc_buf_lock);
364static unsigned long stc_error_buf[128];
365static unsigned long stc_tag_buf[16];
366static unsigned long stc_line_buf[16];
367
368static void __psycho_check_one_stc(struct pci_controller_info *p,
369 struct pci_pbm_info *pbm,
370 int is_pbm_a)
371{
372 struct pci_strbuf *strbuf = &pbm->stc;
373 unsigned long regbase = p->pbm_A.controller_regs;
374 unsigned long err_base, tag_base, line_base;
375 u64 control;
376 int i;
377
378 if (is_pbm_a) {
379 err_base = regbase + PSYCHO_STC_ERR_A;
380 tag_base = regbase + PSYCHO_STC_TAG_A;
381 line_base = regbase + PSYCHO_STC_LINE_A;
382 } else {
383 err_base = regbase + PSYCHO_STC_ERR_B;
384 tag_base = regbase + PSYCHO_STC_TAG_B;
385 line_base = regbase + PSYCHO_STC_LINE_B;
386 }
387
388 spin_lock(&stc_buf_lock);
389
390 /* This is __REALLY__ dangerous. When we put the
391 * streaming buffer into diagnostic mode to probe
392 * it's tags and error status, we _must_ clear all
393 * of the line tag valid bits before re-enabling
394 * the streaming buffer. If any dirty data lives
395 * in the STC when we do this, we will end up
396 * invalidating it before it has a chance to reach
397 * main memory.
398 */
399 control = psycho_read(strbuf->strbuf_control);
400 psycho_write(strbuf->strbuf_control,
401 (control | PSYCHO_STRBUF_CTRL_DENAB));
402 for (i = 0; i < 128; i++) {
403 unsigned long val;
404
405 val = psycho_read(err_base + (i * 8UL));
406 psycho_write(err_base + (i * 8UL), 0UL);
407 stc_error_buf[i] = val;
408 }
409 for (i = 0; i < 16; i++) {
410 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
411 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
412 psycho_write(tag_base + (i * 8UL), 0UL);
413 psycho_write(line_base + (i * 8UL), 0UL);
414 }
415
416 /* OK, state is logged, exit diagnostic mode. */
417 psycho_write(strbuf->strbuf_control, control);
418
419 for (i = 0; i < 16; i++) {
420 int j, saw_error, first, last;
421
422 saw_error = 0;
423 first = i * 8;
424 last = first + 8;
425 for (j = first; j < last; j++) {
426 unsigned long errval = stc_error_buf[j];
427 if (errval != 0) {
428 saw_error++;
429 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
430 p->index,
431 (is_pbm_a ? 'A' : 'B'),
432 j,
433 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
434 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
435 }
436 }
437 if (saw_error != 0) {
438 unsigned long tagval = stc_tag_buf[i];
439 unsigned long lineval = stc_line_buf[i];
440 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
441 p->index,
442 (is_pbm_a ? 'A' : 'B'),
443 i,
444 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
445 (tagval & PSYCHO_STCTAG_VPN),
446 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
447 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
448 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
449 "V(%d)FOFN(%d)]\n",
450 p->index,
451 (is_pbm_a ? 'A' : 'B'),
452 i,
453 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
454 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
455 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
456 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
457 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
458 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
459 }
460 }
461
462 spin_unlock(&stc_buf_lock);
463}
464
465static void __psycho_check_stc_error(struct pci_controller_info *p,
466 unsigned long afsr,
467 unsigned long afar,
468 enum psycho_error_type type)
469{
470 struct pci_pbm_info *pbm;
471
472 pbm = &p->pbm_A;
473 if (pbm->stc.strbuf_enabled)
474 __psycho_check_one_stc(p, pbm, 1);
475
476 pbm = &p->pbm_B;
477 if (pbm->stc.strbuf_enabled)
478 __psycho_check_one_stc(p, pbm, 0);
479}
480
481/* When an Uncorrectable Error or a PCI Error happens, we
482 * interrogate the IOMMU state to see if it is the cause.
483 */
484#define PSYCHO_IOMMU_CONTROL 0x0200UL
485#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
486#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
487#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
488#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
489#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
490#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
491#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
492#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
493#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
494#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
495#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
496#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
497#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
498#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
499#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
500#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
501#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
502#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
503#define PSYCHO_IOMMU_TSBBASE 0x0208UL
504#define PSYCHO_IOMMU_FLUSH 0x0210UL
505#define PSYCHO_IOMMU_TAG 0xa580UL
506#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
507#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
508#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
509#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
510#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
511#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
512#define PSYCHO_IOMMU_DATA 0xa600UL
513#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
514#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
515#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
516static void psycho_check_iommu_error(struct pci_controller_info *p,
517 unsigned long afsr,
518 unsigned long afar,
519 enum psycho_error_type type)
520{
521 struct pci_iommu *iommu = p->pbm_A.iommu;
522 unsigned long iommu_tag[16];
523 unsigned long iommu_data[16];
524 unsigned long flags;
525 u64 control;
526 int i;
527
528 spin_lock_irqsave(&iommu->lock, flags);
529 control = psycho_read(iommu->iommu_control);
530 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
531 char *type_string;
532
533 /* Clear the error encountered bit. */
534 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
535 psycho_write(iommu->iommu_control, control);
536
537 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
538 case 0:
539 type_string = "Protection Error";
540 break;
541 case 1:
542 type_string = "Invalid Error";
543 break;
544 case 2:
545 type_string = "TimeOut Error";
546 break;
547 case 3:
548 default:
549 type_string = "ECC Error";
550 break;
551 };
552 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
553 p->index, type_string);
554
555 /* Put the IOMMU into diagnostic mode and probe
556 * it's TLB for entries with error status.
557 *
558 * It is very possible for another DVMA to occur
559 * while we do this probe, and corrupt the system
560 * further. But we are so screwed at this point
561 * that we are likely to crash hard anyways, so
562 * get as much diagnostic information to the
563 * console as we can.
564 */
565 psycho_write(iommu->iommu_control,
566 control | PSYCHO_IOMMU_CTRL_DENAB);
567 for (i = 0; i < 16; i++) {
568 unsigned long base = p->pbm_A.controller_regs;
569
570 iommu_tag[i] =
571 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
572 iommu_data[i] =
573 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
574
575 /* Now clear out the entry. */
576 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
577 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
578 }
579
580 /* Leave diagnostic mode. */
581 psycho_write(iommu->iommu_control, control);
582
583 for (i = 0; i < 16; i++) {
584 unsigned long tag, data;
585
586 tag = iommu_tag[i];
587 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
588 continue;
589
590 data = iommu_data[i];
591 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
592 case 0:
593 type_string = "Protection Error";
594 break;
595 case 1:
596 type_string = "Invalid Error";
597 break;
598 case 2:
599 type_string = "TimeOut Error";
600 break;
601 case 3:
602 default:
603 type_string = "ECC Error";
604 break;
605 };
606 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
607 p->index, i, type_string,
608 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
609 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
610 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
611 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
612 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
613 p->index, i,
614 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
615 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
616 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
617 }
618 }
619 __psycho_check_stc_error(p, afsr, afar, type);
620 spin_unlock_irqrestore(&iommu->lock, flags);
621}
622
623/* Uncorrectable Errors. Cause of the error and the address are
624 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
625 * relating to UPA interface transactions.
626 */
627#define PSYCHO_UE_AFSR 0x0030UL
628#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
629#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
630#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
631#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
632#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
633#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
634#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
635#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
636#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
637#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
638#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
639#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
640#define PSYCHO_UE_AFAR 0x0038UL
641
642static irqreturn_t psycho_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
643{
644 struct pci_controller_info *p = dev_id;
645 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR;
646 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR;
647 unsigned long afsr, afar, error_bits;
648 int reported;
649
650 /* Latch uncorrectable error status. */
651 afar = psycho_read(afar_reg);
652 afsr = psycho_read(afsr_reg);
653
654 /* Clear the primary/secondary error status bits. */
655 error_bits = afsr &
656 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
657 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
658 if (!error_bits)
659 return IRQ_NONE;
660 psycho_write(afsr_reg, error_bits);
661
662 /* Log the error. */
663 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
664 p->index,
665 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
666 "PIO" :
667 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
668 "DMA Read" :
669 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
670 "DMA Write" : "???")))));
671 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
672 p->index,
673 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
674 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
675 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
676 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
677 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
678 printk("PSYCHO%d: UE Secondary errors [", p->index);
679 reported = 0;
680 if (afsr & PSYCHO_UEAFSR_SPIO) {
681 reported++;
682 printk("(PIO)");
683 }
684 if (afsr & PSYCHO_UEAFSR_SDRD) {
685 reported++;
686 printk("(DMA Read)");
687 }
688 if (afsr & PSYCHO_UEAFSR_SDWR) {
689 reported++;
690 printk("(DMA Write)");
691 }
692 if (!reported)
693 printk("(none)");
694 printk("]\n");
695
696 /* Interrogate IOMMU for error status. */
697 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
698
699 return IRQ_HANDLED;
700}
701
702/* Correctable Errors. */
703#define PSYCHO_CE_AFSR 0x0040UL
704#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
705#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
706#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
707#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
708#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
709#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
710#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
711#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
712#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
713#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
714#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
715#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
716#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
717#define PSYCHO_CE_AFAR 0x0040UL
718
719static irqreturn_t psycho_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
720{
721 struct pci_controller_info *p = dev_id;
722 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR;
723 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR;
724 unsigned long afsr, afar, error_bits;
725 int reported;
726
727 /* Latch error status. */
728 afar = psycho_read(afar_reg);
729 afsr = psycho_read(afsr_reg);
730
731 /* Clear primary/secondary error status bits. */
732 error_bits = afsr &
733 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
734 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
735 if (!error_bits)
736 return IRQ_NONE;
737 psycho_write(afsr_reg, error_bits);
738
739 /* Log the error. */
740 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
741 p->index,
742 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
743 "PIO" :
744 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
745 "DMA Read" :
746 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
747 "DMA Write" : "???")))));
748
749 /* XXX Use syndrome and afar to print out module string just like
750 * XXX UDB CE trap handler does... -DaveM
751 */
752 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
753 "UPA_MID[%02lx] was_block(%d)\n",
754 p->index,
755 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
756 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
757 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
758 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
759 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
760 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
761 printk("PSYCHO%d: CE Secondary errors [", p->index);
762 reported = 0;
763 if (afsr & PSYCHO_CEAFSR_SPIO) {
764 reported++;
765 printk("(PIO)");
766 }
767 if (afsr & PSYCHO_CEAFSR_SDRD) {
768 reported++;
769 printk("(DMA Read)");
770 }
771 if (afsr & PSYCHO_CEAFSR_SDWR) {
772 reported++;
773 printk("(DMA Write)");
774 }
775 if (!reported)
776 printk("(none)");
777 printk("]\n");
778
779 return IRQ_HANDLED;
780}
781
782/* PCI Errors. They are signalled by the PCI bus module since they
783 * are associated with a specific bus segment.
784 */
785#define PSYCHO_PCI_AFSR_A 0x2010UL
786#define PSYCHO_PCI_AFSR_B 0x4010UL
787#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
788#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
789#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
790#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
791#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
792#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
793#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
794#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
795#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
796#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
797#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
798#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
799#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
800#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
801#define PSYCHO_PCI_AFAR_A 0x2018UL
802#define PSYCHO_PCI_AFAR_B 0x4018UL
803
804static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
805{
806 unsigned long csr_reg, csr, csr_error_bits;
807 irqreturn_t ret = IRQ_NONE;
808 u16 stat;
809
810 if (is_pbm_a) {
811 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
812 } else {
813 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
814 }
815 csr = psycho_read(csr_reg);
816 csr_error_bits =
817 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
818 if (csr_error_bits) {
819 /* Clear the errors. */
820 psycho_write(csr_reg, csr);
821
822 /* Log 'em. */
823 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
824 printk("%s: PCI streaming byte hole error asserted.\n",
825 pbm->name);
826 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
827 printk("%s: PCI SERR signal asserted.\n", pbm->name);
828 ret = IRQ_HANDLED;
829 }
830 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
831 if (stat & (PCI_STATUS_PARITY |
832 PCI_STATUS_SIG_TARGET_ABORT |
833 PCI_STATUS_REC_TARGET_ABORT |
834 PCI_STATUS_REC_MASTER_ABORT |
835 PCI_STATUS_SIG_SYSTEM_ERROR)) {
836 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
837 pbm->name, stat);
838 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
839 ret = IRQ_HANDLED;
840 }
841 return ret;
842}
843
844static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
845{
846 struct pci_pbm_info *pbm = dev_id;
847 struct pci_controller_info *p = pbm->parent;
848 unsigned long afsr_reg, afar_reg;
849 unsigned long afsr, afar, error_bits;
850 int is_pbm_a, reported;
851
852 is_pbm_a = (pbm == &pbm->parent->pbm_A);
853 if (is_pbm_a) {
854 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
855 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
856 } else {
857 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
858 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
859 }
860
861 /* Latch error status. */
862 afar = psycho_read(afar_reg);
863 afsr = psycho_read(afsr_reg);
864
865 /* Clear primary/secondary error status bits. */
866 error_bits = afsr &
867 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
868 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
869 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
870 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
871 if (!error_bits)
872 return psycho_pcierr_intr_other(pbm, is_pbm_a);
873 psycho_write(afsr_reg, error_bits);
874
875 /* Log the error. */
876 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
877 p->index, (is_pbm_a ? 'A' : 'B'),
878 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
879 "Master Abort" :
880 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
881 "Target Abort" :
882 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
883 "Excessive Retries" :
884 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
885 "Parity Error" : "???"))))));
886 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
887 p->index, (is_pbm_a ? 'A' : 'B'),
888 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
889 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
890 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
891 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
892 p->index, (is_pbm_a ? 'A' : 'B'), afar);
893 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
894 p->index, (is_pbm_a ? 'A' : 'B'));
895 reported = 0;
896 if (afsr & PSYCHO_PCIAFSR_SMA) {
897 reported++;
898 printk("(Master Abort)");
899 }
900 if (afsr & PSYCHO_PCIAFSR_STA) {
901 reported++;
902 printk("(Target Abort)");
903 }
904 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
905 reported++;
906 printk("(Excessive Retries)");
907 }
908 if (afsr & PSYCHO_PCIAFSR_SPERR) {
909 reported++;
910 printk("(Parity Error)");
911 }
912 if (!reported)
913 printk("(none)");
914 printk("]\n");
915
916 /* For the error types shown, scan PBM's PCI bus for devices
917 * which have logged that error type.
918 */
919
920 /* If we see a Target Abort, this could be the result of an
921 * IOMMU translation error of some sort. It is extremely
922 * useful to log this information as usually it indicates
923 * a bug in the IOMMU support code or a PCI device driver.
924 */
925 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
926 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
927 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
928 }
929 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
930 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
931
932 /* For excessive retries, PSYCHO/PBM will abort the device
933 * and there is no way to specifically check for excessive
934 * retries in the config space status registers. So what
935 * we hope is that we'll catch it via the master/target
936 * abort events.
937 */
938
939 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
940 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
941
942 return IRQ_HANDLED;
943}
944
945/* XXX What about PowerFail/PowerManagement??? -DaveM */
946#define PSYCHO_ECC_CTRL 0x0020
947#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
948#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
949#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
950#define PSYCHO_UE_INO 0x2e
951#define PSYCHO_CE_INO 0x2f
952#define PSYCHO_PCIERR_A_INO 0x30
953#define PSYCHO_PCIERR_B_INO 0x31
085ae41f 954static void psycho_register_error_handlers(struct pci_controller_info *p)
1da177e4
LT		 955{
956 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
957 unsigned long base = p->pbm_A.controller_regs;
958 unsigned int irq, portid = pbm->portid;
959 u64 tmp;
960
961 /* Build IRQs and register handlers. */
962 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_UE_INO);
963 if (request_irq(irq, psycho_ue_intr,
964 SA_SHIRQ, "PSYCHO UE", p) < 0) {
965 prom_printf("PSYCHO%d: Cannot register UE interrupt.\n",
966 p->index);
967 prom_halt();
968 }
969
970 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_CE_INO);
971 if (request_irq(irq, psycho_ce_intr,
972 SA_SHIRQ, "PSYCHO CE", p) < 0) {
973 prom_printf("PSYCHO%d: Cannot register CE interrupt.\n",
974 p->index);
975 prom_halt();
976 }
977
978 pbm = &p->pbm_A;
979 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_A_INO);
980 if (request_irq(irq, psycho_pcierr_intr,
981 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_A) < 0) {
982 prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n",
983 p->index);
984 prom_halt();
985 }
986
987 pbm = &p->pbm_B;
988 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_B_INO);
989 if (request_irq(irq, psycho_pcierr_intr,
990 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_B) < 0) {
991 prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n",
992 p->index);
993 prom_halt();
994 }
995
996 /* Enable UE and CE interrupts for controller. */
997 psycho_write(base + PSYCHO_ECC_CTRL,
998 (PSYCHO_ECCCTRL_EE |
999 PSYCHO_ECCCTRL_UE |
1000 PSYCHO_ECCCTRL_CE));
1001
1002 /* Enable PCI Error interrupts and clear error
1003 * bits for each PBM.
1004 */
1005 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
1006 tmp |= (PSYCHO_PCICTRL_SERR |
1007 PSYCHO_PCICTRL_SBH_ERR |
1008 PSYCHO_PCICTRL_EEN);
1009 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1010 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
1011
1012 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
1013 tmp |= (PSYCHO_PCICTRL_SERR |
1014 PSYCHO_PCICTRL_SBH_ERR |
1015 PSYCHO_PCICTRL_EEN);
1016 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1017 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
1018}
1019
1020/* PSYCHO boot time probing and initialization. */
085ae41f
DM		 1021static void psycho_resource_adjust(struct pci_dev *pdev,
1022 struct resource *res,
1023 struct resource *root)
1da177e4
LT		 1024{
1025 res->start += root->start;
1026 res->end += root->start;
1027}
1028
085ae41f 1029static void psycho_base_address_update(struct pci_dev *pdev, int resource)
1da177e4
LT		 1030{
1031 struct pcidev_cookie *pcp = pdev->sysdata;
1032 struct pci_pbm_info *pbm = pcp->pbm;
1033 struct resource *res, *root;
1034 u32 reg;
1035 int where, size, is_64bit;
1036
1037 res = &pdev->resource[resource];
1038 if (resource < 6) {
1039 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1040 } else if (resource == PCI_ROM_RESOURCE) {
1041 where = pdev->rom_base_reg;
1042 } else {
1043 /* Somebody might have asked allocation of a non-standard resource */
1044 return;
1045 }
1046
1047 is_64bit = 0;
1048 if (res->flags & IORESOURCE_IO)
1049 root = &pbm->io_space;
1050 else {
1051 root = &pbm->mem_space;
1052 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1053 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1054 is_64bit = 1;
1055 }
1056
1057 size = res->end - res->start;
1058 pci_read_config_dword(pdev, where, &reg);
1059 reg = ((reg & size) |
1060 (((u32)(res->start - root->start)) & ~size));
1061 if (resource == PCI_ROM_RESOURCE) {
1062 reg |= PCI_ROM_ADDRESS_ENABLE;
1063 res->flags |= IORESOURCE_ROM_ENABLE;
1064 }
1065 pci_write_config_dword(pdev, where, reg);
1066
1067 /* This knows that the upper 32-bits of the address
1068 * must be zero. Our PCI common layer enforces this.
1069 */
1070 if (is_64bit)
1071 pci_write_config_dword(pdev, where + 4, 0);
1072}
1073
085ae41f 1074static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 1075{
1076 u8 *addr;
1077
1078 /* Set cache-line size to 64 bytes, this is actually
1079 * a nop but I do it for completeness.
1080 */
1081 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1082 0, PCI_CACHE_LINE_SIZE);
1083 pci_config_write8(addr, 64 / sizeof(u32));
1084
1085 /* Set PBM latency timer to 64 PCI clocks. */
1086 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1087 0, PCI_LATENCY_TIMER);
1088 pci_config_write8(addr, 64);
1089}
1090
085ae41f
DM		 1091static void pbm_scan_bus(struct pci_controller_info *p,
1092 struct pci_pbm_info *pbm)
1da177e4 1093{
9132983a 1094 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
1da177e4
LT		 1095
1096 if (!cookie) {
1097 prom_printf("PSYCHO: Critical allocation failure.\n");
1098 prom_halt();
1099 }
1100
1101 /* All we care about is the PBM. */
1da177e4
LT		 1102 cookie->pbm = pbm;
1103
1104 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1105 p->pci_ops,
1106 pbm);
1107 pci_fixup_host_bridge_self(pbm->pci_bus);
1108 pbm->pci_bus->self->sysdata = cookie;
1109
1110 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1111 pci_record_assignments(pbm, pbm->pci_bus);
1112 pci_assign_unassigned(pbm, pbm->pci_bus);
1113 pci_fixup_irq(pbm, pbm->pci_bus);
1114 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1115 pci_setup_busmastering(pbm, pbm->pci_bus);
1116}
1117
085ae41f 1118static void psycho_scan_bus(struct pci_controller_info *p)
1da177e4
LT		 1119{
1120 pbm_config_busmastering(&p->pbm_B);
1121 p->pbm_B.is_66mhz_capable = 0;
1122 pbm_config_busmastering(&p->pbm_A);
1123 p->pbm_A.is_66mhz_capable = 1;
1124 pbm_scan_bus(p, &p->pbm_B);
1125 pbm_scan_bus(p, &p->pbm_A);
1126
1127 /* After the PCI bus scan is complete, we can register
1128 * the error interrupt handlers.
1129 */
1130 psycho_register_error_handlers(p);
1131}
1132
085ae41f 1133static void psycho_iommu_init(struct pci_controller_info *p)
1da177e4
LT		 1134{
1135 struct pci_iommu *iommu = p->pbm_A.iommu;
51e85136 1136 unsigned long i;
1da177e4
LT		 1137 u64 control;
1138
1da177e4
LT		 1139 /* Register addresses. */
1140 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
1141 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
1142 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
1143 /* PSYCHO's IOMMU lacks ctx flushing. */
1144 iommu->iommu_ctxflush = 0;
1145
1146 /* We use the main control register of PSYCHO as the write
1147 * completion register.
1148 */
1149 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
1150
1151 /*
1152 * Invalidate TLB Entries.
1153 */
1154 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1155 control |= PSYCHO_IOMMU_CTRL_DENAB;
1156 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1157 for(i = 0; i < 16; i++) {
1158 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
1159 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1160 }
1161
1162 /* Leave diag mode enabled for full-flushing done
1163 * in pci_iommu.c
1164 */
51e85136 1165 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
1da177e4 1166
51e85136
DM		 1167 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
1168 __pa(iommu->page_table));
1da177e4
LT		 1169
1170 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1171 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
1172 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
1173 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1174
1175 /* If necessary, hook us up for starfire IRQ translations. */
51e85136 1176 if (this_is_starfire)
1da177e4
LT		 1177 p->starfire_cookie = starfire_hookup(p->pbm_A.portid);
1178 else
1179 p->starfire_cookie = NULL;
1180}
1181
1182#define PSYCHO_IRQ_RETRY 0x1a00UL
1183#define PSYCHO_PCIA_DIAG 0x2020UL
1184#define PSYCHO_PCIB_DIAG 0x4020UL
1185#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
1186#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
1187#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
1188#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
1189#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
1190#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
1191#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
1192#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
1193
1194static void psycho_controller_hwinit(struct pci_controller_info *p)
1195{
1196 u64 tmp;
1197
864ae180 1198 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1da177e4
LT		 1199
1200 /* Enable arbiter for all PCI slots. */
1201 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
1202 tmp |= PSYCHO_PCICTRL_AEN;
1203 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
1204
1205 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1206 tmp |= PSYCHO_PCICTRL_AEN;
1207 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1208
1209 /* Disable DMA write / PIO read synchronization on
1210 * both PCI bus segments.
1211 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1212 */
1213 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1214 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1215 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1216
1217 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1218 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1219 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1220}
1221
085ae41f
DM		 1222static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1223 struct pci_pbm_info *pbm)
1da177e4
LT		 1224{
1225 char *name = pbm->name;
1226
1227 sprintf(name, "PSYCHO%d PBM%c",
1228 p->index,
1229 (pbm == &p->pbm_A ? 'A' : 'B'));
1230 pbm->io_space.name = pbm->mem_space.name = name;
1231
1232 request_resource(&ioport_resource, &pbm->io_space);
1233 request_resource(&iomem_resource, &pbm->mem_space);
1234 pci_register_legacy_regions(&pbm->io_space,
1235 &pbm->mem_space);
1236}
1237
1238static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1239 struct pci_pbm_info *pbm,
1240 int is_pbm_a)
1241{
1242 unsigned long base = pbm->controller_regs;
1243 u64 control;
1244
1245 if (is_pbm_a) {
1246 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1247 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1248 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1249 } else {
1250 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1251 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1252 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1253 }
1254 /* PSYCHO's streaming buffer lacks ctx flushing. */
1255 pbm->stc.strbuf_ctxflush = 0;
1256 pbm->stc.strbuf_ctxmatch_base = 0;
1257
1258 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1259 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1260 + 63UL)
1261 & ~63UL);
1262 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1263 __pa(pbm->stc.strbuf_flushflag);
1264
1265 /* Enable the streaming buffer. We have to be careful
1266 * just in case OBP left it with LRU locking enabled.
1267 *
1268 * It is possible to control if PBM will be rerun on
1269 * line misses. Currently I just retain whatever setting
1270 * OBP left us with. All checks so far show it having
1271 * a value of zero.
1272 */
1273#undef PSYCHO_STRBUF_RERUN_ENABLE
1274#undef PSYCHO_STRBUF_RERUN_DISABLE
1275 control = psycho_read(pbm->stc.strbuf_control);
1276 control |= PSYCHO_STRBUF_CTRL_ENAB;
1277 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1278#ifdef PSYCHO_STRBUF_RERUN_ENABLE
1279 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1280#else
1281#ifdef PSYCHO_STRBUF_RERUN_DISABLE
1282 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1283#endif
1284#endif
1285 psycho_write(pbm->stc.strbuf_control, control);
1286
1287 pbm->stc.strbuf_enabled = 1;
1288}
1289
1290#define PSYCHO_IOSPACE_A 0x002000000UL
1291#define PSYCHO_IOSPACE_B 0x002010000UL
1292#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1293#define PSYCHO_MEMSPACE_A 0x100000000UL
1294#define PSYCHO_MEMSPACE_B 0x180000000UL
1295#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1296
1297static void psycho_pbm_init(struct pci_controller_info *p,
1298 int prom_node, int is_pbm_a)
1299{
1300 unsigned int busrange[2];
1301 struct pci_pbm_info *pbm;
1302 int err;
1303
1304 if (is_pbm_a) {
1305 pbm = &p->pbm_A;
1306 pbm->pci_first_slot = 1;
1307 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_A;
1308 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_A;
1309 } else {
1310 pbm = &p->pbm_B;
1311 pbm->pci_first_slot = 2;
1312 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_B;
1313 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_B;
1314 }
1315
1316 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
1317 pbm->chip_version =
1318 prom_getintdefault(prom_node, "version#", 0);
1319 pbm->chip_revision =
1320 prom_getintdefault(prom_node, "module-revision#", 0);
1321
1322 pbm->io_space.end = pbm->io_space.start + PSYCHO_IOSPACE_SIZE;
1323 pbm->io_space.flags = IORESOURCE_IO;
1324 pbm->mem_space.end = pbm->mem_space.start + PSYCHO_MEMSPACE_SIZE;
1325 pbm->mem_space.flags = IORESOURCE_MEM;
1326 pbm_register_toplevel_resources(p, pbm);
1327
1328 pbm->parent = p;
1329 pbm->prom_node = prom_node;
1330 prom_getstring(prom_node, "name",
1331 pbm->prom_name,
1332 sizeof(pbm->prom_name));
1333
1334 err = prom_getproperty(prom_node, "ranges",
1335 (char *)pbm->pbm_ranges,
1336 sizeof(pbm->pbm_ranges));
1337 if (err != -1)
1338 pbm->num_pbm_ranges =
1339 (err / sizeof(struct linux_prom_pci_ranges));
1340 else
1341 pbm->num_pbm_ranges = 0;
1342
1343 err = prom_getproperty(prom_node, "interrupt-map",
1344 (char *)pbm->pbm_intmap,
1345 sizeof(pbm->pbm_intmap));
1346 if (err != -1) {
1347 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1348 err = prom_getproperty(prom_node, "interrupt-map-mask",
1349 (char *)&pbm->pbm_intmask,
1350 sizeof(pbm->pbm_intmask));
1351 if (err == -1) {
1352 prom_printf("PSYCHO-PBM: Fatal error, no "
1353 "interrupt-map-mask.\n");
1354 prom_halt();
1355 }
1356 } else {
1357 pbm->num_pbm_intmap = 0;
1358 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1359 }
1360
1361 err = prom_getproperty(prom_node, "bus-range",
1362 (char *)&busrange[0],
1363 sizeof(busrange));
1364 if (err == 0 || err == -1) {
1365 prom_printf("PSYCHO-PBM: Fatal error, no bus-range.\n");
1366 prom_halt();
1367 }
1368 pbm->pci_first_busno = busrange[0];
1369 pbm->pci_last_busno = busrange[1];
1370
1371 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1372}
1373
1374#define PSYCHO_CONFIGSPACE 0x001000000UL
1375
085ae41f 1376void psycho_init(int node, char *model_name)
1da177e4
LT		 1377{
1378 struct linux_prom64_registers pr_regs[3];
1379 struct pci_controller_info *p;
1380 struct pci_iommu *iommu;
1381 u32 upa_portid;
1382 int is_pbm_a, err;
1383
1384 upa_portid = prom_getintdefault(node, "upa-portid", 0xff);
1385
1386 for(p = pci_controller_root; p; p = p->next) {
1387 if (p->pbm_A.portid == upa_portid) {
1388 is_pbm_a = (p->pbm_A.prom_node == 0);
1389 psycho_pbm_init(p, node, is_pbm_a);
1390 return;
1391 }
1392 }
1393
9132983a 1394 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1da177e4
LT		 1395 if (!p) {
1396 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1397 prom_halt();
1398 }
9132983a 1399 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1da177e4
LT		 1400 if (!iommu) {
1401 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1402 prom_halt();
1403 }
1da177e4
LT		 1404 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1405
1406 p->next = pci_controller_root;
1407 pci_controller_root = p;
1408
1409 p->pbm_A.portid = upa_portid;
1410 p->pbm_B.portid = upa_portid;
1411 p->index = pci_num_controllers++;
1412 p->pbms_same_domain = 0;
1413 p->scan_bus = psycho_scan_bus;
1414 p->irq_build = psycho_irq_build;
1415 p->base_address_update = psycho_base_address_update;
1416 p->resource_adjust = psycho_resource_adjust;
1417 p->pci_ops = &psycho_ops;
1418
1419 err = prom_getproperty(node, "reg",
1420 (char *)&pr_regs[0],
1421 sizeof(pr_regs));
1422 if (err == 0 || err == -1) {
1423 prom_printf("PSYCHO: Fatal error, no reg property.\n");
1424 prom_halt();
1425 }
1426
1427 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1428 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1429 printk("PCI: Found PSYCHO, control regs at %016lx\n",
1430 p->pbm_A.controller_regs);
1431
1432 p->pbm_A.config_space = p->pbm_B.config_space =
1433 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1434 printk("PSYCHO: Shared PCI config space at %016lx\n",
1435 p->pbm_A.config_space);
1436
1437 /*
1438 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1439 * we need to adjust our MEM space mask.
1440 */
1441 pci_memspace_mask = 0x7fffffffUL;
1442
1443 psycho_controller_hwinit(p);
1444
1445 psycho_iommu_init(p);
1446
1447 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1448 psycho_pbm_init(p, node, is_pbm_a);
1449}
Linux kernel - Deliverables
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