Commit | Line | Data |
---|---|---|
9fd8b647 | 1 | /* pci_psycho.c: PSYCHO/U2P specific PCI controller support. |
1da177e4 | 2 | * |
9fd8b647 | 3 | * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) | |
6 | */ | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/types.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/interrupt.h> | |
14 | ||
1da177e4 LT |
15 | #include <asm/iommu.h> |
16 | #include <asm/irq.h> | |
17 | #include <asm/starfire.h> | |
e87dc350 | 18 | #include <asm/prom.h> |
2b1e5978 | 19 | #include <asm/of_device.h> |
c57c2ffb | 20 | #include <asm/oplib.h> |
1da177e4 LT |
21 | |
22 | #include "pci_impl.h" | |
23 | #include "iommu_common.h" | |
24 | ||
25 | /* All PSYCHO registers are 64-bits. The following accessor | |
26 | * routines are how they are accessed. The REG parameter | |
27 | * is a physical address. | |
28 | */ | |
29 | #define psycho_read(__reg) \ | |
30 | ({ u64 __ret; \ | |
31 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
32 | : "=r" (__ret) \ | |
33 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
34 | : "memory"); \ | |
35 | __ret; \ | |
36 | }) | |
37 | #define psycho_write(__reg, __val) \ | |
38 | __asm__ __volatile__("stxa %0, [%1] %2" \ | |
39 | : /* no outputs */ \ | |
40 | : "r" (__val), "r" (__reg), \ | |
41 | "i" (ASI_PHYS_BYPASS_EC_E) \ | |
42 | : "memory") | |
43 | ||
44 | /* Misc. PSYCHO PCI controller register offsets and definitions. */ | |
45 | #define PSYCHO_CONTROL 0x0010UL | |
46 | #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ | |
47 | #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ | |
48 | #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ | |
49 | #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ | |
50 | #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ | |
51 | #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ | |
52 | #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ | |
53 | #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ | |
54 | #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ | |
55 | #define PSYCHO_PCIA_CTRL 0x2000UL | |
56 | #define PSYCHO_PCIB_CTRL 0x4000UL | |
57 | #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ | |
58 | #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ | |
59 | #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ | |
60 | #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ | |
61 | #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ | |
62 | #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ | |
63 | #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ | |
64 | #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ | |
65 | #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ | |
66 | #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ | |
67 | #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ | |
68 | #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ | |
69 | ||
70 | /* U2P Programmer's Manual, page 13-55, configuration space | |
71 | * address format: | |
72 | * | |
73 | * 32 24 23 16 15 11 10 8 7 2 1 0 | |
74 | * --------------------------------------------------------- | |
75 | * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 | | |
76 | * --------------------------------------------------------- | |
77 | */ | |
78 | #define PSYCHO_CONFIG_BASE(PBM) \ | |
79 | ((PBM)->config_space | (1UL << 24)) | |
80 | #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ | |
81 | (((unsigned long)(BUS) << 16) | \ | |
82 | ((unsigned long)(DEVFN) << 8) | \ | |
83 | ((unsigned long)(REG))) | |
84 | ||
85 | static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm, | |
86 | unsigned char bus, | |
87 | unsigned int devfn, | |
88 | int where) | |
89 | { | |
90 | if (!pbm) | |
91 | return NULL; | |
92 | return (void *) | |
93 | (PSYCHO_CONFIG_BASE(pbm) | | |
94 | PSYCHO_CONFIG_ENCODE(bus, devfn, where)); | |
95 | } | |
96 | ||
1da177e4 LT |
97 | /* PSYCHO error handling support. */ |
98 | enum psycho_error_type { | |
99 | UE_ERR, CE_ERR, PCI_ERR | |
100 | }; | |
101 | ||
102 | /* Helper function of IOMMU error checking, which checks out | |
103 | * the state of the streaming buffers. The IOMMU lock is | |
104 | * held when this is called. | |
105 | * | |
106 | * For the PCI error case we know which PBM (and thus which | |
107 | * streaming buffer) caused the error, but for the uncorrectable | |
108 | * error case we do not. So we always check both streaming caches. | |
109 | */ | |
110 | #define PSYCHO_STRBUF_CONTROL_A 0x2800UL | |
111 | #define PSYCHO_STRBUF_CONTROL_B 0x4800UL | |
112 | #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ | |
113 | #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ | |
114 | #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ | |
115 | #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ | |
116 | #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ | |
117 | #define PSYCHO_STRBUF_FLUSH_A 0x2808UL | |
118 | #define PSYCHO_STRBUF_FLUSH_B 0x4808UL | |
119 | #define PSYCHO_STRBUF_FSYNC_A 0x2810UL | |
120 | #define PSYCHO_STRBUF_FSYNC_B 0x4810UL | |
121 | #define PSYCHO_STC_DATA_A 0xb000UL | |
122 | #define PSYCHO_STC_DATA_B 0xc000UL | |
123 | #define PSYCHO_STC_ERR_A 0xb400UL | |
124 | #define PSYCHO_STC_ERR_B 0xc400UL | |
125 | #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */ | |
126 | #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */ | |
127 | #define PSYCHO_STC_TAG_A 0xb800UL | |
128 | #define PSYCHO_STC_TAG_B 0xc800UL | |
129 | #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */ | |
130 | #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */ | |
131 | #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */ | |
132 | #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */ | |
133 | #define PSYCHO_STC_LINE_A 0xb900UL | |
134 | #define PSYCHO_STC_LINE_B 0xc900UL | |
135 | #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */ | |
136 | #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */ | |
137 | #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */ | |
138 | #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */ | |
139 | #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */ | |
140 | #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */ | |
141 | ||
142 | static DEFINE_SPINLOCK(stc_buf_lock); | |
143 | static unsigned long stc_error_buf[128]; | |
144 | static unsigned long stc_tag_buf[16]; | |
145 | static unsigned long stc_line_buf[16]; | |
146 | ||
34768bc8 | 147 | static void __psycho_check_one_stc(struct pci_pbm_info *pbm, |
1da177e4 LT |
148 | int is_pbm_a) |
149 | { | |
16ce82d8 | 150 | struct strbuf *strbuf = &pbm->stc; |
34768bc8 | 151 | unsigned long regbase = pbm->controller_regs; |
1da177e4 LT |
152 | unsigned long err_base, tag_base, line_base; |
153 | u64 control; | |
154 | int i; | |
155 | ||
156 | if (is_pbm_a) { | |
157 | err_base = regbase + PSYCHO_STC_ERR_A; | |
158 | tag_base = regbase + PSYCHO_STC_TAG_A; | |
159 | line_base = regbase + PSYCHO_STC_LINE_A; | |
160 | } else { | |
161 | err_base = regbase + PSYCHO_STC_ERR_B; | |
162 | tag_base = regbase + PSYCHO_STC_TAG_B; | |
163 | line_base = regbase + PSYCHO_STC_LINE_B; | |
164 | } | |
165 | ||
166 | spin_lock(&stc_buf_lock); | |
167 | ||
168 | /* This is __REALLY__ dangerous. When we put the | |
169 | * streaming buffer into diagnostic mode to probe | |
170 | * it's tags and error status, we _must_ clear all | |
171 | * of the line tag valid bits before re-enabling | |
172 | * the streaming buffer. If any dirty data lives | |
173 | * in the STC when we do this, we will end up | |
174 | * invalidating it before it has a chance to reach | |
175 | * main memory. | |
176 | */ | |
177 | control = psycho_read(strbuf->strbuf_control); | |
178 | psycho_write(strbuf->strbuf_control, | |
179 | (control | PSYCHO_STRBUF_CTRL_DENAB)); | |
180 | for (i = 0; i < 128; i++) { | |
181 | unsigned long val; | |
182 | ||
183 | val = psycho_read(err_base + (i * 8UL)); | |
184 | psycho_write(err_base + (i * 8UL), 0UL); | |
185 | stc_error_buf[i] = val; | |
186 | } | |
187 | for (i = 0; i < 16; i++) { | |
188 | stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL)); | |
189 | stc_line_buf[i] = psycho_read(line_base + (i * 8UL)); | |
190 | psycho_write(tag_base + (i * 8UL), 0UL); | |
191 | psycho_write(line_base + (i * 8UL), 0UL); | |
192 | } | |
193 | ||
194 | /* OK, state is logged, exit diagnostic mode. */ | |
195 | psycho_write(strbuf->strbuf_control, control); | |
196 | ||
197 | for (i = 0; i < 16; i++) { | |
198 | int j, saw_error, first, last; | |
199 | ||
200 | saw_error = 0; | |
201 | first = i * 8; | |
202 | last = first + 8; | |
203 | for (j = first; j < last; j++) { | |
204 | unsigned long errval = stc_error_buf[j]; | |
205 | if (errval != 0) { | |
206 | saw_error++; | |
6c108f12 DM |
207 | printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", |
208 | pbm->name, | |
1da177e4 LT |
209 | j, |
210 | (errval & PSYCHO_STCERR_WRITE) ? 1 : 0, | |
211 | (errval & PSYCHO_STCERR_READ) ? 1 : 0); | |
212 | } | |
213 | } | |
214 | if (saw_error != 0) { | |
215 | unsigned long tagval = stc_tag_buf[i]; | |
216 | unsigned long lineval = stc_line_buf[i]; | |
6c108f12 DM |
217 | printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n", |
218 | pbm->name, | |
1da177e4 LT |
219 | i, |
220 | ((tagval & PSYCHO_STCTAG_PPN) >> 19UL), | |
221 | (tagval & PSYCHO_STCTAG_VPN), | |
222 | ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0), | |
223 | ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0)); | |
6c108f12 | 224 | printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" |
1da177e4 | 225 | "V(%d)FOFN(%d)]\n", |
6c108f12 | 226 | pbm->name, |
1da177e4 LT |
227 | i, |
228 | ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL), | |
229 | ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL), | |
230 | ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL), | |
231 | ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL), | |
232 | ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0), | |
233 | ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0)); | |
234 | } | |
235 | } | |
236 | ||
237 | spin_unlock(&stc_buf_lock); | |
238 | } | |
239 | ||
34768bc8 | 240 | static void __psycho_check_stc_error(struct pci_pbm_info *pbm, |
1da177e4 LT |
241 | unsigned long afsr, |
242 | unsigned long afar, | |
243 | enum psycho_error_type type) | |
244 | { | |
34768bc8 DM |
245 | __psycho_check_one_stc(pbm, |
246 | (pbm == &pbm->parent->pbm_A)); | |
1da177e4 LT |
247 | } |
248 | ||
249 | /* When an Uncorrectable Error or a PCI Error happens, we | |
250 | * interrogate the IOMMU state to see if it is the cause. | |
251 | */ | |
252 | #define PSYCHO_IOMMU_CONTROL 0x0200UL | |
253 | #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ | |
254 | #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ | |
255 | #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ | |
256 | #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ | |
257 | #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ | |
258 | #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ | |
259 | #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ | |
260 | #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ | |
261 | #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ | |
262 | #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ | |
263 | #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ | |
264 | #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ | |
265 | #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ | |
266 | #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ | |
267 | #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ | |
268 | #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ | |
269 | #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ | |
270 | #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ | |
271 | #define PSYCHO_IOMMU_TSBBASE 0x0208UL | |
272 | #define PSYCHO_IOMMU_FLUSH 0x0210UL | |
273 | #define PSYCHO_IOMMU_TAG 0xa580UL | |
274 | #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL) | |
275 | #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL) | |
276 | #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL) | |
277 | #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL) | |
278 | #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL) | |
279 | #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL | |
280 | #define PSYCHO_IOMMU_DATA 0xa600UL | |
281 | #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL) | |
282 | #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL) | |
283 | #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL | |
34768bc8 | 284 | static void psycho_check_iommu_error(struct pci_pbm_info *pbm, |
1da177e4 LT |
285 | unsigned long afsr, |
286 | unsigned long afar, | |
287 | enum psycho_error_type type) | |
288 | { | |
34768bc8 | 289 | struct iommu *iommu = pbm->iommu; |
1da177e4 LT |
290 | unsigned long iommu_tag[16]; |
291 | unsigned long iommu_data[16]; | |
292 | unsigned long flags; | |
293 | u64 control; | |
294 | int i; | |
295 | ||
296 | spin_lock_irqsave(&iommu->lock, flags); | |
297 | control = psycho_read(iommu->iommu_control); | |
298 | if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { | |
299 | char *type_string; | |
300 | ||
301 | /* Clear the error encountered bit. */ | |
302 | control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; | |
303 | psycho_write(iommu->iommu_control, control); | |
304 | ||
305 | switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) { | |
306 | case 0: | |
307 | type_string = "Protection Error"; | |
308 | break; | |
309 | case 1: | |
310 | type_string = "Invalid Error"; | |
311 | break; | |
312 | case 2: | |
313 | type_string = "TimeOut Error"; | |
314 | break; | |
315 | case 3: | |
316 | default: | |
317 | type_string = "ECC Error"; | |
318 | break; | |
319 | }; | |
6c108f12 DM |
320 | printk("%s: IOMMU Error, type[%s]\n", |
321 | pbm->name, type_string); | |
1da177e4 LT |
322 | |
323 | /* Put the IOMMU into diagnostic mode and probe | |
324 | * it's TLB for entries with error status. | |
325 | * | |
326 | * It is very possible for another DVMA to occur | |
327 | * while we do this probe, and corrupt the system | |
328 | * further. But we are so screwed at this point | |
329 | * that we are likely to crash hard anyways, so | |
330 | * get as much diagnostic information to the | |
331 | * console as we can. | |
332 | */ | |
333 | psycho_write(iommu->iommu_control, | |
334 | control | PSYCHO_IOMMU_CTRL_DENAB); | |
335 | for (i = 0; i < 16; i++) { | |
34768bc8 | 336 | unsigned long base = pbm->controller_regs; |
1da177e4 LT |
337 | |
338 | iommu_tag[i] = | |
339 | psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL)); | |
340 | iommu_data[i] = | |
341 | psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL)); | |
342 | ||
343 | /* Now clear out the entry. */ | |
344 | psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0); | |
345 | psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0); | |
346 | } | |
347 | ||
348 | /* Leave diagnostic mode. */ | |
349 | psycho_write(iommu->iommu_control, control); | |
350 | ||
351 | for (i = 0; i < 16; i++) { | |
352 | unsigned long tag, data; | |
353 | ||
354 | tag = iommu_tag[i]; | |
355 | if (!(tag & PSYCHO_IOMMU_TAG_ERR)) | |
356 | continue; | |
357 | ||
358 | data = iommu_data[i]; | |
359 | switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) { | |
360 | case 0: | |
361 | type_string = "Protection Error"; | |
362 | break; | |
363 | case 1: | |
364 | type_string = "Invalid Error"; | |
365 | break; | |
366 | case 2: | |
367 | type_string = "TimeOut Error"; | |
368 | break; | |
369 | case 3: | |
370 | default: | |
371 | type_string = "ECC Error"; | |
372 | break; | |
373 | }; | |
6c108f12 DM |
374 | printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n", |
375 | pbm->name, i, type_string, | |
1da177e4 LT |
376 | ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0), |
377 | ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0), | |
378 | ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8), | |
379 | (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); | |
6c108f12 DM |
380 | printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", |
381 | pbm->name, i, | |
1da177e4 LT |
382 | ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0), |
383 | ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0), | |
384 | (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); | |
385 | } | |
386 | } | |
34768bc8 | 387 | __psycho_check_stc_error(pbm, afsr, afar, type); |
1da177e4 LT |
388 | spin_unlock_irqrestore(&iommu->lock, flags); |
389 | } | |
390 | ||
391 | /* Uncorrectable Errors. Cause of the error and the address are | |
392 | * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors | |
393 | * relating to UPA interface transactions. | |
394 | */ | |
395 | #define PSYCHO_UE_AFSR 0x0030UL | |
396 | #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ | |
397 | #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ | |
398 | #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ | |
399 | #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ | |
400 | #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ | |
401 | #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ | |
402 | #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ | |
403 | #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ | |
404 | #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ | |
405 | #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ | |
406 | #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ | |
407 | #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ | |
408 | #define PSYCHO_UE_AFAR 0x0038UL | |
409 | ||
6d24c8dc | 410 | static irqreturn_t psycho_ue_intr(int irq, void *dev_id) |
1da177e4 | 411 | { |
34768bc8 DM |
412 | struct pci_pbm_info *pbm = dev_id; |
413 | struct pci_controller_info *p = pbm->parent; | |
414 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; | |
415 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; | |
1da177e4 LT |
416 | unsigned long afsr, afar, error_bits; |
417 | int reported; | |
418 | ||
419 | /* Latch uncorrectable error status. */ | |
420 | afar = psycho_read(afar_reg); | |
421 | afsr = psycho_read(afsr_reg); | |
422 | ||
423 | /* Clear the primary/secondary error status bits. */ | |
424 | error_bits = afsr & | |
425 | (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | | |
426 | PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); | |
427 | if (!error_bits) | |
428 | return IRQ_NONE; | |
429 | psycho_write(afsr_reg, error_bits); | |
430 | ||
431 | /* Log the error. */ | |
6c108f12 DM |
432 | printk("%s: Uncorrectable Error, primary error type[%s]\n", |
433 | pbm->name, | |
1da177e4 LT |
434 | (((error_bits & PSYCHO_UEAFSR_PPIO) ? |
435 | "PIO" : | |
436 | ((error_bits & PSYCHO_UEAFSR_PDRD) ? | |
437 | "DMA Read" : | |
438 | ((error_bits & PSYCHO_UEAFSR_PDWR) ? | |
439 | "DMA Write" : "???"))))); | |
6c108f12 DM |
440 | printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", |
441 | pbm->name, | |
1da177e4 LT |
442 | (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, |
443 | (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, | |
444 | (afsr & PSYCHO_UEAFSR_MID) >> 24UL, | |
445 | ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); | |
6c108f12 DM |
446 | printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); |
447 | printk("%s: UE Secondary errors [", pbm->name); | |
1da177e4 LT |
448 | reported = 0; |
449 | if (afsr & PSYCHO_UEAFSR_SPIO) { | |
450 | reported++; | |
451 | printk("(PIO)"); | |
452 | } | |
453 | if (afsr & PSYCHO_UEAFSR_SDRD) { | |
454 | reported++; | |
455 | printk("(DMA Read)"); | |
456 | } | |
457 | if (afsr & PSYCHO_UEAFSR_SDWR) { | |
458 | reported++; | |
459 | printk("(DMA Write)"); | |
460 | } | |
461 | if (!reported) | |
462 | printk("(none)"); | |
463 | printk("]\n"); | |
464 | ||
34768bc8 DM |
465 | /* Interrogate both IOMMUs for error status. */ |
466 | psycho_check_iommu_error(&p->pbm_A, afsr, afar, UE_ERR); | |
467 | psycho_check_iommu_error(&p->pbm_B, afsr, afar, UE_ERR); | |
1da177e4 LT |
468 | |
469 | return IRQ_HANDLED; | |
470 | } | |
471 | ||
472 | /* Correctable Errors. */ | |
473 | #define PSYCHO_CE_AFSR 0x0040UL | |
474 | #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ | |
475 | #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ | |
476 | #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ | |
477 | #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ | |
478 | #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ | |
479 | #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ | |
480 | #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ | |
481 | #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ | |
482 | #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ | |
483 | #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ | |
484 | #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ | |
485 | #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ | |
486 | #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ | |
487 | #define PSYCHO_CE_AFAR 0x0040UL | |
488 | ||
6d24c8dc | 489 | static irqreturn_t psycho_ce_intr(int irq, void *dev_id) |
1da177e4 | 490 | { |
34768bc8 | 491 | struct pci_pbm_info *pbm = dev_id; |
34768bc8 DM |
492 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR; |
493 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR; | |
1da177e4 LT |
494 | unsigned long afsr, afar, error_bits; |
495 | int reported; | |
496 | ||
497 | /* Latch error status. */ | |
498 | afar = psycho_read(afar_reg); | |
499 | afsr = psycho_read(afsr_reg); | |
500 | ||
501 | /* Clear primary/secondary error status bits. */ | |
502 | error_bits = afsr & | |
503 | (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | | |
504 | PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); | |
505 | if (!error_bits) | |
506 | return IRQ_NONE; | |
507 | psycho_write(afsr_reg, error_bits); | |
508 | ||
509 | /* Log the error. */ | |
6c108f12 DM |
510 | printk("%s: Correctable Error, primary error type[%s]\n", |
511 | pbm->name, | |
1da177e4 LT |
512 | (((error_bits & PSYCHO_CEAFSR_PPIO) ? |
513 | "PIO" : | |
514 | ((error_bits & PSYCHO_CEAFSR_PDRD) ? | |
515 | "DMA Read" : | |
516 | ((error_bits & PSYCHO_CEAFSR_PDWR) ? | |
517 | "DMA Write" : "???"))))); | |
518 | ||
519 | /* XXX Use syndrome and afar to print out module string just like | |
520 | * XXX UDB CE trap handler does... -DaveM | |
521 | */ | |
6c108f12 | 522 | printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
1da177e4 | 523 | "UPA_MID[%02lx] was_block(%d)\n", |
6c108f12 | 524 | pbm->name, |
1da177e4 LT |
525 | (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, |
526 | (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, | |
527 | (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, | |
528 | (afsr & PSYCHO_CEAFSR_MID) >> 24UL, | |
529 | ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); | |
6c108f12 DM |
530 | printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); |
531 | printk("%s: CE Secondary errors [", pbm->name); | |
1da177e4 LT |
532 | reported = 0; |
533 | if (afsr & PSYCHO_CEAFSR_SPIO) { | |
534 | reported++; | |
535 | printk("(PIO)"); | |
536 | } | |
537 | if (afsr & PSYCHO_CEAFSR_SDRD) { | |
538 | reported++; | |
539 | printk("(DMA Read)"); | |
540 | } | |
541 | if (afsr & PSYCHO_CEAFSR_SDWR) { | |
542 | reported++; | |
543 | printk("(DMA Write)"); | |
544 | } | |
545 | if (!reported) | |
546 | printk("(none)"); | |
547 | printk("]\n"); | |
548 | ||
549 | return IRQ_HANDLED; | |
550 | } | |
551 | ||
552 | /* PCI Errors. They are signalled by the PCI bus module since they | |
553 | * are associated with a specific bus segment. | |
554 | */ | |
555 | #define PSYCHO_PCI_AFSR_A 0x2010UL | |
556 | #define PSYCHO_PCI_AFSR_B 0x4010UL | |
557 | #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */ | |
558 | #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */ | |
559 | #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ | |
560 | #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ | |
561 | #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */ | |
562 | #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */ | |
563 | #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ | |
564 | #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ | |
565 | #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */ | |
566 | #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ | |
567 | #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */ | |
568 | #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */ | |
569 | #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */ | |
570 | #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */ | |
571 | #define PSYCHO_PCI_AFAR_A 0x2018UL | |
572 | #define PSYCHO_PCI_AFAR_B 0x4018UL | |
573 | ||
574 | static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a) | |
575 | { | |
576 | unsigned long csr_reg, csr, csr_error_bits; | |
577 | irqreturn_t ret = IRQ_NONE; | |
578 | u16 stat; | |
579 | ||
580 | if (is_pbm_a) { | |
581 | csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL; | |
582 | } else { | |
583 | csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL; | |
584 | } | |
585 | csr = psycho_read(csr_reg); | |
586 | csr_error_bits = | |
587 | csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR); | |
588 | if (csr_error_bits) { | |
589 | /* Clear the errors. */ | |
590 | psycho_write(csr_reg, csr); | |
591 | ||
592 | /* Log 'em. */ | |
593 | if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR) | |
594 | printk("%s: PCI streaming byte hole error asserted.\n", | |
595 | pbm->name); | |
596 | if (csr_error_bits & PSYCHO_PCICTRL_SERR) | |
597 | printk("%s: PCI SERR signal asserted.\n", pbm->name); | |
598 | ret = IRQ_HANDLED; | |
599 | } | |
600 | pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); | |
601 | if (stat & (PCI_STATUS_PARITY | | |
602 | PCI_STATUS_SIG_TARGET_ABORT | | |
603 | PCI_STATUS_REC_TARGET_ABORT | | |
604 | PCI_STATUS_REC_MASTER_ABORT | | |
605 | PCI_STATUS_SIG_SYSTEM_ERROR)) { | |
606 | printk("%s: PCI bus error, PCI_STATUS[%04x]\n", | |
607 | pbm->name, stat); | |
608 | pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); | |
609 | ret = IRQ_HANDLED; | |
610 | } | |
611 | return ret; | |
612 | } | |
613 | ||
6d24c8dc | 614 | static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id) |
1da177e4 LT |
615 | { |
616 | struct pci_pbm_info *pbm = dev_id; | |
617 | struct pci_controller_info *p = pbm->parent; | |
618 | unsigned long afsr_reg, afar_reg; | |
619 | unsigned long afsr, afar, error_bits; | |
620 | int is_pbm_a, reported; | |
621 | ||
622 | is_pbm_a = (pbm == &pbm->parent->pbm_A); | |
623 | if (is_pbm_a) { | |
624 | afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A; | |
625 | afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A; | |
626 | } else { | |
627 | afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B; | |
628 | afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B; | |
629 | } | |
630 | ||
631 | /* Latch error status. */ | |
632 | afar = psycho_read(afar_reg); | |
633 | afsr = psycho_read(afsr_reg); | |
634 | ||
635 | /* Clear primary/secondary error status bits. */ | |
636 | error_bits = afsr & | |
637 | (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA | | |
638 | PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR | | |
639 | PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA | | |
640 | PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR); | |
641 | if (!error_bits) | |
642 | return psycho_pcierr_intr_other(pbm, is_pbm_a); | |
643 | psycho_write(afsr_reg, error_bits); | |
644 | ||
645 | /* Log the error. */ | |
6c108f12 DM |
646 | printk("%s: PCI Error, primary error type[%s]\n", |
647 | pbm->name, | |
1da177e4 LT |
648 | (((error_bits & PSYCHO_PCIAFSR_PMA) ? |
649 | "Master Abort" : | |
650 | ((error_bits & PSYCHO_PCIAFSR_PTA) ? | |
651 | "Target Abort" : | |
652 | ((error_bits & PSYCHO_PCIAFSR_PRTRY) ? | |
653 | "Excessive Retries" : | |
654 | ((error_bits & PSYCHO_PCIAFSR_PPERR) ? | |
655 | "Parity Error" : "???")))))); | |
6c108f12 DM |
656 | printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n", |
657 | pbm->name, | |
1da177e4 LT |
658 | (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL, |
659 | (afsr & PSYCHO_PCIAFSR_MID) >> 25UL, | |
660 | (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0); | |
6c108f12 DM |
661 | printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar); |
662 | printk("%s: PCI Secondary errors [", pbm->name); | |
1da177e4 LT |
663 | reported = 0; |
664 | if (afsr & PSYCHO_PCIAFSR_SMA) { | |
665 | reported++; | |
666 | printk("(Master Abort)"); | |
667 | } | |
668 | if (afsr & PSYCHO_PCIAFSR_STA) { | |
669 | reported++; | |
670 | printk("(Target Abort)"); | |
671 | } | |
672 | if (afsr & PSYCHO_PCIAFSR_SRTRY) { | |
673 | reported++; | |
674 | printk("(Excessive Retries)"); | |
675 | } | |
676 | if (afsr & PSYCHO_PCIAFSR_SPERR) { | |
677 | reported++; | |
678 | printk("(Parity Error)"); | |
679 | } | |
680 | if (!reported) | |
681 | printk("(none)"); | |
682 | printk("]\n"); | |
683 | ||
684 | /* For the error types shown, scan PBM's PCI bus for devices | |
685 | * which have logged that error type. | |
686 | */ | |
687 | ||
688 | /* If we see a Target Abort, this could be the result of an | |
689 | * IOMMU translation error of some sort. It is extremely | |
690 | * useful to log this information as usually it indicates | |
691 | * a bug in the IOMMU support code or a PCI device driver. | |
692 | */ | |
693 | if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) { | |
34768bc8 | 694 | psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR); |
6c108f12 | 695 | pci_scan_for_target_abort(pbm, pbm->pci_bus); |
1da177e4 LT |
696 | } |
697 | if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA)) | |
6c108f12 | 698 | pci_scan_for_master_abort(pbm, pbm->pci_bus); |
1da177e4 LT |
699 | |
700 | /* For excessive retries, PSYCHO/PBM will abort the device | |
701 | * and there is no way to specifically check for excessive | |
702 | * retries in the config space status registers. So what | |
703 | * we hope is that we'll catch it via the master/target | |
704 | * abort events. | |
705 | */ | |
706 | ||
707 | if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR)) | |
6c108f12 | 708 | pci_scan_for_parity_error(pbm, pbm->pci_bus); |
1da177e4 LT |
709 | |
710 | return IRQ_HANDLED; | |
711 | } | |
712 | ||
713 | /* XXX What about PowerFail/PowerManagement??? -DaveM */ | |
714 | #define PSYCHO_ECC_CTRL 0x0020 | |
715 | #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ | |
716 | #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ | |
717 | #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ | |
34768bc8 | 718 | static void psycho_register_error_handlers(struct pci_pbm_info *pbm) |
1da177e4 | 719 | { |
2b1e5978 | 720 | struct of_device *op = of_find_device_by_node(pbm->prom_node); |
34768bc8 | 721 | unsigned long base = pbm->controller_regs; |
1da177e4 | 722 | u64 tmp; |
af80318e | 723 | int err; |
1da177e4 | 724 | |
2b1e5978 DM |
725 | if (!op) |
726 | return; | |
1da177e4 | 727 | |
2b1e5978 | 728 | /* Psycho interrupt property order is: |
34768bc8 | 729 | * 0: PCIERR INO for this PBM |
2b1e5978 DM |
730 | * 1: UE ERR |
731 | * 2: CE ERR | |
732 | * 3: POWER FAIL | |
733 | * 4: SPARE HARDWARE | |
34768bc8 | 734 | * 5: POWER MANAGEMENT |
2b1e5978 | 735 | */ |
1da177e4 | 736 | |
2b1e5978 DM |
737 | if (op->num_irqs < 6) |
738 | return; | |
1da177e4 | 739 | |
af80318e DM |
740 | /* We really mean to ignore the return result here. Two |
741 | * PCI controller share the same interrupt numbers and | |
742 | * drive the same front-end hardware. Whichever of the | |
743 | * two get in here first will register the IRQ handler | |
744 | * the second will just error out since we do not pass in | |
745 | * IRQF_SHARED. | |
746 | */ | |
747 | err = request_irq(op->irqs[1], psycho_ue_intr, 0, | |
748 | "PSYCHO_UE", pbm); | |
749 | err = request_irq(op->irqs[2], psycho_ce_intr, 0, | |
750 | "PSYCHO_CE", pbm); | |
751 | ||
752 | /* This one, however, ought not to fail. We can just warn | |
753 | * about it since the system can still operate properly even | |
754 | * if this fails. | |
755 | */ | |
756 | err = request_irq(op->irqs[0], psycho_pcierr_intr, 0, | |
757 | "PSYCHO_PCIERR", pbm); | |
758 | if (err) | |
759 | printk(KERN_WARNING "%s: Could not register PCIERR, " | |
760 | "err=%d\n", pbm->name, err); | |
1da177e4 LT |
761 | |
762 | /* Enable UE and CE interrupts for controller. */ | |
763 | psycho_write(base + PSYCHO_ECC_CTRL, | |
764 | (PSYCHO_ECCCTRL_EE | | |
765 | PSYCHO_ECCCTRL_UE | | |
766 | PSYCHO_ECCCTRL_CE)); | |
767 | ||
768 | /* Enable PCI Error interrupts and clear error | |
769 | * bits for each PBM. | |
770 | */ | |
771 | tmp = psycho_read(base + PSYCHO_PCIA_CTRL); | |
772 | tmp |= (PSYCHO_PCICTRL_SERR | | |
773 | PSYCHO_PCICTRL_SBH_ERR | | |
774 | PSYCHO_PCICTRL_EEN); | |
775 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); | |
776 | psycho_write(base + PSYCHO_PCIA_CTRL, tmp); | |
777 | ||
778 | tmp = psycho_read(base + PSYCHO_PCIB_CTRL); | |
779 | tmp |= (PSYCHO_PCICTRL_SERR | | |
780 | PSYCHO_PCICTRL_SBH_ERR | | |
781 | PSYCHO_PCICTRL_EEN); | |
782 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); | |
783 | psycho_write(base + PSYCHO_PCIB_CTRL, tmp); | |
784 | } | |
785 | ||
786 | /* PSYCHO boot time probing and initialization. */ | |
085ae41f | 787 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
1da177e4 LT |
788 | { |
789 | u8 *addr; | |
790 | ||
791 | /* Set cache-line size to 64 bytes, this is actually | |
792 | * a nop but I do it for completeness. | |
793 | */ | |
794 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
795 | 0, PCI_CACHE_LINE_SIZE); | |
796 | pci_config_write8(addr, 64 / sizeof(u32)); | |
797 | ||
798 | /* Set PBM latency timer to 64 PCI clocks. */ | |
799 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
800 | 0, PCI_LATENCY_TIMER); | |
801 | pci_config_write8(addr, 64); | |
802 | } | |
803 | ||
34768bc8 | 804 | static void psycho_scan_bus(struct pci_pbm_info *pbm) |
1da177e4 | 805 | { |
34768bc8 DM |
806 | pbm_config_busmastering(pbm); |
807 | pbm->is_66mhz_capable = 0; | |
a2fb23af | 808 | pbm->pci_bus = pci_scan_one_pbm(pbm); |
1da177e4 LT |
809 | |
810 | /* After the PCI bus scan is complete, we can register | |
811 | * the error interrupt handlers. | |
812 | */ | |
34768bc8 | 813 | psycho_register_error_handlers(pbm); |
1da177e4 LT |
814 | } |
815 | ||
ad7ad57c | 816 | static int psycho_iommu_init(struct pci_pbm_info *pbm) |
1da177e4 | 817 | { |
28113a99 | 818 | struct iommu *iommu = pbm->iommu; |
51e85136 | 819 | unsigned long i; |
1da177e4 | 820 | u64 control; |
ad7ad57c | 821 | int err; |
1da177e4 | 822 | |
1da177e4 | 823 | /* Register addresses. */ |
28113a99 DM |
824 | iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL; |
825 | iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE; | |
826 | iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH; | |
ad7ad57c DM |
827 | iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL); |
828 | ||
1da177e4 LT |
829 | /* PSYCHO's IOMMU lacks ctx flushing. */ |
830 | iommu->iommu_ctxflush = 0; | |
831 | ||
832 | /* We use the main control register of PSYCHO as the write | |
833 | * completion register. | |
834 | */ | |
28113a99 | 835 | iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL; |
1da177e4 LT |
836 | |
837 | /* | |
838 | * Invalidate TLB Entries. | |
839 | */ | |
28113a99 | 840 | control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL); |
1da177e4 | 841 | control |= PSYCHO_IOMMU_CTRL_DENAB; |
28113a99 | 842 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control); |
1da177e4 | 843 | for(i = 0; i < 16; i++) { |
28113a99 DM |
844 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0); |
845 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0); | |
1da177e4 LT |
846 | } |
847 | ||
848 | /* Leave diag mode enabled for full-flushing done | |
849 | * in pci_iommu.c | |
850 | */ | |
ad7ad57c DM |
851 | err = iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff); |
852 | if (err) | |
853 | return err; | |
1da177e4 | 854 | |
28113a99 | 855 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE, |
51e85136 | 856 | __pa(iommu->page_table)); |
1da177e4 | 857 | |
28113a99 | 858 | control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL); |
1da177e4 LT |
859 | control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); |
860 | control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB); | |
28113a99 | 861 | psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control); |
1da177e4 LT |
862 | |
863 | /* If necessary, hook us up for starfire IRQ translations. */ | |
51e85136 | 864 | if (this_is_starfire) |
28113a99 | 865 | starfire_hookup(pbm->portid); |
ad7ad57c DM |
866 | |
867 | return 0; | |
1da177e4 LT |
868 | } |
869 | ||
870 | #define PSYCHO_IRQ_RETRY 0x1a00UL | |
871 | #define PSYCHO_PCIA_DIAG 0x2020UL | |
872 | #define PSYCHO_PCIB_DIAG 0x4020UL | |
873 | #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ | |
874 | #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ | |
875 | #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ | |
876 | #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ | |
877 | #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ | |
878 | #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ | |
879 | #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ | |
880 | #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ | |
881 | ||
28113a99 | 882 | static void psycho_controller_hwinit(struct pci_pbm_info *pbm) |
1da177e4 LT |
883 | { |
884 | u64 tmp; | |
885 | ||
28113a99 | 886 | psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5); |
1da177e4 LT |
887 | |
888 | /* Enable arbiter for all PCI slots. */ | |
28113a99 | 889 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL); |
1da177e4 | 890 | tmp |= PSYCHO_PCICTRL_AEN; |
28113a99 | 891 | psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp); |
1da177e4 | 892 | |
28113a99 | 893 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL); |
1da177e4 | 894 | tmp |= PSYCHO_PCICTRL_AEN; |
28113a99 | 895 | psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp); |
1da177e4 LT |
896 | |
897 | /* Disable DMA write / PIO read synchronization on | |
898 | * both PCI bus segments. | |
899 | * [ U2P Erratum 1243770, STP2223BGA data sheet ] | |
900 | */ | |
28113a99 | 901 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG); |
1da177e4 | 902 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
28113a99 | 903 | psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp); |
1da177e4 | 904 | |
28113a99 | 905 | tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG); |
1da177e4 | 906 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
28113a99 | 907 | psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp); |
1da177e4 LT |
908 | } |
909 | ||
28113a99 | 910 | static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, |
1da177e4 LT |
911 | int is_pbm_a) |
912 | { | |
913 | unsigned long base = pbm->controller_regs; | |
914 | u64 control; | |
915 | ||
916 | if (is_pbm_a) { | |
917 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; | |
918 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; | |
919 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; | |
920 | } else { | |
921 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; | |
922 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; | |
923 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; | |
924 | } | |
925 | /* PSYCHO's streaming buffer lacks ctx flushing. */ | |
926 | pbm->stc.strbuf_ctxflush = 0; | |
927 | pbm->stc.strbuf_ctxmatch_base = 0; | |
928 | ||
929 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) | |
930 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) | |
931 | + 63UL) | |
932 | & ~63UL); | |
933 | pbm->stc.strbuf_flushflag_pa = (unsigned long) | |
934 | __pa(pbm->stc.strbuf_flushflag); | |
935 | ||
936 | /* Enable the streaming buffer. We have to be careful | |
937 | * just in case OBP left it with LRU locking enabled. | |
938 | * | |
939 | * It is possible to control if PBM will be rerun on | |
940 | * line misses. Currently I just retain whatever setting | |
941 | * OBP left us with. All checks so far show it having | |
942 | * a value of zero. | |
943 | */ | |
944 | #undef PSYCHO_STRBUF_RERUN_ENABLE | |
945 | #undef PSYCHO_STRBUF_RERUN_DISABLE | |
946 | control = psycho_read(pbm->stc.strbuf_control); | |
947 | control |= PSYCHO_STRBUF_CTRL_ENAB; | |
948 | control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); | |
949 | #ifdef PSYCHO_STRBUF_RERUN_ENABLE | |
950 | control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); | |
951 | #else | |
952 | #ifdef PSYCHO_STRBUF_RERUN_DISABLE | |
953 | control |= PSYCHO_STRBUF_CTRL_RRDIS; | |
954 | #endif | |
955 | #endif | |
956 | psycho_write(pbm->stc.strbuf_control, control); | |
957 | ||
958 | pbm->stc.strbuf_enabled = 1; | |
959 | } | |
960 | ||
961 | #define PSYCHO_IOSPACE_A 0x002000000UL | |
962 | #define PSYCHO_IOSPACE_B 0x002010000UL | |
963 | #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL | |
964 | #define PSYCHO_MEMSPACE_A 0x100000000UL | |
965 | #define PSYCHO_MEMSPACE_B 0x180000000UL | |
966 | #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL | |
967 | ||
968 | static void psycho_pbm_init(struct pci_controller_info *p, | |
e87dc350 | 969 | struct device_node *dp, int is_pbm_a) |
1da177e4 | 970 | { |
e87dc350 | 971 | struct property *prop; |
1da177e4 | 972 | struct pci_pbm_info *pbm; |
1da177e4 | 973 | |
0bba2dd8 | 974 | if (is_pbm_a) |
1da177e4 | 975 | pbm = &p->pbm_A; |
0bba2dd8 | 976 | else |
1da177e4 | 977 | pbm = &p->pbm_B; |
1da177e4 | 978 | |
34768bc8 DM |
979 | pbm->next = pci_pbm_root; |
980 | pci_pbm_root = pbm; | |
981 | ||
982 | pbm->scan_bus = psycho_scan_bus; | |
ca3dd88e DM |
983 | pbm->pci_ops = &sun4u_pci_ops; |
984 | pbm->config_space_reg_bits = 8; | |
34768bc8 | 985 | |
6c108f12 DM |
986 | pbm->index = pci_num_pbms++; |
987 | ||
1da177e4 | 988 | pbm->chip_type = PBM_CHIP_TYPE_PSYCHO; |
e87dc350 DM |
989 | pbm->chip_version = 0; |
990 | prop = of_find_property(dp, "version#", NULL); | |
991 | if (prop) | |
992 | pbm->chip_version = *(int *) prop->value; | |
993 | pbm->chip_revision = 0; | |
994 | prop = of_find_property(dp, "module-revision#", NULL); | |
995 | if (prop) | |
996 | pbm->chip_revision = *(int *) prop->value; | |
1da177e4 | 997 | |
1da177e4 | 998 | pbm->parent = p; |
e87dc350 DM |
999 | pbm->prom_node = dp; |
1000 | pbm->name = dp->full_name; | |
1001 | ||
1002 | printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n", | |
1003 | pbm->name, | |
1004 | pbm->chip_version, pbm->chip_revision); | |
1005 | ||
0f3e2504 DM |
1006 | pci_determine_mem_io_space(pbm); |
1007 | ||
cfa0652c | 1008 | pci_get_pbm_props(pbm); |
1da177e4 | 1009 | |
28113a99 | 1010 | psycho_pbm_strbuf_init(pbm, is_pbm_a); |
1da177e4 LT |
1011 | } |
1012 | ||
1013 | #define PSYCHO_CONFIGSPACE 0x001000000UL | |
1014 | ||
e87dc350 | 1015 | void psycho_init(struct device_node *dp, char *model_name) |
1da177e4 | 1016 | { |
e87dc350 | 1017 | struct linux_prom64_registers *pr_regs; |
1da177e4 | 1018 | struct pci_controller_info *p; |
34768bc8 | 1019 | struct pci_pbm_info *pbm; |
16ce82d8 | 1020 | struct iommu *iommu; |
e87dc350 | 1021 | struct property *prop; |
1da177e4 | 1022 | u32 upa_portid; |
e87dc350 | 1023 | int is_pbm_a; |
1da177e4 | 1024 | |
e87dc350 DM |
1025 | upa_portid = 0xff; |
1026 | prop = of_find_property(dp, "upa-portid", NULL); | |
1027 | if (prop) | |
1028 | upa_portid = *(u32 *) prop->value; | |
1da177e4 | 1029 | |
34768bc8 DM |
1030 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { |
1031 | struct pci_controller_info *p = pbm->parent; | |
1032 | ||
1da177e4 | 1033 | if (p->pbm_A.portid == upa_portid) { |
e87dc350 DM |
1034 | is_pbm_a = (p->pbm_A.prom_node == NULL); |
1035 | psycho_pbm_init(p, dp, is_pbm_a); | |
1da177e4 LT |
1036 | return; |
1037 | } | |
1038 | } | |
1039 | ||
9132983a | 1040 | p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); |
ad7ad57c DM |
1041 | if (!p) |
1042 | goto fatal_memory_error; | |
16ce82d8 | 1043 | iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); |
ad7ad57c DM |
1044 | if (!iommu) |
1045 | goto fatal_memory_error; | |
1046 | ||
1da177e4 LT |
1047 | p->pbm_A.iommu = p->pbm_B.iommu = iommu; |
1048 | ||
1da177e4 LT |
1049 | p->pbm_A.portid = upa_portid; |
1050 | p->pbm_B.portid = upa_portid; | |
1da177e4 | 1051 | |
e87dc350 DM |
1052 | prop = of_find_property(dp, "reg", NULL); |
1053 | pr_regs = prop->value; | |
1da177e4 LT |
1054 | |
1055 | p->pbm_A.controller_regs = pr_regs[2].phys_addr; | |
1056 | p->pbm_B.controller_regs = pr_regs[2].phys_addr; | |
1da177e4 LT |
1057 | |
1058 | p->pbm_A.config_space = p->pbm_B.config_space = | |
1059 | (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); | |
1da177e4 | 1060 | |
28113a99 | 1061 | psycho_controller_hwinit(&p->pbm_A); |
1da177e4 | 1062 | |
ad7ad57c DM |
1063 | if (psycho_iommu_init(&p->pbm_A)) |
1064 | goto fatal_memory_error; | |
1da177e4 LT |
1065 | |
1066 | is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); | |
e87dc350 | 1067 | psycho_pbm_init(p, dp, is_pbm_a); |
ad7ad57c DM |
1068 | return; |
1069 | ||
1070 | fatal_memory_error: | |
1071 | prom_printf("PSYCHO: Fatal memory allocation error.\n"); | |
1072 | prom_halt(); | |
1da177e4 | 1073 | } |