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sparc64: Get rid of pci_controller_info.
[deliverable/linux.git] / arch / sparc64 / kernel / pci_psycho.c
CommitLineData
9fd8b647 1/* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
764f2579 14#include <linux/of_device.h>
1da177e4 15
1da177e4
LT		 16#include <asm/iommu.h>
17#include <asm/irq.h>
18#include <asm/starfire.h>
e87dc350 19#include <asm/prom.h>
1da177e4
LT		 20
21#include "pci_impl.h"
22#include "iommu_common.h"
23
b20bfe41
DM		 24#define DRIVER_NAME "psycho"
25#define PFX DRIVER_NAME ": "
26
1da177e4
LT		 27/* All PSYCHO registers are 64-bits. The following accessor
28 * routines are how they are accessed. The REG parameter
29 * is a physical address.
30 */
31#define psycho_read(__reg) \
32({ u64 __ret; \
33 __asm__ __volatile__("ldxa [%1] %2, %0" \
34 : "=r" (__ret) \
35 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
36 : "memory"); \
37 __ret; \
38})
39#define psycho_write(__reg, __val) \
40 __asm__ __volatile__("stxa %0, [%1] %2" \
41 : /* no outputs */ \
42 : "r" (__val), "r" (__reg), \
43 "i" (ASI_PHYS_BYPASS_EC_E) \
44 : "memory")
45
46/* Misc. PSYCHO PCI controller register offsets and definitions. */
47#define PSYCHO_CONTROL 0x0010UL
48#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
49#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
50#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
51#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
52#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
53#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
54#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
55#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
56#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
57#define PSYCHO_PCIA_CTRL 0x2000UL
58#define PSYCHO_PCIB_CTRL 0x4000UL
59#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
60#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
61#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
62#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
63#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
64#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
65#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
66#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
67#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
68#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
69#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
70#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
71
72/* U2P Programmer's Manual, page 13-55, configuration space
73 * address format:
74 *
75 * 32 24 23 16 15 11 10 8 7 2 1 0
76 * ---------------------------------------------------------
77 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
78 * ---------------------------------------------------------
79 */
80#define PSYCHO_CONFIG_BASE(PBM) \
81 ((PBM)->config_space | (1UL << 24))
82#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
83 (((unsigned long)(BUS) << 16) | \
84 ((unsigned long)(DEVFN) << 8) | \
85 ((unsigned long)(REG)))
86
87static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
88 unsigned char bus,
89 unsigned int devfn,
90 int where)
91{
92 if (!pbm)
93 return NULL;
94 return (void *)
95 (PSYCHO_CONFIG_BASE(pbm) |
96 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
97}
98
1da177e4
LT		 99/* PSYCHO error handling support. */
100enum psycho_error_type {
101 UE_ERR, CE_ERR, PCI_ERR
102};
103
104/* Helper function of IOMMU error checking, which checks out
105 * the state of the streaming buffers. The IOMMU lock is
106 * held when this is called.
107 *
108 * For the PCI error case we know which PBM (and thus which
109 * streaming buffer) caused the error, but for the uncorrectable
110 * error case we do not. So we always check both streaming caches.
111 */
112#define PSYCHO_STRBUF_CONTROL_A 0x2800UL
113#define PSYCHO_STRBUF_CONTROL_B 0x4800UL
114#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
115#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
116#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
117#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
118#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
119#define PSYCHO_STRBUF_FLUSH_A 0x2808UL
120#define PSYCHO_STRBUF_FLUSH_B 0x4808UL
121#define PSYCHO_STRBUF_FSYNC_A 0x2810UL
122#define PSYCHO_STRBUF_FSYNC_B 0x4810UL
123#define PSYCHO_STC_DATA_A 0xb000UL
124#define PSYCHO_STC_DATA_B 0xc000UL
125#define PSYCHO_STC_ERR_A 0xb400UL
126#define PSYCHO_STC_ERR_B 0xc400UL
127#define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
128#define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
129#define PSYCHO_STC_TAG_A 0xb800UL
130#define PSYCHO_STC_TAG_B 0xc800UL
131#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
132#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
133#define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
134#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
135#define PSYCHO_STC_LINE_A 0xb900UL
136#define PSYCHO_STC_LINE_B 0xc900UL
137#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
138#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
139#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
140#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
141#define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
142#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
143
144static DEFINE_SPINLOCK(stc_buf_lock);
145static unsigned long stc_error_buf[128];
146static unsigned long stc_tag_buf[16];
147static unsigned long stc_line_buf[16];
148
d3ae4b5b 149static void psycho_check_stc_error(struct pci_pbm_info *pbm)
1da177e4 150{
16ce82d8 151 struct strbuf *strbuf = &pbm->stc;
1da177e4
LT		 152 unsigned long err_base, tag_base, line_base;
153 u64 control;
154 int i;
155
d3ae4b5b
DM		 156 err_base = strbuf->strbuf_err_stat;
157 tag_base = strbuf->strbuf_tag_diag;
158 line_base = strbuf->strbuf_line_diag;
1da177e4
LT		 159
160 spin_lock(&stc_buf_lock);
161
162 /* This is __REALLY__ dangerous. When we put the
163 * streaming buffer into diagnostic mode to probe
164 * it's tags and error status, we _must_ clear all
165 * of the line tag valid bits before re-enabling
166 * the streaming buffer. If any dirty data lives
167 * in the STC when we do this, we will end up
168 * invalidating it before it has a chance to reach
169 * main memory.
170 */
171 control = psycho_read(strbuf->strbuf_control);
172 psycho_write(strbuf->strbuf_control,
173 (control | PSYCHO_STRBUF_CTRL_DENAB));
174 for (i = 0; i < 128; i++) {
175 unsigned long val;
176
177 val = psycho_read(err_base + (i * 8UL));
178 psycho_write(err_base + (i * 8UL), 0UL);
179 stc_error_buf[i] = val;
180 }
181 for (i = 0; i < 16; i++) {
182 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
183 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
184 psycho_write(tag_base + (i * 8UL), 0UL);
185 psycho_write(line_base + (i * 8UL), 0UL);
186 }
187
188 /* OK, state is logged, exit diagnostic mode. */
189 psycho_write(strbuf->strbuf_control, control);
190
191 for (i = 0; i < 16; i++) {
192 int j, saw_error, first, last;
193
194 saw_error = 0;
195 first = i * 8;
196 last = first + 8;
197 for (j = first; j < last; j++) {
198 unsigned long errval = stc_error_buf[j];
199 if (errval != 0) {
200 saw_error++;
6c108f12
DM		 201 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
202 pbm->name,
1da177e4
LT		 203 j,
204 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
205 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
206 }
207 }
208 if (saw_error != 0) {
209 unsigned long tagval = stc_tag_buf[i];
210 unsigned long lineval = stc_line_buf[i];
6c108f12
DM		 211 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
212 pbm->name,
1da177e4
LT		 213 i,
214 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
215 (tagval & PSYCHO_STCTAG_VPN),
216 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
217 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
6c108f12 218 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
1da177e4 219 "V(%d)FOFN(%d)]\n",
6c108f12 220 pbm->name,
1da177e4
LT		 221 i,
222 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
223 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
224 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
225 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
226 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
227 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
228 }
229 }
230
231 spin_unlock(&stc_buf_lock);
232}
233
1da177e4
LT		 234/* When an Uncorrectable Error or a PCI Error happens, we
235 * interrogate the IOMMU state to see if it is the cause.
236 */
237#define PSYCHO_IOMMU_CONTROL 0x0200UL
238#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
239#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
240#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
241#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
242#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
243#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
244#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
245#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
246#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
247#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
248#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
249#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
250#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
251#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
252#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
253#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
254#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
255#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
256#define PSYCHO_IOMMU_TSBBASE 0x0208UL
257#define PSYCHO_IOMMU_FLUSH 0x0210UL
258#define PSYCHO_IOMMU_TAG 0xa580UL
259#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
260#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
261#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
262#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
263#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
264#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
265#define PSYCHO_IOMMU_DATA 0xa600UL
266#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
267#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
268#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
34768bc8 269static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
1da177e4
LT		 270 unsigned long afsr,
271 unsigned long afar,
272 enum psycho_error_type type)
273{
34768bc8 274 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 275 unsigned long iommu_tag[16];
276 unsigned long iommu_data[16];
277 unsigned long flags;
278 u64 control;
279 int i;
280
281 spin_lock_irqsave(&iommu->lock, flags);
282 control = psycho_read(iommu->iommu_control);
283 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
284 char *type_string;
285
286 /* Clear the error encountered bit. */
287 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
288 psycho_write(iommu->iommu_control, control);
289
290 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
291 case 0:
292 type_string = "Protection Error";
293 break;
294 case 1:
295 type_string = "Invalid Error";
296 break;
297 case 2:
298 type_string = "TimeOut Error";
299 break;
300 case 3:
301 default:
302 type_string = "ECC Error";
303 break;
304 };
6c108f12
DM		 305 printk("%s: IOMMU Error, type[%s]\n",
306 pbm->name, type_string);
1da177e4
LT		 307
308 /* Put the IOMMU into diagnostic mode and probe
309 * it's TLB for entries with error status.
310 *
311 * It is very possible for another DVMA to occur
312 * while we do this probe, and corrupt the system
313 * further. But we are so screwed at this point
314 * that we are likely to crash hard anyways, so
315 * get as much diagnostic information to the
316 * console as we can.
317 */
318 psycho_write(iommu->iommu_control,
319 control | PSYCHO_IOMMU_CTRL_DENAB);
320 for (i = 0; i < 16; i++) {
34768bc8 321 unsigned long base = pbm->controller_regs;
1da177e4
LT		 322
323 iommu_tag[i] =
324 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
325 iommu_data[i] =
326 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
327
328 /* Now clear out the entry. */
329 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
330 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
331 }
332
333 /* Leave diagnostic mode. */
334 psycho_write(iommu->iommu_control, control);
335
336 for (i = 0; i < 16; i++) {
337 unsigned long tag, data;
338
339 tag = iommu_tag[i];
340 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
341 continue;
342
343 data = iommu_data[i];
344 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
345 case 0:
346 type_string = "Protection Error";
347 break;
348 case 1:
349 type_string = "Invalid Error";
350 break;
351 case 2:
352 type_string = "TimeOut Error";
353 break;
354 case 3:
355 default:
356 type_string = "ECC Error";
357 break;
358 };
6c108f12
DM		 359 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
360 pbm->name, i, type_string,
1da177e4
LT		 361 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
362 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
363 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
364 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
6c108f12
DM		 365 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
366 pbm->name, i,
1da177e4
LT		 367 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
368 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
369 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
370 }
371 }
d3ae4b5b 372 psycho_check_stc_error(pbm);
1da177e4
LT		 373 spin_unlock_irqrestore(&iommu->lock, flags);
374}
375
376/* Uncorrectable Errors. Cause of the error and the address are
377 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
378 * relating to UPA interface transactions.
379 */
380#define PSYCHO_UE_AFSR 0x0030UL
381#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
382#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
383#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
384#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
385#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
386#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
387#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
388#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
389#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
390#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
391#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
392#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
393#define PSYCHO_UE_AFAR 0x0038UL
394
6d24c8dc 395static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
1da177e4 396{
34768bc8 397 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 398 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
399 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
1da177e4
LT		 400 unsigned long afsr, afar, error_bits;
401 int reported;
402
403 /* Latch uncorrectable error status. */
404 afar = psycho_read(afar_reg);
405 afsr = psycho_read(afsr_reg);
406
407 /* Clear the primary/secondary error status bits. */
408 error_bits = afsr &
409 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
410 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
411 if (!error_bits)
412 return IRQ_NONE;
413 psycho_write(afsr_reg, error_bits);
414
415 /* Log the error. */
6c108f12
DM		 416 printk("%s: Uncorrectable Error, primary error type[%s]\n",
417 pbm->name,
1da177e4
LT		 418 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
419 "PIO" :
420 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
421 "DMA Read" :
422 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
423 "DMA Write" : "???")))));
6c108f12
DM		 424 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
425 pbm->name,
1da177e4
LT		 426 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
427 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
428 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
429 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 430 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
431 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 432 reported = 0;
433 if (afsr & PSYCHO_UEAFSR_SPIO) {
434 reported++;
435 printk("(PIO)");
436 }
437 if (afsr & PSYCHO_UEAFSR_SDRD) {
438 reported++;
439 printk("(DMA Read)");
440 }
441 if (afsr & PSYCHO_UEAFSR_SDWR) {
442 reported++;
443 printk("(DMA Write)");
444 }
445 if (!reported)
446 printk("(none)");
447 printk("]\n");
448
34768bc8 449 /* Interrogate both IOMMUs for error status. */
d3ae4b5b
DM		 450 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
451 if (pbm->sibling)
452 psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
1da177e4
LT		 453
454 return IRQ_HANDLED;
455}
456
457/* Correctable Errors. */
458#define PSYCHO_CE_AFSR 0x0040UL
459#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
460#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
461#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
462#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
463#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
464#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
465#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
466#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
467#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
468#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
469#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
470#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
471#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
472#define PSYCHO_CE_AFAR 0x0040UL
473
6d24c8dc 474static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
1da177e4 475{
34768bc8 476 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 477 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
478 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
1da177e4
LT		 479 unsigned long afsr, afar, error_bits;
480 int reported;
481
482 /* Latch error status. */
483 afar = psycho_read(afar_reg);
484 afsr = psycho_read(afsr_reg);
485
486 /* Clear primary/secondary error status bits. */
487 error_bits = afsr &
488 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
489 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
490 if (!error_bits)
491 return IRQ_NONE;
492 psycho_write(afsr_reg, error_bits);
493
494 /* Log the error. */
6c108f12
DM		 495 printk("%s: Correctable Error, primary error type[%s]\n",
496 pbm->name,
1da177e4
LT		 497 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
498 "PIO" :
499 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
500 "DMA Read" :
501 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
502 "DMA Write" : "???")))));
503
504 /* XXX Use syndrome and afar to print out module string just like
505 * XXX UDB CE trap handler does... -DaveM
506 */
6c108f12 507 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
1da177e4 508 "UPA_MID[%02lx] was_block(%d)\n",
6c108f12 509 pbm->name,
1da177e4
LT		 510 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
511 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
512 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
513 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
514 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 515 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
516 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 517 reported = 0;
518 if (afsr & PSYCHO_CEAFSR_SPIO) {
519 reported++;
520 printk("(PIO)");
521 }
522 if (afsr & PSYCHO_CEAFSR_SDRD) {
523 reported++;
524 printk("(DMA Read)");
525 }
526 if (afsr & PSYCHO_CEAFSR_SDWR) {
527 reported++;
528 printk("(DMA Write)");
529 }
530 if (!reported)
531 printk("(none)");
532 printk("]\n");
533
534 return IRQ_HANDLED;
535}
536
537/* PCI Errors. They are signalled by the PCI bus module since they
538 * are associated with a specific bus segment.
539 */
540#define PSYCHO_PCI_AFSR_A 0x2010UL
541#define PSYCHO_PCI_AFSR_B 0x4010UL
542#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
543#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
544#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
545#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
546#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
547#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
548#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
549#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
550#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
551#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
552#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
553#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
554#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
555#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
556#define PSYCHO_PCI_AFAR_A 0x2018UL
557#define PSYCHO_PCI_AFAR_B 0x4018UL
558
d3ae4b5b 559static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
1da177e4 560{
d3ae4b5b 561 unsigned long csr, csr_error_bits;
1da177e4
LT		 562 irqreturn_t ret = IRQ_NONE;
563 u16 stat;
564
d3ae4b5b 565 csr = psycho_read(pbm->pci_csr);
1da177e4
LT		 566 csr_error_bits =
567 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
568 if (csr_error_bits) {
569 /* Clear the errors. */
d3ae4b5b 570 psycho_write(pbm->pci_csr, csr);
1da177e4
LT		 571
572 /* Log 'em. */
573 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
574 printk("%s: PCI streaming byte hole error asserted.\n",
575 pbm->name);
576 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
577 printk("%s: PCI SERR signal asserted.\n", pbm->name);
578 ret = IRQ_HANDLED;
579 }
580 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
581 if (stat & (PCI_STATUS_PARITY |
582 PCI_STATUS_SIG_TARGET_ABORT |
583 PCI_STATUS_REC_TARGET_ABORT |
584 PCI_STATUS_REC_MASTER_ABORT |
585 PCI_STATUS_SIG_SYSTEM_ERROR)) {
586 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
587 pbm->name, stat);
588 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
589 ret = IRQ_HANDLED;
590 }
591 return ret;
592}
593
6d24c8dc 594static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 595{
596 struct pci_pbm_info *pbm = dev_id;
1da177e4
LT		 597 unsigned long afsr_reg, afar_reg;
598 unsigned long afsr, afar, error_bits;
d3ae4b5b 599 int reported;
1da177e4 600
d3ae4b5b
DM		 601 afsr_reg = pbm->pci_afsr;
602 afar_reg = pbm->pci_afar;
1da177e4
LT		 603
604 /* Latch error status. */
605 afar = psycho_read(afar_reg);
606 afsr = psycho_read(afsr_reg);
607
608 /* Clear primary/secondary error status bits. */
609 error_bits = afsr &
610 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
611 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
612 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
613 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
614 if (!error_bits)
d3ae4b5b 615 return psycho_pcierr_intr_other(pbm);
1da177e4
LT		 616 psycho_write(afsr_reg, error_bits);
617
618 /* Log the error. */
6c108f12
DM		 619 printk("%s: PCI Error, primary error type[%s]\n",
620 pbm->name,
1da177e4
LT		 621 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
622 "Master Abort" :
623 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
624 "Target Abort" :
625 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
626 "Excessive Retries" :
627 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
628 "Parity Error" : "???"))))));
6c108f12
DM		 629 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
630 pbm->name,
1da177e4
LT		 631 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
632 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
633 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
6c108f12
DM		 634 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
635 printk("%s: PCI Secondary errors [", pbm->name);
1da177e4
LT		 636 reported = 0;
637 if (afsr & PSYCHO_PCIAFSR_SMA) {
638 reported++;
639 printk("(Master Abort)");
640 }
641 if (afsr & PSYCHO_PCIAFSR_STA) {
642 reported++;
643 printk("(Target Abort)");
644 }
645 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
646 reported++;
647 printk("(Excessive Retries)");
648 }
649 if (afsr & PSYCHO_PCIAFSR_SPERR) {
650 reported++;
651 printk("(Parity Error)");
652 }
653 if (!reported)
654 printk("(none)");
655 printk("]\n");
656
657 /* For the error types shown, scan PBM's PCI bus for devices
658 * which have logged that error type.
659 */
660
661 /* If we see a Target Abort, this could be the result of an
662 * IOMMU translation error of some sort. It is extremely
663 * useful to log this information as usually it indicates
664 * a bug in the IOMMU support code or a PCI device driver.
665 */
666 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
34768bc8 667 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
6c108f12 668 pci_scan_for_target_abort(pbm, pbm->pci_bus);
1da177e4
LT		 669 }
670 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
6c108f12 671 pci_scan_for_master_abort(pbm, pbm->pci_bus);
1da177e4
LT		 672
673 /* For excessive retries, PSYCHO/PBM will abort the device
674 * and there is no way to specifically check for excessive
675 * retries in the config space status registers. So what
676 * we hope is that we'll catch it via the master/target
677 * abort events.
678 */
679
680 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
6c108f12 681 pci_scan_for_parity_error(pbm, pbm->pci_bus);
1da177e4
LT		 682
683 return IRQ_HANDLED;
684}
685
686/* XXX What about PowerFail/PowerManagement??? -DaveM */
687#define PSYCHO_ECC_CTRL 0x0020
688#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
689#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
690#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
34768bc8 691static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 692{
2b1e5978 693 struct of_device *op = of_find_device_by_node(pbm->prom_node);
34768bc8 694 unsigned long base = pbm->controller_regs;
1da177e4 695 u64 tmp;
af80318e 696 int err;
1da177e4 697
2b1e5978
DM		 698 if (!op)
699 return;
1da177e4 700
2b1e5978 701 /* Psycho interrupt property order is:
34768bc8 702 * 0: PCIERR INO for this PBM
2b1e5978
DM		 703 * 1: UE ERR
704 * 2: CE ERR
705 * 3: POWER FAIL
706 * 4: SPARE HARDWARE
34768bc8 707 * 5: POWER MANAGEMENT
2b1e5978 708 */
1da177e4 709
2b1e5978
DM		 710 if (op->num_irqs < 6)
711 return;
1da177e4 712
af80318e
DM		 713 /* We really mean to ignore the return result here. Two
714 * PCI controller share the same interrupt numbers and
715 * drive the same front-end hardware. Whichever of the
716 * two get in here first will register the IRQ handler
717 * the second will just error out since we do not pass in
718 * IRQF_SHARED.
719 */
720 err = request_irq(op->irqs[1], psycho_ue_intr, 0,
721 "PSYCHO_UE", pbm);
722 err = request_irq(op->irqs[2], psycho_ce_intr, 0,
723 "PSYCHO_CE", pbm);
724
725 /* This one, however, ought not to fail. We can just warn
726 * about it since the system can still operate properly even
727 * if this fails.
728 */
729 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
730 "PSYCHO_PCIERR", pbm);
731 if (err)
732 printk(KERN_WARNING "%s: Could not register PCIERR, "
733 "err=%d\n", pbm->name, err);
1da177e4
LT		 734
735 /* Enable UE and CE interrupts for controller. */
736 psycho_write(base + PSYCHO_ECC_CTRL,
737 (PSYCHO_ECCCTRL_EE |
738 PSYCHO_ECCCTRL_UE |
739 PSYCHO_ECCCTRL_CE));
740
741 /* Enable PCI Error interrupts and clear error
742 * bits for each PBM.
743 */
744 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
745 tmp |= (PSYCHO_PCICTRL_SERR |
746 PSYCHO_PCICTRL_SBH_ERR |
747 PSYCHO_PCICTRL_EEN);
748 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
749 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
750
751 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
752 tmp |= (PSYCHO_PCICTRL_SERR |
753 PSYCHO_PCICTRL_SBH_ERR |
754 PSYCHO_PCICTRL_EEN);
755 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
756 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
757}
758
759/* PSYCHO boot time probing and initialization. */
085ae41f 760static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 761{
762 u8 *addr;
763
764 /* Set cache-line size to 64 bytes, this is actually
765 * a nop but I do it for completeness.
766 */
767 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
768 0, PCI_CACHE_LINE_SIZE);
769 pci_config_write8(addr, 64 / sizeof(u32));
770
771 /* Set PBM latency timer to 64 PCI clocks. */
772 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
773 0, PCI_LATENCY_TIMER);
774 pci_config_write8(addr, 64);
775}
776
e822358a
DM		 777static void __init psycho_scan_bus(struct pci_pbm_info *pbm,
778 struct device *parent)
1da177e4 779{
34768bc8
DM		 780 pbm_config_busmastering(pbm);
781 pbm->is_66mhz_capable = 0;
e822358a 782 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1da177e4
LT		 783
784 /* After the PCI bus scan is complete, we can register
785 * the error interrupt handlers.
786 */
34768bc8 787 psycho_register_error_handlers(pbm);
1da177e4
LT		 788}
789
ad7ad57c 790static int psycho_iommu_init(struct pci_pbm_info *pbm)
1da177e4 791{
28113a99 792 struct iommu *iommu = pbm->iommu;
51e85136 793 unsigned long i;
1da177e4 794 u64 control;
ad7ad57c 795 int err;
1da177e4 796
1da177e4 797 /* Register addresses. */
28113a99
DM		 798 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
799 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
800 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
ad7ad57c
DM		 801 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
802
1da177e4
LT		 803 /* PSYCHO's IOMMU lacks ctx flushing. */
804 iommu->iommu_ctxflush = 0;
805
806 /* We use the main control register of PSYCHO as the write
807 * completion register.
808 */
28113a99 809 iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL;
1da177e4
LT		 810
811 /*
812 * Invalidate TLB Entries.
813 */
28113a99 814 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
1da177e4 815 control |= PSYCHO_IOMMU_CTRL_DENAB;
28113a99 816 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
b20bfe41 817 for (i = 0; i < 16; i++) {
28113a99
DM		 818 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
819 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1da177e4
LT		 820 }
821
822 /* Leave diag mode enabled for full-flushing done
823 * in pci_iommu.c
824 */
c1b1a5f1
DM		 825 err = iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff,
826 pbm->numa_node);
b20bfe41
DM		 827 if (err) {
828 printk(KERN_ERR PFX "iommu_table_init() fails\n");
ad7ad57c 829 return err;
b20bfe41 830 }
1da177e4 831
28113a99 832 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE,
51e85136 833 __pa(iommu->page_table));
1da177e4 834
28113a99 835 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
1da177e4
LT		 836 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
837 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
28113a99 838 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
1da177e4
LT		 839
840 /* If necessary, hook us up for starfire IRQ translations. */
51e85136 841 if (this_is_starfire)
28113a99 842 starfire_hookup(pbm->portid);
ad7ad57c
DM		 843
844 return 0;
1da177e4
LT		 845}
846
847#define PSYCHO_IRQ_RETRY 0x1a00UL
848#define PSYCHO_PCIA_DIAG 0x2020UL
849#define PSYCHO_PCIB_DIAG 0x4020UL
850#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
851#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
852#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
853#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
854#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
855#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
856#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
857#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
858
28113a99 859static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
1da177e4
LT		 860{
861 u64 tmp;
862
28113a99 863 psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5);
1da177e4
LT		 864
865 /* Enable arbiter for all PCI slots. */
28113a99 866 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL);
1da177e4 867 tmp |= PSYCHO_PCICTRL_AEN;
28113a99 868 psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp);
1da177e4 869
28113a99 870 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL);
1da177e4 871 tmp |= PSYCHO_PCICTRL_AEN;
28113a99 872 psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp);
1da177e4
LT		 873
874 /* Disable DMA write / PIO read synchronization on
875 * both PCI bus segments.
876 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
877 */
28113a99 878 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG);
1da177e4 879 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
28113a99 880 psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp);
1da177e4 881
28113a99 882 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG);
1da177e4 883 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
28113a99 884 psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp);
1da177e4
LT		 885}
886
28113a99 887static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
1da177e4
LT		 888 int is_pbm_a)
889{
890 unsigned long base = pbm->controller_regs;
891 u64 control;
892
893 if (is_pbm_a) {
894 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
895 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
896 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
d3ae4b5b
DM		 897 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
898 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
899 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
1da177e4
LT		 900 } else {
901 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
902 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
903 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
d3ae4b5b
DM		 904 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
905 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
906 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
1da177e4
LT		 907 }
908 /* PSYCHO's streaming buffer lacks ctx flushing. */
909 pbm->stc.strbuf_ctxflush = 0;
910 pbm->stc.strbuf_ctxmatch_base = 0;
911
912 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
913 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
914 + 63UL)
915 & ~63UL);
916 pbm->stc.strbuf_flushflag_pa = (unsigned long)
917 __pa(pbm->stc.strbuf_flushflag);
918
919 /* Enable the streaming buffer. We have to be careful
920 * just in case OBP left it with LRU locking enabled.
921 *
922 * It is possible to control if PBM will be rerun on
923 * line misses. Currently I just retain whatever setting
924 * OBP left us with. All checks so far show it having
925 * a value of zero.
926 */
927#undef PSYCHO_STRBUF_RERUN_ENABLE
928#undef PSYCHO_STRBUF_RERUN_DISABLE
929 control = psycho_read(pbm->stc.strbuf_control);
930 control |= PSYCHO_STRBUF_CTRL_ENAB;
931 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
932#ifdef PSYCHO_STRBUF_RERUN_ENABLE
933 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
934#else
935#ifdef PSYCHO_STRBUF_RERUN_DISABLE
936 control |= PSYCHO_STRBUF_CTRL_RRDIS;
937#endif
938#endif
939 psycho_write(pbm->stc.strbuf_control, control);
940
941 pbm->stc.strbuf_enabled = 1;
942}
943
944#define PSYCHO_IOSPACE_A 0x002000000UL
945#define PSYCHO_IOSPACE_B 0x002010000UL
946#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
947#define PSYCHO_MEMSPACE_A 0x100000000UL
948#define PSYCHO_MEMSPACE_B 0x180000000UL
949#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
950
d3ae4b5b 951static void __init psycho_pbm_init(struct pci_pbm_info *pbm,
e822358a 952 struct of_device *op, int is_pbm_a)
1da177e4 953{
e822358a 954 struct device_node *dp = op->node;
1da177e4 955
34768bc8
DM		 956 pbm->next = pci_pbm_root;
957 pci_pbm_root = pbm;
958
c1b1a5f1
DM		 959 pbm->numa_node = -1;
960
ca3dd88e
DM		 961 pbm->pci_ops = &sun4u_pci_ops;
962 pbm->config_space_reg_bits = 8;
34768bc8 963
6c108f12
DM		 964 pbm->index = pci_num_pbms++;
965
1da177e4 966 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
0f73d1bb
DM		 967 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
968 pbm->chip_revision = of_getintprop_default(dp, "module-revision#", 0);
1da177e4 969
e87dc350
DM		 970 pbm->prom_node = dp;
971 pbm->name = dp->full_name;
972
b20bfe41 973 printk(KERN_INFO "%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
e87dc350
DM		 974 pbm->name,
975 pbm->chip_version, pbm->chip_revision);
976
0f3e2504
DM		 977 pci_determine_mem_io_space(pbm);
978
cfa0652c 979 pci_get_pbm_props(pbm);
1da177e4 980
28113a99 981 psycho_pbm_strbuf_init(pbm, is_pbm_a);
b20bfe41 982
e822358a 983 psycho_scan_bus(pbm, &op->dev);
1da177e4
LT		 984}
985
d3ae4b5b
DM		 986static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid)
987{
988 struct pci_pbm_info *pbm;
989
990 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
991 if (pbm->portid == upa_portid)
992 return pbm;
993 }
994 return NULL;
995}
996
1da177e4
LT		 997#define PSYCHO_CONFIGSPACE 0x001000000UL
998
b20bfe41
DM		 999static int __devinit psycho_probe(struct of_device *op,
1000 const struct of_device_id *match)
1da177e4 1001{
b20bfe41
DM		 1002 const struct linux_prom64_registers *pr_regs;
1003 struct device_node *dp = op->node;
34768bc8 1004 struct pci_pbm_info *pbm;
16ce82d8 1005 struct iommu *iommu;
b20bfe41 1006 int is_pbm_a, err;
1da177e4 1007 u32 upa_portid;
1da177e4 1008
0f73d1bb 1009 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
1da177e4 1010
b20bfe41 1011 err = -ENOMEM;
d3ae4b5b
DM		 1012 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1013 if (!pbm) {
1014 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
d7472c38 1015 goto out_err;
b20bfe41
DM		 1016 }
1017
d3ae4b5b
DM		 1018 pbm->sibling = psycho_find_sibling(upa_portid);
1019 if (pbm->sibling) {
1020 iommu = pbm->sibling->iommu;
1021 } else {
1022 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1023 if (!iommu) {
1024 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
1025 goto out_free_controller;
1026 }
b20bfe41 1027 }
ad7ad57c 1028
d3ae4b5b
DM		 1029 pbm->iommu = iommu;
1030 pbm->portid = upa_portid;
1da177e4 1031
b20bfe41
DM		 1032 pr_regs = of_get_property(dp, "reg", NULL);
1033 err = -ENODEV;
1034 if (!pr_regs) {
1035 printk(KERN_ERR PFX "No reg property.\n");
d7472c38 1036 goto out_free_iommu;
b20bfe41 1037 }
1da177e4 1038
d3ae4b5b
DM		 1039 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1040
1041 pbm->controller_regs = pr_regs[2].phys_addr;
1042 pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1da177e4 1043
d3ae4b5b
DM		 1044 if (is_pbm_a) {
1045 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
1046 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
1047 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL;
1048 } else {
1049 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
1050 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
1051 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL;
1052 }
1da177e4 1053
d3ae4b5b
DM		 1054 psycho_controller_hwinit(pbm);
1055 if (!pbm->sibling) {
1056 err = psycho_iommu_init(pbm);
1057 if (err)
1058 goto out_free_iommu;
1059 }
1da177e4 1060
d3ae4b5b 1061 psycho_pbm_init(pbm, op, is_pbm_a);
1da177e4 1062
d3ae4b5b
DM		 1063 if (pbm->sibling)
1064 pbm->sibling->sibling = pbm;
b20bfe41 1065
d3ae4b5b 1066 dev_set_drvdata(&op->dev, pbm);
ad7ad57c 1067
b20bfe41
DM		 1068 return 0;
1069
d7472c38 1070out_free_iommu:
d3ae4b5b
DM		 1071 if (!pbm->sibling)
1072 kfree(pbm->iommu);
d7472c38
DM		 1073
1074out_free_controller:
d3ae4b5b 1075 kfree(pbm);
d7472c38
DM		 1076
1077out_err:
b20bfe41
DM		 1078 return err;
1079}
1080
fd098316 1081static struct of_device_id __initdata psycho_match[] = {
b20bfe41
DM		 1082 {
1083 .name = "pci",
1084 .compatible = "pci108e,8000",
1085 },
1086 {},
1087};
1088
1089static struct of_platform_driver psycho_driver = {
1090 .name = DRIVER_NAME,
1091 .match_table = psycho_match,
1092 .probe = psycho_probe,
1093};
1094
1095static int __init psycho_init(void)
1096{
1097 return of_register_driver(&psycho_driver, &of_bus_type);
1da177e4 1098}
b20bfe41
DM		 1099
1100subsys_initcall(psycho_init);
Linux kernel - Deliverables
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