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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
[deliverable/linux.git] / arch / sparc64 / kernel / pci_schizo.c
CommitLineData
9fd8b647 1/* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 2001, 2002, 2003, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/interrupt.h>
12
1da177e4
LT		 13#include <asm/iommu.h>
14#include <asm/irq.h>
15#include <asm/upa.h>
bb6743f4 16#include <asm/pstate.h>
e87dc350 17#include <asm/prom.h>
c57c2ffb
DM		 18#include <asm/of_device.h>
19#include <asm/oplib.h>
1da177e4
LT		 20
21#include "pci_impl.h"
22#include "iommu_common.h"
23
24/* All SCHIZO registers are 64-bits. The following accessor
25 * routines are how they are accessed. The REG parameter
26 * is a physical address.
27 */
28#define schizo_read(__reg) \
29({ u64 __ret; \
30 __asm__ __volatile__("ldxa [%1] %2, %0" \
31 : "=r" (__ret) \
32 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
33 : "memory"); \
34 __ret; \
35})
36#define schizo_write(__reg, __val) \
37 __asm__ __volatile__("stxa %0, [%1] %2" \
38 : /* no outputs */ \
39 : "r" (__val), "r" (__reg), \
40 "i" (ASI_PHYS_BYPASS_EC_E) \
41 : "memory")
42
43/* This is a convention that at least Excalibur and Merlin
44 * follow. I suppose the SCHIZO used in Starcat and friends
45 * will do similar.
46 *
47 * The only way I could see this changing is if the newlink
48 * block requires more space in Schizo's address space than
49 * they predicted, thus requiring an address space reorg when
50 * the newer Schizo is taped out.
51 */
52
53/* Streaming buffer control register. */
54#define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
55#define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
56#define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
57#define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
58#define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
59
60/* IOMMU control register. */
61#define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
62#define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
63#define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
64#define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
65#define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
66#define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
67#define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
68#define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
69#define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
70#define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
71#define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
72#define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
73#define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
74#define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
75#define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
76#define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
77#define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
78#define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
79
80/* Schizo config space address format is nearly identical to
81 * that of PSYCHO:
82 *
83 * 32 24 23 16 15 11 10 8 7 2 1 0
84 * ---------------------------------------------------------
85 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
86 * ---------------------------------------------------------
87 */
88#define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
89#define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
90 (((unsigned long)(BUS) << 16) | \
91 ((unsigned long)(DEVFN) << 8) | \
92 ((unsigned long)(REG)))
93
94static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
95 unsigned char bus,
96 unsigned int devfn,
97 int where)
98{
99 if (!pbm)
100 return NULL;
101 bus -= pbm->pci_first_busno;
102 return (void *)
103 (SCHIZO_CONFIG_BASE(pbm) |
104 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
105}
106
107/* Just make sure the bus number is in range. */
108static int schizo_out_of_range(struct pci_pbm_info *pbm,
109 unsigned char bus,
110 unsigned char devfn)
111{
112 if (bus < pbm->pci_first_busno ||
113 bus > pbm->pci_last_busno)
114 return 1;
115 return 0;
116}
117
118/* SCHIZO PCI configuration space accessors. */
119
120static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
121 int where, int size, u32 *value)
122{
123 struct pci_pbm_info *pbm = bus_dev->sysdata;
124 unsigned char bus = bus_dev->number;
125 u32 *addr;
126 u16 tmp16;
127 u8 tmp8;
128
97b3cf05
DM		 129 if (bus_dev == pbm->pci_bus && devfn == 0x00)
130 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
131 size, value);
1da177e4
LT		 132 switch (size) {
133 case 1:
134 *value = 0xff;
135 break;
136 case 2:
137 *value = 0xffff;
138 break;
139 case 4:
140 *value = 0xffffffff;
141 break;
142 }
143
144 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
145 if (!addr)
146 return PCIBIOS_SUCCESSFUL;
147
148 if (schizo_out_of_range(pbm, bus, devfn))
149 return PCIBIOS_SUCCESSFUL;
150 switch (size) {
151 case 1:
152 pci_config_read8((u8 *)addr, &tmp8);
153 *value = tmp8;
154 break;
155
156 case 2:
157 if (where & 0x01) {
158 printk("pci_read_config_word: misaligned reg [%x]\n",
159 where);
160 return PCIBIOS_SUCCESSFUL;
161 }
162 pci_config_read16((u16 *)addr, &tmp16);
163 *value = tmp16;
164 break;
165
166 case 4:
167 if (where & 0x03) {
168 printk("pci_read_config_dword: misaligned reg [%x]\n",
169 where);
170 return PCIBIOS_SUCCESSFUL;
171 }
172 pci_config_read32(addr, value);
173 break;
174 }
175 return PCIBIOS_SUCCESSFUL;
176}
177
178static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
179 int where, int size, u32 value)
180{
181 struct pci_pbm_info *pbm = bus_dev->sysdata;
182 unsigned char bus = bus_dev->number;
183 u32 *addr;
184
97b3cf05
DM		 185 if (bus_dev == pbm->pci_bus && devfn == 0x00)
186 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
187 size, value);
1da177e4
LT		 188 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
189 if (!addr)
190 return PCIBIOS_SUCCESSFUL;
191
192 if (schizo_out_of_range(pbm, bus, devfn))
193 return PCIBIOS_SUCCESSFUL;
194
195 switch (size) {
196 case 1:
197 pci_config_write8((u8 *)addr, value);
198 break;
199
200 case 2:
201 if (where & 0x01) {
202 printk("pci_write_config_word: misaligned reg [%x]\n",
203 where);
204 return PCIBIOS_SUCCESSFUL;
205 }
206 pci_config_write16((u16 *)addr, value);
207 break;
208
209 case 4:
210 if (where & 0x03) {
211 printk("pci_write_config_dword: misaligned reg [%x]\n",
212 where);
213 return PCIBIOS_SUCCESSFUL;
214 }
215
216 pci_config_write32(addr, value);
217 }
218 return PCIBIOS_SUCCESSFUL;
219}
220
221static struct pci_ops schizo_ops = {
222 .read = schizo_read_pci_cfg,
223 .write = schizo_write_pci_cfg,
224};
225
1da177e4
LT		 226/* SCHIZO error handling support. */
227enum schizo_error_type {
228 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
229};
230
231static DEFINE_SPINLOCK(stc_buf_lock);
232static unsigned long stc_error_buf[128];
233static unsigned long stc_tag_buf[16];
234static unsigned long stc_line_buf[16];
235
236#define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
237#define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
238#define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
239#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
240#define SCHIZO_SERR_INO 0x34 /* Safari interface error */
241
1da177e4
LT		 242#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
243#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
244#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
245
246#define SCHIZO_STCERR_WRITE 0x2UL
247#define SCHIZO_STCERR_READ 0x1UL
248
249#define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
250#define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
251#define SCHIZO_STCTAG_VALID 0x8000000000000000UL
252#define SCHIZO_STCTAG_READ 0x4000000000000000UL
253
254#define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
255#define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
256#define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
257#define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
258#define SCHIZO_STCLINE_VALID 0x0000000000600000UL
259#define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
260
261static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
262 enum schizo_error_type type)
263{
16ce82d8 264 struct strbuf *strbuf = &pbm->stc;
1da177e4
LT		 265 unsigned long regbase = pbm->pbm_regs;
266 unsigned long err_base, tag_base, line_base;
267 u64 control;
268 int i;
269
270 err_base = regbase + SCHIZO_STC_ERR;
271 tag_base = regbase + SCHIZO_STC_TAG;
272 line_base = regbase + SCHIZO_STC_LINE;
273
274 spin_lock(&stc_buf_lock);
275
276 /* This is __REALLY__ dangerous. When we put the
277 * streaming buffer into diagnostic mode to probe
278 * it's tags and error status, we _must_ clear all
279 * of the line tag valid bits before re-enabling
280 * the streaming buffer. If any dirty data lives
281 * in the STC when we do this, we will end up
282 * invalidating it before it has a chance to reach
283 * main memory.
284 */
285 control = schizo_read(strbuf->strbuf_control);
286 schizo_write(strbuf->strbuf_control,
287 (control | SCHIZO_STRBUF_CTRL_DENAB));
288 for (i = 0; i < 128; i++) {
289 unsigned long val;
290
291 val = schizo_read(err_base + (i * 8UL));
292 schizo_write(err_base + (i * 8UL), 0UL);
293 stc_error_buf[i] = val;
294 }
295 for (i = 0; i < 16; i++) {
296 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
297 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
298 schizo_write(tag_base + (i * 8UL), 0UL);
299 schizo_write(line_base + (i * 8UL), 0UL);
300 }
301
302 /* OK, state is logged, exit diagnostic mode. */
303 schizo_write(strbuf->strbuf_control, control);
304
305 for (i = 0; i < 16; i++) {
306 int j, saw_error, first, last;
307
308 saw_error = 0;
309 first = i * 8;
310 last = first + 8;
311 for (j = first; j < last; j++) {
312 unsigned long errval = stc_error_buf[j];
313 if (errval != 0) {
314 saw_error++;
315 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
316 pbm->name,
317 j,
318 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
319 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
320 }
321 }
322 if (saw_error != 0) {
323 unsigned long tagval = stc_tag_buf[i];
324 unsigned long lineval = stc_line_buf[i];
325 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
326 pbm->name,
327 i,
328 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
329 (tagval & SCHIZO_STCTAG_VPN),
330 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
331 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
332
333 /* XXX Should spit out per-bank error information... -DaveM */
334 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
335 "V(%d)FOFN(%d)]\n",
336 pbm->name,
337 i,
338 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
339 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
340 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
341 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
342 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
343 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
344 }
345 }
346
347 spin_unlock(&stc_buf_lock);
348}
349
350/* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
351 * controller level errors.
352 */
353
354#define SCHIZO_IOMMU_TAG 0xa580UL
355#define SCHIZO_IOMMU_DATA 0xa600UL
356
357#define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
358#define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
359#define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
360#define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
361#define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
362#define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
363#define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
364
365#define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
366#define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
367#define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
368
369static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
370 enum schizo_error_type type)
371{
16ce82d8 372 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 373 unsigned long iommu_tag[16];
374 unsigned long iommu_data[16];
375 unsigned long flags;
376 u64 control;
377 int i;
378
379 spin_lock_irqsave(&iommu->lock, flags);
380 control = schizo_read(iommu->iommu_control);
381 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
382 unsigned long base;
383 char *type_string;
384
385 /* Clear the error encountered bit. */
386 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
387 schizo_write(iommu->iommu_control, control);
388
389 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
390 case 0:
391 type_string = "Protection Error";
392 break;
393 case 1:
394 type_string = "Invalid Error";
395 break;
396 case 2:
397 type_string = "TimeOut Error";
398 break;
399 case 3:
400 default:
401 type_string = "ECC Error";
402 break;
403 };
404 printk("%s: IOMMU Error, type[%s]\n",
405 pbm->name, type_string);
406
407 /* Put the IOMMU into diagnostic mode and probe
408 * it's TLB for entries with error status.
409 *
410 * It is very possible for another DVMA to occur
411 * while we do this probe, and corrupt the system
412 * further. But we are so screwed at this point
413 * that we are likely to crash hard anyways, so
414 * get as much diagnostic information to the
415 * console as we can.
416 */
417 schizo_write(iommu->iommu_control,
418 control | SCHIZO_IOMMU_CTRL_DENAB);
419
420 base = pbm->pbm_regs;
421
422 for (i = 0; i < 16; i++) {
423 iommu_tag[i] =
424 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
425 iommu_data[i] =
426 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
427
428 /* Now clear out the entry. */
429 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
430 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
431 }
432
433 /* Leave diagnostic mode. */
434 schizo_write(iommu->iommu_control, control);
435
436 for (i = 0; i < 16; i++) {
437 unsigned long tag, data;
438
439 tag = iommu_tag[i];
440 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
441 continue;
442
443 data = iommu_data[i];
444 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
445 case 0:
446 type_string = "Protection Error";
447 break;
448 case 1:
449 type_string = "Invalid Error";
450 break;
451 case 2:
452 type_string = "TimeOut Error";
453 break;
454 case 3:
455 default:
456 type_string = "ECC Error";
457 break;
458 };
459 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
460 "sz(%dK) vpg(%08lx)]\n",
461 pbm->name, i, type_string,
462 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
463 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
464 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
465 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
466 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
467 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
468 pbm->name, i,
469 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
470 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
471 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
472 }
473 }
474 if (pbm->stc.strbuf_enabled)
475 __schizo_check_stc_error_pbm(pbm, type);
476 spin_unlock_irqrestore(&iommu->lock, flags);
477}
478
479static void schizo_check_iommu_error(struct pci_controller_info *p,
480 enum schizo_error_type type)
481{
482 schizo_check_iommu_error_pbm(&p->pbm_A, type);
483 schizo_check_iommu_error_pbm(&p->pbm_B, type);
484}
485
486/* Uncorrectable ECC error status gathering. */
487#define SCHIZO_UE_AFSR 0x10030UL
488#define SCHIZO_UE_AFAR 0x10038UL
489
490#define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
491#define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
492#define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
493#define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
494#define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
495#define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
496#define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
497#define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
498#define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
499#define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
500#define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
501#define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
502#define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
503#define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
504
6d24c8dc 505static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
1da177e4 506{
34768bc8
DM		 507 struct pci_pbm_info *pbm = dev_id;
508 struct pci_controller_info *p = pbm->parent;
509 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
510 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
1da177e4
LT		 511 unsigned long afsr, afar, error_bits;
512 int reported, limit;
513
514 /* Latch uncorrectable error status. */
515 afar = schizo_read(afar_reg);
516
517 /* If either of the error pending bits are set in the
518 * AFSR, the error status is being actively updated by
519 * the hardware and we must re-read to get a clean value.
520 */
521 limit = 1000;
522 do {
523 afsr = schizo_read(afsr_reg);
524 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
525
526 /* Clear the primary/secondary error status bits. */
527 error_bits = afsr &
528 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
529 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
530 if (!error_bits)
531 return IRQ_NONE;
532 schizo_write(afsr_reg, error_bits);
533
534 /* Log the error. */
6c108f12
DM		 535 printk("%s: Uncorrectable Error, primary error type[%s]\n",
536 pbm->name,
1da177e4
LT		 537 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
538 "PIO" :
539 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
540 "DMA Read" :
541 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
542 "DMA Write" : "???")))));
6c108f12
DM		 543 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
544 pbm->name,
1da177e4
LT		 545 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
546 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
547 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 548 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
549 pbm->name,
1da177e4
LT		 550 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
551 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
552 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
553 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
554 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 555 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
556 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 557 reported = 0;
558 if (afsr & SCHIZO_UEAFSR_SPIO) {
559 reported++;
560 printk("(PIO)");
561 }
562 if (afsr & SCHIZO_UEAFSR_SDMA) {
563 reported++;
564 printk("(DMA)");
565 }
566 if (!reported)
567 printk("(none)");
568 printk("]\n");
569
570 /* Interrogate IOMMU for error status. */
571 schizo_check_iommu_error(p, UE_ERR);
572
1da177e4
LT		 573 return IRQ_HANDLED;
574}
575
576#define SCHIZO_CE_AFSR 0x10040UL
577#define SCHIZO_CE_AFAR 0x10048UL
578
579#define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
580#define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
581#define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
582#define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
583#define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
584#define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
585#define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
586#define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
587#define SCHIZO_CEAFSR_AID 0x000000001f000000UL
588#define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
589#define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
590#define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
591#define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
592#define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
593
6d24c8dc 594static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
1da177e4 595{
34768bc8 596 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 597 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
598 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
1da177e4
LT		 599 unsigned long afsr, afar, error_bits;
600 int reported, limit;
601
602 /* Latch error status. */
603 afar = schizo_read(afar_reg);
604
605 /* If either of the error pending bits are set in the
606 * AFSR, the error status is being actively updated by
607 * the hardware and we must re-read to get a clean value.
608 */
609 limit = 1000;
610 do {
611 afsr = schizo_read(afsr_reg);
612 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
613
614 /* Clear primary/secondary error status bits. */
615 error_bits = afsr &
616 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
617 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
618 if (!error_bits)
619 return IRQ_NONE;
620 schizo_write(afsr_reg, error_bits);
621
622 /* Log the error. */
6c108f12
DM		 623 printk("%s: Correctable Error, primary error type[%s]\n",
624 pbm->name,
1da177e4
LT		 625 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
626 "PIO" :
627 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
628 "DMA Read" :
629 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
630 "DMA Write" : "???")))));
631
632 /* XXX Use syndrome and afar to print out module string just like
633 * XXX UDB CE trap handler does... -DaveM
634 */
6c108f12
DM		 635 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
636 pbm->name,
1da177e4
LT		 637 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
638 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
639 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 640 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
641 pbm->name,
1da177e4
LT		 642 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
643 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
644 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
645 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
646 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 647 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
648 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 649 reported = 0;
650 if (afsr & SCHIZO_CEAFSR_SPIO) {
651 reported++;
652 printk("(PIO)");
653 }
654 if (afsr & SCHIZO_CEAFSR_SDMA) {
655 reported++;
656 printk("(DMA)");
657 }
658 if (!reported)
659 printk("(none)");
660 printk("]\n");
661
1da177e4
LT		 662 return IRQ_HANDLED;
663}
664
665#define SCHIZO_PCI_AFSR 0x2010UL
666#define SCHIZO_PCI_AFAR 0x2018UL
667
668#define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
669#define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
670#define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
671#define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
672#define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
673#define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
674#define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
675#define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
676#define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
677#define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
678#define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
679#define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
680#define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
681#define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
682#define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
683#define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
684#define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
685
686#define SCHIZO_PCI_CTRL (0x2000UL)
687#define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
9fba62a5 688#define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
1da177e4
LT		 689#define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
690#define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
691#define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
692#define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
693#define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
694#define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
695#define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
696#define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
697#define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
698#define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
699#define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
700#define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
701#define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
702#define SCHIZO_PCICTRL_PTO_SHIFT 24UL
703#define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
704#define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
705#define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
706#define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
707#define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
708#define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
709#define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
710#define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
711#define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
712#define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
713#define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
714
715static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
716{
717 unsigned long csr_reg, csr, csr_error_bits;
718 irqreturn_t ret = IRQ_NONE;
719 u16 stat;
720
721 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
722 csr = schizo_read(csr_reg);
723 csr_error_bits =
724 csr & (SCHIZO_PCICTRL_BUS_UNUS |
725 SCHIZO_PCICTRL_TTO_ERR |
726 SCHIZO_PCICTRL_RTRY_ERR |
727 SCHIZO_PCICTRL_DTO_ERR |
728 SCHIZO_PCICTRL_SBH_ERR |
729 SCHIZO_PCICTRL_SERR);
730 if (csr_error_bits) {
731 /* Clear the errors. */
732 schizo_write(csr_reg, csr);
733
734 /* Log 'em. */
735 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
736 printk("%s: Bus unusable error asserted.\n",
737 pbm->name);
738 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
739 printk("%s: PCI TRDY# timeout error asserted.\n",
740 pbm->name);
741 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
742 printk("%s: PCI excessive retry error asserted.\n",
743 pbm->name);
744 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
745 printk("%s: PCI discard timeout error asserted.\n",
746 pbm->name);
747 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
748 printk("%s: PCI streaming byte hole error asserted.\n",
749 pbm->name);
750 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
751 printk("%s: PCI SERR signal asserted.\n",
752 pbm->name);
753 ret = IRQ_HANDLED;
754 }
755 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
756 if (stat & (PCI_STATUS_PARITY |
757 PCI_STATUS_SIG_TARGET_ABORT |
758 PCI_STATUS_REC_TARGET_ABORT |
759 PCI_STATUS_REC_MASTER_ABORT |
760 PCI_STATUS_SIG_SYSTEM_ERROR)) {
761 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
762 pbm->name, stat);
763 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
764 ret = IRQ_HANDLED;
765 }
766 return ret;
767}
768
6d24c8dc 769static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 770{
771 struct pci_pbm_info *pbm = dev_id;
772 struct pci_controller_info *p = pbm->parent;
773 unsigned long afsr_reg, afar_reg, base;
774 unsigned long afsr, afar, error_bits;
775 int reported;
776
777 base = pbm->pbm_regs;
778
779 afsr_reg = base + SCHIZO_PCI_AFSR;
780 afar_reg = base + SCHIZO_PCI_AFAR;
781
782 /* Latch error status. */
783 afar = schizo_read(afar_reg);
784 afsr = schizo_read(afsr_reg);
785
786 /* Clear primary/secondary error status bits. */
787 error_bits = afsr &
788 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
789 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
790 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
791 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
792 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
793 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
794 if (!error_bits)
795 return schizo_pcierr_intr_other(pbm);
796 schizo_write(afsr_reg, error_bits);
797
798 /* Log the error. */
799 printk("%s: PCI Error, primary error type[%s]\n",
800 pbm->name,
801 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
802 "Master Abort" :
803 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
804 "Target Abort" :
805 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
806 "Excessive Retries" :
807 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
808 "Parity Error" :
809 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
810 "Timeout" :
811 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
812 "Bus Unusable" : "???"))))))));
813 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
814 pbm->name,
815 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
816 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
817 ((afsr & SCHIZO_PCIAFSR_CFG) ?
818 "Config" :
819 ((afsr & SCHIZO_PCIAFSR_MEM) ?
820 "Memory" :
821 ((afsr & SCHIZO_PCIAFSR_IO) ?
822 "I/O" : "???"))));
823 printk("%s: PCI AFAR [%016lx]\n",
824 pbm->name, afar);
825 printk("%s: PCI Secondary errors [",
826 pbm->name);
827 reported = 0;
828 if (afsr & SCHIZO_PCIAFSR_SMA) {
829 reported++;
830 printk("(Master Abort)");
831 }
832 if (afsr & SCHIZO_PCIAFSR_STA) {
833 reported++;
834 printk("(Target Abort)");
835 }
836 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
837 reported++;
838 printk("(Excessive Retries)");
839 }
840 if (afsr & SCHIZO_PCIAFSR_SPERR) {
841 reported++;
842 printk("(Parity Error)");
843 }
844 if (afsr & SCHIZO_PCIAFSR_STTO) {
845 reported++;
846 printk("(Timeout)");
847 }
848 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
849 reported++;
850 printk("(Bus Unusable)");
851 }
852 if (!reported)
853 printk("(none)");
854 printk("]\n");
855
856 /* For the error types shown, scan PBM's PCI bus for devices
857 * which have logged that error type.
858 */
859
860 /* If we see a Target Abort, this could be the result of an
861 * IOMMU translation error of some sort. It is extremely
862 * useful to log this information as usually it indicates
863 * a bug in the IOMMU support code or a PCI device driver.
864 */
865 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
866 schizo_check_iommu_error(p, PCI_ERR);
6c108f12 867 pci_scan_for_target_abort(pbm, pbm->pci_bus);
1da177e4
LT		 868 }
869 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
6c108f12 870 pci_scan_for_master_abort(pbm, pbm->pci_bus);
1da177e4
LT		 871
872 /* For excessive retries, PSYCHO/PBM will abort the device
873 * and there is no way to specifically check for excessive
874 * retries in the config space status registers. So what
875 * we hope is that we'll catch it via the master/target
876 * abort events.
877 */
878
879 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
6c108f12 880 pci_scan_for_parity_error(pbm, pbm->pci_bus);
1da177e4 881
1da177e4
LT		 882 return IRQ_HANDLED;
883}
884
885#define SCHIZO_SAFARI_ERRLOG 0x10018UL
886
887#define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
888
889#define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
890#define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
891#define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
892#define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
893#define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
894#define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
895#define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
896#define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
897#define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
898#define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
899#define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
900#define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
901#define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
902#define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
903#define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
904#define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
905#define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
906#define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
907#define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
908#define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
909#define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
910#define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
911#define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
912#define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
913#define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
914#define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
915#define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
916#define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
917#define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
918#define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
919#define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
920
921/* We only expect UNMAP errors here. The rest of the Safari errors
922 * are marked fatal and thus cause a system reset.
923 */
6d24c8dc 924static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
1da177e4 925{
34768bc8
DM		 926 struct pci_pbm_info *pbm = dev_id;
927 struct pci_controller_info *p = pbm->parent;
1da177e4
LT		 928 u64 errlog;
929
34768bc8
DM		 930 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
931 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG,
1da177e4
LT		 932 errlog & ~(SAFARI_ERRLOG_ERROUT));
933
934 if (!(errlog & BUS_ERROR_UNMAP)) {
6c108f12
DM		 935 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
936 pbm->name, errlog);
1da177e4 937
1da177e4
LT		 938 return IRQ_HANDLED;
939 }
940
6c108f12
DM		 941 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
942 pbm->name);
1da177e4
LT		 943 schizo_check_iommu_error(p, SAFARI_ERR);
944
1da177e4
LT		 945 return IRQ_HANDLED;
946}
947
948/* Nearly identical to PSYCHO equivalents... */
949#define SCHIZO_ECC_CTRL 0x10020UL
950#define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
951#define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
952#define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
953
954#define SCHIZO_SAFARI_ERRCTRL 0x10008UL
955#define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
956#define SCHIZO_SAFARI_IRQCTRL 0x10010UL
957#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
958
34768bc8
DM		 959static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
960{
961 ino &= IMAP_INO;
962
963 if (pbm->ino_bitmap & (1UL << ino))
964 return 1;
965
966 return 0;
967}
968
1da177e4
LT		 969/* How the Tomatillo IRQs are routed around is pure guesswork here.
970 *
971 * All the Tomatillo devices I see in prtconf dumps seem to have only
972 * a single PCI bus unit attached to it. It would seem they are seperate
973 * devices because their PortID (ie. JBUS ID) values are all different
974 * and thus the registers are mapped to totally different locations.
975 *
976 * However, two Tomatillo's look "similar" in that the only difference
977 * in their PortID is the lowest bit.
978 *
979 * So if we were to ignore this lower bit, it certainly looks like two
980 * PCI bus units of the same Tomatillo. I still have not really
981 * figured this out...
982 */
34768bc8 983static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 984{
34768bc8 985 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 986 u64 tmp, err_mask, err_no_mask;
af80318e 987 int err;
1da177e4 988
2b1e5978
DM		 989 /* Tomatillo IRQ property layout is:
990 * 0: PCIERR
991 * 1: UE ERR
992 * 2: CE ERR
993 * 3: SERR
994 * 4: POWER FAIL?
995 */
996
af80318e
DM		 997 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
998 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
999 "TOMATILLO_UE", pbm);
1000 if (err)
1001 printk(KERN_WARNING "%s: Could not register UE, "
1002 "err=%d\n", pbm->name, err);
1003 }
1004 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
1005 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
1006 "TOMATILLO_CE", pbm);
1007 if (err)
1008 printk(KERN_WARNING "%s: Could not register CE, "
1009 "err=%d\n", pbm->name, err);
1010 }
1011 err = 0;
1012 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
1013 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1014 "TOMATILLO_PCIERR", pbm);
1015 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
1016 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1017 "TOMATILLO_PCIERR", pbm);
1018 }
1019 if (err)
1020 printk(KERN_WARNING "%s: Could not register PCIERR, "
1021 "err=%d\n", pbm->name, err);
1022
1023 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
1024 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1025 "TOMATILLO_SERR", pbm);
1026 if (err)
1027 printk(KERN_WARNING "%s: Could not register SERR, "
1028 "err=%d\n", pbm->name, err);
1029 }
34768bc8
DM		 1030
1031 /* Enable UE and CE interrupts for controller. */
1032 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 1033 (SCHIZO_ECCCTRL_EE |
1034 SCHIZO_ECCCTRL_UE |
1035 SCHIZO_ECCCTRL_CE));
1036
1037 /* Enable PCI Error interrupts and clear error
1038 * bits.
1039 */
1040 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1041 SCHIZO_PCICTRL_TTO_ERR |
1042 SCHIZO_PCICTRL_RTRY_ERR |
1043 SCHIZO_PCICTRL_SERR |
1044 SCHIZO_PCICTRL_EEN);
1045
1046 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
1047
34768bc8 1048 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 1049 tmp |= err_mask;
1050 tmp &= ~err_no_mask;
34768bc8 1051 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4
LT		 1052
1053 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1054 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1055 SCHIZO_PCIAFSR_PTTO |
1056 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1057 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1058 SCHIZO_PCIAFSR_STTO);
1059
34768bc8 1060 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1da177e4
LT		 1061
1062 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
1063 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
1064 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
1065 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
1066 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
1067 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
1068 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
1069 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
1070 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
1071
34768bc8 1072 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4
LT		 1073 (SCHIZO_SAFERRCTRL_EN | err_mask));
1074
34768bc8 1075 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL,
1da177e4
LT		 1076 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1077}
1078
34768bc8 1079static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 1080{
34768bc8 1081 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 1082 u64 tmp, err_mask, err_no_mask;
af80318e 1083 int err;
1da177e4 1084
2b1e5978
DM		 1085 /* Schizo IRQ property layout is:
1086 * 0: PCIERR
1087 * 1: UE ERR
1088 * 2: CE ERR
1089 * 3: SERR
1090 * 4: POWER FAIL?
1091 */
1092
af80318e
DM		 1093 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
1094 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
1095 "SCHIZO_UE", pbm);
1096 if (err)
1097 printk(KERN_WARNING "%s: Could not register UE, "
1098 "err=%d\n", pbm->name, err);
1099 }
1100 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
1101 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
1102 "SCHIZO_CE", pbm);
1103 if (err)
1104 printk(KERN_WARNING "%s: Could not register CE, "
1105 "err=%d\n", pbm->name, err);
1106 }
1107 err = 0;
1108 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
1109 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1110 "SCHIZO_PCIERR", pbm);
1111 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
1112 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
1113 "SCHIZO_PCIERR", pbm);
1114 }
1115 if (err)
1116 printk(KERN_WARNING "%s: Could not register PCIERR, "
1117 "err=%d\n", pbm->name, err);
1118
1119 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
1120 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1121 "SCHIZO_SERR", pbm);
1122 if (err)
1123 printk(KERN_WARNING "%s: Could not register SERR, "
1124 "err=%d\n", pbm->name, err);
1125 }
1da177e4
LT		 1126
1127 /* Enable UE and CE interrupts for controller. */
34768bc8 1128 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 1129 (SCHIZO_ECCCTRL_EE |
1130 SCHIZO_ECCCTRL_UE |
1131 SCHIZO_ECCCTRL_CE));
1132
1133 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1134 SCHIZO_PCICTRL_ESLCK |
1135 SCHIZO_PCICTRL_TTO_ERR |
1136 SCHIZO_PCICTRL_RTRY_ERR |
1137 SCHIZO_PCICTRL_SBH_ERR |
1138 SCHIZO_PCICTRL_SERR |
1139 SCHIZO_PCICTRL_EEN);
1140
1141 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1142 SCHIZO_PCICTRL_SBH_INT);
1143
1144 /* Enable PCI Error interrupts and clear error
1145 * bits for each PBM.
1146 */
34768bc8 1147 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 1148 tmp |= err_mask;
1149 tmp &= ~err_no_mask;
34768bc8 1150 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4 1151
34768bc8 1152 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR,
1da177e4
LT		 1153 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1154 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1155 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1156 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1157 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1158 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1159
1160 /* Make all Safari error conditions fatal except unmapped
1161 * errors which we make generate interrupts.
1162 */
1163 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1164 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1165 BUS_ERROR_BADMC |
1166 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1167 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1168 BUS_ERROR_CIQTO |
1169 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1170 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1171 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1172 BUS_ERROR_ILL);
1173#if 1
1174 /* XXX Something wrong with some Excalibur systems
1175 * XXX Sun is shipping. The behavior on a 2-cpu
1176 * XXX machine is that both CPU1 parity error bits
1177 * XXX are set and are immediately set again when
1178 * XXX their error status bits are cleared. Just
1179 * XXX ignore them for now. -DaveM
1180 */
1181 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1182 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1183#endif
1184
34768bc8 1185 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4 1186 (SCHIZO_SAFERRCTRL_EN | err_mask));
1da177e4
LT		 1187}
1188
085ae41f 1189static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 1190{
1191 u8 *addr;
1192
1193 /* Set cache-line size to 64 bytes, this is actually
1194 * a nop but I do it for completeness.
1195 */
1196 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1197 0, PCI_CACHE_LINE_SIZE);
1198 pci_config_write8(addr, 64 / sizeof(u32));
1199
1200 /* Set PBM latency timer to 64 PCI clocks. */
1201 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1202 0, PCI_LATENCY_TIMER);
1203 pci_config_write8(addr, 64);
1204}
1205
34768bc8 1206static void schizo_scan_bus(struct pci_pbm_info *pbm)
1da177e4 1207{
34768bc8
DM		 1208 pbm_config_busmastering(pbm);
1209 pbm->is_66mhz_capable =
1210 (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
e87dc350 1211 != NULL);
bc606f3c 1212
34768bc8 1213 pbm->pci_bus = pci_scan_one_pbm(pbm);
1da177e4 1214
34768bc8
DM		 1215 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1216 tomatillo_register_error_handlers(pbm);
1da177e4 1217 else
34768bc8 1218 schizo_register_error_handlers(pbm);
1da177e4
LT		 1219}
1220
1da177e4
LT		 1221#define SCHIZO_STRBUF_CONTROL (0x02800UL)
1222#define SCHIZO_STRBUF_FLUSH (0x02808UL)
1223#define SCHIZO_STRBUF_FSYNC (0x02810UL)
1224#define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1225#define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1226
1227static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1228{
1229 unsigned long base = pbm->pbm_regs;
1230 u64 control;
1231
1232 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1233 /* TOMATILLO lacks streaming cache. */
1234 return;
1235 }
1236
1237 /* SCHIZO has context flushing. */
1238 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1239 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1240 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1241 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1242 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1243
1244 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1245 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1246 + 63UL)
1247 & ~63UL);
1248 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1249 __pa(pbm->stc.strbuf_flushflag);
1250
1251 /* Turn off LRU locking and diag mode, enable the
1252 * streaming buffer and leave the rerun-disable
1253 * setting however OBP set it.
1254 */
1255 control = schizo_read(pbm->stc.strbuf_control);
1256 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1257 SCHIZO_STRBUF_CTRL_LENAB |
1258 SCHIZO_STRBUF_CTRL_DENAB);
1259 control |= SCHIZO_STRBUF_CTRL_ENAB;
1260 schizo_write(pbm->stc.strbuf_control, control);
1261
1262 pbm->stc.strbuf_enabled = 1;
1263}
1264
1265#define SCHIZO_IOMMU_CONTROL (0x00200UL)
1266#define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1267#define SCHIZO_IOMMU_FLUSH (0x00210UL)
1268#define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1269
1270static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1271{
16ce82d8 1272 struct iommu *iommu = pbm->iommu;
51e85136 1273 unsigned long i, tagbase, database;
e87dc350 1274 struct property *prop;
1da177e4
LT		 1275 u32 vdma[2], dma_mask;
1276 u64 control;
e87dc350 1277 int tsbsize;
1da177e4 1278
e87dc350
DM		 1279 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
1280 if (prop) {
1281 u32 *val = prop->value;
1282
1283 vdma[0] = val[0];
1284 vdma[1] = val[1];
1285 } else {
1da177e4
LT		 1286 /* No property, use default values. */
1287 vdma[0] = 0xc0000000;
1288 vdma[1] = 0x40000000;
1289 }
1290
1291 dma_mask = vdma[0];
1292 switch (vdma[1]) {
1293 case 0x20000000:
1294 dma_mask |= 0x1fffffff;
1295 tsbsize = 64;
1296 break;
1297
1298 case 0x40000000:
1299 dma_mask |= 0x3fffffff;
1300 tsbsize = 128;
1301 break;
1302
1303 case 0x80000000:
1304 dma_mask |= 0x7fffffff;
1305 tsbsize = 128;
1306 break;
1307
1308 default:
1309 prom_printf("SCHIZO: strange virtual-dma size.\n");
1310 prom_halt();
1311 };
1312
1da177e4
LT		 1313 /* Register addresses, SCHIZO has iommu ctx flushing. */
1314 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1315 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1316 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1317 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1318
1319 /* We use the main control/status register of SCHIZO as the write
1320 * completion register.
1321 */
1322 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1323
1324 /*
1325 * Invalidate TLB Entries.
1326 */
1327 control = schizo_read(iommu->iommu_control);
1328 control |= SCHIZO_IOMMU_CTRL_DENAB;
1329 schizo_write(iommu->iommu_control, control);
1330
1331 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1332
1333 for(i = 0; i < 16; i++) {
1334 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1335 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1336 }
1337
1338 /* Leave diag mode enabled for full-flushing done
1339 * in pci_iommu.c
1340 */
51e85136 1341 pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
1da177e4 1342
51e85136 1343 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1da177e4
LT		 1344
1345 control = schizo_read(iommu->iommu_control);
1346 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1347 switch (tsbsize) {
1348 case 64:
1349 control |= SCHIZO_IOMMU_TSBSZ_64K;
1350 break;
1351 case 128:
1352 control |= SCHIZO_IOMMU_TSBSZ_128K;
1353 break;
1354 };
1355
1356 control |= SCHIZO_IOMMU_CTRL_ENAB;
1357 schizo_write(iommu->iommu_control, control);
1358}
1359
1360#define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1361#define SCHIZO_IRQ_RETRY_INF 0xffUL
1362
1363#define SCHIZO_PCI_DIAG (0x2020UL)
1364#define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1365#define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1366#define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1367#define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1368#define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1369#define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1370#define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1371#define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1372#define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1373
1374#define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1375#define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1376#define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1377#define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1378#define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1379#define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1380#define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1381#define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1382#define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1383#define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1384#define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1385#define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1386#define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1387#define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1388#define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1389#define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1390
1391#define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1392#define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1393
085ae41f 1394static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1da177e4 1395{
e87dc350 1396 struct property *prop;
1da177e4
LT		 1397 u64 tmp;
1398
864ae180 1399 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1da177e4 1400
1da177e4 1401 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4 1402
9fba62a5
DM		 1403 /* Enable arbiter for all PCI slots. */
1404 tmp |= 0xff;
1405
1da177e4
LT		 1406 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1407 pbm->chip_version >= 0x2)
1408 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1da177e4 1409
e87dc350
DM		 1410 prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL);
1411 if (!prop)
1da177e4 1412 tmp |= SCHIZO_PCICTRL_PARK;
9fba62a5
DM		 1413 else
1414 tmp &= ~SCHIZO_PCICTRL_PARK;
1da177e4
LT		 1415
1416 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1417 pbm->chip_version <= 0x1)
9fba62a5 1418 tmp |= SCHIZO_PCICTRL_DTO_INT;
1da177e4 1419 else
9fba62a5 1420 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1da177e4
LT		 1421
1422 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1423 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1424 SCHIZO_PCICTRL_RDO_PREF |
1425 SCHIZO_PCICTRL_RDL_PREF);
1426
1427 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1428
1429 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1430 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1431 SCHIZO_PCIDIAG_D_RETRY |
1432 SCHIZO_PCIDIAG_D_INTSYNC);
1433 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1434
1435 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1436 /* Clear prefetch lengths to workaround a bug in
1437 * Jalapeno...
1438 */
1439 tmp = (TOMATILLO_IOC_PART_WPENAB |
1440 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1441 TOMATILLO_IOC_RDMULT_CPENAB |
1442 TOMATILLO_IOC_RDONE_CPENAB |
1443 TOMATILLO_IOC_RDLINE_CPENAB);
1444
1445 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1446 tmp);
1447 }
1448}
1449
085ae41f 1450static void schizo_pbm_init(struct pci_controller_info *p,
e87dc350 1451 struct device_node *dp, u32 portid,
085ae41f 1452 int chip_type)
1da177e4 1453{
a165b420 1454 const struct linux_prom64_registers *regs;
1da177e4
LT		 1455 struct pci_pbm_info *pbm;
1456 const char *chipset_name;
1da177e4 1457 int is_pbm_a;
1da177e4
LT		 1458
1459 switch (chip_type) {
1460 case PBM_CHIP_TYPE_TOMATILLO:
1461 chipset_name = "TOMATILLO";
1462 break;
1463
1464 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1465 chipset_name = "SCHIZO+";
1466 break;
1467
1468 case PBM_CHIP_TYPE_SCHIZO:
1469 default:
1470 chipset_name = "SCHIZO";
1471 break;
1472 };
1473
1474 /* For SCHIZO, three OBP regs:
1475 * 1) PBM controller regs
1476 * 2) Schizo front-end controller regs (same for both PBMs)
1477 * 3) PBM PCI config space
1478 *
1479 * For TOMATILLO, four OBP regs:
1480 * 1) PBM controller regs
1481 * 2) Tomatillo front-end controller regs
1482 * 3) PBM PCI config space
1483 * 4) Ichip regs
1484 */
bc606f3c 1485 regs = of_get_property(dp, "reg", NULL);
1da177e4 1486
e87dc350 1487 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1da177e4
LT		 1488 if (is_pbm_a)
1489 pbm = &p->pbm_A;
1490 else
1491 pbm = &p->pbm_B;
1492
34768bc8
DM		 1493 pbm->next = pci_pbm_root;
1494 pci_pbm_root = pbm;
1495
1496 pbm->scan_bus = schizo_scan_bus;
f1cd8de2 1497 pbm->pci_ops = &schizo_ops;
34768bc8 1498
6c108f12
DM		 1499 pbm->index = pci_num_pbms++;
1500
1da177e4
LT		 1501 pbm->portid = portid;
1502 pbm->parent = p;
e87dc350 1503 pbm->prom_node = dp;
1da177e4
LT		 1504
1505 pbm->chip_type = chip_type;
bc606f3c
DM		 1506 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1507 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
e87dc350
DM		 1508
1509 pbm->pbm_regs = regs[0].phys_addr;
1510 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1da177e4 1511
bb6743f4 1512 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
e87dc350 1513 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
bb6743f4 1514
e87dc350 1515 pbm->name = dp->full_name;
1da177e4 1516
e87dc350 1517 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
bc606f3c 1518 pbm->name, chipset_name,
e87dc350 1519 pbm->chip_version, pbm->chip_revision);
1da177e4
LT		 1520
1521 schizo_pbm_hw_init(pbm);
1522
9fd8b647 1523 pci_determine_mem_io_space(pbm);
1da177e4 1524
cfa0652c 1525 pci_get_pbm_props(pbm);
1da177e4
LT		 1526
1527 schizo_pbm_iommu_init(pbm);
1528 schizo_pbm_strbuf_init(pbm);
1529}
1530
1531static inline int portid_compare(u32 x, u32 y, int chip_type)
1532{
1533 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1534 if (x == (y ^ 1))
1535 return 1;
1536 return 0;
1537 }
1538 return (x == y);
1539}
1540
e87dc350 1541static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
1da177e4
LT		 1542{
1543 struct pci_controller_info *p;
34768bc8 1544 struct pci_pbm_info *pbm;
16ce82d8 1545 struct iommu *iommu;
1da177e4
LT		 1546 u32 portid;
1547
bc606f3c 1548 portid = of_getintprop_default(dp, "portid", 0xff);
1da177e4 1549
34768bc8 1550 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1da177e4 1551 if (portid_compare(pbm->portid, portid, chip_type)) {
34768bc8 1552 schizo_pbm_init(pbm->parent, dp, portid, chip_type);
1da177e4
LT		 1553 return;
1554 }
1555 }
1556
9132983a 1557 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
bc606f3c
DM		 1558 if (!p)
1559 goto memfail;
1da177e4 1560
16ce82d8 1561 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
bc606f3c
DM		 1562 if (!iommu)
1563 goto memfail;
1564
1da177e4
LT		 1565 p->pbm_A.iommu = iommu;
1566
16ce82d8 1567 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
bc606f3c
DM		 1568 if (!iommu)
1569 goto memfail;
1570
1da177e4
LT		 1571 p->pbm_B.iommu = iommu;
1572
1da177e4
LT		 1573 /* Like PSYCHO we have a 2GB aligned area for memory space. */
1574 pci_memspace_mask = 0x7fffffffUL;
1575
e87dc350 1576 schizo_pbm_init(p, dp, portid, chip_type);
bc606f3c
DM		 1577 return;
1578
1579memfail:
1580 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1581 prom_halt();
1da177e4
LT		 1582}
1583
e87dc350 1584void schizo_init(struct device_node *dp, char *model_name)
1da177e4 1585{
e87dc350 1586 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO);
1da177e4
LT		 1587}
1588
e87dc350 1589void schizo_plus_init(struct device_node *dp, char *model_name)
1da177e4 1590{
e87dc350 1591 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
1da177e4
LT		 1592}
1593
e87dc350 1594void tomatillo_init(struct device_node *dp, char *model_name)
1da177e4 1595{
e87dc350 1596 __schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO);
1da177e4 1597}
Linux kernel - Deliverables
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