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1da177e4 LT |
1 | /* $Id: pci_schizo.c,v 1.24 2002/01/23 11:27:32 davem Exp $ |
2 | * pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003 David S. Miller (davem@redhat.com) | |
5 | */ | |
6 | ||
7 | #include <linux/kernel.h> | |
8 | #include <linux/types.h> | |
9 | #include <linux/pci.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/interrupt.h> | |
13 | ||
14 | #include <asm/pbm.h> | |
15 | #include <asm/iommu.h> | |
16 | #include <asm/irq.h> | |
17 | #include <asm/upa.h> | |
bb6743f4 | 18 | #include <asm/pstate.h> |
e87dc350 | 19 | #include <asm/prom.h> |
1da177e4 LT |
20 | |
21 | #include "pci_impl.h" | |
22 | #include "iommu_common.h" | |
23 | ||
24 | /* All SCHIZO registers are 64-bits. The following accessor | |
25 | * routines are how they are accessed. The REG parameter | |
26 | * is a physical address. | |
27 | */ | |
28 | #define schizo_read(__reg) \ | |
29 | ({ u64 __ret; \ | |
30 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
31 | : "=r" (__ret) \ | |
32 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
33 | : "memory"); \ | |
34 | __ret; \ | |
35 | }) | |
36 | #define schizo_write(__reg, __val) \ | |
37 | __asm__ __volatile__("stxa %0, [%1] %2" \ | |
38 | : /* no outputs */ \ | |
39 | : "r" (__val), "r" (__reg), \ | |
40 | "i" (ASI_PHYS_BYPASS_EC_E) \ | |
41 | : "memory") | |
42 | ||
43 | /* This is a convention that at least Excalibur and Merlin | |
44 | * follow. I suppose the SCHIZO used in Starcat and friends | |
45 | * will do similar. | |
46 | * | |
47 | * The only way I could see this changing is if the newlink | |
48 | * block requires more space in Schizo's address space than | |
49 | * they predicted, thus requiring an address space reorg when | |
50 | * the newer Schizo is taped out. | |
51 | */ | |
52 | ||
53 | /* Streaming buffer control register. */ | |
54 | #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ | |
55 | #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ | |
56 | #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ | |
57 | #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ | |
58 | #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ | |
59 | ||
60 | /* IOMMU control register. */ | |
61 | #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ | |
62 | #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ | |
63 | #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ | |
64 | #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ | |
65 | #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ | |
66 | #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ | |
67 | #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ | |
68 | #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ | |
69 | #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ | |
70 | #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ | |
71 | #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ | |
72 | #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ | |
73 | #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ | |
74 | #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ | |
75 | #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ | |
76 | #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ | |
77 | #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ | |
78 | #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ | |
79 | ||
80 | /* Schizo config space address format is nearly identical to | |
81 | * that of PSYCHO: | |
82 | * | |
83 | * 32 24 23 16 15 11 10 8 7 2 1 0 | |
84 | * --------------------------------------------------------- | |
85 | * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | | |
86 | * --------------------------------------------------------- | |
87 | */ | |
88 | #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) | |
89 | #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ | |
90 | (((unsigned long)(BUS) << 16) | \ | |
91 | ((unsigned long)(DEVFN) << 8) | \ | |
92 | ((unsigned long)(REG))) | |
93 | ||
94 | static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, | |
95 | unsigned char bus, | |
96 | unsigned int devfn, | |
97 | int where) | |
98 | { | |
99 | if (!pbm) | |
100 | return NULL; | |
101 | bus -= pbm->pci_first_busno; | |
102 | return (void *) | |
103 | (SCHIZO_CONFIG_BASE(pbm) | | |
104 | SCHIZO_CONFIG_ENCODE(bus, devfn, where)); | |
105 | } | |
106 | ||
107 | /* Just make sure the bus number is in range. */ | |
108 | static int schizo_out_of_range(struct pci_pbm_info *pbm, | |
109 | unsigned char bus, | |
110 | unsigned char devfn) | |
111 | { | |
112 | if (bus < pbm->pci_first_busno || | |
113 | bus > pbm->pci_last_busno) | |
114 | return 1; | |
115 | return 0; | |
116 | } | |
117 | ||
118 | /* SCHIZO PCI configuration space accessors. */ | |
119 | ||
120 | static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
121 | int where, int size, u32 *value) | |
122 | { | |
123 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
124 | unsigned char bus = bus_dev->number; | |
125 | u32 *addr; | |
126 | u16 tmp16; | |
127 | u8 tmp8; | |
128 | ||
129 | switch (size) { | |
130 | case 1: | |
131 | *value = 0xff; | |
132 | break; | |
133 | case 2: | |
134 | *value = 0xffff; | |
135 | break; | |
136 | case 4: | |
137 | *value = 0xffffffff; | |
138 | break; | |
139 | } | |
140 | ||
141 | addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where); | |
142 | if (!addr) | |
143 | return PCIBIOS_SUCCESSFUL; | |
144 | ||
145 | if (schizo_out_of_range(pbm, bus, devfn)) | |
146 | return PCIBIOS_SUCCESSFUL; | |
147 | switch (size) { | |
148 | case 1: | |
149 | pci_config_read8((u8 *)addr, &tmp8); | |
150 | *value = tmp8; | |
151 | break; | |
152 | ||
153 | case 2: | |
154 | if (where & 0x01) { | |
155 | printk("pci_read_config_word: misaligned reg [%x]\n", | |
156 | where); | |
157 | return PCIBIOS_SUCCESSFUL; | |
158 | } | |
159 | pci_config_read16((u16 *)addr, &tmp16); | |
160 | *value = tmp16; | |
161 | break; | |
162 | ||
163 | case 4: | |
164 | if (where & 0x03) { | |
165 | printk("pci_read_config_dword: misaligned reg [%x]\n", | |
166 | where); | |
167 | return PCIBIOS_SUCCESSFUL; | |
168 | } | |
169 | pci_config_read32(addr, value); | |
170 | break; | |
171 | } | |
172 | return PCIBIOS_SUCCESSFUL; | |
173 | } | |
174 | ||
175 | static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
176 | int where, int size, u32 value) | |
177 | { | |
178 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
179 | unsigned char bus = bus_dev->number; | |
180 | u32 *addr; | |
181 | ||
182 | addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where); | |
183 | if (!addr) | |
184 | return PCIBIOS_SUCCESSFUL; | |
185 | ||
186 | if (schizo_out_of_range(pbm, bus, devfn)) | |
187 | return PCIBIOS_SUCCESSFUL; | |
188 | ||
189 | switch (size) { | |
190 | case 1: | |
191 | pci_config_write8((u8 *)addr, value); | |
192 | break; | |
193 | ||
194 | case 2: | |
195 | if (where & 0x01) { | |
196 | printk("pci_write_config_word: misaligned reg [%x]\n", | |
197 | where); | |
198 | return PCIBIOS_SUCCESSFUL; | |
199 | } | |
200 | pci_config_write16((u16 *)addr, value); | |
201 | break; | |
202 | ||
203 | case 4: | |
204 | if (where & 0x03) { | |
205 | printk("pci_write_config_dword: misaligned reg [%x]\n", | |
206 | where); | |
207 | return PCIBIOS_SUCCESSFUL; | |
208 | } | |
209 | ||
210 | pci_config_write32(addr, value); | |
211 | } | |
212 | return PCIBIOS_SUCCESSFUL; | |
213 | } | |
214 | ||
215 | static struct pci_ops schizo_ops = { | |
216 | .read = schizo_read_pci_cfg, | |
217 | .write = schizo_write_pci_cfg, | |
218 | }; | |
219 | ||
220 | /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the | |
221 | * imap/iclr registers are per-PBM. | |
222 | */ | |
223 | #define SCHIZO_IMAP_BASE 0x1000UL | |
224 | #define SCHIZO_ICLR_BASE 0x1400UL | |
225 | ||
226 | static unsigned long schizo_imap_offset(unsigned long ino) | |
227 | { | |
228 | return SCHIZO_IMAP_BASE + (ino * 8UL); | |
229 | } | |
230 | ||
231 | static unsigned long schizo_iclr_offset(unsigned long ino) | |
232 | { | |
233 | return SCHIZO_ICLR_BASE + (ino * 8UL); | |
234 | } | |
235 | ||
e18e2a00 | 236 | static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2) |
bb6743f4 DM |
237 | { |
238 | unsigned long sync_reg = (unsigned long) _arg2; | |
e18e2a00 | 239 | u64 mask = 1UL << (ino & IMAP_INO); |
bb6743f4 DM |
240 | u64 val; |
241 | int limit; | |
242 | ||
243 | schizo_write(sync_reg, mask); | |
244 | ||
245 | limit = 100000; | |
246 | val = 0; | |
247 | while (--limit) { | |
248 | val = schizo_read(sync_reg); | |
249 | if (!(val & mask)) | |
250 | break; | |
251 | } | |
252 | if (limit <= 0) { | |
253 | printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n", | |
254 | val, mask); | |
255 | } | |
256 | ||
257 | if (_arg1) { | |
258 | static unsigned char cacheline[64] | |
259 | __attribute__ ((aligned (64))); | |
260 | ||
261 | __asm__ __volatile__("rd %%fprs, %0\n\t" | |
262 | "or %0, %4, %1\n\t" | |
263 | "wr %1, 0x0, %%fprs\n\t" | |
264 | "stda %%f0, [%5] %6\n\t" | |
265 | "wr %0, 0x0, %%fprs\n\t" | |
266 | "membar #Sync" | |
267 | : "=&r" (mask), "=&r" (val) | |
268 | : "0" (mask), "1" (val), | |
269 | "i" (FPRS_FEF), "r" (&cacheline[0]), | |
270 | "i" (ASI_BLK_COMMIT_P)); | |
271 | } | |
272 | } | |
273 | ||
8047e247 DM |
274 | static unsigned long schizo_ino_to_iclr(struct pci_pbm_info *pbm, |
275 | unsigned int ino) | |
276 | { | |
277 | ino &= PCI_IRQ_INO; | |
278 | return pbm->pbm_regs + schizo_iclr_offset(ino) + 4; | |
279 | } | |
280 | ||
281 | static unsigned long schizo_ino_to_imap(struct pci_pbm_info *pbm, | |
282 | unsigned int ino) | |
283 | { | |
284 | ino &= PCI_IRQ_INO; | |
285 | return pbm->pbm_regs + schizo_imap_offset(ino) + 4; | |
286 | } | |
287 | ||
1da177e4 LT |
288 | static unsigned int schizo_irq_build(struct pci_pbm_info *pbm, |
289 | struct pci_dev *pdev, | |
290 | unsigned int ino) | |
291 | { | |
1da177e4 | 292 | unsigned long imap, iclr; |
37cdcd9e | 293 | int ign_fixup; |
8047e247 | 294 | int virt_irq; |
1da177e4 LT |
295 | |
296 | ino &= PCI_IRQ_INO; | |
1da177e4 LT |
297 | |
298 | /* Now build the IRQ bucket. */ | |
8047e247 DM |
299 | imap = schizo_ino_to_imap(pbm, ino); |
300 | iclr = schizo_ino_to_iclr(pbm, ino); | |
1da177e4 LT |
301 | |
302 | /* On Schizo, no inofixup occurs. This is because each | |
303 | * INO has it's own IMAP register. On Psycho and Sabre | |
304 | * there is only one IMAP register for each PCI slot even | |
305 | * though four different INOs can be generated by each | |
306 | * PCI slot. | |
307 | * | |
308 | * But, for JBUS variants (essentially, Tomatillo), we have | |
309 | * to fixup the lowest bit of the interrupt group number. | |
310 | */ | |
311 | ign_fixup = 0; | |
312 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
313 | if (pbm->portid & 1) | |
314 | ign_fixup = (1 << 6); | |
315 | } | |
316 | ||
e18e2a00 | 317 | virt_irq = build_irq(ign_fixup, iclr, imap); |
1da177e4 | 318 | |
bb6743f4 | 319 | if (pdev && pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { |
8047e247 DM |
320 | irq_install_pre_handler(virt_irq, |
321 | tomatillo_wsync_handler, | |
322 | ((pbm->chip_version <= 4) ? | |
323 | (void *) 1 : (void *) 0), | |
324 | (void *) pbm->sync_reg); | |
bb6743f4 DM |
325 | } |
326 | ||
8047e247 | 327 | return virt_irq; |
1da177e4 LT |
328 | } |
329 | ||
330 | /* SCHIZO error handling support. */ | |
331 | enum schizo_error_type { | |
332 | UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR | |
333 | }; | |
334 | ||
335 | static DEFINE_SPINLOCK(stc_buf_lock); | |
336 | static unsigned long stc_error_buf[128]; | |
337 | static unsigned long stc_tag_buf[16]; | |
338 | static unsigned long stc_line_buf[16]; | |
339 | ||
340 | #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ | |
341 | #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ | |
342 | #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ | |
343 | #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ | |
344 | #define SCHIZO_SERR_INO 0x34 /* Safari interface error */ | |
345 | ||
346 | struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino) | |
347 | { | |
348 | ino &= IMAP_INO; | |
349 | if (p->pbm_A.ino_bitmap & (1UL << ino)) | |
350 | return &p->pbm_A; | |
351 | if (p->pbm_B.ino_bitmap & (1UL << ino)) | |
352 | return &p->pbm_B; | |
353 | ||
354 | printk("PCI%d: No ino_bitmap entry for ino[%x], bitmaps " | |
355 | "PBM_A[%016lx] PBM_B[%016lx]", | |
356 | p->index, ino, | |
357 | p->pbm_A.ino_bitmap, | |
358 | p->pbm_B.ino_bitmap); | |
359 | printk("PCI%d: Using PBM_A, report this problem immediately.\n", | |
360 | p->index); | |
361 | ||
362 | return &p->pbm_A; | |
363 | } | |
364 | ||
365 | static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq) | |
366 | { | |
367 | struct pci_pbm_info *pbm; | |
1da177e4 LT |
368 | unsigned long iclr; |
369 | ||
370 | /* Do not clear the interrupt for the other PCI bus. | |
371 | * | |
372 | * This "ACK both PBM IRQs" only needs to be performed | |
373 | * for chip-wide error interrupts. | |
374 | */ | |
375 | if ((irq & IMAP_INO) == SCHIZO_PCIERR_A_INO || | |
376 | (irq & IMAP_INO) == SCHIZO_PCIERR_B_INO) | |
377 | return; | |
378 | ||
379 | pbm = pbm_for_ino(p, irq); | |
380 | if (pbm == &p->pbm_A) | |
381 | pbm = &p->pbm_B; | |
382 | else | |
383 | pbm = &p->pbm_A; | |
384 | ||
8047e247 DM |
385 | schizo_irq_build(pbm, NULL, |
386 | (pbm->portid << 6) | (irq & IMAP_INO)); | |
1da177e4 | 387 | |
8047e247 DM |
388 | iclr = schizo_ino_to_iclr(pbm, |
389 | (pbm->portid << 6) | (irq & IMAP_INO)); | |
1da177e4 LT |
390 | upa_writel(ICLR_IDLE, iclr); |
391 | } | |
392 | ||
393 | #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ | |
394 | #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ | |
395 | #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ | |
396 | ||
397 | #define SCHIZO_STCERR_WRITE 0x2UL | |
398 | #define SCHIZO_STCERR_READ 0x1UL | |
399 | ||
400 | #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL | |
401 | #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL | |
402 | #define SCHIZO_STCTAG_VALID 0x8000000000000000UL | |
403 | #define SCHIZO_STCTAG_READ 0x4000000000000000UL | |
404 | ||
405 | #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL | |
406 | #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL | |
407 | #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL | |
408 | #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL | |
409 | #define SCHIZO_STCLINE_VALID 0x0000000000600000UL | |
410 | #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL | |
411 | ||
412 | static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, | |
413 | enum schizo_error_type type) | |
414 | { | |
415 | struct pci_strbuf *strbuf = &pbm->stc; | |
416 | unsigned long regbase = pbm->pbm_regs; | |
417 | unsigned long err_base, tag_base, line_base; | |
418 | u64 control; | |
419 | int i; | |
420 | ||
421 | err_base = regbase + SCHIZO_STC_ERR; | |
422 | tag_base = regbase + SCHIZO_STC_TAG; | |
423 | line_base = regbase + SCHIZO_STC_LINE; | |
424 | ||
425 | spin_lock(&stc_buf_lock); | |
426 | ||
427 | /* This is __REALLY__ dangerous. When we put the | |
428 | * streaming buffer into diagnostic mode to probe | |
429 | * it's tags and error status, we _must_ clear all | |
430 | * of the line tag valid bits before re-enabling | |
431 | * the streaming buffer. If any dirty data lives | |
432 | * in the STC when we do this, we will end up | |
433 | * invalidating it before it has a chance to reach | |
434 | * main memory. | |
435 | */ | |
436 | control = schizo_read(strbuf->strbuf_control); | |
437 | schizo_write(strbuf->strbuf_control, | |
438 | (control | SCHIZO_STRBUF_CTRL_DENAB)); | |
439 | for (i = 0; i < 128; i++) { | |
440 | unsigned long val; | |
441 | ||
442 | val = schizo_read(err_base + (i * 8UL)); | |
443 | schizo_write(err_base + (i * 8UL), 0UL); | |
444 | stc_error_buf[i] = val; | |
445 | } | |
446 | for (i = 0; i < 16; i++) { | |
447 | stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL)); | |
448 | stc_line_buf[i] = schizo_read(line_base + (i * 8UL)); | |
449 | schizo_write(tag_base + (i * 8UL), 0UL); | |
450 | schizo_write(line_base + (i * 8UL), 0UL); | |
451 | } | |
452 | ||
453 | /* OK, state is logged, exit diagnostic mode. */ | |
454 | schizo_write(strbuf->strbuf_control, control); | |
455 | ||
456 | for (i = 0; i < 16; i++) { | |
457 | int j, saw_error, first, last; | |
458 | ||
459 | saw_error = 0; | |
460 | first = i * 8; | |
461 | last = first + 8; | |
462 | for (j = first; j < last; j++) { | |
463 | unsigned long errval = stc_error_buf[j]; | |
464 | if (errval != 0) { | |
465 | saw_error++; | |
466 | printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", | |
467 | pbm->name, | |
468 | j, | |
469 | (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, | |
470 | (errval & SCHIZO_STCERR_READ) ? 1 : 0); | |
471 | } | |
472 | } | |
473 | if (saw_error != 0) { | |
474 | unsigned long tagval = stc_tag_buf[i]; | |
475 | unsigned long lineval = stc_line_buf[i]; | |
476 | printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", | |
477 | pbm->name, | |
478 | i, | |
479 | ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), | |
480 | (tagval & SCHIZO_STCTAG_VPN), | |
481 | ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), | |
482 | ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); | |
483 | ||
484 | /* XXX Should spit out per-bank error information... -DaveM */ | |
485 | printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" | |
486 | "V(%d)FOFN(%d)]\n", | |
487 | pbm->name, | |
488 | i, | |
489 | ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), | |
490 | ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), | |
491 | ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), | |
492 | ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), | |
493 | ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), | |
494 | ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); | |
495 | } | |
496 | } | |
497 | ||
498 | spin_unlock(&stc_buf_lock); | |
499 | } | |
500 | ||
501 | /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous | |
502 | * controller level errors. | |
503 | */ | |
504 | ||
505 | #define SCHIZO_IOMMU_TAG 0xa580UL | |
506 | #define SCHIZO_IOMMU_DATA 0xa600UL | |
507 | ||
508 | #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL | |
509 | #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL | |
510 | #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL | |
511 | #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL | |
512 | #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL | |
513 | #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL | |
514 | #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL | |
515 | ||
516 | #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL | |
517 | #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL | |
518 | #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL | |
519 | ||
520 | static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, | |
521 | enum schizo_error_type type) | |
522 | { | |
523 | struct pci_iommu *iommu = pbm->iommu; | |
524 | unsigned long iommu_tag[16]; | |
525 | unsigned long iommu_data[16]; | |
526 | unsigned long flags; | |
527 | u64 control; | |
528 | int i; | |
529 | ||
530 | spin_lock_irqsave(&iommu->lock, flags); | |
531 | control = schizo_read(iommu->iommu_control); | |
532 | if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { | |
533 | unsigned long base; | |
534 | char *type_string; | |
535 | ||
536 | /* Clear the error encountered bit. */ | |
537 | control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; | |
538 | schizo_write(iommu->iommu_control, control); | |
539 | ||
540 | switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { | |
541 | case 0: | |
542 | type_string = "Protection Error"; | |
543 | break; | |
544 | case 1: | |
545 | type_string = "Invalid Error"; | |
546 | break; | |
547 | case 2: | |
548 | type_string = "TimeOut Error"; | |
549 | break; | |
550 | case 3: | |
551 | default: | |
552 | type_string = "ECC Error"; | |
553 | break; | |
554 | }; | |
555 | printk("%s: IOMMU Error, type[%s]\n", | |
556 | pbm->name, type_string); | |
557 | ||
558 | /* Put the IOMMU into diagnostic mode and probe | |
559 | * it's TLB for entries with error status. | |
560 | * | |
561 | * It is very possible for another DVMA to occur | |
562 | * while we do this probe, and corrupt the system | |
563 | * further. But we are so screwed at this point | |
564 | * that we are likely to crash hard anyways, so | |
565 | * get as much diagnostic information to the | |
566 | * console as we can. | |
567 | */ | |
568 | schizo_write(iommu->iommu_control, | |
569 | control | SCHIZO_IOMMU_CTRL_DENAB); | |
570 | ||
571 | base = pbm->pbm_regs; | |
572 | ||
573 | for (i = 0; i < 16; i++) { | |
574 | iommu_tag[i] = | |
575 | schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL)); | |
576 | iommu_data[i] = | |
577 | schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL)); | |
578 | ||
579 | /* Now clear out the entry. */ | |
580 | schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0); | |
581 | schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0); | |
582 | } | |
583 | ||
584 | /* Leave diagnostic mode. */ | |
585 | schizo_write(iommu->iommu_control, control); | |
586 | ||
587 | for (i = 0; i < 16; i++) { | |
588 | unsigned long tag, data; | |
589 | ||
590 | tag = iommu_tag[i]; | |
591 | if (!(tag & SCHIZO_IOMMU_TAG_ERR)) | |
592 | continue; | |
593 | ||
594 | data = iommu_data[i]; | |
595 | switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { | |
596 | case 0: | |
597 | type_string = "Protection Error"; | |
598 | break; | |
599 | case 1: | |
600 | type_string = "Invalid Error"; | |
601 | break; | |
602 | case 2: | |
603 | type_string = "TimeOut Error"; | |
604 | break; | |
605 | case 3: | |
606 | default: | |
607 | type_string = "ECC Error"; | |
608 | break; | |
609 | }; | |
610 | printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " | |
611 | "sz(%dK) vpg(%08lx)]\n", | |
612 | pbm->name, i, type_string, | |
613 | (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), | |
614 | ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), | |
615 | ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), | |
616 | ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), | |
617 | (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); | |
618 | printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", | |
619 | pbm->name, i, | |
620 | ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), | |
621 | ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), | |
622 | (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); | |
623 | } | |
624 | } | |
625 | if (pbm->stc.strbuf_enabled) | |
626 | __schizo_check_stc_error_pbm(pbm, type); | |
627 | spin_unlock_irqrestore(&iommu->lock, flags); | |
628 | } | |
629 | ||
630 | static void schizo_check_iommu_error(struct pci_controller_info *p, | |
631 | enum schizo_error_type type) | |
632 | { | |
633 | schizo_check_iommu_error_pbm(&p->pbm_A, type); | |
634 | schizo_check_iommu_error_pbm(&p->pbm_B, type); | |
635 | } | |
636 | ||
637 | /* Uncorrectable ECC error status gathering. */ | |
638 | #define SCHIZO_UE_AFSR 0x10030UL | |
639 | #define SCHIZO_UE_AFAR 0x10038UL | |
640 | ||
641 | #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ | |
642 | #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ | |
643 | #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ | |
644 | #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ | |
645 | #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ | |
646 | #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ | |
647 | #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ | |
648 | #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ | |
649 | #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ | |
650 | #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ | |
651 | #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ | |
652 | #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ | |
653 | #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ | |
654 | #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ | |
655 | ||
656 | static irqreturn_t schizo_ue_intr(int irq, void *dev_id, struct pt_regs *regs) | |
657 | { | |
658 | struct pci_controller_info *p = dev_id; | |
659 | unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR; | |
660 | unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR; | |
661 | unsigned long afsr, afar, error_bits; | |
662 | int reported, limit; | |
663 | ||
664 | /* Latch uncorrectable error status. */ | |
665 | afar = schizo_read(afar_reg); | |
666 | ||
667 | /* If either of the error pending bits are set in the | |
668 | * AFSR, the error status is being actively updated by | |
669 | * the hardware and we must re-read to get a clean value. | |
670 | */ | |
671 | limit = 1000; | |
672 | do { | |
673 | afsr = schizo_read(afsr_reg); | |
674 | } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); | |
675 | ||
676 | /* Clear the primary/secondary error status bits. */ | |
677 | error_bits = afsr & | |
678 | (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | | |
679 | SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); | |
680 | if (!error_bits) | |
681 | return IRQ_NONE; | |
682 | schizo_write(afsr_reg, error_bits); | |
683 | ||
684 | /* Log the error. */ | |
685 | printk("PCI%d: Uncorrectable Error, primary error type[%s]\n", | |
686 | p->index, | |
687 | (((error_bits & SCHIZO_UEAFSR_PPIO) ? | |
688 | "PIO" : | |
689 | ((error_bits & SCHIZO_UEAFSR_PDRD) ? | |
690 | "DMA Read" : | |
691 | ((error_bits & SCHIZO_UEAFSR_PDWR) ? | |
692 | "DMA Write" : "???"))))); | |
693 | printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", | |
694 | p->index, | |
695 | (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, | |
696 | (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, | |
697 | (afsr & SCHIZO_UEAFSR_AID) >> 24UL); | |
698 | printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", | |
699 | p->index, | |
700 | (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, | |
701 | (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, | |
702 | (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, | |
703 | (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, | |
704 | (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); | |
705 | printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar); | |
706 | printk("PCI%d: UE Secondary errors [", p->index); | |
707 | reported = 0; | |
708 | if (afsr & SCHIZO_UEAFSR_SPIO) { | |
709 | reported++; | |
710 | printk("(PIO)"); | |
711 | } | |
712 | if (afsr & SCHIZO_UEAFSR_SDMA) { | |
713 | reported++; | |
714 | printk("(DMA)"); | |
715 | } | |
716 | if (!reported) | |
717 | printk("(none)"); | |
718 | printk("]\n"); | |
719 | ||
720 | /* Interrogate IOMMU for error status. */ | |
721 | schizo_check_iommu_error(p, UE_ERR); | |
722 | ||
723 | schizo_clear_other_err_intr(p, irq); | |
724 | ||
725 | return IRQ_HANDLED; | |
726 | } | |
727 | ||
728 | #define SCHIZO_CE_AFSR 0x10040UL | |
729 | #define SCHIZO_CE_AFAR 0x10048UL | |
730 | ||
731 | #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL | |
732 | #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL | |
733 | #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL | |
734 | #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL | |
735 | #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL | |
736 | #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL | |
737 | #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL | |
738 | #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL | |
739 | #define SCHIZO_CEAFSR_AID 0x000000001f000000UL | |
740 | #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL | |
741 | #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL | |
742 | #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL | |
743 | #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL | |
744 | #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL | |
745 | ||
746 | static irqreturn_t schizo_ce_intr(int irq, void *dev_id, struct pt_regs *regs) | |
747 | { | |
748 | struct pci_controller_info *p = dev_id; | |
749 | unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR; | |
750 | unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR; | |
751 | unsigned long afsr, afar, error_bits; | |
752 | int reported, limit; | |
753 | ||
754 | /* Latch error status. */ | |
755 | afar = schizo_read(afar_reg); | |
756 | ||
757 | /* If either of the error pending bits are set in the | |
758 | * AFSR, the error status is being actively updated by | |
759 | * the hardware and we must re-read to get a clean value. | |
760 | */ | |
761 | limit = 1000; | |
762 | do { | |
763 | afsr = schizo_read(afsr_reg); | |
764 | } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); | |
765 | ||
766 | /* Clear primary/secondary error status bits. */ | |
767 | error_bits = afsr & | |
768 | (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | | |
769 | SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); | |
770 | if (!error_bits) | |
771 | return IRQ_NONE; | |
772 | schizo_write(afsr_reg, error_bits); | |
773 | ||
774 | /* Log the error. */ | |
775 | printk("PCI%d: Correctable Error, primary error type[%s]\n", | |
776 | p->index, | |
777 | (((error_bits & SCHIZO_CEAFSR_PPIO) ? | |
778 | "PIO" : | |
779 | ((error_bits & SCHIZO_CEAFSR_PDRD) ? | |
780 | "DMA Read" : | |
781 | ((error_bits & SCHIZO_CEAFSR_PDWR) ? | |
782 | "DMA Write" : "???"))))); | |
783 | ||
784 | /* XXX Use syndrome and afar to print out module string just like | |
785 | * XXX UDB CE trap handler does... -DaveM | |
786 | */ | |
787 | printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", | |
788 | p->index, | |
789 | (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, | |
790 | (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, | |
791 | (afsr & SCHIZO_UEAFSR_AID) >> 24UL); | |
792 | printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", | |
793 | p->index, | |
794 | (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, | |
795 | (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, | |
796 | (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, | |
797 | (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, | |
798 | (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); | |
799 | printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar); | |
800 | printk("PCI%d: CE Secondary errors [", p->index); | |
801 | reported = 0; | |
802 | if (afsr & SCHIZO_CEAFSR_SPIO) { | |
803 | reported++; | |
804 | printk("(PIO)"); | |
805 | } | |
806 | if (afsr & SCHIZO_CEAFSR_SDMA) { | |
807 | reported++; | |
808 | printk("(DMA)"); | |
809 | } | |
810 | if (!reported) | |
811 | printk("(none)"); | |
812 | printk("]\n"); | |
813 | ||
814 | schizo_clear_other_err_intr(p, irq); | |
815 | ||
816 | return IRQ_HANDLED; | |
817 | } | |
818 | ||
819 | #define SCHIZO_PCI_AFSR 0x2010UL | |
820 | #define SCHIZO_PCI_AFAR 0x2018UL | |
821 | ||
822 | #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ | |
823 | #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ | |
824 | #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ | |
825 | #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ | |
826 | #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ | |
827 | #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ | |
828 | #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ | |
829 | #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ | |
830 | #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ | |
831 | #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ | |
832 | #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ | |
833 | #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ | |
834 | #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ | |
835 | #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ | |
836 | #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ | |
837 | #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ | |
838 | #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ | |
839 | ||
840 | #define SCHIZO_PCI_CTRL (0x2000UL) | |
841 | #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ | |
9fba62a5 | 842 | #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ |
1da177e4 LT |
843 | #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ |
844 | #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ | |
845 | #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ | |
846 | #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ | |
847 | #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ | |
848 | #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ | |
849 | #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ | |
850 | #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ | |
851 | #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ | |
852 | #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ | |
853 | #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ | |
854 | #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ | |
855 | #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ | |
856 | #define SCHIZO_PCICTRL_PTO_SHIFT 24UL | |
857 | #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ | |
858 | #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ | |
859 | #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ | |
860 | #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ | |
861 | #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ | |
862 | #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ | |
863 | #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ | |
864 | #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ | |
865 | #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ | |
866 | #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ | |
867 | #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ | |
868 | ||
869 | static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) | |
870 | { | |
871 | unsigned long csr_reg, csr, csr_error_bits; | |
872 | irqreturn_t ret = IRQ_NONE; | |
873 | u16 stat; | |
874 | ||
875 | csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; | |
876 | csr = schizo_read(csr_reg); | |
877 | csr_error_bits = | |
878 | csr & (SCHIZO_PCICTRL_BUS_UNUS | | |
879 | SCHIZO_PCICTRL_TTO_ERR | | |
880 | SCHIZO_PCICTRL_RTRY_ERR | | |
881 | SCHIZO_PCICTRL_DTO_ERR | | |
882 | SCHIZO_PCICTRL_SBH_ERR | | |
883 | SCHIZO_PCICTRL_SERR); | |
884 | if (csr_error_bits) { | |
885 | /* Clear the errors. */ | |
886 | schizo_write(csr_reg, csr); | |
887 | ||
888 | /* Log 'em. */ | |
889 | if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) | |
890 | printk("%s: Bus unusable error asserted.\n", | |
891 | pbm->name); | |
892 | if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) | |
893 | printk("%s: PCI TRDY# timeout error asserted.\n", | |
894 | pbm->name); | |
895 | if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) | |
896 | printk("%s: PCI excessive retry error asserted.\n", | |
897 | pbm->name); | |
898 | if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) | |
899 | printk("%s: PCI discard timeout error asserted.\n", | |
900 | pbm->name); | |
901 | if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) | |
902 | printk("%s: PCI streaming byte hole error asserted.\n", | |
903 | pbm->name); | |
904 | if (csr_error_bits & SCHIZO_PCICTRL_SERR) | |
905 | printk("%s: PCI SERR signal asserted.\n", | |
906 | pbm->name); | |
907 | ret = IRQ_HANDLED; | |
908 | } | |
909 | pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); | |
910 | if (stat & (PCI_STATUS_PARITY | | |
911 | PCI_STATUS_SIG_TARGET_ABORT | | |
912 | PCI_STATUS_REC_TARGET_ABORT | | |
913 | PCI_STATUS_REC_MASTER_ABORT | | |
914 | PCI_STATUS_SIG_SYSTEM_ERROR)) { | |
915 | printk("%s: PCI bus error, PCI_STATUS[%04x]\n", | |
916 | pbm->name, stat); | |
917 | pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); | |
918 | ret = IRQ_HANDLED; | |
919 | } | |
920 | return ret; | |
921 | } | |
922 | ||
923 | static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs) | |
924 | { | |
925 | struct pci_pbm_info *pbm = dev_id; | |
926 | struct pci_controller_info *p = pbm->parent; | |
927 | unsigned long afsr_reg, afar_reg, base; | |
928 | unsigned long afsr, afar, error_bits; | |
929 | int reported; | |
930 | ||
931 | base = pbm->pbm_regs; | |
932 | ||
933 | afsr_reg = base + SCHIZO_PCI_AFSR; | |
934 | afar_reg = base + SCHIZO_PCI_AFAR; | |
935 | ||
936 | /* Latch error status. */ | |
937 | afar = schizo_read(afar_reg); | |
938 | afsr = schizo_read(afsr_reg); | |
939 | ||
940 | /* Clear primary/secondary error status bits. */ | |
941 | error_bits = afsr & | |
942 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
943 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
944 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | | |
945 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
946 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
947 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); | |
948 | if (!error_bits) | |
949 | return schizo_pcierr_intr_other(pbm); | |
950 | schizo_write(afsr_reg, error_bits); | |
951 | ||
952 | /* Log the error. */ | |
953 | printk("%s: PCI Error, primary error type[%s]\n", | |
954 | pbm->name, | |
955 | (((error_bits & SCHIZO_PCIAFSR_PMA) ? | |
956 | "Master Abort" : | |
957 | ((error_bits & SCHIZO_PCIAFSR_PTA) ? | |
958 | "Target Abort" : | |
959 | ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? | |
960 | "Excessive Retries" : | |
961 | ((error_bits & SCHIZO_PCIAFSR_PPERR) ? | |
962 | "Parity Error" : | |
963 | ((error_bits & SCHIZO_PCIAFSR_PTTO) ? | |
964 | "Timeout" : | |
965 | ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? | |
966 | "Bus Unusable" : "???")))))))); | |
967 | printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", | |
968 | pbm->name, | |
969 | (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, | |
970 | (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, | |
971 | ((afsr & SCHIZO_PCIAFSR_CFG) ? | |
972 | "Config" : | |
973 | ((afsr & SCHIZO_PCIAFSR_MEM) ? | |
974 | "Memory" : | |
975 | ((afsr & SCHIZO_PCIAFSR_IO) ? | |
976 | "I/O" : "???")))); | |
977 | printk("%s: PCI AFAR [%016lx]\n", | |
978 | pbm->name, afar); | |
979 | printk("%s: PCI Secondary errors [", | |
980 | pbm->name); | |
981 | reported = 0; | |
982 | if (afsr & SCHIZO_PCIAFSR_SMA) { | |
983 | reported++; | |
984 | printk("(Master Abort)"); | |
985 | } | |
986 | if (afsr & SCHIZO_PCIAFSR_STA) { | |
987 | reported++; | |
988 | printk("(Target Abort)"); | |
989 | } | |
990 | if (afsr & SCHIZO_PCIAFSR_SRTRY) { | |
991 | reported++; | |
992 | printk("(Excessive Retries)"); | |
993 | } | |
994 | if (afsr & SCHIZO_PCIAFSR_SPERR) { | |
995 | reported++; | |
996 | printk("(Parity Error)"); | |
997 | } | |
998 | if (afsr & SCHIZO_PCIAFSR_STTO) { | |
999 | reported++; | |
1000 | printk("(Timeout)"); | |
1001 | } | |
1002 | if (afsr & SCHIZO_PCIAFSR_SUNUS) { | |
1003 | reported++; | |
1004 | printk("(Bus Unusable)"); | |
1005 | } | |
1006 | if (!reported) | |
1007 | printk("(none)"); | |
1008 | printk("]\n"); | |
1009 | ||
1010 | /* For the error types shown, scan PBM's PCI bus for devices | |
1011 | * which have logged that error type. | |
1012 | */ | |
1013 | ||
1014 | /* If we see a Target Abort, this could be the result of an | |
1015 | * IOMMU translation error of some sort. It is extremely | |
1016 | * useful to log this information as usually it indicates | |
1017 | * a bug in the IOMMU support code or a PCI device driver. | |
1018 | */ | |
1019 | if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { | |
1020 | schizo_check_iommu_error(p, PCI_ERR); | |
1021 | pci_scan_for_target_abort(p, pbm, pbm->pci_bus); | |
1022 | } | |
1023 | if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) | |
1024 | pci_scan_for_master_abort(p, pbm, pbm->pci_bus); | |
1025 | ||
1026 | /* For excessive retries, PSYCHO/PBM will abort the device | |
1027 | * and there is no way to specifically check for excessive | |
1028 | * retries in the config space status registers. So what | |
1029 | * we hope is that we'll catch it via the master/target | |
1030 | * abort events. | |
1031 | */ | |
1032 | ||
1033 | if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) | |
1034 | pci_scan_for_parity_error(p, pbm, pbm->pci_bus); | |
1035 | ||
1036 | schizo_clear_other_err_intr(p, irq); | |
1037 | ||
1038 | return IRQ_HANDLED; | |
1039 | } | |
1040 | ||
1041 | #define SCHIZO_SAFARI_ERRLOG 0x10018UL | |
1042 | ||
1043 | #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL | |
1044 | ||
1045 | #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ | |
1046 | #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ | |
1047 | #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ | |
1048 | #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ | |
1049 | #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ | |
1050 | #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ | |
1051 | #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ | |
1052 | #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ | |
1053 | #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ | |
1054 | #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ | |
1055 | #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ | |
1056 | #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ | |
1057 | #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ | |
1058 | #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ | |
1059 | #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ | |
1060 | #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ | |
1061 | #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ | |
1062 | #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ | |
1063 | #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ | |
1064 | #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ | |
1065 | #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ | |
1066 | #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ | |
1067 | #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ | |
1068 | #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ | |
1069 | #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ | |
1070 | #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ | |
1071 | #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ | |
1072 | #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ | |
1073 | #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ | |
1074 | #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ | |
1075 | #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ | |
1076 | ||
1077 | /* We only expect UNMAP errors here. The rest of the Safari errors | |
1078 | * are marked fatal and thus cause a system reset. | |
1079 | */ | |
1080 | static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1081 | { | |
1082 | struct pci_controller_info *p = dev_id; | |
1083 | u64 errlog; | |
1084 | ||
1085 | errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG); | |
1086 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG, | |
1087 | errlog & ~(SAFARI_ERRLOG_ERROUT)); | |
1088 | ||
1089 | if (!(errlog & BUS_ERROR_UNMAP)) { | |
1090 | printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n", | |
1091 | p->index, errlog); | |
1092 | ||
1093 | schizo_clear_other_err_intr(p, irq); | |
1094 | return IRQ_HANDLED; | |
1095 | } | |
1096 | ||
1097 | printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", | |
1098 | p->index); | |
1099 | schizo_check_iommu_error(p, SAFARI_ERR); | |
1100 | ||
1101 | schizo_clear_other_err_intr(p, irq); | |
1102 | return IRQ_HANDLED; | |
1103 | } | |
1104 | ||
1105 | /* Nearly identical to PSYCHO equivalents... */ | |
1106 | #define SCHIZO_ECC_CTRL 0x10020UL | |
1107 | #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ | |
1108 | #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ | |
1109 | #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ | |
1110 | ||
1111 | #define SCHIZO_SAFARI_ERRCTRL 0x10008UL | |
1112 | #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL | |
1113 | #define SCHIZO_SAFARI_IRQCTRL 0x10010UL | |
1114 | #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL | |
1115 | ||
1116 | /* How the Tomatillo IRQs are routed around is pure guesswork here. | |
1117 | * | |
1118 | * All the Tomatillo devices I see in prtconf dumps seem to have only | |
1119 | * a single PCI bus unit attached to it. It would seem they are seperate | |
1120 | * devices because their PortID (ie. JBUS ID) values are all different | |
1121 | * and thus the registers are mapped to totally different locations. | |
1122 | * | |
1123 | * However, two Tomatillo's look "similar" in that the only difference | |
1124 | * in their PortID is the lowest bit. | |
1125 | * | |
1126 | * So if we were to ignore this lower bit, it certainly looks like two | |
1127 | * PCI bus units of the same Tomatillo. I still have not really | |
1128 | * figured this out... | |
1129 | */ | |
085ae41f | 1130 | static void tomatillo_register_error_handlers(struct pci_controller_info *p) |
1da177e4 LT |
1131 | { |
1132 | struct pci_pbm_info *pbm; | |
1133 | unsigned int irq; | |
1da177e4 LT |
1134 | u64 tmp, err_mask, err_no_mask; |
1135 | ||
1136 | /* Build IRQs and register handlers. */ | |
1137 | pbm = pbm_for_ino(p, SCHIZO_UE_INO); | |
1138 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO); | |
1139 | if (request_irq(irq, schizo_ue_intr, | |
1140 | SA_SHIRQ, "TOMATILLO UE", p) < 0) { | |
1141 | prom_printf("%s: Cannot register UE interrupt.\n", | |
1142 | pbm->name); | |
1143 | prom_halt(); | |
1144 | } | |
8047e247 | 1145 | tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO)); |
1da177e4 LT |
1146 | upa_writel(tmp, (pbm->pbm_regs + |
1147 | schizo_imap_offset(SCHIZO_UE_INO) + 4)); | |
1148 | ||
1149 | pbm = pbm_for_ino(p, SCHIZO_CE_INO); | |
1150 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO); | |
1151 | if (request_irq(irq, schizo_ce_intr, | |
1152 | SA_SHIRQ, "TOMATILLO CE", p) < 0) { | |
1153 | prom_printf("%s: Cannot register CE interrupt.\n", | |
1154 | pbm->name); | |
1155 | prom_halt(); | |
1156 | } | |
8047e247 | 1157 | tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO)); |
1da177e4 LT |
1158 | upa_writel(tmp, (pbm->pbm_regs + |
1159 | schizo_imap_offset(SCHIZO_CE_INO) + 4)); | |
1160 | ||
1161 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); | |
1162 | irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) | | |
1163 | SCHIZO_PCIERR_A_INO)); | |
1164 | if (request_irq(irq, schizo_pcierr_intr, | |
1165 | SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) { | |
1166 | prom_printf("%s: Cannot register PBM A PciERR interrupt.\n", | |
1167 | pbm->name); | |
1168 | prom_halt(); | |
1169 | } | |
8047e247 DM |
1170 | tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) | |
1171 | SCHIZO_PCIERR_A_INO))); | |
1da177e4 LT |
1172 | upa_writel(tmp, (pbm->pbm_regs + |
1173 | schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4)); | |
1174 | ||
1175 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); | |
1176 | irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) | | |
1177 | SCHIZO_PCIERR_B_INO)); | |
1178 | if (request_irq(irq, schizo_pcierr_intr, | |
1179 | SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) { | |
1180 | prom_printf("%s: Cannot register PBM B PciERR interrupt.\n", | |
1181 | pbm->name); | |
1182 | prom_halt(); | |
1183 | } | |
8047e247 DM |
1184 | tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) | |
1185 | SCHIZO_PCIERR_B_INO))); | |
1da177e4 LT |
1186 | upa_writel(tmp, (pbm->pbm_regs + |
1187 | schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4)); | |
1188 | ||
1189 | pbm = pbm_for_ino(p, SCHIZO_SERR_INO); | |
1190 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO); | |
1191 | if (request_irq(irq, schizo_safarierr_intr, | |
1192 | SA_SHIRQ, "TOMATILLO SERR", p) < 0) { | |
1193 | prom_printf("%s: Cannot register SafariERR interrupt.\n", | |
1194 | pbm->name); | |
1195 | prom_halt(); | |
1196 | } | |
8047e247 DM |
1197 | tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) | |
1198 | SCHIZO_SERR_INO))); | |
1da177e4 LT |
1199 | upa_writel(tmp, (pbm->pbm_regs + |
1200 | schizo_imap_offset(SCHIZO_SERR_INO) + 4)); | |
1201 | ||
1202 | /* Enable UE and CE interrupts for controller. */ | |
1203 | schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, | |
1204 | (SCHIZO_ECCCTRL_EE | | |
1205 | SCHIZO_ECCCTRL_UE | | |
1206 | SCHIZO_ECCCTRL_CE)); | |
1207 | ||
1208 | schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL, | |
1209 | (SCHIZO_ECCCTRL_EE | | |
1210 | SCHIZO_ECCCTRL_UE | | |
1211 | SCHIZO_ECCCTRL_CE)); | |
1212 | ||
1213 | /* Enable PCI Error interrupts and clear error | |
1214 | * bits. | |
1215 | */ | |
1216 | err_mask = (SCHIZO_PCICTRL_BUS_UNUS | | |
1217 | SCHIZO_PCICTRL_TTO_ERR | | |
1218 | SCHIZO_PCICTRL_RTRY_ERR | | |
1219 | SCHIZO_PCICTRL_SERR | | |
1220 | SCHIZO_PCICTRL_EEN); | |
1221 | ||
1222 | err_no_mask = SCHIZO_PCICTRL_DTO_ERR; | |
1223 | ||
1224 | tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); | |
1225 | tmp |= err_mask; | |
1226 | tmp &= ~err_no_mask; | |
1227 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1228 | ||
1229 | tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL); | |
1230 | tmp |= err_mask; | |
1231 | tmp &= ~err_no_mask; | |
1232 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1233 | ||
1234 | err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
1235 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
1236 | SCHIZO_PCIAFSR_PTTO | | |
1237 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
1238 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
1239 | SCHIZO_PCIAFSR_STTO); | |
1240 | ||
1241 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask); | |
1242 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask); | |
1243 | ||
1244 | err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | | |
1245 | BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | | |
1246 | BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | | |
1247 | BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | | |
1248 | BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | | |
1249 | BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | | |
1250 | BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | | |
1251 | BUS_ERROR_APERR | BUS_ERROR_UNMAP | | |
1252 | BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); | |
1253 | ||
1254 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, | |
1255 | (SCHIZO_SAFERRCTRL_EN | err_mask)); | |
1256 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL, | |
1257 | (SCHIZO_SAFERRCTRL_EN | err_mask)); | |
1258 | ||
1259 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL, | |
1260 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); | |
1261 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL, | |
1262 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); | |
1263 | } | |
1264 | ||
085ae41f | 1265 | static void schizo_register_error_handlers(struct pci_controller_info *p) |
1da177e4 LT |
1266 | { |
1267 | struct pci_pbm_info *pbm; | |
1268 | unsigned int irq; | |
1da177e4 LT |
1269 | u64 tmp, err_mask, err_no_mask; |
1270 | ||
1271 | /* Build IRQs and register handlers. */ | |
1272 | pbm = pbm_for_ino(p, SCHIZO_UE_INO); | |
1273 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO); | |
1274 | if (request_irq(irq, schizo_ue_intr, | |
1275 | SA_SHIRQ, "SCHIZO UE", p) < 0) { | |
1276 | prom_printf("%s: Cannot register UE interrupt.\n", | |
1277 | pbm->name); | |
1278 | prom_halt(); | |
1279 | } | |
8047e247 | 1280 | tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO)); |
1da177e4 LT |
1281 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4)); |
1282 | ||
1283 | pbm = pbm_for_ino(p, SCHIZO_CE_INO); | |
1284 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO); | |
1285 | if (request_irq(irq, schizo_ce_intr, | |
1286 | SA_SHIRQ, "SCHIZO CE", p) < 0) { | |
1287 | prom_printf("%s: Cannot register CE interrupt.\n", | |
1288 | pbm->name); | |
1289 | prom_halt(); | |
1290 | } | |
8047e247 | 1291 | tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO)); |
1da177e4 LT |
1292 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4)); |
1293 | ||
1294 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); | |
1295 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO); | |
1296 | if (request_irq(irq, schizo_pcierr_intr, | |
1297 | SA_SHIRQ, "SCHIZO PCIERR", pbm) < 0) { | |
1298 | prom_printf("%s: Cannot register PBM A PciERR interrupt.\n", | |
1299 | pbm->name); | |
1300 | prom_halt(); | |
1301 | } | |
8047e247 | 1302 | tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO)); |
1da177e4 LT |
1303 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4)); |
1304 | ||
1305 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); | |
1306 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO); | |
1307 | if (request_irq(irq, schizo_pcierr_intr, | |
1308 | SA_SHIRQ, "SCHIZO PCIERR", &p->pbm_B) < 0) { | |
1309 | prom_printf("%s: Cannot register PBM B PciERR interrupt.\n", | |
1310 | pbm->name); | |
1311 | prom_halt(); | |
1312 | } | |
8047e247 | 1313 | tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO)); |
1da177e4 LT |
1314 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4)); |
1315 | ||
1316 | pbm = pbm_for_ino(p, SCHIZO_SERR_INO); | |
1317 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO); | |
1318 | if (request_irq(irq, schizo_safarierr_intr, | |
1319 | SA_SHIRQ, "SCHIZO SERR", p) < 0) { | |
1320 | prom_printf("%s: Cannot register SafariERR interrupt.\n", | |
1321 | pbm->name); | |
1322 | prom_halt(); | |
1323 | } | |
8047e247 | 1324 | tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_SERR_INO)); |
1da177e4 LT |
1325 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4)); |
1326 | ||
1327 | /* Enable UE and CE interrupts for controller. */ | |
1328 | schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, | |
1329 | (SCHIZO_ECCCTRL_EE | | |
1330 | SCHIZO_ECCCTRL_UE | | |
1331 | SCHIZO_ECCCTRL_CE)); | |
1332 | ||
1333 | err_mask = (SCHIZO_PCICTRL_BUS_UNUS | | |
1334 | SCHIZO_PCICTRL_ESLCK | | |
1335 | SCHIZO_PCICTRL_TTO_ERR | | |
1336 | SCHIZO_PCICTRL_RTRY_ERR | | |
1337 | SCHIZO_PCICTRL_SBH_ERR | | |
1338 | SCHIZO_PCICTRL_SERR | | |
1339 | SCHIZO_PCICTRL_EEN); | |
1340 | ||
1341 | err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | | |
1342 | SCHIZO_PCICTRL_SBH_INT); | |
1343 | ||
1344 | /* Enable PCI Error interrupts and clear error | |
1345 | * bits for each PBM. | |
1346 | */ | |
1347 | tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); | |
1348 | tmp |= err_mask; | |
1349 | tmp &= ~err_no_mask; | |
1350 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1351 | ||
1352 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, | |
1353 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
1354 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
1355 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | | |
1356 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
1357 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
1358 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); | |
1359 | ||
1360 | tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL); | |
1361 | tmp |= err_mask; | |
1362 | tmp &= ~err_no_mask; | |
1363 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1364 | ||
1365 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, | |
1366 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
1367 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
1368 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | | |
1369 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
1370 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
1371 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); | |
1372 | ||
1373 | /* Make all Safari error conditions fatal except unmapped | |
1374 | * errors which we make generate interrupts. | |
1375 | */ | |
1376 | err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | | |
1377 | BUS_ERROR_BADMA | BUS_ERROR_BADMB | | |
1378 | BUS_ERROR_BADMC | | |
1379 | BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | | |
1380 | BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | | |
1381 | BUS_ERROR_CIQTO | | |
1382 | BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | | |
1383 | BUS_ERROR_UFPQTO | BUS_ERROR_APERR | | |
1384 | BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | | |
1385 | BUS_ERROR_ILL); | |
1386 | #if 1 | |
1387 | /* XXX Something wrong with some Excalibur systems | |
1388 | * XXX Sun is shipping. The behavior on a 2-cpu | |
1389 | * XXX machine is that both CPU1 parity error bits | |
1390 | * XXX are set and are immediately set again when | |
1391 | * XXX their error status bits are cleared. Just | |
1392 | * XXX ignore them for now. -DaveM | |
1393 | */ | |
1394 | err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | | |
1395 | BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); | |
1396 | #endif | |
1397 | ||
1398 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, | |
1399 | (SCHIZO_SAFERRCTRL_EN | err_mask)); | |
1400 | ||
1401 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL, | |
1402 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); | |
1403 | } | |
1404 | ||
085ae41f | 1405 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
1da177e4 LT |
1406 | { |
1407 | u8 *addr; | |
1408 | ||
1409 | /* Set cache-line size to 64 bytes, this is actually | |
1410 | * a nop but I do it for completeness. | |
1411 | */ | |
1412 | addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
1413 | 0, PCI_CACHE_LINE_SIZE); | |
1414 | pci_config_write8(addr, 64 / sizeof(u32)); | |
1415 | ||
1416 | /* Set PBM latency timer to 64 PCI clocks. */ | |
1417 | addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
1418 | 0, PCI_LATENCY_TIMER); | |
1419 | pci_config_write8(addr, 64); | |
1420 | } | |
1421 | ||
085ae41f DM |
1422 | static void pbm_scan_bus(struct pci_controller_info *p, |
1423 | struct pci_pbm_info *pbm) | |
1da177e4 | 1424 | { |
9132983a | 1425 | struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); |
1da177e4 LT |
1426 | |
1427 | if (!cookie) { | |
1428 | prom_printf("%s: Critical allocation failure.\n", pbm->name); | |
1429 | prom_halt(); | |
1430 | } | |
1431 | ||
1432 | /* All we care about is the PBM. */ | |
1da177e4 LT |
1433 | cookie->pbm = pbm; |
1434 | ||
1435 | pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, | |
1436 | p->pci_ops, | |
1437 | pbm); | |
1438 | pci_fixup_host_bridge_self(pbm->pci_bus); | |
1439 | pbm->pci_bus->self->sysdata = cookie; | |
1440 | ||
e87dc350 | 1441 | pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node->node); |
1da177e4 LT |
1442 | pci_record_assignments(pbm, pbm->pci_bus); |
1443 | pci_assign_unassigned(pbm, pbm->pci_bus); | |
1444 | pci_fixup_irq(pbm, pbm->pci_bus); | |
1445 | pci_determine_66mhz_disposition(pbm, pbm->pci_bus); | |
1446 | pci_setup_busmastering(pbm, pbm->pci_bus); | |
1447 | } | |
1448 | ||
085ae41f DM |
1449 | static void __schizo_scan_bus(struct pci_controller_info *p, |
1450 | int chip_type) | |
1da177e4 LT |
1451 | { |
1452 | if (!p->pbm_B.prom_node || !p->pbm_A.prom_node) { | |
1453 | printk("PCI: Only one PCI bus module of controller found.\n"); | |
1454 | printk("PCI: Ignoring entire controller.\n"); | |
1455 | return; | |
1456 | } | |
1457 | ||
1458 | pbm_config_busmastering(&p->pbm_B); | |
1459 | p->pbm_B.is_66mhz_capable = | |
e87dc350 DM |
1460 | (of_find_property(p->pbm_B.prom_node, "66mhz-capable", NULL) |
1461 | != NULL); | |
1da177e4 LT |
1462 | pbm_config_busmastering(&p->pbm_A); |
1463 | p->pbm_A.is_66mhz_capable = | |
e87dc350 DM |
1464 | (of_find_property(p->pbm_A.prom_node, "66mhz-capable", NULL) |
1465 | != NULL); | |
1da177e4 LT |
1466 | pbm_scan_bus(p, &p->pbm_B); |
1467 | pbm_scan_bus(p, &p->pbm_A); | |
1468 | ||
1469 | /* After the PCI bus scan is complete, we can register | |
1470 | * the error interrupt handlers. | |
1471 | */ | |
1472 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) | |
1473 | tomatillo_register_error_handlers(p); | |
1474 | else | |
1475 | schizo_register_error_handlers(p); | |
1476 | } | |
1477 | ||
085ae41f | 1478 | static void schizo_scan_bus(struct pci_controller_info *p) |
1da177e4 LT |
1479 | { |
1480 | __schizo_scan_bus(p, PBM_CHIP_TYPE_SCHIZO); | |
1481 | } | |
1482 | ||
085ae41f | 1483 | static void tomatillo_scan_bus(struct pci_controller_info *p) |
1da177e4 LT |
1484 | { |
1485 | __schizo_scan_bus(p, PBM_CHIP_TYPE_TOMATILLO); | |
1486 | } | |
1487 | ||
085ae41f | 1488 | static void schizo_base_address_update(struct pci_dev *pdev, int resource) |
1da177e4 LT |
1489 | { |
1490 | struct pcidev_cookie *pcp = pdev->sysdata; | |
1491 | struct pci_pbm_info *pbm = pcp->pbm; | |
1492 | struct resource *res, *root; | |
1493 | u32 reg; | |
1494 | int where, size, is_64bit; | |
1495 | ||
1496 | res = &pdev->resource[resource]; | |
1497 | if (resource < 6) { | |
1498 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | |
1499 | } else if (resource == PCI_ROM_RESOURCE) { | |
1500 | where = pdev->rom_base_reg; | |
1501 | } else { | |
1502 | /* Somebody might have asked allocation of a non-standard resource */ | |
1503 | return; | |
1504 | } | |
1505 | ||
1506 | is_64bit = 0; | |
1507 | if (res->flags & IORESOURCE_IO) | |
1508 | root = &pbm->io_space; | |
1509 | else { | |
1510 | root = &pbm->mem_space; | |
1511 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | |
1512 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | |
1513 | is_64bit = 1; | |
1514 | } | |
1515 | ||
1516 | size = res->end - res->start; | |
1517 | pci_read_config_dword(pdev, where, ®); | |
1518 | reg = ((reg & size) | | |
1519 | (((u32)(res->start - root->start)) & ~size)); | |
1520 | if (resource == PCI_ROM_RESOURCE) { | |
1521 | reg |= PCI_ROM_ADDRESS_ENABLE; | |
1522 | res->flags |= IORESOURCE_ROM_ENABLE; | |
1523 | } | |
1524 | pci_write_config_dword(pdev, where, reg); | |
1525 | ||
1526 | /* This knows that the upper 32-bits of the address | |
1527 | * must be zero. Our PCI common layer enforces this. | |
1528 | */ | |
1529 | if (is_64bit) | |
1530 | pci_write_config_dword(pdev, where + 4, 0); | |
1531 | } | |
1532 | ||
085ae41f DM |
1533 | static void schizo_resource_adjust(struct pci_dev *pdev, |
1534 | struct resource *res, | |
1535 | struct resource *root) | |
1da177e4 LT |
1536 | { |
1537 | res->start += root->start; | |
1538 | res->end += root->start; | |
1539 | } | |
1540 | ||
1541 | /* Use ranges property to determine where PCI MEM, I/O, and Config | |
1542 | * space are for this PCI bus module. | |
1543 | */ | |
1544 | static void schizo_determine_mem_io_space(struct pci_pbm_info *pbm) | |
1545 | { | |
1546 | int i, saw_cfg, saw_mem, saw_io; | |
1547 | ||
1548 | saw_cfg = saw_mem = saw_io = 0; | |
1549 | for (i = 0; i < pbm->num_pbm_ranges; i++) { | |
1550 | struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i]; | |
1551 | unsigned long a; | |
1552 | int type; | |
1553 | ||
1554 | type = (pr->child_phys_hi >> 24) & 0x3; | |
1555 | a = (((unsigned long)pr->parent_phys_hi << 32UL) | | |
1556 | ((unsigned long)pr->parent_phys_lo << 0UL)); | |
1557 | ||
1558 | switch (type) { | |
1559 | case 0: | |
1560 | /* PCI config space, 16MB */ | |
1561 | pbm->config_space = a; | |
1562 | saw_cfg = 1; | |
1563 | break; | |
1564 | ||
1565 | case 1: | |
1566 | /* 16-bit IO space, 16MB */ | |
1567 | pbm->io_space.start = a; | |
1568 | pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL); | |
1569 | pbm->io_space.flags = IORESOURCE_IO; | |
1570 | saw_io = 1; | |
1571 | break; | |
1572 | ||
1573 | case 2: | |
1574 | /* 32-bit MEM space, 2GB */ | |
1575 | pbm->mem_space.start = a; | |
1576 | pbm->mem_space.end = a + (0x80000000UL - 1UL); | |
1577 | pbm->mem_space.flags = IORESOURCE_MEM; | |
1578 | saw_mem = 1; | |
1579 | break; | |
1580 | ||
1581 | default: | |
1582 | break; | |
1583 | }; | |
1584 | } | |
1585 | ||
1586 | if (!saw_cfg || !saw_io || !saw_mem) { | |
1587 | prom_printf("%s: Fatal error, missing %s PBM range.\n", | |
1588 | pbm->name, | |
1589 | ((!saw_cfg ? | |
1590 | "CFG" : | |
1591 | (!saw_io ? | |
1592 | "IO" : "MEM")))); | |
1593 | prom_halt(); | |
1594 | } | |
1595 | ||
1596 | printk("%s: PCI CFG[%lx] IO[%lx] MEM[%lx]\n", | |
1597 | pbm->name, | |
1598 | pbm->config_space, | |
1599 | pbm->io_space.start, | |
1600 | pbm->mem_space.start); | |
1601 | } | |
1602 | ||
085ae41f DM |
1603 | static void pbm_register_toplevel_resources(struct pci_controller_info *p, |
1604 | struct pci_pbm_info *pbm) | |
1da177e4 LT |
1605 | { |
1606 | pbm->io_space.name = pbm->mem_space.name = pbm->name; | |
1607 | ||
1608 | request_resource(&ioport_resource, &pbm->io_space); | |
1609 | request_resource(&iomem_resource, &pbm->mem_space); | |
1610 | pci_register_legacy_regions(&pbm->io_space, | |
1611 | &pbm->mem_space); | |
1612 | } | |
1613 | ||
1614 | #define SCHIZO_STRBUF_CONTROL (0x02800UL) | |
1615 | #define SCHIZO_STRBUF_FLUSH (0x02808UL) | |
1616 | #define SCHIZO_STRBUF_FSYNC (0x02810UL) | |
1617 | #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) | |
1618 | #define SCHIZO_STRBUF_CTXMATCH (0x10000UL) | |
1619 | ||
1620 | static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) | |
1621 | { | |
1622 | unsigned long base = pbm->pbm_regs; | |
1623 | u64 control; | |
1624 | ||
1625 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
1626 | /* TOMATILLO lacks streaming cache. */ | |
1627 | return; | |
1628 | } | |
1629 | ||
1630 | /* SCHIZO has context flushing. */ | |
1631 | pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; | |
1632 | pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; | |
1633 | pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; | |
1634 | pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; | |
1635 | pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; | |
1636 | ||
1637 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) | |
1638 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) | |
1639 | + 63UL) | |
1640 | & ~63UL); | |
1641 | pbm->stc.strbuf_flushflag_pa = (unsigned long) | |
1642 | __pa(pbm->stc.strbuf_flushflag); | |
1643 | ||
1644 | /* Turn off LRU locking and diag mode, enable the | |
1645 | * streaming buffer and leave the rerun-disable | |
1646 | * setting however OBP set it. | |
1647 | */ | |
1648 | control = schizo_read(pbm->stc.strbuf_control); | |
1649 | control &= ~(SCHIZO_STRBUF_CTRL_LPTR | | |
1650 | SCHIZO_STRBUF_CTRL_LENAB | | |
1651 | SCHIZO_STRBUF_CTRL_DENAB); | |
1652 | control |= SCHIZO_STRBUF_CTRL_ENAB; | |
1653 | schizo_write(pbm->stc.strbuf_control, control); | |
1654 | ||
1655 | pbm->stc.strbuf_enabled = 1; | |
1656 | } | |
1657 | ||
1658 | #define SCHIZO_IOMMU_CONTROL (0x00200UL) | |
1659 | #define SCHIZO_IOMMU_TSBBASE (0x00208UL) | |
1660 | #define SCHIZO_IOMMU_FLUSH (0x00210UL) | |
1661 | #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) | |
1662 | ||
1663 | static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm) | |
1664 | { | |
1665 | struct pci_iommu *iommu = pbm->iommu; | |
51e85136 | 1666 | unsigned long i, tagbase, database; |
e87dc350 | 1667 | struct property *prop; |
1da177e4 LT |
1668 | u32 vdma[2], dma_mask; |
1669 | u64 control; | |
e87dc350 | 1670 | int tsbsize; |
1da177e4 | 1671 | |
e87dc350 DM |
1672 | prop = of_find_property(pbm->prom_node, "virtual-dma", NULL); |
1673 | if (prop) { | |
1674 | u32 *val = prop->value; | |
1675 | ||
1676 | vdma[0] = val[0]; | |
1677 | vdma[1] = val[1]; | |
1678 | } else { | |
1da177e4 LT |
1679 | /* No property, use default values. */ |
1680 | vdma[0] = 0xc0000000; | |
1681 | vdma[1] = 0x40000000; | |
1682 | } | |
1683 | ||
1684 | dma_mask = vdma[0]; | |
1685 | switch (vdma[1]) { | |
1686 | case 0x20000000: | |
1687 | dma_mask |= 0x1fffffff; | |
1688 | tsbsize = 64; | |
1689 | break; | |
1690 | ||
1691 | case 0x40000000: | |
1692 | dma_mask |= 0x3fffffff; | |
1693 | tsbsize = 128; | |
1694 | break; | |
1695 | ||
1696 | case 0x80000000: | |
1697 | dma_mask |= 0x7fffffff; | |
1698 | tsbsize = 128; | |
1699 | break; | |
1700 | ||
1701 | default: | |
1702 | prom_printf("SCHIZO: strange virtual-dma size.\n"); | |
1703 | prom_halt(); | |
1704 | }; | |
1705 | ||
1da177e4 LT |
1706 | /* Register addresses, SCHIZO has iommu ctx flushing. */ |
1707 | iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; | |
1708 | iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; | |
1709 | iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; | |
1710 | iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; | |
1711 | ||
1712 | /* We use the main control/status register of SCHIZO as the write | |
1713 | * completion register. | |
1714 | */ | |
1715 | iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; | |
1716 | ||
1717 | /* | |
1718 | * Invalidate TLB Entries. | |
1719 | */ | |
1720 | control = schizo_read(iommu->iommu_control); | |
1721 | control |= SCHIZO_IOMMU_CTRL_DENAB; | |
1722 | schizo_write(iommu->iommu_control, control); | |
1723 | ||
1724 | tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; | |
1725 | ||
1726 | for(i = 0; i < 16; i++) { | |
1727 | schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0); | |
1728 | schizo_write(pbm->pbm_regs + database + (i * 8UL), 0); | |
1729 | } | |
1730 | ||
1731 | /* Leave diag mode enabled for full-flushing done | |
1732 | * in pci_iommu.c | |
1733 | */ | |
51e85136 | 1734 | pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask); |
1da177e4 | 1735 | |
51e85136 | 1736 | schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table)); |
1da177e4 LT |
1737 | |
1738 | control = schizo_read(iommu->iommu_control); | |
1739 | control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); | |
1740 | switch (tsbsize) { | |
1741 | case 64: | |
1742 | control |= SCHIZO_IOMMU_TSBSZ_64K; | |
1743 | break; | |
1744 | case 128: | |
1745 | control |= SCHIZO_IOMMU_TSBSZ_128K; | |
1746 | break; | |
1747 | }; | |
1748 | ||
1749 | control |= SCHIZO_IOMMU_CTRL_ENAB; | |
1750 | schizo_write(iommu->iommu_control, control); | |
1751 | } | |
1752 | ||
1753 | #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) | |
1754 | #define SCHIZO_IRQ_RETRY_INF 0xffUL | |
1755 | ||
1756 | #define SCHIZO_PCI_DIAG (0x2020UL) | |
1757 | #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ | |
1758 | #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ | |
1759 | #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ | |
1760 | #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ | |
1761 | #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ | |
1762 | #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ | |
1763 | #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ | |
1764 | #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ | |
1765 | #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ | |
1766 | ||
1767 | #define TOMATILLO_PCI_IOC_CSR (0x2248UL) | |
1768 | #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL | |
1769 | #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL | |
1770 | #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL | |
1771 | #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL | |
1772 | #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL | |
1773 | #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL | |
1774 | #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL | |
1775 | #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL | |
1776 | #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL | |
1777 | #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL | |
1778 | #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL | |
1779 | #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL | |
1780 | #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL | |
1781 | #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL | |
1782 | #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL | |
1783 | ||
1784 | #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) | |
1785 | #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) | |
1786 | ||
085ae41f | 1787 | static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) |
1da177e4 | 1788 | { |
e87dc350 | 1789 | struct property *prop; |
1da177e4 LT |
1790 | u64 tmp; |
1791 | ||
864ae180 | 1792 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5); |
1da177e4 | 1793 | |
1da177e4 | 1794 | tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); |
1da177e4 | 1795 | |
9fba62a5 DM |
1796 | /* Enable arbiter for all PCI slots. */ |
1797 | tmp |= 0xff; | |
1798 | ||
1da177e4 LT |
1799 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && |
1800 | pbm->chip_version >= 0x2) | |
1801 | tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; | |
1da177e4 | 1802 | |
e87dc350 DM |
1803 | prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL); |
1804 | if (!prop) | |
1da177e4 | 1805 | tmp |= SCHIZO_PCICTRL_PARK; |
9fba62a5 DM |
1806 | else |
1807 | tmp &= ~SCHIZO_PCICTRL_PARK; | |
1da177e4 LT |
1808 | |
1809 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && | |
1810 | pbm->chip_version <= 0x1) | |
9fba62a5 | 1811 | tmp |= SCHIZO_PCICTRL_DTO_INT; |
1da177e4 | 1812 | else |
9fba62a5 | 1813 | tmp &= ~SCHIZO_PCICTRL_DTO_INT; |
1da177e4 LT |
1814 | |
1815 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) | |
1816 | tmp |= (SCHIZO_PCICTRL_MRM_PREF | | |
1817 | SCHIZO_PCICTRL_RDO_PREF | | |
1818 | SCHIZO_PCICTRL_RDL_PREF); | |
1819 | ||
1820 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1821 | ||
1822 | tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG); | |
1823 | tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | | |
1824 | SCHIZO_PCIDIAG_D_RETRY | | |
1825 | SCHIZO_PCIDIAG_D_INTSYNC); | |
1826 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp); | |
1827 | ||
1828 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
1829 | /* Clear prefetch lengths to workaround a bug in | |
1830 | * Jalapeno... | |
1831 | */ | |
1832 | tmp = (TOMATILLO_IOC_PART_WPENAB | | |
1833 | (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | | |
1834 | TOMATILLO_IOC_RDMULT_CPENAB | | |
1835 | TOMATILLO_IOC_RDONE_CPENAB | | |
1836 | TOMATILLO_IOC_RDLINE_CPENAB); | |
1837 | ||
1838 | schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR, | |
1839 | tmp); | |
1840 | } | |
1841 | } | |
1842 | ||
085ae41f | 1843 | static void schizo_pbm_init(struct pci_controller_info *p, |
e87dc350 | 1844 | struct device_node *dp, u32 portid, |
085ae41f | 1845 | int chip_type) |
1da177e4 | 1846 | { |
e87dc350 DM |
1847 | struct linux_prom64_registers *regs; |
1848 | struct property *prop; | |
1849 | unsigned int *busrange; | |
1da177e4 LT |
1850 | struct pci_pbm_info *pbm; |
1851 | const char *chipset_name; | |
e87dc350 | 1852 | u32 *ino_bitmap; |
1da177e4 | 1853 | int is_pbm_a; |
e87dc350 | 1854 | int len; |
1da177e4 LT |
1855 | |
1856 | switch (chip_type) { | |
1857 | case PBM_CHIP_TYPE_TOMATILLO: | |
1858 | chipset_name = "TOMATILLO"; | |
1859 | break; | |
1860 | ||
1861 | case PBM_CHIP_TYPE_SCHIZO_PLUS: | |
1862 | chipset_name = "SCHIZO+"; | |
1863 | break; | |
1864 | ||
1865 | case PBM_CHIP_TYPE_SCHIZO: | |
1866 | default: | |
1867 | chipset_name = "SCHIZO"; | |
1868 | break; | |
1869 | }; | |
1870 | ||
1871 | /* For SCHIZO, three OBP regs: | |
1872 | * 1) PBM controller regs | |
1873 | * 2) Schizo front-end controller regs (same for both PBMs) | |
1874 | * 3) PBM PCI config space | |
1875 | * | |
1876 | * For TOMATILLO, four OBP regs: | |
1877 | * 1) PBM controller regs | |
1878 | * 2) Tomatillo front-end controller regs | |
1879 | * 3) PBM PCI config space | |
1880 | * 4) Ichip regs | |
1881 | */ | |
e87dc350 DM |
1882 | prop = of_find_property(dp, "reg", NULL); |
1883 | regs = prop->value; | |
1da177e4 | 1884 | |
e87dc350 | 1885 | is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000); |
1da177e4 LT |
1886 | |
1887 | if (is_pbm_a) | |
1888 | pbm = &p->pbm_A; | |
1889 | else | |
1890 | pbm = &p->pbm_B; | |
1891 | ||
1892 | pbm->portid = portid; | |
1893 | pbm->parent = p; | |
e87dc350 | 1894 | pbm->prom_node = dp; |
1da177e4 LT |
1895 | pbm->pci_first_slot = 1; |
1896 | ||
1897 | pbm->chip_type = chip_type; | |
e87dc350 DM |
1898 | pbm->chip_version = 0; |
1899 | prop = of_find_property(dp, "version#", NULL); | |
1900 | if (prop) | |
1901 | pbm->chip_version = *(int *) prop->value; | |
1902 | pbm->chip_revision = 0; | |
1903 | prop = of_find_property(dp, "module-revision#", NULL); | |
1904 | if (prop) | |
1905 | pbm->chip_revision = *(int *) prop->value; | |
1906 | ||
1907 | pbm->pbm_regs = regs[0].phys_addr; | |
1908 | pbm->controller_regs = regs[1].phys_addr - 0x10000UL; | |
1da177e4 | 1909 | |
bb6743f4 | 1910 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) |
e87dc350 | 1911 | pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; |
bb6743f4 | 1912 | |
e87dc350 | 1913 | pbm->name = dp->full_name; |
1da177e4 | 1914 | |
e87dc350 | 1915 | printk("%s: %s PCI Bus Module ver[%x:%x]\n", |
1da177e4 | 1916 | pbm->name, |
e87dc350 DM |
1917 | (chip_type == PBM_CHIP_TYPE_TOMATILLO ? |
1918 | "TOMATILLO" : "SCHIZO"), | |
1919 | pbm->chip_version, pbm->chip_revision); | |
1da177e4 LT |
1920 | |
1921 | schizo_pbm_hw_init(pbm); | |
1922 | ||
e87dc350 DM |
1923 | prop = of_find_property(dp, "ranges", &len); |
1924 | pbm->pbm_ranges = prop->value; | |
1da177e4 | 1925 | pbm->num_pbm_ranges = |
e87dc350 | 1926 | (len / sizeof(struct linux_prom_pci_ranges)); |
1da177e4 LT |
1927 | |
1928 | schizo_determine_mem_io_space(pbm); | |
1929 | pbm_register_toplevel_resources(p, pbm); | |
1930 | ||
e87dc350 DM |
1931 | prop = of_find_property(dp, "interrupt-map", &len); |
1932 | if (prop) { | |
1933 | pbm->pbm_intmap = prop->value; | |
1934 | pbm->num_pbm_intmap = | |
1935 | (len / sizeof(struct linux_prom_pci_intmap)); | |
1936 | ||
1937 | prop = of_find_property(dp, "interrupt-map-mask", NULL); | |
1938 | pbm->pbm_intmask = prop->value; | |
1da177e4 LT |
1939 | } else { |
1940 | pbm->num_pbm_intmap = 0; | |
1da177e4 LT |
1941 | } |
1942 | ||
e87dc350 DM |
1943 | prop = of_find_property(dp, "ino-bitmap", NULL); |
1944 | ino_bitmap = prop->value; | |
1da177e4 LT |
1945 | pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) | |
1946 | ((u64)ino_bitmap[0] << 0UL)); | |
1947 | ||
e87dc350 DM |
1948 | prop = of_find_property(dp, "bus-range", NULL); |
1949 | busrange = prop->value; | |
1da177e4 LT |
1950 | pbm->pci_first_busno = busrange[0]; |
1951 | pbm->pci_last_busno = busrange[1]; | |
1952 | ||
1953 | schizo_pbm_iommu_init(pbm); | |
1954 | schizo_pbm_strbuf_init(pbm); | |
1955 | } | |
1956 | ||
1957 | static inline int portid_compare(u32 x, u32 y, int chip_type) | |
1958 | { | |
1959 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
1960 | if (x == (y ^ 1)) | |
1961 | return 1; | |
1962 | return 0; | |
1963 | } | |
1964 | return (x == y); | |
1965 | } | |
1966 | ||
e87dc350 | 1967 | static void __schizo_init(struct device_node *dp, char *model_name, int chip_type) |
1da177e4 LT |
1968 | { |
1969 | struct pci_controller_info *p; | |
1970 | struct pci_iommu *iommu; | |
e87dc350 | 1971 | struct property *prop; |
1da177e4 LT |
1972 | int is_pbm_a; |
1973 | u32 portid; | |
1974 | ||
e87dc350 DM |
1975 | portid = 0xff; |
1976 | prop = of_find_property(dp, "portid", NULL); | |
1977 | if (prop) | |
1978 | portid = *(u32 *) prop->value; | |
1da177e4 | 1979 | |
e87dc350 | 1980 | for (p = pci_controller_root; p; p = p->next) { |
1da177e4 LT |
1981 | struct pci_pbm_info *pbm; |
1982 | ||
1983 | if (p->pbm_A.prom_node && p->pbm_B.prom_node) | |
1984 | continue; | |
1985 | ||
1986 | pbm = (p->pbm_A.prom_node ? | |
1987 | &p->pbm_A : | |
1988 | &p->pbm_B); | |
1989 | ||
1990 | if (portid_compare(pbm->portid, portid, chip_type)) { | |
e87dc350 DM |
1991 | is_pbm_a = (p->pbm_A.prom_node == NULL); |
1992 | schizo_pbm_init(p, dp, portid, chip_type); | |
1da177e4 LT |
1993 | return; |
1994 | } | |
1995 | } | |
1996 | ||
9132983a | 1997 | p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); |
1da177e4 LT |
1998 | if (!p) { |
1999 | prom_printf("SCHIZO: Fatal memory allocation error.\n"); | |
2000 | prom_halt(); | |
2001 | } | |
1da177e4 | 2002 | |
9132983a | 2003 | iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC); |
1da177e4 LT |
2004 | if (!iommu) { |
2005 | prom_printf("SCHIZO: Fatal memory allocation error.\n"); | |
2006 | prom_halt(); | |
2007 | } | |
1da177e4 LT |
2008 | p->pbm_A.iommu = iommu; |
2009 | ||
9132983a | 2010 | iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC); |
1da177e4 LT |
2011 | if (!iommu) { |
2012 | prom_printf("SCHIZO: Fatal memory allocation error.\n"); | |
2013 | prom_halt(); | |
2014 | } | |
1da177e4 LT |
2015 | p->pbm_B.iommu = iommu; |
2016 | ||
2017 | p->next = pci_controller_root; | |
2018 | pci_controller_root = p; | |
2019 | ||
2020 | p->index = pci_num_controllers++; | |
2021 | p->pbms_same_domain = 0; | |
2022 | p->scan_bus = (chip_type == PBM_CHIP_TYPE_TOMATILLO ? | |
2023 | tomatillo_scan_bus : | |
2024 | schizo_scan_bus); | |
2025 | p->irq_build = schizo_irq_build; | |
2026 | p->base_address_update = schizo_base_address_update; | |
2027 | p->resource_adjust = schizo_resource_adjust; | |
2028 | p->pci_ops = &schizo_ops; | |
2029 | ||
2030 | /* Like PSYCHO we have a 2GB aligned area for memory space. */ | |
2031 | pci_memspace_mask = 0x7fffffffUL; | |
2032 | ||
e87dc350 | 2033 | schizo_pbm_init(p, dp, portid, chip_type); |
1da177e4 LT |
2034 | } |
2035 | ||
e87dc350 | 2036 | void schizo_init(struct device_node *dp, char *model_name) |
1da177e4 | 2037 | { |
e87dc350 | 2038 | __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO); |
1da177e4 LT |
2039 | } |
2040 | ||
e87dc350 | 2041 | void schizo_plus_init(struct device_node *dp, char *model_name) |
1da177e4 | 2042 | { |
e87dc350 | 2043 | __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS); |
1da177e4 LT |
2044 | } |
2045 | ||
e87dc350 | 2046 | void tomatillo_init(struct device_node *dp, char *model_name) |
1da177e4 | 2047 | { |
e87dc350 | 2048 | __schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO); |
1da177e4 | 2049 | } |