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sparc64: Kill the scan_bus function pointer in struct pci_pbm_info.
[deliverable/linux.git] / arch / sparc64 / kernel / pci_schizo.c
CommitLineData
9fd8b647 1/* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
1da177e4 2 *
6d19c88f 3 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/interrupt.h>
764f2579 12#include <linux/of_device.h>
1da177e4 13
1da177e4
LT		 14#include <asm/iommu.h>
15#include <asm/irq.h>
bb6743f4 16#include <asm/pstate.h>
e87dc350 17#include <asm/prom.h>
1da177e4
LT		 18
19#include "pci_impl.h"
20#include "iommu_common.h"
21
6d19c88f
DM		 22#define DRIVER_NAME "schizo"
23#define PFX DRIVER_NAME ": "
24
1da177e4
LT		 25/* All SCHIZO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29#define schizo_read(__reg) \
30({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36})
37#define schizo_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44/* This is a convention that at least Excalibur and Merlin
45 * follow. I suppose the SCHIZO used in Starcat and friends
46 * will do similar.
47 *
48 * The only way I could see this changing is if the newlink
49 * block requires more space in Schizo's address space than
50 * they predicted, thus requiring an address space reorg when
51 * the newer Schizo is taped out.
52 */
53
54/* Streaming buffer control register. */
55#define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
56#define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
57#define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
58#define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
59#define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
60
61/* IOMMU control register. */
62#define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
63#define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
64#define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
65#define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
66#define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
67#define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
68#define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
69#define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
70#define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
71#define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
72#define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
73#define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
74#define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
75#define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
76#define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
77#define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
78#define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
79#define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
80
81/* Schizo config space address format is nearly identical to
82 * that of PSYCHO:
83 *
84 * 32 24 23 16 15 11 10 8 7 2 1 0
85 * ---------------------------------------------------------
86 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
87 * ---------------------------------------------------------
88 */
89#define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
90#define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
91 (((unsigned long)(BUS) << 16) | \
92 ((unsigned long)(DEVFN) << 8) | \
93 ((unsigned long)(REG)))
94
95static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
96 unsigned char bus,
97 unsigned int devfn,
98 int where)
99{
100 if (!pbm)
101 return NULL;
102 bus -= pbm->pci_first_busno;
103 return (void *)
104 (SCHIZO_CONFIG_BASE(pbm) |
105 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
106}
107
1da177e4
LT		 108/* SCHIZO error handling support. */
109enum schizo_error_type {
110 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
111};
112
113static DEFINE_SPINLOCK(stc_buf_lock);
114static unsigned long stc_error_buf[128];
115static unsigned long stc_tag_buf[16];
116static unsigned long stc_line_buf[16];
117
118#define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
119#define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
120#define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
121#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
122#define SCHIZO_SERR_INO 0x34 /* Safari interface error */
123
1da177e4
LT		 124#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
125#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
126#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
127
128#define SCHIZO_STCERR_WRITE 0x2UL
129#define SCHIZO_STCERR_READ 0x1UL
130
131#define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
132#define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
133#define SCHIZO_STCTAG_VALID 0x8000000000000000UL
134#define SCHIZO_STCTAG_READ 0x4000000000000000UL
135
136#define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
137#define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
138#define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
139#define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
140#define SCHIZO_STCLINE_VALID 0x0000000000600000UL
141#define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
142
143static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
144 enum schizo_error_type type)
145{
16ce82d8 146 struct strbuf *strbuf = &pbm->stc;
1da177e4
LT		 147 unsigned long regbase = pbm->pbm_regs;
148 unsigned long err_base, tag_base, line_base;
149 u64 control;
150 int i;
151
152 err_base = regbase + SCHIZO_STC_ERR;
153 tag_base = regbase + SCHIZO_STC_TAG;
154 line_base = regbase + SCHIZO_STC_LINE;
155
156 spin_lock(&stc_buf_lock);
157
158 /* This is __REALLY__ dangerous. When we put the
159 * streaming buffer into diagnostic mode to probe
160 * it's tags and error status, we _must_ clear all
161 * of the line tag valid bits before re-enabling
162 * the streaming buffer. If any dirty data lives
163 * in the STC when we do this, we will end up
164 * invalidating it before it has a chance to reach
165 * main memory.
166 */
167 control = schizo_read(strbuf->strbuf_control);
168 schizo_write(strbuf->strbuf_control,
169 (control | SCHIZO_STRBUF_CTRL_DENAB));
170 for (i = 0; i < 128; i++) {
171 unsigned long val;
172
173 val = schizo_read(err_base + (i * 8UL));
174 schizo_write(err_base + (i * 8UL), 0UL);
175 stc_error_buf[i] = val;
176 }
177 for (i = 0; i < 16; i++) {
178 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
179 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
180 schizo_write(tag_base + (i * 8UL), 0UL);
181 schizo_write(line_base + (i * 8UL), 0UL);
182 }
183
184 /* OK, state is logged, exit diagnostic mode. */
185 schizo_write(strbuf->strbuf_control, control);
186
187 for (i = 0; i < 16; i++) {
188 int j, saw_error, first, last;
189
190 saw_error = 0;
191 first = i * 8;
192 last = first + 8;
193 for (j = first; j < last; j++) {
194 unsigned long errval = stc_error_buf[j];
195 if (errval != 0) {
196 saw_error++;
197 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
198 pbm->name,
199 j,
200 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
201 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
202 }
203 }
204 if (saw_error != 0) {
205 unsigned long tagval = stc_tag_buf[i];
206 unsigned long lineval = stc_line_buf[i];
207 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
208 pbm->name,
209 i,
210 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
211 (tagval & SCHIZO_STCTAG_VPN),
212 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
213 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
214
215 /* XXX Should spit out per-bank error information... -DaveM */
216 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
217 "V(%d)FOFN(%d)]\n",
218 pbm->name,
219 i,
220 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
221 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
222 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
223 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
224 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
225 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
226 }
227 }
228
229 spin_unlock(&stc_buf_lock);
230}
231
232/* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
233 * controller level errors.
234 */
235
236#define SCHIZO_IOMMU_TAG 0xa580UL
237#define SCHIZO_IOMMU_DATA 0xa600UL
238
239#define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
240#define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
241#define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
242#define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
243#define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
244#define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
245#define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
246
247#define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
248#define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
249#define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
250
251static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
252 enum schizo_error_type type)
253{
16ce82d8 254 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 255 unsigned long iommu_tag[16];
256 unsigned long iommu_data[16];
257 unsigned long flags;
258 u64 control;
259 int i;
260
261 spin_lock_irqsave(&iommu->lock, flags);
262 control = schizo_read(iommu->iommu_control);
263 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
264 unsigned long base;
265 char *type_string;
266
267 /* Clear the error encountered bit. */
268 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
269 schizo_write(iommu->iommu_control, control);
270
271 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
272 case 0:
273 type_string = "Protection Error";
274 break;
275 case 1:
276 type_string = "Invalid Error";
277 break;
278 case 2:
279 type_string = "TimeOut Error";
280 break;
281 case 3:
282 default:
283 type_string = "ECC Error";
284 break;
285 };
286 printk("%s: IOMMU Error, type[%s]\n",
287 pbm->name, type_string);
288
289 /* Put the IOMMU into diagnostic mode and probe
290 * it's TLB for entries with error status.
291 *
292 * It is very possible for another DVMA to occur
293 * while we do this probe, and corrupt the system
294 * further. But we are so screwed at this point
295 * that we are likely to crash hard anyways, so
296 * get as much diagnostic information to the
297 * console as we can.
298 */
299 schizo_write(iommu->iommu_control,
300 control | SCHIZO_IOMMU_CTRL_DENAB);
301
302 base = pbm->pbm_regs;
303
304 for (i = 0; i < 16; i++) {
305 iommu_tag[i] =
306 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
307 iommu_data[i] =
308 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
309
310 /* Now clear out the entry. */
311 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
312 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
313 }
314
315 /* Leave diagnostic mode. */
316 schizo_write(iommu->iommu_control, control);
317
318 for (i = 0; i < 16; i++) {
319 unsigned long tag, data;
320
321 tag = iommu_tag[i];
322 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
323 continue;
324
325 data = iommu_data[i];
326 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
327 case 0:
328 type_string = "Protection Error";
329 break;
330 case 1:
331 type_string = "Invalid Error";
332 break;
333 case 2:
334 type_string = "TimeOut Error";
335 break;
336 case 3:
337 default:
338 type_string = "ECC Error";
339 break;
340 };
341 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
342 "sz(%dK) vpg(%08lx)]\n",
343 pbm->name, i, type_string,
344 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
345 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
346 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
347 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
348 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
349 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
350 pbm->name, i,
351 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
352 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
353 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
354 }
355 }
356 if (pbm->stc.strbuf_enabled)
357 __schizo_check_stc_error_pbm(pbm, type);
358 spin_unlock_irqrestore(&iommu->lock, flags);
359}
360
361static void schizo_check_iommu_error(struct pci_controller_info *p,
362 enum schizo_error_type type)
363{
364 schizo_check_iommu_error_pbm(&p->pbm_A, type);
365 schizo_check_iommu_error_pbm(&p->pbm_B, type);
366}
367
368/* Uncorrectable ECC error status gathering. */
369#define SCHIZO_UE_AFSR 0x10030UL
370#define SCHIZO_UE_AFAR 0x10038UL
371
372#define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
373#define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
374#define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
375#define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
376#define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
377#define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
378#define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
379#define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
380#define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
381#define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
382#define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
383#define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
384#define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
385#define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
386
6d24c8dc 387static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
1da177e4 388{
34768bc8
DM		 389 struct pci_pbm_info *pbm = dev_id;
390 struct pci_controller_info *p = pbm->parent;
391 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
392 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
1da177e4
LT		 393 unsigned long afsr, afar, error_bits;
394 int reported, limit;
395
396 /* Latch uncorrectable error status. */
397 afar = schizo_read(afar_reg);
398
399 /* If either of the error pending bits are set in the
400 * AFSR, the error status is being actively updated by
401 * the hardware and we must re-read to get a clean value.
402 */
403 limit = 1000;
404 do {
405 afsr = schizo_read(afsr_reg);
406 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
407
408 /* Clear the primary/secondary error status bits. */
409 error_bits = afsr &
410 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
411 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
412 if (!error_bits)
413 return IRQ_NONE;
414 schizo_write(afsr_reg, error_bits);
415
416 /* Log the error. */
6c108f12
DM		 417 printk("%s: Uncorrectable Error, primary error type[%s]\n",
418 pbm->name,
1da177e4
LT		 419 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
420 "PIO" :
421 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
422 "DMA Read" :
423 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
424 "DMA Write" : "???")))));
6c108f12
DM		 425 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
426 pbm->name,
1da177e4
LT		 427 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
428 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
429 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 430 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
431 pbm->name,
1da177e4
LT		 432 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
433 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
434 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
435 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
436 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 437 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
438 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 439 reported = 0;
440 if (afsr & SCHIZO_UEAFSR_SPIO) {
441 reported++;
442 printk("(PIO)");
443 }
444 if (afsr & SCHIZO_UEAFSR_SDMA) {
445 reported++;
446 printk("(DMA)");
447 }
448 if (!reported)
449 printk("(none)");
450 printk("]\n");
451
452 /* Interrogate IOMMU for error status. */
453 schizo_check_iommu_error(p, UE_ERR);
454
1da177e4
LT		 455 return IRQ_HANDLED;
456}
457
458#define SCHIZO_CE_AFSR 0x10040UL
459#define SCHIZO_CE_AFAR 0x10048UL
460
461#define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
462#define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
463#define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
464#define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
465#define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
466#define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
467#define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
468#define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
469#define SCHIZO_CEAFSR_AID 0x000000001f000000UL
470#define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
471#define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
472#define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
473#define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
474#define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
475
6d24c8dc 476static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
1da177e4 477{
34768bc8 478 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 479 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
480 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
1da177e4
LT		 481 unsigned long afsr, afar, error_bits;
482 int reported, limit;
483
484 /* Latch error status. */
485 afar = schizo_read(afar_reg);
486
487 /* If either of the error pending bits are set in the
488 * AFSR, the error status is being actively updated by
489 * the hardware and we must re-read to get a clean value.
490 */
491 limit = 1000;
492 do {
493 afsr = schizo_read(afsr_reg);
494 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
495
496 /* Clear primary/secondary error status bits. */
497 error_bits = afsr &
498 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
499 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
500 if (!error_bits)
501 return IRQ_NONE;
502 schizo_write(afsr_reg, error_bits);
503
504 /* Log the error. */
6c108f12
DM		 505 printk("%s: Correctable Error, primary error type[%s]\n",
506 pbm->name,
1da177e4
LT		 507 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
508 "PIO" :
509 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
510 "DMA Read" :
511 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
512 "DMA Write" : "???")))));
513
514 /* XXX Use syndrome and afar to print out module string just like
515 * XXX UDB CE trap handler does... -DaveM
516 */
6c108f12
DM		 517 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
518 pbm->name,
1da177e4
LT		 519 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
520 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
521 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 522 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
523 pbm->name,
1da177e4
LT		 524 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
525 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
526 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
527 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
528 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 529 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
530 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 531 reported = 0;
532 if (afsr & SCHIZO_CEAFSR_SPIO) {
533 reported++;
534 printk("(PIO)");
535 }
536 if (afsr & SCHIZO_CEAFSR_SDMA) {
537 reported++;
538 printk("(DMA)");
539 }
540 if (!reported)
541 printk("(none)");
542 printk("]\n");
543
1da177e4
LT		 544 return IRQ_HANDLED;
545}
546
547#define SCHIZO_PCI_AFSR 0x2010UL
548#define SCHIZO_PCI_AFAR 0x2018UL
549
550#define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
551#define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
552#define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
553#define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
554#define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
555#define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
556#define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
557#define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
558#define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
559#define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
560#define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
561#define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
562#define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
563#define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
564#define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
565#define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
566#define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
567
568#define SCHIZO_PCI_CTRL (0x2000UL)
569#define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
9fba62a5 570#define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
1da177e4
LT		 571#define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
572#define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
573#define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
574#define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
575#define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
576#define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
577#define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
578#define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
579#define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
580#define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
581#define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
582#define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
583#define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
584#define SCHIZO_PCICTRL_PTO_SHIFT 24UL
585#define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
586#define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
587#define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
588#define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
589#define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
590#define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
591#define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
592#define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
593#define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
594#define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
595#define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
596
597static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
598{
599 unsigned long csr_reg, csr, csr_error_bits;
600 irqreturn_t ret = IRQ_NONE;
601 u16 stat;
602
603 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
604 csr = schizo_read(csr_reg);
605 csr_error_bits =
606 csr & (SCHIZO_PCICTRL_BUS_UNUS |
607 SCHIZO_PCICTRL_TTO_ERR |
608 SCHIZO_PCICTRL_RTRY_ERR |
609 SCHIZO_PCICTRL_DTO_ERR |
610 SCHIZO_PCICTRL_SBH_ERR |
611 SCHIZO_PCICTRL_SERR);
612 if (csr_error_bits) {
613 /* Clear the errors. */
614 schizo_write(csr_reg, csr);
615
616 /* Log 'em. */
617 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
618 printk("%s: Bus unusable error asserted.\n",
619 pbm->name);
620 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
621 printk("%s: PCI TRDY# timeout error asserted.\n",
622 pbm->name);
623 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
624 printk("%s: PCI excessive retry error asserted.\n",
625 pbm->name);
626 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
627 printk("%s: PCI discard timeout error asserted.\n",
628 pbm->name);
629 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
630 printk("%s: PCI streaming byte hole error asserted.\n",
631 pbm->name);
632 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
633 printk("%s: PCI SERR signal asserted.\n",
634 pbm->name);
635 ret = IRQ_HANDLED;
636 }
637 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
638 if (stat & (PCI_STATUS_PARITY |
639 PCI_STATUS_SIG_TARGET_ABORT |
640 PCI_STATUS_REC_TARGET_ABORT |
641 PCI_STATUS_REC_MASTER_ABORT |
642 PCI_STATUS_SIG_SYSTEM_ERROR)) {
643 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
644 pbm->name, stat);
645 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
646 ret = IRQ_HANDLED;
647 }
648 return ret;
649}
650
6d24c8dc 651static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 652{
653 struct pci_pbm_info *pbm = dev_id;
654 struct pci_controller_info *p = pbm->parent;
655 unsigned long afsr_reg, afar_reg, base;
656 unsigned long afsr, afar, error_bits;
657 int reported;
658
659 base = pbm->pbm_regs;
660
661 afsr_reg = base + SCHIZO_PCI_AFSR;
662 afar_reg = base + SCHIZO_PCI_AFAR;
663
664 /* Latch error status. */
665 afar = schizo_read(afar_reg);
666 afsr = schizo_read(afsr_reg);
667
668 /* Clear primary/secondary error status bits. */
669 error_bits = afsr &
670 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
671 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
672 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
673 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
674 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
675 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
676 if (!error_bits)
677 return schizo_pcierr_intr_other(pbm);
678 schizo_write(afsr_reg, error_bits);
679
680 /* Log the error. */
681 printk("%s: PCI Error, primary error type[%s]\n",
682 pbm->name,
683 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
684 "Master Abort" :
685 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
686 "Target Abort" :
687 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
688 "Excessive Retries" :
689 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
690 "Parity Error" :
691 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
692 "Timeout" :
693 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
694 "Bus Unusable" : "???"))))))));
695 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
696 pbm->name,
697 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
698 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
699 ((afsr & SCHIZO_PCIAFSR_CFG) ?
700 "Config" :
701 ((afsr & SCHIZO_PCIAFSR_MEM) ?
702 "Memory" :
703 ((afsr & SCHIZO_PCIAFSR_IO) ?
704 "I/O" : "???"))));
705 printk("%s: PCI AFAR [%016lx]\n",
706 pbm->name, afar);
707 printk("%s: PCI Secondary errors [",
708 pbm->name);
709 reported = 0;
710 if (afsr & SCHIZO_PCIAFSR_SMA) {
711 reported++;
712 printk("(Master Abort)");
713 }
714 if (afsr & SCHIZO_PCIAFSR_STA) {
715 reported++;
716 printk("(Target Abort)");
717 }
718 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
719 reported++;
720 printk("(Excessive Retries)");
721 }
722 if (afsr & SCHIZO_PCIAFSR_SPERR) {
723 reported++;
724 printk("(Parity Error)");
725 }
726 if (afsr & SCHIZO_PCIAFSR_STTO) {
727 reported++;
728 printk("(Timeout)");
729 }
730 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
731 reported++;
732 printk("(Bus Unusable)");
733 }
734 if (!reported)
735 printk("(none)");
736 printk("]\n");
737
738 /* For the error types shown, scan PBM's PCI bus for devices
739 * which have logged that error type.
740 */
741
742 /* If we see a Target Abort, this could be the result of an
743 * IOMMU translation error of some sort. It is extremely
744 * useful to log this information as usually it indicates
745 * a bug in the IOMMU support code or a PCI device driver.
746 */
747 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
748 schizo_check_iommu_error(p, PCI_ERR);
6c108f12 749 pci_scan_for_target_abort(pbm, pbm->pci_bus);
1da177e4
LT		 750 }
751 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
6c108f12 752 pci_scan_for_master_abort(pbm, pbm->pci_bus);
1da177e4
LT		 753
754 /* For excessive retries, PSYCHO/PBM will abort the device
755 * and there is no way to specifically check for excessive
756 * retries in the config space status registers. So what
757 * we hope is that we'll catch it via the master/target
758 * abort events.
759 */
760
761 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
6c108f12 762 pci_scan_for_parity_error(pbm, pbm->pci_bus);
1da177e4 763
1da177e4
LT		 764 return IRQ_HANDLED;
765}
766
767#define SCHIZO_SAFARI_ERRLOG 0x10018UL
768
769#define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
770
771#define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
772#define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
773#define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
774#define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
775#define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
776#define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
777#define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
778#define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
779#define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
780#define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
781#define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
782#define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
783#define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
784#define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
785#define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
786#define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
787#define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
788#define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
789#define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
790#define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
791#define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
792#define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
793#define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
794#define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
795#define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
796#define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
797#define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
798#define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
799#define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
800#define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
801#define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
802
803/* We only expect UNMAP errors here. The rest of the Safari errors
804 * are marked fatal and thus cause a system reset.
805 */
6d24c8dc 806static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
1da177e4 807{
34768bc8
DM		 808 struct pci_pbm_info *pbm = dev_id;
809 struct pci_controller_info *p = pbm->parent;
1da177e4
LT		 810 u64 errlog;
811
34768bc8
DM		 812 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
813 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG,
1da177e4
LT		 814 errlog & ~(SAFARI_ERRLOG_ERROUT));
815
816 if (!(errlog & BUS_ERROR_UNMAP)) {
6c108f12
DM		 817 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
818 pbm->name, errlog);
1da177e4 819
1da177e4
LT		 820 return IRQ_HANDLED;
821 }
822
6c108f12
DM		 823 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
824 pbm->name);
1da177e4
LT		 825 schizo_check_iommu_error(p, SAFARI_ERR);
826
1da177e4
LT		 827 return IRQ_HANDLED;
828}
829
830/* Nearly identical to PSYCHO equivalents... */
831#define SCHIZO_ECC_CTRL 0x10020UL
832#define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
833#define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
834#define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
835
836#define SCHIZO_SAFARI_ERRCTRL 0x10008UL
837#define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
838#define SCHIZO_SAFARI_IRQCTRL 0x10010UL
839#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
840
34768bc8
DM		 841static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
842{
843 ino &= IMAP_INO;
844
845 if (pbm->ino_bitmap & (1UL << ino))
846 return 1;
847
848 return 0;
849}
850
1da177e4
LT		 851/* How the Tomatillo IRQs are routed around is pure guesswork here.
852 *
853 * All the Tomatillo devices I see in prtconf dumps seem to have only
33ccc190 854 * a single PCI bus unit attached to it. It would seem they are separate
1da177e4
LT		 855 * devices because their PortID (ie. JBUS ID) values are all different
856 * and thus the registers are mapped to totally different locations.
857 *
858 * However, two Tomatillo's look "similar" in that the only difference
859 * in their PortID is the lowest bit.
860 *
861 * So if we were to ignore this lower bit, it certainly looks like two
862 * PCI bus units of the same Tomatillo. I still have not really
863 * figured this out...
864 */
34768bc8 865static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 866{
34768bc8 867 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 868 u64 tmp, err_mask, err_no_mask;
af80318e 869 int err;
1da177e4 870
2b1e5978
DM		 871 /* Tomatillo IRQ property layout is:
872 * 0: PCIERR
873 * 1: UE ERR
874 * 2: CE ERR
875 * 3: SERR
876 * 4: POWER FAIL?
877 */
878
af80318e
DM		 879 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
880 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
881 "TOMATILLO_UE", pbm);
882 if (err)
883 printk(KERN_WARNING "%s: Could not register UE, "
884 "err=%d\n", pbm->name, err);
885 }
886 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
887 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
888 "TOMATILLO_CE", pbm);
889 if (err)
890 printk(KERN_WARNING "%s: Could not register CE, "
891 "err=%d\n", pbm->name, err);
892 }
893 err = 0;
894 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
895 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
896 "TOMATILLO_PCIERR", pbm);
897 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
898 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
899 "TOMATILLO_PCIERR", pbm);
900 }
901 if (err)
902 printk(KERN_WARNING "%s: Could not register PCIERR, "
903 "err=%d\n", pbm->name, err);
904
905 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
906 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
907 "TOMATILLO_SERR", pbm);
908 if (err)
909 printk(KERN_WARNING "%s: Could not register SERR, "
910 "err=%d\n", pbm->name, err);
911 }
34768bc8
DM		 912
913 /* Enable UE and CE interrupts for controller. */
914 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 915 (SCHIZO_ECCCTRL_EE |
916 SCHIZO_ECCCTRL_UE |
917 SCHIZO_ECCCTRL_CE));
918
919 /* Enable PCI Error interrupts and clear error
920 * bits.
921 */
922 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
923 SCHIZO_PCICTRL_TTO_ERR |
924 SCHIZO_PCICTRL_RTRY_ERR |
925 SCHIZO_PCICTRL_SERR |
926 SCHIZO_PCICTRL_EEN);
927
928 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
929
34768bc8 930 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 931 tmp |= err_mask;
932 tmp &= ~err_no_mask;
34768bc8 933 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4
LT		 934
935 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
936 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
937 SCHIZO_PCIAFSR_PTTO |
938 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
939 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
940 SCHIZO_PCIAFSR_STTO);
941
34768bc8 942 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1da177e4
LT		 943
944 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
945 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
946 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
947 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
948 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
949 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
950 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
951 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
952 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
953
34768bc8 954 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4
LT		 955 (SCHIZO_SAFERRCTRL_EN | err_mask));
956
34768bc8 957 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL,
1da177e4
LT		 958 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
959}
960
34768bc8 961static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 962{
34768bc8 963 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 964 u64 tmp, err_mask, err_no_mask;
af80318e 965 int err;
1da177e4 966
2b1e5978
DM		 967 /* Schizo IRQ property layout is:
968 * 0: PCIERR
969 * 1: UE ERR
970 * 2: CE ERR
971 * 3: SERR
972 * 4: POWER FAIL?
973 */
974
af80318e
DM		 975 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
976 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
977 "SCHIZO_UE", pbm);
978 if (err)
979 printk(KERN_WARNING "%s: Could not register UE, "
980 "err=%d\n", pbm->name, err);
981 }
982 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
983 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
984 "SCHIZO_CE", pbm);
985 if (err)
986 printk(KERN_WARNING "%s: Could not register CE, "
987 "err=%d\n", pbm->name, err);
988 }
989 err = 0;
990 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
991 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
992 "SCHIZO_PCIERR", pbm);
993 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
994 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
995 "SCHIZO_PCIERR", pbm);
996 }
997 if (err)
998 printk(KERN_WARNING "%s: Could not register PCIERR, "
999 "err=%d\n", pbm->name, err);
1000
1001 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
1002 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1003 "SCHIZO_SERR", pbm);
1004 if (err)
1005 printk(KERN_WARNING "%s: Could not register SERR, "
1006 "err=%d\n", pbm->name, err);
1007 }
1da177e4
LT		 1008
1009 /* Enable UE and CE interrupts for controller. */
34768bc8 1010 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 1011 (SCHIZO_ECCCTRL_EE |
1012 SCHIZO_ECCCTRL_UE |
1013 SCHIZO_ECCCTRL_CE));
1014
1015 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1016 SCHIZO_PCICTRL_ESLCK |
1017 SCHIZO_PCICTRL_TTO_ERR |
1018 SCHIZO_PCICTRL_RTRY_ERR |
1019 SCHIZO_PCICTRL_SBH_ERR |
1020 SCHIZO_PCICTRL_SERR |
1021 SCHIZO_PCICTRL_EEN);
1022
1023 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1024 SCHIZO_PCICTRL_SBH_INT);
1025
1026 /* Enable PCI Error interrupts and clear error
1027 * bits for each PBM.
1028 */
34768bc8 1029 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 1030 tmp |= err_mask;
1031 tmp &= ~err_no_mask;
34768bc8 1032 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4 1033
34768bc8 1034 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR,
1da177e4
LT		 1035 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1036 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1037 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1038 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1039 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1040 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1041
1042 /* Make all Safari error conditions fatal except unmapped
1043 * errors which we make generate interrupts.
1044 */
1045 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1046 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1047 BUS_ERROR_BADMC |
1048 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1049 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1050 BUS_ERROR_CIQTO |
1051 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1052 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1053 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1054 BUS_ERROR_ILL);
1055#if 1
1056 /* XXX Something wrong with some Excalibur systems
1057 * XXX Sun is shipping. The behavior on a 2-cpu
1058 * XXX machine is that both CPU1 parity error bits
1059 * XXX are set and are immediately set again when
1060 * XXX their error status bits are cleared. Just
1061 * XXX ignore them for now. -DaveM
1062 */
1063 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1064 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1065#endif
1066
34768bc8 1067 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4 1068 (SCHIZO_SAFERRCTRL_EN | err_mask));
1da177e4
LT		 1069}
1070
085ae41f 1071static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 1072{
1073 u8 *addr;
1074
1075 /* Set cache-line size to 64 bytes, this is actually
1076 * a nop but I do it for completeness.
1077 */
1078 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1079 0, PCI_CACHE_LINE_SIZE);
1080 pci_config_write8(addr, 64 / sizeof(u32));
1081
1082 /* Set PBM latency timer to 64 PCI clocks. */
1083 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1084 0, PCI_LATENCY_TIMER);
1085 pci_config_write8(addr, 64);
1086}
1087
6d19c88f 1088static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm)
1da177e4 1089{
34768bc8
DM		 1090 pbm_config_busmastering(pbm);
1091 pbm->is_66mhz_capable =
1092 (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
e87dc350 1093 != NULL);
bc606f3c 1094
34768bc8 1095 pbm->pci_bus = pci_scan_one_pbm(pbm);
1da177e4 1096
34768bc8
DM		 1097 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1098 tomatillo_register_error_handlers(pbm);
1da177e4 1099 else
34768bc8 1100 schizo_register_error_handlers(pbm);
1da177e4
LT		 1101}
1102
1da177e4
LT		 1103#define SCHIZO_STRBUF_CONTROL (0x02800UL)
1104#define SCHIZO_STRBUF_FLUSH (0x02808UL)
1105#define SCHIZO_STRBUF_FSYNC (0x02810UL)
1106#define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1107#define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1108
1109static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1110{
1111 unsigned long base = pbm->pbm_regs;
1112 u64 control;
1113
1114 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1115 /* TOMATILLO lacks streaming cache. */
1116 return;
1117 }
1118
1119 /* SCHIZO has context flushing. */
1120 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1121 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1122 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1123 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1124 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1125
1126 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1127 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1128 + 63UL)
1129 & ~63UL);
1130 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1131 __pa(pbm->stc.strbuf_flushflag);
1132
1133 /* Turn off LRU locking and diag mode, enable the
1134 * streaming buffer and leave the rerun-disable
1135 * setting however OBP set it.
1136 */
1137 control = schizo_read(pbm->stc.strbuf_control);
1138 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1139 SCHIZO_STRBUF_CTRL_LENAB |
1140 SCHIZO_STRBUF_CTRL_DENAB);
1141 control |= SCHIZO_STRBUF_CTRL_ENAB;
1142 schizo_write(pbm->stc.strbuf_control, control);
1143
1144 pbm->stc.strbuf_enabled = 1;
1145}
1146
1147#define SCHIZO_IOMMU_CONTROL (0x00200UL)
1148#define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1149#define SCHIZO_IOMMU_FLUSH (0x00210UL)
1150#define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1151
ad7ad57c 1152static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1da177e4 1153{
16ce82d8 1154 struct iommu *iommu = pbm->iommu;
51e85136 1155 unsigned long i, tagbase, database;
e87dc350 1156 struct property *prop;
1da177e4 1157 u32 vdma[2], dma_mask;
ad7ad57c 1158 int tsbsize, err;
1da177e4 1159 u64 control;
1da177e4 1160
e87dc350
DM		 1161 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
1162 if (prop) {
1163 u32 *val = prop->value;
1164
1165 vdma[0] = val[0];
1166 vdma[1] = val[1];
1167 } else {
1da177e4
LT		 1168 /* No property, use default values. */
1169 vdma[0] = 0xc0000000;
1170 vdma[1] = 0x40000000;
1171 }
1172
1173 dma_mask = vdma[0];
1174 switch (vdma[1]) {
1175 case 0x20000000:
1176 dma_mask |= 0x1fffffff;
1177 tsbsize = 64;
1178 break;
1179
1180 case 0x40000000:
1181 dma_mask |= 0x3fffffff;
1182 tsbsize = 128;
1183 break;
1184
1185 case 0x80000000:
1186 dma_mask |= 0x7fffffff;
1187 tsbsize = 128;
1188 break;
1189
1190 default:
6d19c88f
DM		 1191 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1192 return -EINVAL;
1193 }
1da177e4 1194
1da177e4
LT		 1195 /* Register addresses, SCHIZO has iommu ctx flushing. */
1196 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1197 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1198 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
ad7ad57c 1199 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
1da177e4
LT		 1200 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1201
1202 /* We use the main control/status register of SCHIZO as the write
1203 * completion register.
1204 */
1205 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1206
1207 /*
1208 * Invalidate TLB Entries.
1209 */
1210 control = schizo_read(iommu->iommu_control);
1211 control |= SCHIZO_IOMMU_CTRL_DENAB;
1212 schizo_write(iommu->iommu_control, control);
1213
1214 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1215
6d19c88f 1216 for (i = 0; i < 16; i++) {
1da177e4
LT		 1217 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1218 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1219 }
1220
1221 /* Leave diag mode enabled for full-flushing done
1222 * in pci_iommu.c
1223 */
c1b1a5f1
DM		 1224 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1225 pbm->numa_node);
6d19c88f
DM		 1226 if (err) {
1227 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
ad7ad57c 1228 return err;
6d19c88f 1229 }
1da177e4 1230
51e85136 1231 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1da177e4
LT		 1232
1233 control = schizo_read(iommu->iommu_control);
1234 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1235 switch (tsbsize) {
1236 case 64:
1237 control |= SCHIZO_IOMMU_TSBSZ_64K;
1238 break;
1239 case 128:
1240 control |= SCHIZO_IOMMU_TSBSZ_128K;
1241 break;
6d19c88f 1242 }
1da177e4
LT		 1243
1244 control |= SCHIZO_IOMMU_CTRL_ENAB;
1245 schizo_write(iommu->iommu_control, control);
ad7ad57c
DM		 1246
1247 return 0;
1da177e4
LT		 1248}
1249
1250#define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1251#define SCHIZO_IRQ_RETRY_INF 0xffUL
1252
1253#define SCHIZO_PCI_DIAG (0x2020UL)
1254#define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1255#define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1256#define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1257#define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1258#define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1259#define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1260#define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1261#define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1262#define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1263
1264#define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1265#define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1266#define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1267#define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1268#define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1269#define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1270#define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1271#define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1272#define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1273#define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1274#define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1275#define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1276#define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1277#define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1278#define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1279#define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1280
1281#define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1282#define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1283
085ae41f 1284static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1da177e4 1285{
e87dc350 1286 struct property *prop;
1da177e4
LT		 1287 u64 tmp;
1288
864ae180 1289 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1da177e4 1290
1da177e4 1291 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4 1292
9fba62a5
DM		 1293 /* Enable arbiter for all PCI slots. */
1294 tmp |= 0xff;
1295
1da177e4
LT		 1296 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1297 pbm->chip_version >= 0x2)
1298 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1da177e4 1299
e87dc350
DM		 1300 prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL);
1301 if (!prop)
1da177e4 1302 tmp |= SCHIZO_PCICTRL_PARK;
9fba62a5
DM		 1303 else
1304 tmp &= ~SCHIZO_PCICTRL_PARK;
1da177e4
LT		 1305
1306 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1307 pbm->chip_version <= 0x1)
9fba62a5 1308 tmp |= SCHIZO_PCICTRL_DTO_INT;
1da177e4 1309 else
9fba62a5 1310 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1da177e4
LT		 1311
1312 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1313 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1314 SCHIZO_PCICTRL_RDO_PREF |
1315 SCHIZO_PCICTRL_RDL_PREF);
1316
1317 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1318
1319 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1320 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1321 SCHIZO_PCIDIAG_D_RETRY |
1322 SCHIZO_PCIDIAG_D_INTSYNC);
1323 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1324
1325 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1326 /* Clear prefetch lengths to workaround a bug in
1327 * Jalapeno...
1328 */
1329 tmp = (TOMATILLO_IOC_PART_WPENAB |
1330 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1331 TOMATILLO_IOC_RDMULT_CPENAB |
1332 TOMATILLO_IOC_RDONE_CPENAB |
1333 TOMATILLO_IOC_RDLINE_CPENAB);
1334
1335 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1336 tmp);
1337 }
1338}
1339
6d19c88f
DM		 1340static int __devinit schizo_pbm_init(struct pci_controller_info *p,
1341 struct device_node *dp, u32 portid,
1342 int chip_type)
1da177e4 1343{
a165b420 1344 const struct linux_prom64_registers *regs;
1da177e4
LT		 1345 struct pci_pbm_info *pbm;
1346 const char *chipset_name;
ad7ad57c 1347 int is_pbm_a, err;
1da177e4
LT		 1348
1349 switch (chip_type) {
1350 case PBM_CHIP_TYPE_TOMATILLO:
1351 chipset_name = "TOMATILLO";
1352 break;
1353
1354 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1355 chipset_name = "SCHIZO+";
1356 break;
1357
1358 case PBM_CHIP_TYPE_SCHIZO:
1359 default:
1360 chipset_name = "SCHIZO";
1361 break;
1362 };
1363
1364 /* For SCHIZO, three OBP regs:
1365 * 1) PBM controller regs
1366 * 2) Schizo front-end controller regs (same for both PBMs)
1367 * 3) PBM PCI config space
1368 *
1369 * For TOMATILLO, four OBP regs:
1370 * 1) PBM controller regs
1371 * 2) Tomatillo front-end controller regs
1372 * 3) PBM PCI config space
1373 * 4) Ichip regs
1374 */
bc606f3c 1375 regs = of_get_property(dp, "reg", NULL);
1da177e4 1376
e87dc350 1377 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1da177e4
LT		 1378 if (is_pbm_a)
1379 pbm = &p->pbm_A;
1380 else
1381 pbm = &p->pbm_B;
1382
34768bc8
DM		 1383 pbm->next = pci_pbm_root;
1384 pci_pbm_root = pbm;
1385
c1b1a5f1
DM		 1386 pbm->numa_node = -1;
1387
ca3dd88e
DM		 1388 pbm->pci_ops = &sun4u_pci_ops;
1389 pbm->config_space_reg_bits = 8;
34768bc8 1390
6c108f12
DM		 1391 pbm->index = pci_num_pbms++;
1392
1da177e4
LT		 1393 pbm->portid = portid;
1394 pbm->parent = p;
e87dc350 1395 pbm->prom_node = dp;
1da177e4
LT		 1396
1397 pbm->chip_type = chip_type;
bc606f3c
DM		 1398 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1399 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
e87dc350
DM		 1400
1401 pbm->pbm_regs = regs[0].phys_addr;
1402 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1da177e4 1403
bb6743f4 1404 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
e87dc350 1405 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
bb6743f4 1406
e87dc350 1407 pbm->name = dp->full_name;
1da177e4 1408
e87dc350 1409 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
bc606f3c 1410 pbm->name, chipset_name,
e87dc350 1411 pbm->chip_version, pbm->chip_revision);
1da177e4
LT		 1412
1413 schizo_pbm_hw_init(pbm);
1414
9fd8b647 1415 pci_determine_mem_io_space(pbm);
1da177e4 1416
cfa0652c 1417 pci_get_pbm_props(pbm);
1da177e4 1418
ad7ad57c
DM		 1419 err = schizo_pbm_iommu_init(pbm);
1420 if (err)
1421 return err;
1422
1da177e4 1423 schizo_pbm_strbuf_init(pbm);
ad7ad57c 1424
6d19c88f
DM		 1425 schizo_scan_bus(pbm);
1426
ad7ad57c 1427 return 0;
1da177e4
LT		 1428}
1429
1430static inline int portid_compare(u32 x, u32 y, int chip_type)
1431{
1432 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1433 if (x == (y ^ 1))
1434 return 1;
1435 return 0;
1436 }
1437 return (x == y);
1438}
1439
6d19c88f 1440static int __devinit __schizo_init(struct device_node *dp, unsigned long chip_type)
1da177e4
LT		 1441{
1442 struct pci_controller_info *p;
34768bc8 1443 struct pci_pbm_info *pbm;
16ce82d8 1444 struct iommu *iommu;
1da177e4 1445 u32 portid;
d7472c38 1446 int err;
1da177e4 1447
bc606f3c 1448 portid = of_getintprop_default(dp, "portid", 0xff);
1da177e4 1449
d7472c38 1450 err = -ENOMEM;
34768bc8 1451 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1da177e4 1452 if (portid_compare(pbm->portid, portid, chip_type)) {
ad7ad57c
DM		 1453 if (schizo_pbm_init(pbm->parent, dp,
1454 portid, chip_type))
d7472c38 1455 goto out_err;
6d19c88f 1456 return 0;
1da177e4
LT		 1457 }
1458 }
1459
9132983a 1460 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
6d19c88f
DM		 1461 if (!p) {
1462 printk(KERN_ERR PFX "Cannot allocate controller info.\n");
d7472c38 1463 goto out_err;
6d19c88f 1464 }
1da177e4 1465
16ce82d8 1466 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
6d19c88f
DM		 1467 if (!iommu) {
1468 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
d7472c38 1469 goto out_free_controller;
6d19c88f 1470 }
bc606f3c 1471
1da177e4
LT		 1472 p->pbm_A.iommu = iommu;
1473
16ce82d8 1474 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
6d19c88f
DM		 1475 if (!iommu) {
1476 printk(KERN_ERR PFX "Cannot allocate PBM B iommu.\n");
d7472c38 1477 goto out_free_iommu_A;
6d19c88f 1478 }
bc606f3c 1479
1da177e4
LT		 1480 p->pbm_B.iommu = iommu;
1481
ad7ad57c 1482 if (schizo_pbm_init(p, dp, portid, chip_type))
d7472c38 1483 goto out_free_iommu_B;
ad7ad57c 1484
6d19c88f 1485 return 0;
bc606f3c 1486
d7472c38
DM		 1487out_free_iommu_B:
1488 kfree(p->pbm_B.iommu);
1489
1490out_free_iommu_A:
1491 kfree(p->pbm_A.iommu);
1492
1493out_free_controller:
1494 kfree(p);
1495
1496out_err:
1497 return err;
1da177e4
LT		 1498}
1499
6d19c88f
DM		 1500static int __devinit schizo_probe(struct of_device *op,
1501 const struct of_device_id *match)
1da177e4 1502{
6d19c88f 1503 return __schizo_init(op->node, (unsigned long) match->data);
1da177e4
LT		 1504}
1505
6d19c88f
DM		 1506/* The ordering of this table is very important. Some Tomatillo
1507 * nodes announce that they are compatible with both pci108e,a801
1508 * and pci108e,8001. So list the chips in reverse chronological
1509 * order.
1510 */
fd098316 1511static struct of_device_id __initdata schizo_match[] = {
6d19c88f
DM		 1512 {
1513 .name = "pci",
1514 .compatible = "pci108e,a801",
1515 .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1516 },
1517 {
1518 .name = "pci",
1519 .compatible = "pci108e,8002",
1520 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1521 },
1522 {
1523 .name = "pci",
1524 .compatible = "pci108e,8001",
1525 .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1526 },
1527 {},
1528};
1da177e4 1529
6d19c88f
DM		 1530static struct of_platform_driver schizo_driver = {
1531 .name = DRIVER_NAME,
1532 .match_table = schizo_match,
1533 .probe = schizo_probe,
1534};
1535
1536static int __init schizo_init(void)
1da177e4 1537{
6d19c88f 1538 return of_register_driver(&schizo_driver, &of_bus_type);
1da177e4 1539}
6d19c88f
DM		 1540
1541subsys_initcall(schizo_init);
Linux kernel - Deliverables
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