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[SPARC64] PCI: Consolidate PCI access code into pci_common.c
[deliverable/linux.git] / arch / sparc64 / kernel / pci_schizo.c
CommitLineData
9fd8b647 1/* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 2001, 2002, 2003, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/interrupt.h>
12
1da177e4
LT		 13#include <asm/iommu.h>
14#include <asm/irq.h>
15#include <asm/upa.h>
bb6743f4 16#include <asm/pstate.h>
e87dc350 17#include <asm/prom.h>
c57c2ffb
DM		 18#include <asm/of_device.h>
19#include <asm/oplib.h>
1da177e4
LT		 20
21#include "pci_impl.h"
22#include "iommu_common.h"
23
24/* All SCHIZO registers are 64-bits. The following accessor
25 * routines are how they are accessed. The REG parameter
26 * is a physical address.
27 */
28#define schizo_read(__reg) \
29({ u64 __ret; \
30 __asm__ __volatile__("ldxa [%1] %2, %0" \
31 : "=r" (__ret) \
32 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
33 : "memory"); \
34 __ret; \
35})
36#define schizo_write(__reg, __val) \
37 __asm__ __volatile__("stxa %0, [%1] %2" \
38 : /* no outputs */ \
39 : "r" (__val), "r" (__reg), \
40 "i" (ASI_PHYS_BYPASS_EC_E) \
41 : "memory")
42
43/* This is a convention that at least Excalibur and Merlin
44 * follow. I suppose the SCHIZO used in Starcat and friends
45 * will do similar.
46 *
47 * The only way I could see this changing is if the newlink
48 * block requires more space in Schizo's address space than
49 * they predicted, thus requiring an address space reorg when
50 * the newer Schizo is taped out.
51 */
52
53/* Streaming buffer control register. */
54#define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
55#define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
56#define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
57#define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
58#define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
59
60/* IOMMU control register. */
61#define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
62#define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
63#define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
64#define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
65#define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
66#define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
67#define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
68#define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
69#define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
70#define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
71#define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
72#define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
73#define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
74#define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
75#define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
76#define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
77#define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
78#define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
79
80/* Schizo config space address format is nearly identical to
81 * that of PSYCHO:
82 *
83 * 32 24 23 16 15 11 10 8 7 2 1 0
84 * ---------------------------------------------------------
85 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
86 * ---------------------------------------------------------
87 */
88#define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
89#define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
90 (((unsigned long)(BUS) << 16) | \
91 ((unsigned long)(DEVFN) << 8) | \
92 ((unsigned long)(REG)))
93
94static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
95 unsigned char bus,
96 unsigned int devfn,
97 int where)
98{
99 if (!pbm)
100 return NULL;
101 bus -= pbm->pci_first_busno;
102 return (void *)
103 (SCHIZO_CONFIG_BASE(pbm) |
104 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
105}
106
1da177e4
LT		 107/* SCHIZO error handling support. */
108enum schizo_error_type {
109 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
110};
111
112static DEFINE_SPINLOCK(stc_buf_lock);
113static unsigned long stc_error_buf[128];
114static unsigned long stc_tag_buf[16];
115static unsigned long stc_line_buf[16];
116
117#define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
118#define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
119#define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
120#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
121#define SCHIZO_SERR_INO 0x34 /* Safari interface error */
122
1da177e4
LT		 123#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
124#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
125#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
126
127#define SCHIZO_STCERR_WRITE 0x2UL
128#define SCHIZO_STCERR_READ 0x1UL
129
130#define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
131#define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
132#define SCHIZO_STCTAG_VALID 0x8000000000000000UL
133#define SCHIZO_STCTAG_READ 0x4000000000000000UL
134
135#define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
136#define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
137#define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
138#define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
139#define SCHIZO_STCLINE_VALID 0x0000000000600000UL
140#define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
141
142static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
143 enum schizo_error_type type)
144{
16ce82d8 145 struct strbuf *strbuf = &pbm->stc;
1da177e4
LT		 146 unsigned long regbase = pbm->pbm_regs;
147 unsigned long err_base, tag_base, line_base;
148 u64 control;
149 int i;
150
151 err_base = regbase + SCHIZO_STC_ERR;
152 tag_base = regbase + SCHIZO_STC_TAG;
153 line_base = regbase + SCHIZO_STC_LINE;
154
155 spin_lock(&stc_buf_lock);
156
157 /* This is __REALLY__ dangerous. When we put the
158 * streaming buffer into diagnostic mode to probe
159 * it's tags and error status, we _must_ clear all
160 * of the line tag valid bits before re-enabling
161 * the streaming buffer. If any dirty data lives
162 * in the STC when we do this, we will end up
163 * invalidating it before it has a chance to reach
164 * main memory.
165 */
166 control = schizo_read(strbuf->strbuf_control);
167 schizo_write(strbuf->strbuf_control,
168 (control | SCHIZO_STRBUF_CTRL_DENAB));
169 for (i = 0; i < 128; i++) {
170 unsigned long val;
171
172 val = schizo_read(err_base + (i * 8UL));
173 schizo_write(err_base + (i * 8UL), 0UL);
174 stc_error_buf[i] = val;
175 }
176 for (i = 0; i < 16; i++) {
177 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
178 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
179 schizo_write(tag_base + (i * 8UL), 0UL);
180 schizo_write(line_base + (i * 8UL), 0UL);
181 }
182
183 /* OK, state is logged, exit diagnostic mode. */
184 schizo_write(strbuf->strbuf_control, control);
185
186 for (i = 0; i < 16; i++) {
187 int j, saw_error, first, last;
188
189 saw_error = 0;
190 first = i * 8;
191 last = first + 8;
192 for (j = first; j < last; j++) {
193 unsigned long errval = stc_error_buf[j];
194 if (errval != 0) {
195 saw_error++;
196 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
197 pbm->name,
198 j,
199 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
200 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
201 }
202 }
203 if (saw_error != 0) {
204 unsigned long tagval = stc_tag_buf[i];
205 unsigned long lineval = stc_line_buf[i];
206 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
207 pbm->name,
208 i,
209 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
210 (tagval & SCHIZO_STCTAG_VPN),
211 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
212 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
213
214 /* XXX Should spit out per-bank error information... -DaveM */
215 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
216 "V(%d)FOFN(%d)]\n",
217 pbm->name,
218 i,
219 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
220 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
221 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
222 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
223 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
224 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
225 }
226 }
227
228 spin_unlock(&stc_buf_lock);
229}
230
231/* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
232 * controller level errors.
233 */
234
235#define SCHIZO_IOMMU_TAG 0xa580UL
236#define SCHIZO_IOMMU_DATA 0xa600UL
237
238#define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
239#define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
240#define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
241#define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
242#define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
243#define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
244#define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
245
246#define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
247#define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
248#define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
249
250static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
251 enum schizo_error_type type)
252{
16ce82d8 253 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 254 unsigned long iommu_tag[16];
255 unsigned long iommu_data[16];
256 unsigned long flags;
257 u64 control;
258 int i;
259
260 spin_lock_irqsave(&iommu->lock, flags);
261 control = schizo_read(iommu->iommu_control);
262 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
263 unsigned long base;
264 char *type_string;
265
266 /* Clear the error encountered bit. */
267 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
268 schizo_write(iommu->iommu_control, control);
269
270 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
271 case 0:
272 type_string = "Protection Error";
273 break;
274 case 1:
275 type_string = "Invalid Error";
276 break;
277 case 2:
278 type_string = "TimeOut Error";
279 break;
280 case 3:
281 default:
282 type_string = "ECC Error";
283 break;
284 };
285 printk("%s: IOMMU Error, type[%s]\n",
286 pbm->name, type_string);
287
288 /* Put the IOMMU into diagnostic mode and probe
289 * it's TLB for entries with error status.
290 *
291 * It is very possible for another DVMA to occur
292 * while we do this probe, and corrupt the system
293 * further. But we are so screwed at this point
294 * that we are likely to crash hard anyways, so
295 * get as much diagnostic information to the
296 * console as we can.
297 */
298 schizo_write(iommu->iommu_control,
299 control | SCHIZO_IOMMU_CTRL_DENAB);
300
301 base = pbm->pbm_regs;
302
303 for (i = 0; i < 16; i++) {
304 iommu_tag[i] =
305 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
306 iommu_data[i] =
307 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
308
309 /* Now clear out the entry. */
310 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
311 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
312 }
313
314 /* Leave diagnostic mode. */
315 schizo_write(iommu->iommu_control, control);
316
317 for (i = 0; i < 16; i++) {
318 unsigned long tag, data;
319
320 tag = iommu_tag[i];
321 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
322 continue;
323
324 data = iommu_data[i];
325 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
326 case 0:
327 type_string = "Protection Error";
328 break;
329 case 1:
330 type_string = "Invalid Error";
331 break;
332 case 2:
333 type_string = "TimeOut Error";
334 break;
335 case 3:
336 default:
337 type_string = "ECC Error";
338 break;
339 };
340 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
341 "sz(%dK) vpg(%08lx)]\n",
342 pbm->name, i, type_string,
343 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
344 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
345 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
346 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
347 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
348 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
349 pbm->name, i,
350 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
351 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
352 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
353 }
354 }
355 if (pbm->stc.strbuf_enabled)
356 __schizo_check_stc_error_pbm(pbm, type);
357 spin_unlock_irqrestore(&iommu->lock, flags);
358}
359
360static void schizo_check_iommu_error(struct pci_controller_info *p,
361 enum schizo_error_type type)
362{
363 schizo_check_iommu_error_pbm(&p->pbm_A, type);
364 schizo_check_iommu_error_pbm(&p->pbm_B, type);
365}
366
367/* Uncorrectable ECC error status gathering. */
368#define SCHIZO_UE_AFSR 0x10030UL
369#define SCHIZO_UE_AFAR 0x10038UL
370
371#define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
372#define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
373#define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
374#define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
375#define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
376#define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
377#define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
378#define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
379#define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
380#define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
381#define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
382#define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
383#define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
384#define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
385
6d24c8dc 386static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
1da177e4 387{
34768bc8
DM		 388 struct pci_pbm_info *pbm = dev_id;
389 struct pci_controller_info *p = pbm->parent;
390 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
391 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
1da177e4
LT		 392 unsigned long afsr, afar, error_bits;
393 int reported, limit;
394
395 /* Latch uncorrectable error status. */
396 afar = schizo_read(afar_reg);
397
398 /* If either of the error pending bits are set in the
399 * AFSR, the error status is being actively updated by
400 * the hardware and we must re-read to get a clean value.
401 */
402 limit = 1000;
403 do {
404 afsr = schizo_read(afsr_reg);
405 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
406
407 /* Clear the primary/secondary error status bits. */
408 error_bits = afsr &
409 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
410 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
411 if (!error_bits)
412 return IRQ_NONE;
413 schizo_write(afsr_reg, error_bits);
414
415 /* Log the error. */
6c108f12
DM		 416 printk("%s: Uncorrectable Error, primary error type[%s]\n",
417 pbm->name,
1da177e4
LT		 418 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
419 "PIO" :
420 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
421 "DMA Read" :
422 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
423 "DMA Write" : "???")))));
6c108f12
DM		 424 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
425 pbm->name,
1da177e4
LT		 426 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
427 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
428 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 429 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
430 pbm->name,
1da177e4
LT		 431 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
432 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
433 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
434 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
435 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 436 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
437 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 438 reported = 0;
439 if (afsr & SCHIZO_UEAFSR_SPIO) {
440 reported++;
441 printk("(PIO)");
442 }
443 if (afsr & SCHIZO_UEAFSR_SDMA) {
444 reported++;
445 printk("(DMA)");
446 }
447 if (!reported)
448 printk("(none)");
449 printk("]\n");
450
451 /* Interrogate IOMMU for error status. */
452 schizo_check_iommu_error(p, UE_ERR);
453
1da177e4
LT		 454 return IRQ_HANDLED;
455}
456
457#define SCHIZO_CE_AFSR 0x10040UL
458#define SCHIZO_CE_AFAR 0x10048UL
459
460#define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
461#define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
462#define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
463#define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
464#define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
465#define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
466#define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
467#define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
468#define SCHIZO_CEAFSR_AID 0x000000001f000000UL
469#define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
470#define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
471#define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
472#define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
473#define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
474
6d24c8dc 475static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
1da177e4 476{
34768bc8 477 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 478 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
479 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
1da177e4
LT		 480 unsigned long afsr, afar, error_bits;
481 int reported, limit;
482
483 /* Latch error status. */
484 afar = schizo_read(afar_reg);
485
486 /* If either of the error pending bits are set in the
487 * AFSR, the error status is being actively updated by
488 * the hardware and we must re-read to get a clean value.
489 */
490 limit = 1000;
491 do {
492 afsr = schizo_read(afsr_reg);
493 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
494
495 /* Clear primary/secondary error status bits. */
496 error_bits = afsr &
497 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
498 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
499 if (!error_bits)
500 return IRQ_NONE;
501 schizo_write(afsr_reg, error_bits);
502
503 /* Log the error. */
6c108f12
DM		 504 printk("%s: Correctable Error, primary error type[%s]\n",
505 pbm->name,
1da177e4
LT		 506 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
507 "PIO" :
508 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
509 "DMA Read" :
510 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
511 "DMA Write" : "???")))));
512
513 /* XXX Use syndrome and afar to print out module string just like
514 * XXX UDB CE trap handler does... -DaveM
515 */
6c108f12
DM		 516 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
517 pbm->name,
1da177e4
LT		 518 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
519 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
520 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 521 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
522 pbm->name,
1da177e4
LT		 523 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
524 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
525 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
526 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
527 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 528 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
529 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 530 reported = 0;
531 if (afsr & SCHIZO_CEAFSR_SPIO) {
532 reported++;
533 printk("(PIO)");
534 }
535 if (afsr & SCHIZO_CEAFSR_SDMA) {
536 reported++;
537 printk("(DMA)");
538 }
539 if (!reported)
540 printk("(none)");
541 printk("]\n");
542
1da177e4
LT		 543 return IRQ_HANDLED;
544}
545
546#define SCHIZO_PCI_AFSR 0x2010UL
547#define SCHIZO_PCI_AFAR 0x2018UL
548
549#define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
550#define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
551#define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
552#define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
553#define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
554#define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
555#define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
556#define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
557#define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
558#define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
559#define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
560#define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
561#define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
562#define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
563#define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
564#define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
565#define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
566
567#define SCHIZO_PCI_CTRL (0x2000UL)
568#define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
9fba62a5 569#define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
1da177e4
LT		 570#define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
571#define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
572#define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
573#define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
574#define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
575#define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
576#define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
577#define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
578#define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
579#define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
580#define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
581#define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
582#define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
583#define SCHIZO_PCICTRL_PTO_SHIFT 24UL
584#define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
585#define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
586#define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
587#define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
588#define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
589#define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
590#define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
591#define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
592#define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
593#define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
594#define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
595
596static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
597{
598 unsigned long csr_reg, csr, csr_error_bits;
599 irqreturn_t ret = IRQ_NONE;
600 u16 stat;
601
602 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
603 csr = schizo_read(csr_reg);
604 csr_error_bits =
605 csr & (SCHIZO_PCICTRL_BUS_UNUS |
606 SCHIZO_PCICTRL_TTO_ERR |
607 SCHIZO_PCICTRL_RTRY_ERR |
608 SCHIZO_PCICTRL_DTO_ERR |
609 SCHIZO_PCICTRL_SBH_ERR |
610 SCHIZO_PCICTRL_SERR);
611 if (csr_error_bits) {
612 /* Clear the errors. */
613 schizo_write(csr_reg, csr);
614
615 /* Log 'em. */
616 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
617 printk("%s: Bus unusable error asserted.\n",
618 pbm->name);
619 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
620 printk("%s: PCI TRDY# timeout error asserted.\n",
621 pbm->name);
622 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
623 printk("%s: PCI excessive retry error asserted.\n",
624 pbm->name);
625 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
626 printk("%s: PCI discard timeout error asserted.\n",
627 pbm->name);
628 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
629 printk("%s: PCI streaming byte hole error asserted.\n",
630 pbm->name);
631 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
632 printk("%s: PCI SERR signal asserted.\n",
633 pbm->name);
634 ret = IRQ_HANDLED;
635 }
636 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
637 if (stat & (PCI_STATUS_PARITY |
638 PCI_STATUS_SIG_TARGET_ABORT |
639 PCI_STATUS_REC_TARGET_ABORT |
640 PCI_STATUS_REC_MASTER_ABORT |
641 PCI_STATUS_SIG_SYSTEM_ERROR)) {
642 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
643 pbm->name, stat);
644 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
645 ret = IRQ_HANDLED;
646 }
647 return ret;
648}
649
6d24c8dc 650static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 651{
652 struct pci_pbm_info *pbm = dev_id;
653 struct pci_controller_info *p = pbm->parent;
654 unsigned long afsr_reg, afar_reg, base;
655 unsigned long afsr, afar, error_bits;
656 int reported;
657
658 base = pbm->pbm_regs;
659
660 afsr_reg = base + SCHIZO_PCI_AFSR;
661 afar_reg = base + SCHIZO_PCI_AFAR;
662
663 /* Latch error status. */
664 afar = schizo_read(afar_reg);
665 afsr = schizo_read(afsr_reg);
666
667 /* Clear primary/secondary error status bits. */
668 error_bits = afsr &
669 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
670 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
671 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
672 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
673 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
674 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
675 if (!error_bits)
676 return schizo_pcierr_intr_other(pbm);
677 schizo_write(afsr_reg, error_bits);
678
679 /* Log the error. */
680 printk("%s: PCI Error, primary error type[%s]\n",
681 pbm->name,
682 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
683 "Master Abort" :
684 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
685 "Target Abort" :
686 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
687 "Excessive Retries" :
688 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
689 "Parity Error" :
690 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
691 "Timeout" :
692 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
693 "Bus Unusable" : "???"))))))));
694 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
695 pbm->name,
696 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
697 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
698 ((afsr & SCHIZO_PCIAFSR_CFG) ?
699 "Config" :
700 ((afsr & SCHIZO_PCIAFSR_MEM) ?
701 "Memory" :
702 ((afsr & SCHIZO_PCIAFSR_IO) ?
703 "I/O" : "???"))));
704 printk("%s: PCI AFAR [%016lx]\n",
705 pbm->name, afar);
706 printk("%s: PCI Secondary errors [",
707 pbm->name);
708 reported = 0;
709 if (afsr & SCHIZO_PCIAFSR_SMA) {
710 reported++;
711 printk("(Master Abort)");
712 }
713 if (afsr & SCHIZO_PCIAFSR_STA) {
714 reported++;
715 printk("(Target Abort)");
716 }
717 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
718 reported++;
719 printk("(Excessive Retries)");
720 }
721 if (afsr & SCHIZO_PCIAFSR_SPERR) {
722 reported++;
723 printk("(Parity Error)");
724 }
725 if (afsr & SCHIZO_PCIAFSR_STTO) {
726 reported++;
727 printk("(Timeout)");
728 }
729 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
730 reported++;
731 printk("(Bus Unusable)");
732 }
733 if (!reported)
734 printk("(none)");
735 printk("]\n");
736
737 /* For the error types shown, scan PBM's PCI bus for devices
738 * which have logged that error type.
739 */
740
741 /* If we see a Target Abort, this could be the result of an
742 * IOMMU translation error of some sort. It is extremely
743 * useful to log this information as usually it indicates
744 * a bug in the IOMMU support code or a PCI device driver.
745 */
746 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
747 schizo_check_iommu_error(p, PCI_ERR);
6c108f12 748 pci_scan_for_target_abort(pbm, pbm->pci_bus);
1da177e4
LT		 749 }
750 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
6c108f12 751 pci_scan_for_master_abort(pbm, pbm->pci_bus);
1da177e4
LT		 752
753 /* For excessive retries, PSYCHO/PBM will abort the device
754 * and there is no way to specifically check for excessive
755 * retries in the config space status registers. So what
756 * we hope is that we'll catch it via the master/target
757 * abort events.
758 */
759
760 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
6c108f12 761 pci_scan_for_parity_error(pbm, pbm->pci_bus);
1da177e4 762
1da177e4
LT		 763 return IRQ_HANDLED;
764}
765
766#define SCHIZO_SAFARI_ERRLOG 0x10018UL
767
768#define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
769
770#define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
771#define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
772#define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
773#define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
774#define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
775#define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
776#define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
777#define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
778#define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
779#define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
780#define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
781#define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
782#define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
783#define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
784#define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
785#define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
786#define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
787#define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
788#define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
789#define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
790#define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
791#define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
792#define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
793#define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
794#define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
795#define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
796#define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
797#define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
798#define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
799#define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
800#define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
801
802/* We only expect UNMAP errors here. The rest of the Safari errors
803 * are marked fatal and thus cause a system reset.
804 */
6d24c8dc 805static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
1da177e4 806{
34768bc8
DM		 807 struct pci_pbm_info *pbm = dev_id;
808 struct pci_controller_info *p = pbm->parent;
1da177e4
LT		 809 u64 errlog;
810
34768bc8
DM		 811 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
812 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG,
1da177e4
LT		 813 errlog & ~(SAFARI_ERRLOG_ERROUT));
814
815 if (!(errlog & BUS_ERROR_UNMAP)) {
6c108f12
DM		 816 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
817 pbm->name, errlog);
1da177e4 818
1da177e4
LT		 819 return IRQ_HANDLED;
820 }
821
6c108f12
DM		 822 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
823 pbm->name);
1da177e4
LT		 824 schizo_check_iommu_error(p, SAFARI_ERR);
825
1da177e4
LT		 826 return IRQ_HANDLED;
827}
828
829/* Nearly identical to PSYCHO equivalents... */
830#define SCHIZO_ECC_CTRL 0x10020UL
831#define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
832#define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
833#define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
834
835#define SCHIZO_SAFARI_ERRCTRL 0x10008UL
836#define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
837#define SCHIZO_SAFARI_IRQCTRL 0x10010UL
838#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
839
34768bc8
DM		 840static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
841{
842 ino &= IMAP_INO;
843
844 if (pbm->ino_bitmap & (1UL << ino))
845 return 1;
846
847 return 0;
848}
849
1da177e4
LT		 850/* How the Tomatillo IRQs are routed around is pure guesswork here.
851 *
852 * All the Tomatillo devices I see in prtconf dumps seem to have only
853 * a single PCI bus unit attached to it. It would seem they are seperate
854 * devices because their PortID (ie. JBUS ID) values are all different
855 * and thus the registers are mapped to totally different locations.
856 *
857 * However, two Tomatillo's look "similar" in that the only difference
858 * in their PortID is the lowest bit.
859 *
860 * So if we were to ignore this lower bit, it certainly looks like two
861 * PCI bus units of the same Tomatillo. I still have not really
862 * figured this out...
863 */
34768bc8 864static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 865{
34768bc8 866 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 867 u64 tmp, err_mask, err_no_mask;
af80318e 868 int err;
1da177e4 869
2b1e5978
DM		 870 /* Tomatillo IRQ property layout is:
871 * 0: PCIERR
872 * 1: UE ERR
873 * 2: CE ERR
874 * 3: SERR
875 * 4: POWER FAIL?
876 */
877
af80318e
DM		 878 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
879 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
880 "TOMATILLO_UE", pbm);
881 if (err)
882 printk(KERN_WARNING "%s: Could not register UE, "
883 "err=%d\n", pbm->name, err);
884 }
885 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
886 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
887 "TOMATILLO_CE", pbm);
888 if (err)
889 printk(KERN_WARNING "%s: Could not register CE, "
890 "err=%d\n", pbm->name, err);
891 }
892 err = 0;
893 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
894 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
895 "TOMATILLO_PCIERR", pbm);
896 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
897 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
898 "TOMATILLO_PCIERR", pbm);
899 }
900 if (err)
901 printk(KERN_WARNING "%s: Could not register PCIERR, "
902 "err=%d\n", pbm->name, err);
903
904 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
905 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
906 "TOMATILLO_SERR", pbm);
907 if (err)
908 printk(KERN_WARNING "%s: Could not register SERR, "
909 "err=%d\n", pbm->name, err);
910 }
34768bc8
DM		 911
912 /* Enable UE and CE interrupts for controller. */
913 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 914 (SCHIZO_ECCCTRL_EE |
915 SCHIZO_ECCCTRL_UE |
916 SCHIZO_ECCCTRL_CE));
917
918 /* Enable PCI Error interrupts and clear error
919 * bits.
920 */
921 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
922 SCHIZO_PCICTRL_TTO_ERR |
923 SCHIZO_PCICTRL_RTRY_ERR |
924 SCHIZO_PCICTRL_SERR |
925 SCHIZO_PCICTRL_EEN);
926
927 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
928
34768bc8 929 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 930 tmp |= err_mask;
931 tmp &= ~err_no_mask;
34768bc8 932 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4
LT		 933
934 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
935 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
936 SCHIZO_PCIAFSR_PTTO |
937 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
938 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
939 SCHIZO_PCIAFSR_STTO);
940
34768bc8 941 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1da177e4
LT		 942
943 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
944 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
945 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
946 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
947 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
948 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
949 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
950 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
951 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
952
34768bc8 953 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4
LT		 954 (SCHIZO_SAFERRCTRL_EN | err_mask));
955
34768bc8 956 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL,
1da177e4
LT		 957 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
958}
959
34768bc8 960static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 961{
34768bc8 962 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 963 u64 tmp, err_mask, err_no_mask;
af80318e 964 int err;
1da177e4 965
2b1e5978
DM		 966 /* Schizo IRQ property layout is:
967 * 0: PCIERR
968 * 1: UE ERR
969 * 2: CE ERR
970 * 3: SERR
971 * 4: POWER FAIL?
972 */
973
af80318e
DM		 974 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
975 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
976 "SCHIZO_UE", pbm);
977 if (err)
978 printk(KERN_WARNING "%s: Could not register UE, "
979 "err=%d\n", pbm->name, err);
980 }
981 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
982 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
983 "SCHIZO_CE", pbm);
984 if (err)
985 printk(KERN_WARNING "%s: Could not register CE, "
986 "err=%d\n", pbm->name, err);
987 }
988 err = 0;
989 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
990 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
991 "SCHIZO_PCIERR", pbm);
992 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
993 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
994 "SCHIZO_PCIERR", pbm);
995 }
996 if (err)
997 printk(KERN_WARNING "%s: Could not register PCIERR, "
998 "err=%d\n", pbm->name, err);
999
1000 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
1001 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1002 "SCHIZO_SERR", pbm);
1003 if (err)
1004 printk(KERN_WARNING "%s: Could not register SERR, "
1005 "err=%d\n", pbm->name, err);
1006 }
1da177e4
LT		 1007
1008 /* Enable UE and CE interrupts for controller. */
34768bc8 1009 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 1010 (SCHIZO_ECCCTRL_EE |
1011 SCHIZO_ECCCTRL_UE |
1012 SCHIZO_ECCCTRL_CE));
1013
1014 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1015 SCHIZO_PCICTRL_ESLCK |
1016 SCHIZO_PCICTRL_TTO_ERR |
1017 SCHIZO_PCICTRL_RTRY_ERR |
1018 SCHIZO_PCICTRL_SBH_ERR |
1019 SCHIZO_PCICTRL_SERR |
1020 SCHIZO_PCICTRL_EEN);
1021
1022 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1023 SCHIZO_PCICTRL_SBH_INT);
1024
1025 /* Enable PCI Error interrupts and clear error
1026 * bits for each PBM.
1027 */
34768bc8 1028 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 1029 tmp |= err_mask;
1030 tmp &= ~err_no_mask;
34768bc8 1031 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4 1032
34768bc8 1033 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR,
1da177e4
LT		 1034 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1035 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1036 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1037 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1038 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1039 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1040
1041 /* Make all Safari error conditions fatal except unmapped
1042 * errors which we make generate interrupts.
1043 */
1044 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1045 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1046 BUS_ERROR_BADMC |
1047 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1048 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1049 BUS_ERROR_CIQTO |
1050 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1051 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1052 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1053 BUS_ERROR_ILL);
1054#if 1
1055 /* XXX Something wrong with some Excalibur systems
1056 * XXX Sun is shipping. The behavior on a 2-cpu
1057 * XXX machine is that both CPU1 parity error bits
1058 * XXX are set and are immediately set again when
1059 * XXX their error status bits are cleared. Just
1060 * XXX ignore them for now. -DaveM
1061 */
1062 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1063 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1064#endif
1065
34768bc8 1066 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4 1067 (SCHIZO_SAFERRCTRL_EN | err_mask));
1da177e4
LT		 1068}
1069
085ae41f 1070static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 1071{
1072 u8 *addr;
1073
1074 /* Set cache-line size to 64 bytes, this is actually
1075 * a nop but I do it for completeness.
1076 */
1077 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1078 0, PCI_CACHE_LINE_SIZE);
1079 pci_config_write8(addr, 64 / sizeof(u32));
1080
1081 /* Set PBM latency timer to 64 PCI clocks. */
1082 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1083 0, PCI_LATENCY_TIMER);
1084 pci_config_write8(addr, 64);
1085}
1086
34768bc8 1087static void schizo_scan_bus(struct pci_pbm_info *pbm)
1da177e4 1088{
34768bc8
DM		 1089 pbm_config_busmastering(pbm);
1090 pbm->is_66mhz_capable =
1091 (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
e87dc350 1092 != NULL);
bc606f3c 1093
34768bc8 1094 pbm->pci_bus = pci_scan_one_pbm(pbm);
1da177e4 1095
34768bc8
DM		 1096 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1097 tomatillo_register_error_handlers(pbm);
1da177e4 1098 else
34768bc8 1099 schizo_register_error_handlers(pbm);
1da177e4
LT		 1100}
1101
1da177e4
LT		 1102#define SCHIZO_STRBUF_CONTROL (0x02800UL)
1103#define SCHIZO_STRBUF_FLUSH (0x02808UL)
1104#define SCHIZO_STRBUF_FSYNC (0x02810UL)
1105#define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1106#define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1107
1108static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1109{
1110 unsigned long base = pbm->pbm_regs;
1111 u64 control;
1112
1113 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1114 /* TOMATILLO lacks streaming cache. */
1115 return;
1116 }
1117
1118 /* SCHIZO has context flushing. */
1119 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1120 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1121 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1122 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1123 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1124
1125 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1126 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1127 + 63UL)
1128 & ~63UL);
1129 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1130 __pa(pbm->stc.strbuf_flushflag);
1131
1132 /* Turn off LRU locking and diag mode, enable the
1133 * streaming buffer and leave the rerun-disable
1134 * setting however OBP set it.
1135 */
1136 control = schizo_read(pbm->stc.strbuf_control);
1137 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1138 SCHIZO_STRBUF_CTRL_LENAB |
1139 SCHIZO_STRBUF_CTRL_DENAB);
1140 control |= SCHIZO_STRBUF_CTRL_ENAB;
1141 schizo_write(pbm->stc.strbuf_control, control);
1142
1143 pbm->stc.strbuf_enabled = 1;
1144}
1145
1146#define SCHIZO_IOMMU_CONTROL (0x00200UL)
1147#define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1148#define SCHIZO_IOMMU_FLUSH (0x00210UL)
1149#define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1150
1151static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1152{
16ce82d8 1153 struct iommu *iommu = pbm->iommu;
51e85136 1154 unsigned long i, tagbase, database;
e87dc350 1155 struct property *prop;
1da177e4
LT		 1156 u32 vdma[2], dma_mask;
1157 u64 control;
e87dc350 1158 int tsbsize;
1da177e4 1159
e87dc350
DM		 1160 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
1161 if (prop) {
1162 u32 *val = prop->value;
1163
1164 vdma[0] = val[0];
1165 vdma[1] = val[1];
1166 } else {
1da177e4
LT		 1167 /* No property, use default values. */
1168 vdma[0] = 0xc0000000;
1169 vdma[1] = 0x40000000;
1170 }
1171
1172 dma_mask = vdma[0];
1173 switch (vdma[1]) {
1174 case 0x20000000:
1175 dma_mask |= 0x1fffffff;
1176 tsbsize = 64;
1177 break;
1178
1179 case 0x40000000:
1180 dma_mask |= 0x3fffffff;
1181 tsbsize = 128;
1182 break;
1183
1184 case 0x80000000:
1185 dma_mask |= 0x7fffffff;
1186 tsbsize = 128;
1187 break;
1188
1189 default:
1190 prom_printf("SCHIZO: strange virtual-dma size.\n");
1191 prom_halt();
1192 };
1193
1da177e4
LT		 1194 /* Register addresses, SCHIZO has iommu ctx flushing. */
1195 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1196 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1197 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1198 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1199
1200 /* We use the main control/status register of SCHIZO as the write
1201 * completion register.
1202 */
1203 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1204
1205 /*
1206 * Invalidate TLB Entries.
1207 */
1208 control = schizo_read(iommu->iommu_control);
1209 control |= SCHIZO_IOMMU_CTRL_DENAB;
1210 schizo_write(iommu->iommu_control, control);
1211
1212 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1213
1214 for(i = 0; i < 16; i++) {
1215 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1216 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1217 }
1218
1219 /* Leave diag mode enabled for full-flushing done
1220 * in pci_iommu.c
1221 */
51e85136 1222 pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
1da177e4 1223
51e85136 1224 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1da177e4
LT		 1225
1226 control = schizo_read(iommu->iommu_control);
1227 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1228 switch (tsbsize) {
1229 case 64:
1230 control |= SCHIZO_IOMMU_TSBSZ_64K;
1231 break;
1232 case 128:
1233 control |= SCHIZO_IOMMU_TSBSZ_128K;
1234 break;
1235 };
1236
1237 control |= SCHIZO_IOMMU_CTRL_ENAB;
1238 schizo_write(iommu->iommu_control, control);
1239}
1240
1241#define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1242#define SCHIZO_IRQ_RETRY_INF 0xffUL
1243
1244#define SCHIZO_PCI_DIAG (0x2020UL)
1245#define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1246#define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1247#define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1248#define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1249#define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1250#define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1251#define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1252#define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1253#define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1254
1255#define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1256#define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1257#define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1258#define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1259#define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1260#define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1261#define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1262#define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1263#define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1264#define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1265#define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1266#define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1267#define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1268#define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1269#define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1270#define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1271
1272#define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1273#define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1274
085ae41f 1275static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1da177e4 1276{
e87dc350 1277 struct property *prop;
1da177e4
LT		 1278 u64 tmp;
1279
864ae180 1280 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1da177e4 1281
1da177e4 1282 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4 1283
9fba62a5
DM		 1284 /* Enable arbiter for all PCI slots. */
1285 tmp |= 0xff;
1286
1da177e4
LT		 1287 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1288 pbm->chip_version >= 0x2)
1289 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1da177e4 1290
e87dc350
DM		 1291 prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL);
1292 if (!prop)
1da177e4 1293 tmp |= SCHIZO_PCICTRL_PARK;
9fba62a5
DM		 1294 else
1295 tmp &= ~SCHIZO_PCICTRL_PARK;
1da177e4
LT		 1296
1297 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1298 pbm->chip_version <= 0x1)
9fba62a5 1299 tmp |= SCHIZO_PCICTRL_DTO_INT;
1da177e4 1300 else
9fba62a5 1301 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1da177e4
LT		 1302
1303 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1304 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1305 SCHIZO_PCICTRL_RDO_PREF |
1306 SCHIZO_PCICTRL_RDL_PREF);
1307
1308 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1309
1310 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1311 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1312 SCHIZO_PCIDIAG_D_RETRY |
1313 SCHIZO_PCIDIAG_D_INTSYNC);
1314 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1315
1316 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1317 /* Clear prefetch lengths to workaround a bug in
1318 * Jalapeno...
1319 */
1320 tmp = (TOMATILLO_IOC_PART_WPENAB |
1321 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1322 TOMATILLO_IOC_RDMULT_CPENAB |
1323 TOMATILLO_IOC_RDONE_CPENAB |
1324 TOMATILLO_IOC_RDLINE_CPENAB);
1325
1326 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1327 tmp);
1328 }
1329}
1330
085ae41f 1331static void schizo_pbm_init(struct pci_controller_info *p,
e87dc350 1332 struct device_node *dp, u32 portid,
085ae41f 1333 int chip_type)
1da177e4 1334{
a165b420 1335 const struct linux_prom64_registers *regs;
1da177e4
LT		 1336 struct pci_pbm_info *pbm;
1337 const char *chipset_name;
1da177e4 1338 int is_pbm_a;
1da177e4
LT		 1339
1340 switch (chip_type) {
1341 case PBM_CHIP_TYPE_TOMATILLO:
1342 chipset_name = "TOMATILLO";
1343 break;
1344
1345 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1346 chipset_name = "SCHIZO+";
1347 break;
1348
1349 case PBM_CHIP_TYPE_SCHIZO:
1350 default:
1351 chipset_name = "SCHIZO";
1352 break;
1353 };
1354
1355 /* For SCHIZO, three OBP regs:
1356 * 1) PBM controller regs
1357 * 2) Schizo front-end controller regs (same for both PBMs)
1358 * 3) PBM PCI config space
1359 *
1360 * For TOMATILLO, four OBP regs:
1361 * 1) PBM controller regs
1362 * 2) Tomatillo front-end controller regs
1363 * 3) PBM PCI config space
1364 * 4) Ichip regs
1365 */
bc606f3c 1366 regs = of_get_property(dp, "reg", NULL);
1da177e4 1367
e87dc350 1368 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1da177e4
LT		 1369 if (is_pbm_a)
1370 pbm = &p->pbm_A;
1371 else
1372 pbm = &p->pbm_B;
1373
34768bc8
DM		 1374 pbm->next = pci_pbm_root;
1375 pci_pbm_root = pbm;
1376
1377 pbm->scan_bus = schizo_scan_bus;
ca3dd88e
DM		 1378 pbm->pci_ops = &sun4u_pci_ops;
1379 pbm->config_space_reg_bits = 8;
34768bc8 1380
6c108f12
DM		 1381 pbm->index = pci_num_pbms++;
1382
1da177e4
LT		 1383 pbm->portid = portid;
1384 pbm->parent = p;
e87dc350 1385 pbm->prom_node = dp;
1da177e4
LT		 1386
1387 pbm->chip_type = chip_type;
bc606f3c
DM		 1388 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1389 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
e87dc350
DM		 1390
1391 pbm->pbm_regs = regs[0].phys_addr;
1392 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1da177e4 1393
bb6743f4 1394 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
e87dc350 1395 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
bb6743f4 1396
e87dc350 1397 pbm->name = dp->full_name;
1da177e4 1398
e87dc350 1399 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
bc606f3c 1400 pbm->name, chipset_name,
e87dc350 1401 pbm->chip_version, pbm->chip_revision);
1da177e4
LT		 1402
1403 schizo_pbm_hw_init(pbm);
1404
9fd8b647 1405 pci_determine_mem_io_space(pbm);
1da177e4 1406
cfa0652c 1407 pci_get_pbm_props(pbm);
1da177e4
LT		 1408
1409 schizo_pbm_iommu_init(pbm);
1410 schizo_pbm_strbuf_init(pbm);
1411}
1412
1413static inline int portid_compare(u32 x, u32 y, int chip_type)
1414{
1415 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1416 if (x == (y ^ 1))
1417 return 1;
1418 return 0;
1419 }
1420 return (x == y);
1421}
1422
e87dc350 1423static void __schizo_init(struct device_node *dp, char *model_name, int chip_type)
1da177e4
LT		 1424{
1425 struct pci_controller_info *p;
34768bc8 1426 struct pci_pbm_info *pbm;
16ce82d8 1427 struct iommu *iommu;
1da177e4
LT		 1428 u32 portid;
1429
bc606f3c 1430 portid = of_getintprop_default(dp, "portid", 0xff);
1da177e4 1431
34768bc8 1432 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1da177e4 1433 if (portid_compare(pbm->portid, portid, chip_type)) {
34768bc8 1434 schizo_pbm_init(pbm->parent, dp, portid, chip_type);
1da177e4
LT		 1435 return;
1436 }
1437 }
1438
9132983a 1439 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
bc606f3c
DM		 1440 if (!p)
1441 goto memfail;
1da177e4 1442
16ce82d8 1443 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
bc606f3c
DM		 1444 if (!iommu)
1445 goto memfail;
1446
1da177e4
LT		 1447 p->pbm_A.iommu = iommu;
1448
16ce82d8 1449 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
bc606f3c
DM		 1450 if (!iommu)
1451 goto memfail;
1452
1da177e4
LT		 1453 p->pbm_B.iommu = iommu;
1454
1da177e4
LT		 1455 /* Like PSYCHO we have a 2GB aligned area for memory space. */
1456 pci_memspace_mask = 0x7fffffffUL;
1457
e87dc350 1458 schizo_pbm_init(p, dp, portid, chip_type);
bc606f3c
DM		 1459 return;
1460
1461memfail:
1462 prom_printf("SCHIZO: Fatal memory allocation error.\n");
1463 prom_halt();
1da177e4
LT		 1464}
1465
e87dc350 1466void schizo_init(struct device_node *dp, char *model_name)
1da177e4 1467{
e87dc350 1468 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO);
1da177e4
LT		 1469}
1470
e87dc350 1471void schizo_plus_init(struct device_node *dp, char *model_name)
1da177e4 1472{
e87dc350 1473 __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
1da177e4
LT		 1474}
1475
e87dc350 1476void tomatillo_init(struct device_node *dp, char *model_name)
1da177e4 1477{
e87dc350 1478 __schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO);
1da177e4 1479}
Linux kernel - Deliverables
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