Commit | Line | Data |
---|---|---|
8f6a93a1 DM |
1 | /* pci_sun4v.c: SUN4V specific PCI controller support. |
2 | * | |
d284142c | 3 | * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net) |
8f6a93a1 DM |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/types.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/interrupt.h> | |
18397944 | 12 | #include <linux/percpu.h> |
35a17eb6 DM |
13 | #include <linux/irq.h> |
14 | #include <linux/msi.h> | |
59db8102 | 15 | #include <linux/log2.h> |
8f6a93a1 | 16 | |
8f6a93a1 DM |
17 | #include <asm/iommu.h> |
18 | #include <asm/irq.h> | |
19 | #include <asm/upa.h> | |
20 | #include <asm/pstate.h> | |
21 | #include <asm/oplib.h> | |
22 | #include <asm/hypervisor.h> | |
e87dc350 | 23 | #include <asm/prom.h> |
8f6a93a1 DM |
24 | |
25 | #include "pci_impl.h" | |
26 | #include "iommu_common.h" | |
27 | ||
bade5622 DM |
28 | #include "pci_sun4v.h" |
29 | ||
e01c0d6d DM |
30 | static unsigned long vpci_major = 1; |
31 | static unsigned long vpci_minor = 1; | |
32 | ||
7c8f486a | 33 | #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64)) |
18397944 | 34 | |
16ce82d8 | 35 | struct iommu_batch { |
ad7ad57c | 36 | struct device *dev; /* Device mapping is for. */ |
6a32fd4d DM |
37 | unsigned long prot; /* IOMMU page protections */ |
38 | unsigned long entry; /* Index into IOTSB. */ | |
39 | u64 *pglist; /* List of physical pages */ | |
40 | unsigned long npages; /* Number of pages in list. */ | |
18397944 DM |
41 | }; |
42 | ||
ad7ad57c | 43 | static DEFINE_PER_CPU(struct iommu_batch, iommu_batch); |
6a32fd4d DM |
44 | |
45 | /* Interrupts must be disabled. */ | |
ad7ad57c | 46 | static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry) |
6a32fd4d | 47 | { |
ad7ad57c | 48 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d | 49 | |
ad7ad57c | 50 | p->dev = dev; |
6a32fd4d DM |
51 | p->prot = prot; |
52 | p->entry = entry; | |
53 | p->npages = 0; | |
54 | } | |
55 | ||
56 | /* Interrupts must be disabled. */ | |
ad7ad57c | 57 | static long iommu_batch_flush(struct iommu_batch *p) |
6a32fd4d | 58 | { |
ad7ad57c | 59 | struct pci_pbm_info *pbm = p->dev->archdata.host_controller; |
a2fb23af | 60 | unsigned long devhandle = pbm->devhandle; |
6a32fd4d DM |
61 | unsigned long prot = p->prot; |
62 | unsigned long entry = p->entry; | |
63 | u64 *pglist = p->pglist; | |
64 | unsigned long npages = p->npages; | |
65 | ||
d82965c1 | 66 | while (npages != 0) { |
6a32fd4d DM |
67 | long num; |
68 | ||
69 | num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry), | |
70 | npages, prot, __pa(pglist)); | |
71 | if (unlikely(num < 0)) { | |
72 | if (printk_ratelimit()) | |
ad7ad57c | 73 | printk("iommu_batch_flush: IOMMU map of " |
6a32fd4d DM |
74 | "[%08lx:%08lx:%lx:%lx:%lx] failed with " |
75 | "status %ld\n", | |
76 | devhandle, HV_PCI_TSBID(0, entry), | |
77 | npages, prot, __pa(pglist), num); | |
78 | return -1; | |
79 | } | |
80 | ||
81 | entry += num; | |
82 | npages -= num; | |
83 | pglist += num; | |
d82965c1 | 84 | } |
6a32fd4d DM |
85 | |
86 | p->entry = entry; | |
87 | p->npages = 0; | |
88 | ||
89 | return 0; | |
90 | } | |
91 | ||
13fa14e1 DM |
92 | static inline void iommu_batch_new_entry(unsigned long entry) |
93 | { | |
94 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); | |
95 | ||
96 | if (p->entry + p->npages == entry) | |
97 | return; | |
98 | if (p->entry != ~0UL) | |
99 | iommu_batch_flush(p); | |
100 | p->entry = entry; | |
101 | } | |
102 | ||
6a32fd4d | 103 | /* Interrupts must be disabled. */ |
ad7ad57c | 104 | static inline long iommu_batch_add(u64 phys_page) |
6a32fd4d | 105 | { |
ad7ad57c | 106 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d DM |
107 | |
108 | BUG_ON(p->npages >= PGLIST_NENTS); | |
109 | ||
110 | p->pglist[p->npages++] = phys_page; | |
111 | if (p->npages == PGLIST_NENTS) | |
ad7ad57c | 112 | return iommu_batch_flush(p); |
6a32fd4d DM |
113 | |
114 | return 0; | |
115 | } | |
116 | ||
117 | /* Interrupts must be disabled. */ | |
ad7ad57c | 118 | static inline long iommu_batch_end(void) |
6a32fd4d | 119 | { |
ad7ad57c | 120 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d DM |
121 | |
122 | BUG_ON(p->npages >= PGLIST_NENTS); | |
123 | ||
ad7ad57c | 124 | return iommu_batch_flush(p); |
6a32fd4d | 125 | } |
18397944 | 126 | |
ad7ad57c DM |
127 | static void *dma_4v_alloc_coherent(struct device *dev, size_t size, |
128 | dma_addr_t *dma_addrp, gfp_t gfp) | |
8f6a93a1 | 129 | { |
7c8f486a | 130 | unsigned long flags, order, first_page, npages, n; |
c1b1a5f1 DM |
131 | struct iommu *iommu; |
132 | struct page *page; | |
18397944 DM |
133 | void *ret; |
134 | long entry; | |
c1b1a5f1 | 135 | int nid; |
18397944 DM |
136 | |
137 | size = IO_PAGE_ALIGN(size); | |
138 | order = get_order(size); | |
6a32fd4d | 139 | if (unlikely(order >= MAX_ORDER)) |
18397944 DM |
140 | return NULL; |
141 | ||
142 | npages = size >> IO_PAGE_SHIFT; | |
18397944 | 143 | |
c1b1a5f1 DM |
144 | nid = dev->archdata.numa_node; |
145 | page = alloc_pages_node(nid, gfp, order); | |
146 | if (unlikely(!page)) | |
18397944 | 147 | return NULL; |
e7a0453e | 148 | |
c1b1a5f1 | 149 | first_page = (unsigned long) page_address(page); |
18397944 DM |
150 | memset((char *)first_page, 0, PAGE_SIZE << order); |
151 | ||
ad7ad57c | 152 | iommu = dev->archdata.iommu; |
18397944 DM |
153 | |
154 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 155 | entry = iommu_range_alloc(dev, iommu, npages, NULL); |
18397944 DM |
156 | spin_unlock_irqrestore(&iommu->lock, flags); |
157 | ||
d284142c DM |
158 | if (unlikely(entry == DMA_ERROR_CODE)) |
159 | goto range_alloc_fail; | |
18397944 DM |
160 | |
161 | *dma_addrp = (iommu->page_table_map_base + | |
162 | (entry << IO_PAGE_SHIFT)); | |
163 | ret = (void *) first_page; | |
164 | first_page = __pa(first_page); | |
165 | ||
6a32fd4d | 166 | local_irq_save(flags); |
18397944 | 167 | |
ad7ad57c DM |
168 | iommu_batch_start(dev, |
169 | (HV_PCI_MAP_ATTR_READ | | |
170 | HV_PCI_MAP_ATTR_WRITE), | |
171 | entry); | |
18397944 | 172 | |
6a32fd4d | 173 | for (n = 0; n < npages; n++) { |
ad7ad57c | 174 | long err = iommu_batch_add(first_page + (n * PAGE_SIZE)); |
6a32fd4d DM |
175 | if (unlikely(err < 0L)) |
176 | goto iommu_map_fail; | |
177 | } | |
18397944 | 178 | |
ad7ad57c | 179 | if (unlikely(iommu_batch_end() < 0L)) |
6a32fd4d | 180 | goto iommu_map_fail; |
18397944 | 181 | |
6a32fd4d | 182 | local_irq_restore(flags); |
18397944 DM |
183 | |
184 | return ret; | |
6a32fd4d DM |
185 | |
186 | iommu_map_fail: | |
187 | /* Interrupts are disabled. */ | |
188 | spin_lock(&iommu->lock); | |
d284142c | 189 | iommu_range_free(iommu, *dma_addrp, npages); |
6a32fd4d DM |
190 | spin_unlock_irqrestore(&iommu->lock, flags); |
191 | ||
d284142c | 192 | range_alloc_fail: |
6a32fd4d DM |
193 | free_pages(first_page, order); |
194 | return NULL; | |
8f6a93a1 DM |
195 | } |
196 | ||
ad7ad57c DM |
197 | static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu, |
198 | dma_addr_t dvma) | |
8f6a93a1 | 199 | { |
a2fb23af | 200 | struct pci_pbm_info *pbm; |
16ce82d8 | 201 | struct iommu *iommu; |
7c8f486a DM |
202 | unsigned long flags, order, npages, entry; |
203 | u32 devhandle; | |
18397944 DM |
204 | |
205 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
ad7ad57c DM |
206 | iommu = dev->archdata.iommu; |
207 | pbm = dev->archdata.host_controller; | |
a2fb23af | 208 | devhandle = pbm->devhandle; |
18397944 DM |
209 | entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); |
210 | ||
211 | spin_lock_irqsave(&iommu->lock, flags); | |
212 | ||
d284142c | 213 | iommu_range_free(iommu, dvma, npages); |
18397944 DM |
214 | |
215 | do { | |
216 | unsigned long num; | |
217 | ||
218 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
219 | npages); | |
220 | entry += num; | |
221 | npages -= num; | |
222 | } while (npages != 0); | |
223 | ||
224 | spin_unlock_irqrestore(&iommu->lock, flags); | |
225 | ||
226 | order = get_order(size); | |
227 | if (order < 10) | |
228 | free_pages((unsigned long)cpu, order); | |
8f6a93a1 DM |
229 | } |
230 | ||
ad7ad57c DM |
231 | static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz, |
232 | enum dma_data_direction direction) | |
8f6a93a1 | 233 | { |
16ce82d8 | 234 | struct iommu *iommu; |
18397944 | 235 | unsigned long flags, npages, oaddr; |
7c8f486a | 236 | unsigned long i, base_paddr; |
6a32fd4d | 237 | u32 bus_addr, ret; |
18397944 DM |
238 | unsigned long prot; |
239 | long entry; | |
18397944 | 240 | |
ad7ad57c | 241 | iommu = dev->archdata.iommu; |
18397944 | 242 | |
ad7ad57c | 243 | if (unlikely(direction == DMA_NONE)) |
18397944 DM |
244 | goto bad; |
245 | ||
246 | oaddr = (unsigned long)ptr; | |
247 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); | |
248 | npages >>= IO_PAGE_SHIFT; | |
18397944 DM |
249 | |
250 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 251 | entry = iommu_range_alloc(dev, iommu, npages, NULL); |
18397944 DM |
252 | spin_unlock_irqrestore(&iommu->lock, flags); |
253 | ||
d284142c | 254 | if (unlikely(entry == DMA_ERROR_CODE)) |
18397944 DM |
255 | goto bad; |
256 | ||
257 | bus_addr = (iommu->page_table_map_base + | |
258 | (entry << IO_PAGE_SHIFT)); | |
259 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
260 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
261 | prot = HV_PCI_MAP_ATTR_READ; | |
ad7ad57c | 262 | if (direction != DMA_TO_DEVICE) |
18397944 DM |
263 | prot |= HV_PCI_MAP_ATTR_WRITE; |
264 | ||
6a32fd4d | 265 | local_irq_save(flags); |
18397944 | 266 | |
ad7ad57c | 267 | iommu_batch_start(dev, prot, entry); |
18397944 | 268 | |
6a32fd4d | 269 | for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) { |
ad7ad57c | 270 | long err = iommu_batch_add(base_paddr); |
6a32fd4d DM |
271 | if (unlikely(err < 0L)) |
272 | goto iommu_map_fail; | |
273 | } | |
ad7ad57c | 274 | if (unlikely(iommu_batch_end() < 0L)) |
6a32fd4d | 275 | goto iommu_map_fail; |
18397944 | 276 | |
6a32fd4d | 277 | local_irq_restore(flags); |
18397944 DM |
278 | |
279 | return ret; | |
280 | ||
281 | bad: | |
282 | if (printk_ratelimit()) | |
283 | WARN_ON(1); | |
ad7ad57c | 284 | return DMA_ERROR_CODE; |
6a32fd4d DM |
285 | |
286 | iommu_map_fail: | |
287 | /* Interrupts are disabled. */ | |
288 | spin_lock(&iommu->lock); | |
d284142c | 289 | iommu_range_free(iommu, bus_addr, npages); |
6a32fd4d DM |
290 | spin_unlock_irqrestore(&iommu->lock, flags); |
291 | ||
ad7ad57c | 292 | return DMA_ERROR_CODE; |
8f6a93a1 DM |
293 | } |
294 | ||
ad7ad57c DM |
295 | static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr, |
296 | size_t sz, enum dma_data_direction direction) | |
8f6a93a1 | 297 | { |
a2fb23af | 298 | struct pci_pbm_info *pbm; |
16ce82d8 | 299 | struct iommu *iommu; |
7c8f486a | 300 | unsigned long flags, npages; |
18397944 | 301 | long entry; |
7c8f486a | 302 | u32 devhandle; |
18397944 | 303 | |
ad7ad57c | 304 | if (unlikely(direction == DMA_NONE)) { |
18397944 DM |
305 | if (printk_ratelimit()) |
306 | WARN_ON(1); | |
307 | return; | |
308 | } | |
309 | ||
ad7ad57c DM |
310 | iommu = dev->archdata.iommu; |
311 | pbm = dev->archdata.host_controller; | |
a2fb23af | 312 | devhandle = pbm->devhandle; |
18397944 DM |
313 | |
314 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
315 | npages >>= IO_PAGE_SHIFT; | |
316 | bus_addr &= IO_PAGE_MASK; | |
317 | ||
318 | spin_lock_irqsave(&iommu->lock, flags); | |
319 | ||
d284142c | 320 | iommu_range_free(iommu, bus_addr, npages); |
18397944 | 321 | |
d284142c | 322 | entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT; |
18397944 DM |
323 | do { |
324 | unsigned long num; | |
325 | ||
326 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
327 | npages); | |
328 | entry += num; | |
329 | npages -= num; | |
330 | } while (npages != 0); | |
331 | ||
332 | spin_unlock_irqrestore(&iommu->lock, flags); | |
333 | } | |
334 | ||
ad7ad57c DM |
335 | static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist, |
336 | int nelems, enum dma_data_direction direction) | |
8f6a93a1 | 337 | { |
13fa14e1 DM |
338 | struct scatterlist *s, *outs, *segstart; |
339 | unsigned long flags, handle, prot; | |
340 | dma_addr_t dma_next = 0, dma_addr; | |
341 | unsigned int max_seg_size; | |
f0880257 | 342 | unsigned long seg_boundary_size; |
13fa14e1 | 343 | int outcount, incount, i; |
16ce82d8 | 344 | struct iommu *iommu; |
f0880257 | 345 | unsigned long base_shift; |
13fa14e1 DM |
346 | long err; |
347 | ||
348 | BUG_ON(direction == DMA_NONE); | |
18397944 | 349 | |
ad7ad57c | 350 | iommu = dev->archdata.iommu; |
13fa14e1 DM |
351 | if (nelems == 0 || !iommu) |
352 | return 0; | |
18397944 | 353 | |
13fa14e1 DM |
354 | prot = HV_PCI_MAP_ATTR_READ; |
355 | if (direction != DMA_TO_DEVICE) | |
356 | prot |= HV_PCI_MAP_ATTR_WRITE; | |
18397944 | 357 | |
13fa14e1 DM |
358 | outs = s = segstart = &sglist[0]; |
359 | outcount = 1; | |
360 | incount = nelems; | |
361 | handle = 0; | |
18397944 | 362 | |
13fa14e1 DM |
363 | /* Init first segment length for backout at failure */ |
364 | outs->dma_length = 0; | |
18397944 | 365 | |
13fa14e1 | 366 | spin_lock_irqsave(&iommu->lock, flags); |
18397944 | 367 | |
13fa14e1 | 368 | iommu_batch_start(dev, prot, ~0UL); |
18397944 | 369 | |
13fa14e1 | 370 | max_seg_size = dma_get_max_seg_size(dev); |
f0880257 FT |
371 | seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
372 | IO_PAGE_SIZE) >> IO_PAGE_SHIFT; | |
373 | base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT; | |
13fa14e1 | 374 | for_each_sg(sglist, s, nelems, i) { |
f0880257 | 375 | unsigned long paddr, npages, entry, out_entry = 0, slen; |
38192d52 | 376 | |
13fa14e1 DM |
377 | slen = s->length; |
378 | /* Sanity check */ | |
379 | if (slen == 0) { | |
380 | dma_next = 0; | |
381 | continue; | |
382 | } | |
383 | /* Allocate iommu entries for that segment */ | |
384 | paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s); | |
385 | npages = iommu_num_pages(paddr, slen); | |
386 | entry = iommu_range_alloc(dev, iommu, npages, &handle); | |
38192d52 | 387 | |
13fa14e1 DM |
388 | /* Handle failure */ |
389 | if (unlikely(entry == DMA_ERROR_CODE)) { | |
390 | if (printk_ratelimit()) | |
391 | printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx" | |
392 | " npages %lx\n", iommu, paddr, npages); | |
393 | goto iommu_map_failed; | |
394 | } | |
38192d52 | 395 | |
13fa14e1 | 396 | iommu_batch_new_entry(entry); |
38192d52 | 397 | |
13fa14e1 DM |
398 | /* Convert entry to a dma_addr_t */ |
399 | dma_addr = iommu->page_table_map_base + | |
400 | (entry << IO_PAGE_SHIFT); | |
401 | dma_addr |= (s->offset & ~IO_PAGE_MASK); | |
38192d52 | 402 | |
13fa14e1 | 403 | /* Insert into HW table */ |
38192d52 | 404 | paddr &= IO_PAGE_MASK; |
13fa14e1 | 405 | while (npages--) { |
38192d52 | 406 | err = iommu_batch_add(paddr); |
13fa14e1 | 407 | if (unlikely(err < 0L)) |
38192d52 | 408 | goto iommu_map_failed; |
13fa14e1 DM |
409 | paddr += IO_PAGE_SIZE; |
410 | } | |
411 | ||
412 | /* If we are in an open segment, try merging */ | |
413 | if (segstart != s) { | |
414 | /* We cannot merge if: | |
415 | * - allocated dma_addr isn't contiguous to previous allocation | |
416 | */ | |
417 | if ((dma_addr != dma_next) || | |
f0880257 FT |
418 | (outs->dma_length + s->length > max_seg_size) || |
419 | (is_span_boundary(out_entry, base_shift, | |
420 | seg_boundary_size, outs, s))) { | |
13fa14e1 DM |
421 | /* Can't merge: create a new segment */ |
422 | segstart = s; | |
423 | outcount++; | |
424 | outs = sg_next(outs); | |
425 | } else { | |
426 | outs->dma_length += s->length; | |
38192d52 | 427 | } |
13fa14e1 | 428 | } |
38192d52 | 429 | |
13fa14e1 DM |
430 | if (segstart == s) { |
431 | /* This is a new segment, fill entries */ | |
432 | outs->dma_address = dma_addr; | |
433 | outs->dma_length = slen; | |
f0880257 | 434 | out_entry = entry; |
38192d52 | 435 | } |
13fa14e1 DM |
436 | |
437 | /* Calculate next page pointer for contiguous check */ | |
438 | dma_next = dma_addr + slen; | |
38192d52 DM |
439 | } |
440 | ||
441 | err = iommu_batch_end(); | |
442 | ||
6a32fd4d DM |
443 | if (unlikely(err < 0L)) |
444 | goto iommu_map_failed; | |
18397944 | 445 | |
13fa14e1 | 446 | spin_unlock_irqrestore(&iommu->lock, flags); |
18397944 | 447 | |
13fa14e1 DM |
448 | if (outcount < incount) { |
449 | outs = sg_next(outs); | |
450 | outs->dma_address = DMA_ERROR_CODE; | |
451 | outs->dma_length = 0; | |
452 | } | |
453 | ||
454 | return outcount; | |
6a32fd4d DM |
455 | |
456 | iommu_map_failed: | |
13fa14e1 DM |
457 | for_each_sg(sglist, s, nelems, i) { |
458 | if (s->dma_length != 0) { | |
459 | unsigned long vaddr, npages; | |
460 | ||
461 | vaddr = s->dma_address & IO_PAGE_MASK; | |
462 | npages = iommu_num_pages(s->dma_address, s->dma_length); | |
463 | iommu_range_free(iommu, vaddr, npages); | |
464 | /* XXX demap? XXX */ | |
465 | s->dma_address = DMA_ERROR_CODE; | |
466 | s->dma_length = 0; | |
467 | } | |
468 | if (s == outs) | |
469 | break; | |
470 | } | |
6a32fd4d DM |
471 | spin_unlock_irqrestore(&iommu->lock, flags); |
472 | ||
473 | return 0; | |
8f6a93a1 DM |
474 | } |
475 | ||
ad7ad57c DM |
476 | static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist, |
477 | int nelems, enum dma_data_direction direction) | |
8f6a93a1 | 478 | { |
a2fb23af | 479 | struct pci_pbm_info *pbm; |
13fa14e1 | 480 | struct scatterlist *sg; |
16ce82d8 | 481 | struct iommu *iommu; |
13fa14e1 DM |
482 | unsigned long flags; |
483 | u32 devhandle; | |
18397944 | 484 | |
13fa14e1 | 485 | BUG_ON(direction == DMA_NONE); |
18397944 | 486 | |
ad7ad57c DM |
487 | iommu = dev->archdata.iommu; |
488 | pbm = dev->archdata.host_controller; | |
a2fb23af | 489 | devhandle = pbm->devhandle; |
18397944 | 490 | |
18397944 DM |
491 | spin_lock_irqsave(&iommu->lock, flags); |
492 | ||
13fa14e1 DM |
493 | sg = sglist; |
494 | while (nelems--) { | |
495 | dma_addr_t dma_handle = sg->dma_address; | |
496 | unsigned int len = sg->dma_length; | |
497 | unsigned long npages, entry; | |
498 | ||
499 | if (!len) | |
500 | break; | |
501 | npages = iommu_num_pages(dma_handle, len); | |
502 | iommu_range_free(iommu, dma_handle, npages); | |
503 | ||
504 | entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
505 | while (npages) { | |
506 | unsigned long num; | |
507 | ||
508 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
509 | npages); | |
510 | entry += num; | |
511 | npages -= num; | |
512 | } | |
18397944 | 513 | |
13fa14e1 DM |
514 | sg = sg_next(sg); |
515 | } | |
18397944 DM |
516 | |
517 | spin_unlock_irqrestore(&iommu->lock, flags); | |
8f6a93a1 DM |
518 | } |
519 | ||
ad7ad57c DM |
520 | static void dma_4v_sync_single_for_cpu(struct device *dev, |
521 | dma_addr_t bus_addr, size_t sz, | |
522 | enum dma_data_direction direction) | |
8f6a93a1 | 523 | { |
18397944 | 524 | /* Nothing to do... */ |
8f6a93a1 DM |
525 | } |
526 | ||
ad7ad57c DM |
527 | static void dma_4v_sync_sg_for_cpu(struct device *dev, |
528 | struct scatterlist *sglist, int nelems, | |
529 | enum dma_data_direction direction) | |
8f6a93a1 | 530 | { |
18397944 | 531 | /* Nothing to do... */ |
8f6a93a1 DM |
532 | } |
533 | ||
908f5162 | 534 | static const struct dma_ops sun4v_dma_ops = { |
ad7ad57c DM |
535 | .alloc_coherent = dma_4v_alloc_coherent, |
536 | .free_coherent = dma_4v_free_coherent, | |
537 | .map_single = dma_4v_map_single, | |
538 | .unmap_single = dma_4v_unmap_single, | |
539 | .map_sg = dma_4v_map_sg, | |
540 | .unmap_sg = dma_4v_unmap_sg, | |
541 | .sync_single_for_cpu = dma_4v_sync_single_for_cpu, | |
542 | .sync_sg_for_cpu = dma_4v_sync_sg_for_cpu, | |
8f6a93a1 DM |
543 | }; |
544 | ||
a1f35ba3 | 545 | static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm) |
bade5622 | 546 | { |
e87dc350 DM |
547 | struct property *prop; |
548 | struct device_node *dp; | |
549 | ||
34768bc8 DM |
550 | dp = pbm->prom_node; |
551 | prop = of_find_property(dp, "66mhz-capable", NULL); | |
552 | pbm->is_66mhz_capable = (prop != NULL); | |
553 | pbm->pci_bus = pci_scan_one_pbm(pbm); | |
c2609267 DM |
554 | |
555 | /* XXX register error interrupt handlers XXX */ | |
bade5622 DM |
556 | } |
557 | ||
4c622258 AB |
558 | static unsigned long __init probe_existing_entries(struct pci_pbm_info *pbm, |
559 | struct iommu *iommu) | |
18397944 | 560 | { |
9b3627f3 | 561 | struct iommu_arena *arena = &iommu->arena; |
e7a0453e | 562 | unsigned long i, cnt = 0; |
7c8f486a | 563 | u32 devhandle; |
18397944 DM |
564 | |
565 | devhandle = pbm->devhandle; | |
566 | for (i = 0; i < arena->limit; i++) { | |
567 | unsigned long ret, io_attrs, ra; | |
568 | ||
569 | ret = pci_sun4v_iommu_getmap(devhandle, | |
570 | HV_PCI_TSBID(0, i), | |
571 | &io_attrs, &ra); | |
e7a0453e | 572 | if (ret == HV_EOK) { |
c2a5a46b DM |
573 | if (page_in_phys_avail(ra)) { |
574 | pci_sun4v_iommu_demap(devhandle, | |
575 | HV_PCI_TSBID(0, i), 1); | |
576 | } else { | |
577 | cnt++; | |
578 | __set_bit(i, arena->map); | |
579 | } | |
e7a0453e | 580 | } |
18397944 | 581 | } |
e7a0453e DM |
582 | |
583 | return cnt; | |
18397944 DM |
584 | } |
585 | ||
4c622258 | 586 | static void __init pci_sun4v_iommu_init(struct pci_pbm_info *pbm) |
bade5622 | 587 | { |
16ce82d8 | 588 | struct iommu *iommu = pbm->iommu; |
e87dc350 | 589 | struct property *prop; |
59db8102 | 590 | unsigned long num_tsb_entries, sz, tsbsize; |
18397944 | 591 | u32 vdma[2], dma_mask, dma_offset; |
e87dc350 DM |
592 | |
593 | prop = of_find_property(pbm->prom_node, "virtual-dma", NULL); | |
594 | if (prop) { | |
595 | u32 *val = prop->value; | |
18397944 | 596 | |
e87dc350 DM |
597 | vdma[0] = val[0]; |
598 | vdma[1] = val[1]; | |
599 | } else { | |
18397944 DM |
600 | /* No property, use default values. */ |
601 | vdma[0] = 0x80000000; | |
602 | vdma[1] = 0x80000000; | |
603 | } | |
604 | ||
59db8102 DM |
605 | if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) { |
606 | prom_printf("PCI-SUN4V: strange virtual-dma[%08x:%08x].\n", | |
607 | vdma[0], vdma[1]); | |
608 | prom_halt(); | |
18397944 DM |
609 | }; |
610 | ||
59db8102 DM |
611 | dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL); |
612 | num_tsb_entries = vdma[1] / IO_PAGE_SIZE; | |
613 | tsbsize = num_tsb_entries * sizeof(iopte_t); | |
18397944 DM |
614 | |
615 | dma_offset = vdma[0]; | |
616 | ||
617 | /* Setup initial software IOMMU state. */ | |
618 | spin_lock_init(&iommu->lock); | |
619 | iommu->ctx_lowest_free = 1; | |
620 | iommu->page_table_map_base = dma_offset; | |
621 | iommu->dma_addr_mask = dma_mask; | |
622 | ||
623 | /* Allocate and initialize the free area map. */ | |
59db8102 | 624 | sz = (num_tsb_entries + 7) / 8; |
18397944 | 625 | sz = (sz + 7UL) & ~7UL; |
982c2064 | 626 | iommu->arena.map = kzalloc(sz, GFP_KERNEL); |
18397944 DM |
627 | if (!iommu->arena.map) { |
628 | prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n"); | |
629 | prom_halt(); | |
630 | } | |
18397944 DM |
631 | iommu->arena.limit = num_tsb_entries; |
632 | ||
e7a0453e | 633 | sz = probe_existing_entries(pbm, iommu); |
c2a5a46b DM |
634 | if (sz) |
635 | printk("%s: Imported %lu TSB entries from OBP\n", | |
636 | pbm->name, sz); | |
bade5622 DM |
637 | } |
638 | ||
35a17eb6 DM |
639 | #ifdef CONFIG_PCI_MSI |
640 | struct pci_sun4v_msiq_entry { | |
641 | u64 version_type; | |
642 | #define MSIQ_VERSION_MASK 0xffffffff00000000UL | |
643 | #define MSIQ_VERSION_SHIFT 32 | |
644 | #define MSIQ_TYPE_MASK 0x00000000000000ffUL | |
645 | #define MSIQ_TYPE_SHIFT 0 | |
646 | #define MSIQ_TYPE_NONE 0x00 | |
647 | #define MSIQ_TYPE_MSG 0x01 | |
648 | #define MSIQ_TYPE_MSI32 0x02 | |
649 | #define MSIQ_TYPE_MSI64 0x03 | |
650 | #define MSIQ_TYPE_INTX 0x08 | |
651 | #define MSIQ_TYPE_NONE2 0xff | |
652 | ||
653 | u64 intx_sysino; | |
654 | u64 reserved1; | |
655 | u64 stick; | |
656 | u64 req_id; /* bus/device/func */ | |
657 | #define MSIQ_REQID_BUS_MASK 0xff00UL | |
658 | #define MSIQ_REQID_BUS_SHIFT 8 | |
659 | #define MSIQ_REQID_DEVICE_MASK 0x00f8UL | |
660 | #define MSIQ_REQID_DEVICE_SHIFT 3 | |
661 | #define MSIQ_REQID_FUNC_MASK 0x0007UL | |
662 | #define MSIQ_REQID_FUNC_SHIFT 0 | |
663 | ||
664 | u64 msi_address; | |
665 | ||
e5dd42e4 | 666 | /* The format of this value is message type dependent. |
35a17eb6 DM |
667 | * For MSI bits 15:0 are the data from the MSI packet. |
668 | * For MSI-X bits 31:0 are the data from the MSI packet. | |
669 | * For MSG, the message code and message routing code where: | |
670 | * bits 39:32 is the bus/device/fn of the msg target-id | |
671 | * bits 18:16 is the message routing code | |
672 | * bits 7:0 is the message code | |
673 | * For INTx the low order 2-bits are: | |
674 | * 00 - INTA | |
675 | * 01 - INTB | |
676 | * 10 - INTC | |
677 | * 11 - INTD | |
678 | */ | |
679 | u64 msi_data; | |
680 | ||
681 | u64 reserved2; | |
682 | }; | |
683 | ||
759f89e0 DM |
684 | static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
685 | unsigned long *head) | |
35a17eb6 | 686 | { |
759f89e0 | 687 | unsigned long err, limit; |
35a17eb6 | 688 | |
759f89e0 | 689 | err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head); |
35a17eb6 | 690 | if (unlikely(err)) |
759f89e0 | 691 | return -ENXIO; |
35a17eb6 | 692 | |
759f89e0 DM |
693 | limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); |
694 | if (unlikely(*head >= limit)) | |
695 | return -EFBIG; | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm, | |
701 | unsigned long msiqid, unsigned long *head, | |
702 | unsigned long *msi) | |
703 | { | |
704 | struct pci_sun4v_msiq_entry *ep; | |
705 | unsigned long err, type; | |
706 | ||
707 | /* Note: void pointer arithmetic, 'head' is a byte offset */ | |
708 | ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * | |
709 | (pbm->msiq_ent_count * | |
710 | sizeof(struct pci_sun4v_msiq_entry))) + | |
711 | *head); | |
712 | ||
713 | if ((ep->version_type & MSIQ_TYPE_MASK) == 0) | |
714 | return 0; | |
35a17eb6 | 715 | |
759f89e0 DM |
716 | type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT; |
717 | if (unlikely(type != MSIQ_TYPE_MSI32 && | |
718 | type != MSIQ_TYPE_MSI64)) | |
719 | return -EINVAL; | |
35a17eb6 | 720 | |
759f89e0 DM |
721 | *msi = ep->msi_data; |
722 | ||
723 | err = pci_sun4v_msi_setstate(pbm->devhandle, | |
724 | ep->msi_data /* msi_num */, | |
725 | HV_MSISTATE_IDLE); | |
726 | if (unlikely(err)) | |
727 | return -ENXIO; | |
35a17eb6 | 728 | |
759f89e0 DM |
729 | /* Clear the entry. */ |
730 | ep->version_type &= ~MSIQ_TYPE_MASK; | |
35a17eb6 | 731 | |
759f89e0 DM |
732 | (*head) += sizeof(struct pci_sun4v_msiq_entry); |
733 | if (*head >= | |
734 | (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))) | |
735 | *head = 0; | |
35a17eb6 | 736 | |
759f89e0 | 737 | return 1; |
35a17eb6 DM |
738 | } |
739 | ||
759f89e0 DM |
740 | static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
741 | unsigned long head) | |
35a17eb6 | 742 | { |
759f89e0 | 743 | unsigned long err; |
35a17eb6 | 744 | |
759f89e0 DM |
745 | err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head); |
746 | if (unlikely(err)) | |
747 | return -EINVAL; | |
35a17eb6 | 748 | |
759f89e0 DM |
749 | return 0; |
750 | } | |
35a17eb6 | 751 | |
759f89e0 DM |
752 | static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid, |
753 | unsigned long msi, int is_msi64) | |
754 | { | |
755 | if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid, | |
756 | (is_msi64 ? | |
757 | HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32))) | |
758 | return -ENXIO; | |
759 | if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE)) | |
760 | return -ENXIO; | |
761 | if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID)) | |
762 | return -ENXIO; | |
35a17eb6 DM |
763 | return 0; |
764 | } | |
765 | ||
759f89e0 | 766 | static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) |
35a17eb6 | 767 | { |
759f89e0 DM |
768 | unsigned long err, msiqid; |
769 | ||
770 | err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid); | |
771 | if (err) | |
772 | return -ENXIO; | |
773 | ||
774 | pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID); | |
775 | ||
776 | return 0; | |
35a17eb6 DM |
777 | } |
778 | ||
759f89e0 | 779 | static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm) |
35a17eb6 DM |
780 | { |
781 | unsigned long q_size, alloc_size, pages, order; | |
782 | int i; | |
783 | ||
784 | q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); | |
785 | alloc_size = (pbm->msiq_num * q_size); | |
786 | order = get_order(alloc_size); | |
787 | pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order); | |
788 | if (pages == 0UL) { | |
789 | printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n", | |
790 | order); | |
791 | return -ENOMEM; | |
792 | } | |
793 | memset((char *)pages, 0, PAGE_SIZE << order); | |
794 | pbm->msi_queues = (void *) pages; | |
795 | ||
796 | for (i = 0; i < pbm->msiq_num; i++) { | |
797 | unsigned long err, base = __pa(pages + (i * q_size)); | |
798 | unsigned long ret1, ret2; | |
799 | ||
800 | err = pci_sun4v_msiq_conf(pbm->devhandle, | |
801 | pbm->msiq_first + i, | |
802 | base, pbm->msiq_ent_count); | |
803 | if (err) { | |
804 | printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n", | |
805 | err); | |
806 | goto h_error; | |
807 | } | |
808 | ||
809 | err = pci_sun4v_msiq_info(pbm->devhandle, | |
810 | pbm->msiq_first + i, | |
811 | &ret1, &ret2); | |
812 | if (err) { | |
813 | printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n", | |
814 | err); | |
815 | goto h_error; | |
816 | } | |
817 | if (ret1 != base || ret2 != pbm->msiq_ent_count) { | |
818 | printk(KERN_ERR "MSI: Bogus qconf " | |
819 | "expected[%lx:%x] got[%lx:%lx]\n", | |
820 | base, pbm->msiq_ent_count, | |
821 | ret1, ret2); | |
822 | goto h_error; | |
823 | } | |
824 | } | |
825 | ||
826 | return 0; | |
827 | ||
828 | h_error: | |
829 | free_pages(pages, order); | |
830 | return -EINVAL; | |
831 | } | |
832 | ||
759f89e0 | 833 | static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm) |
35a17eb6 | 834 | { |
759f89e0 | 835 | unsigned long q_size, alloc_size, pages, order; |
35a17eb6 DM |
836 | int i; |
837 | ||
759f89e0 DM |
838 | for (i = 0; i < pbm->msiq_num; i++) { |
839 | unsigned long msiqid = pbm->msiq_first + i; | |
35a17eb6 | 840 | |
759f89e0 | 841 | (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0); |
35a17eb6 | 842 | } |
7fe3730d | 843 | |
759f89e0 DM |
844 | q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); |
845 | alloc_size = (pbm->msiq_num * q_size); | |
846 | order = get_order(alloc_size); | |
35a17eb6 | 847 | |
759f89e0 | 848 | pages = (unsigned long) pbm->msi_queues; |
35a17eb6 | 849 | |
759f89e0 | 850 | free_pages(pages, order); |
35a17eb6 | 851 | |
759f89e0 | 852 | pbm->msi_queues = NULL; |
35a17eb6 DM |
853 | } |
854 | ||
759f89e0 DM |
855 | static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm, |
856 | unsigned long msiqid, | |
857 | unsigned long devino) | |
35a17eb6 | 858 | { |
759f89e0 | 859 | unsigned int virt_irq = sun4v_build_irq(pbm->devhandle, devino); |
35a17eb6 | 860 | |
759f89e0 DM |
861 | if (!virt_irq) |
862 | return -ENOMEM; | |
35a17eb6 | 863 | |
759f89e0 DM |
864 | if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE)) |
865 | return -EINVAL; | |
866 | if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID)) | |
867 | return -EINVAL; | |
35a17eb6 | 868 | |
759f89e0 | 869 | return virt_irq; |
35a17eb6 | 870 | } |
e9870c4c | 871 | |
759f89e0 DM |
872 | static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = { |
873 | .get_head = pci_sun4v_get_head, | |
874 | .dequeue_msi = pci_sun4v_dequeue_msi, | |
875 | .set_head = pci_sun4v_set_head, | |
876 | .msi_setup = pci_sun4v_msi_setup, | |
877 | .msi_teardown = pci_sun4v_msi_teardown, | |
878 | .msiq_alloc = pci_sun4v_msiq_alloc, | |
879 | .msiq_free = pci_sun4v_msiq_free, | |
880 | .msiq_build_irq = pci_sun4v_msiq_build_irq, | |
881 | }; | |
882 | ||
e9870c4c DM |
883 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) |
884 | { | |
759f89e0 | 885 | sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops); |
e9870c4c | 886 | } |
35a17eb6 DM |
887 | #else /* CONFIG_PCI_MSI */ |
888 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) | |
889 | { | |
890 | } | |
891 | #endif /* !(CONFIG_PCI_MSI) */ | |
892 | ||
a1f35ba3 SR |
893 | static void __init pci_sun4v_pbm_init(struct pci_controller_info *p, |
894 | struct device_node *dp, u32 devhandle) | |
bade5622 DM |
895 | { |
896 | struct pci_pbm_info *pbm; | |
bade5622 | 897 | |
3833789b DM |
898 | if (devhandle & 0x40) |
899 | pbm = &p->pbm_B; | |
900 | else | |
901 | pbm = &p->pbm_A; | |
bade5622 | 902 | |
34768bc8 DM |
903 | pbm->next = pci_pbm_root; |
904 | pci_pbm_root = pbm; | |
905 | ||
c1b1a5f1 DM |
906 | pbm->numa_node = of_node_to_nid(dp); |
907 | ||
34768bc8 | 908 | pbm->scan_bus = pci_sun4v_scan_bus; |
ca3dd88e DM |
909 | pbm->pci_ops = &sun4v_pci_ops; |
910 | pbm->config_space_reg_bits = 12; | |
34768bc8 | 911 | |
6c108f12 DM |
912 | pbm->index = pci_num_pbms++; |
913 | ||
bade5622 | 914 | pbm->parent = p; |
e87dc350 | 915 | pbm->prom_node = dp; |
bade5622 | 916 | |
3833789b | 917 | pbm->devhandle = devhandle; |
bade5622 | 918 | |
e87dc350 | 919 | pbm->name = dp->full_name; |
bade5622 | 920 | |
e87dc350 | 921 | printk("%s: SUN4V PCI Bus Module\n", pbm->name); |
c1b1a5f1 | 922 | printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node); |
bade5622 | 923 | |
9fd8b647 | 924 | pci_determine_mem_io_space(pbm); |
bade5622 | 925 | |
cfa0652c | 926 | pci_get_pbm_props(pbm); |
bade5622 | 927 | pci_sun4v_iommu_init(pbm); |
35a17eb6 | 928 | pci_sun4v_msi_init(pbm); |
bade5622 DM |
929 | } |
930 | ||
f0429bf7 | 931 | void __init sun4v_pci_init(struct device_node *dp, char *model_name) |
8f6a93a1 | 932 | { |
e01c0d6d | 933 | static int hvapi_negotiated = 0; |
bade5622 | 934 | struct pci_controller_info *p; |
34768bc8 | 935 | struct pci_pbm_info *pbm; |
16ce82d8 | 936 | struct iommu *iommu; |
e87dc350 DM |
937 | struct property *prop; |
938 | struct linux_prom64_registers *regs; | |
7c8f486a DM |
939 | u32 devhandle; |
940 | int i; | |
3833789b | 941 | |
e01c0d6d DM |
942 | if (!hvapi_negotiated++) { |
943 | int err = sun4v_hvapi_register(HV_GRP_PCI, | |
944 | vpci_major, | |
945 | &vpci_minor); | |
946 | ||
947 | if (err) { | |
948 | prom_printf("SUN4V_PCI: Could not register hvapi, " | |
949 | "err=%d\n", err); | |
950 | prom_halt(); | |
951 | } | |
952 | printk("SUN4V_PCI: Registered hvapi major[%lu] minor[%lu]\n", | |
953 | vpci_major, vpci_minor); | |
ad7ad57c DM |
954 | |
955 | dma_ops = &sun4v_dma_ops; | |
e01c0d6d DM |
956 | } |
957 | ||
e87dc350 | 958 | prop = of_find_property(dp, "reg", NULL); |
75c6d141 CG |
959 | if (!prop) { |
960 | prom_printf("SUN4V_PCI: Could not find config registers\n"); | |
961 | prom_halt(); | |
962 | } | |
e87dc350 DM |
963 | regs = prop->value; |
964 | ||
965 | devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
3833789b | 966 | |
34768bc8 | 967 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { |
0b522497 | 968 | if (pbm->devhandle == (devhandle ^ 0x40)) { |
34768bc8 | 969 | pci_sun4v_pbm_init(pbm->parent, dp, devhandle); |
0b522497 DM |
970 | return; |
971 | } | |
3833789b | 972 | } |
bade5622 | 973 | |
a283a525 | 974 | for_each_possible_cpu(i) { |
7c8f486a DM |
975 | unsigned long page = get_zeroed_page(GFP_ATOMIC); |
976 | ||
977 | if (!page) | |
978 | goto fatal_memory_error; | |
979 | ||
ad7ad57c | 980 | per_cpu(iommu_batch, i).pglist = (u64 *) page; |
bade5622 | 981 | } |
7c8f486a | 982 | |
982c2064 | 983 | p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); |
7c8f486a DM |
984 | if (!p) |
985 | goto fatal_memory_error; | |
986 | ||
16ce82d8 | 987 | iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); |
7c8f486a DM |
988 | if (!iommu) |
989 | goto fatal_memory_error; | |
990 | ||
bade5622 DM |
991 | p->pbm_A.iommu = iommu; |
992 | ||
16ce82d8 | 993 | iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); |
7c8f486a DM |
994 | if (!iommu) |
995 | goto fatal_memory_error; | |
996 | ||
bade5622 DM |
997 | p->pbm_B.iommu = iommu; |
998 | ||
e87dc350 | 999 | pci_sun4v_pbm_init(p, dp, devhandle); |
7c8f486a DM |
1000 | return; |
1001 | ||
1002 | fatal_memory_error: | |
1003 | prom_printf("SUN4V_PCI: Fatal memory allocation error.\n"); | |
1004 | prom_halt(); | |
8f6a93a1 | 1005 | } |