projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SPARC64]: Missing 'return' statement in sun4v_pci_init().
[deliverable/linux.git] / arch / sparc64 / kernel / pci_sun4v.c
CommitLineData
8f6a93a1
DM		 1/* pci_sun4v.c: SUN4V specific PCI controller support.
2 *
3 * Copyright (C) 2006 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/interrupt.h>
18397944 12#include <linux/percpu.h>
8f6a93a1
DM		 13
14#include <asm/pbm.h>
15#include <asm/iommu.h>
16#include <asm/irq.h>
17#include <asm/upa.h>
18#include <asm/pstate.h>
19#include <asm/oplib.h>
20#include <asm/hypervisor.h>
21
22#include "pci_impl.h"
23#include "iommu_common.h"
24
bade5622
DM		 25#include "pci_sun4v.h"
26
18397944
DM		 27#define PGLIST_NENTS 2048
28
29struct sun4v_pglist {
30 u64 pglist[PGLIST_NENTS];
31};
32
33static DEFINE_PER_CPU(struct sun4v_pglist, iommu_pglists);
34
35static long pci_arena_alloc(struct pci_iommu_arena *arena, unsigned long npages)
36{
37 unsigned long n, i, start, end, limit;
38 int pass;
39
40 limit = arena->limit;
41 start = arena->hint;
42 pass = 0;
43
44again:
45 n = find_next_zero_bit(arena->map, limit, start);
46 end = n + npages;
47 if (unlikely(end >= limit)) {
48 if (likely(pass < 1)) {
49 limit = start;
50 start = 0;
51 pass++;
52 goto again;
53 } else {
54 /* Scanned the whole thing, give up. */
55 return -1;
56 }
57 }
58
59 for (i = n; i < end; i++) {
60 if (test_bit(i, arena->map)) {
61 start = i + 1;
62 goto again;
63 }
64 }
65
66 for (i = n; i < end; i++)
67 __set_bit(i, arena->map);
68
69 arena->hint = end;
70
71 return n;
72}
73
74static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
75{
76 unsigned long i;
77
78 for (i = base; i < (base + npages); i++)
79 __clear_bit(i, arena->map);
80}
81
8f6a93a1
DM		 82static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
83{
18397944
DM		 84 struct pcidev_cookie *pcp;
85 struct pci_iommu *iommu;
86 unsigned long devhandle, flags, order, first_page, npages, n;
87 void *ret;
88 long entry;
89 u64 *pglist;
90 int cpu;
91
92 size = IO_PAGE_ALIGN(size);
93 order = get_order(size);
94 if (order >= MAX_ORDER)
95 return NULL;
96
97 npages = size >> IO_PAGE_SHIFT;
98 if (npages > PGLIST_NENTS)
99 return NULL;
100
101 first_page = __get_free_pages(GFP_ATOMIC, order);
102 if (first_page == 0UL)
103 return NULL;
104 memset((char *)first_page, 0, PAGE_SIZE << order);
105
106 pcp = pdev->sysdata;
107 devhandle = pcp->pbm->devhandle;
108 iommu = pcp->pbm->iommu;
109
110 spin_lock_irqsave(&iommu->lock, flags);
111 entry = pci_arena_alloc(&iommu->arena, npages);
112 spin_unlock_irqrestore(&iommu->lock, flags);
113
114 if (unlikely(entry < 0L)) {
115 free_pages(first_page, order);
116 return NULL;
117 }
118
119 *dma_addrp = (iommu->page_table_map_base +
120 (entry << IO_PAGE_SHIFT));
121 ret = (void *) first_page;
122 first_page = __pa(first_page);
123
124 cpu = get_cpu();
125
126 pglist = &__get_cpu_var(iommu_pglists).pglist[0];
127 for (n = 0; n < npages; n++)
128 pglist[n] = first_page + (n * PAGE_SIZE);
129
130 do {
131 unsigned long num;
132
133 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
134 npages,
135 (HV_PCI_MAP_ATTR_READ |
136 HV_PCI_MAP_ATTR_WRITE),
137 __pa(pglist));
138 entry += num;
139 npages -= num;
140 pglist += num;
141 } while (npages != 0);
142
143 put_cpu();
144
145 return ret;
8f6a93a1
DM		 146}
147
148static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
149{
18397944
DM		 150 struct pcidev_cookie *pcp;
151 struct pci_iommu *iommu;
152 unsigned long flags, order, npages, entry, devhandle;
153
154 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
155 pcp = pdev->sysdata;
156 iommu = pcp->pbm->iommu;
157 devhandle = pcp->pbm->devhandle;
158 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
159
160 spin_lock_irqsave(&iommu->lock, flags);
161
162 pci_arena_free(&iommu->arena, entry, npages);
163
164 do {
165 unsigned long num;
166
167 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
168 npages);
169 entry += num;
170 npages -= num;
171 } while (npages != 0);
172
173 spin_unlock_irqrestore(&iommu->lock, flags);
174
175 order = get_order(size);
176 if (order < 10)
177 free_pages((unsigned long)cpu, order);
8f6a93a1
DM		 178}
179
180static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
181{
18397944
DM		 182 struct pcidev_cookie *pcp;
183 struct pci_iommu *iommu;
184 unsigned long flags, npages, oaddr;
185 unsigned long i, base_paddr, devhandle;
186 u32 bus_addr, ret;
187 unsigned long prot;
188 long entry;
189 u64 *pglist;
190 int cpu;
191
192 pcp = pdev->sysdata;
193 iommu = pcp->pbm->iommu;
194 devhandle = pcp->pbm->devhandle;
195
196 if (unlikely(direction == PCI_DMA_NONE))
197 goto bad;
198
199 oaddr = (unsigned long)ptr;
200 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
201 npages >>= IO_PAGE_SHIFT;
202 if (unlikely(npages > PGLIST_NENTS))
203 goto bad;
204
205 spin_lock_irqsave(&iommu->lock, flags);
206 entry = pci_arena_alloc(&iommu->arena, npages);
207 spin_unlock_irqrestore(&iommu->lock, flags);
208
209 if (unlikely(entry < 0L))
210 goto bad;
211
212 bus_addr = (iommu->page_table_map_base +
213 (entry << IO_PAGE_SHIFT));
214 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
215 base_paddr = __pa(oaddr & IO_PAGE_MASK);
216 prot = HV_PCI_MAP_ATTR_READ;
217 if (direction != PCI_DMA_TODEVICE)
218 prot |= HV_PCI_MAP_ATTR_WRITE;
219
220 cpu = get_cpu();
221
222 pglist = &__get_cpu_var(iommu_pglists).pglist[0];
223 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE)
224 pglist[i] = base_paddr;
225
226 do {
227 unsigned long num;
228
229 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
230 npages, prot,
231 __pa(pglist));
232 entry += num;
233 npages -= num;
234 pglist += num;
235 } while (npages != 0);
236
237 put_cpu();
238
239 return ret;
240
241bad:
242 if (printk_ratelimit())
243 WARN_ON(1);
244 return PCI_DMA_ERROR_CODE;
8f6a93a1
DM		 245}
246
247static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
248{
18397944
DM		 249 struct pcidev_cookie *pcp;
250 struct pci_iommu *iommu;
251 unsigned long flags, npages, devhandle;
252 long entry;
253
254 if (unlikely(direction == PCI_DMA_NONE)) {
255 if (printk_ratelimit())
256 WARN_ON(1);
257 return;
258 }
259
260 pcp = pdev->sysdata;
261 iommu = pcp->pbm->iommu;
262 devhandle = pcp->pbm->devhandle;
263
264 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
265 npages >>= IO_PAGE_SHIFT;
266 bus_addr &= IO_PAGE_MASK;
267
268 spin_lock_irqsave(&iommu->lock, flags);
269
270 entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
271 pci_arena_free(&iommu->arena, entry, npages);
272
273 do {
274 unsigned long num;
275
276 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
277 npages);
278 entry += num;
279 npages -= num;
280 } while (npages != 0);
281
282 spin_unlock_irqrestore(&iommu->lock, flags);
283}
284
285#define SG_ENT_PHYS_ADDRESS(SG) \
286 (__pa(page_address((SG)->page)) + (SG)->offset)
287
288static inline void fill_sg(long entry, unsigned long devhandle,
289 struct scatterlist *sg,
290 int nused, int nelems, unsigned long prot)
291{
292 struct scatterlist *dma_sg = sg;
293 struct scatterlist *sg_end = sg + nelems;
294 int i, cpu, pglist_ent;
295 u64 *pglist;
296
297 cpu = get_cpu();
298 pglist = &__get_cpu_var(iommu_pglists).pglist[0];
299 pglist_ent = 0;
300 for (i = 0; i < nused; i++) {
301 unsigned long pteval = ~0UL;
302 u32 dma_npages;
303
304 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
305 dma_sg->dma_length +
306 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
307 do {
308 unsigned long offset;
309 signed int len;
310
311 /* If we are here, we know we have at least one
312 * more page to map. So walk forward until we
313 * hit a page crossing, and begin creating new
314 * mappings from that spot.
315 */
316 for (;;) {
317 unsigned long tmp;
318
319 tmp = SG_ENT_PHYS_ADDRESS(sg);
320 len = sg->length;
321 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
322 pteval = tmp & IO_PAGE_MASK;
323 offset = tmp & (IO_PAGE_SIZE - 1UL);
324 break;
325 }
326 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
327 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
328 offset = 0UL;
329 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
330 break;
331 }
332 sg++;
333 }
334
335 pteval = (pteval & IOPTE_PAGE);
336 while (len > 0) {
337 pglist[pglist_ent++] = pteval;
338 pteval += IO_PAGE_SIZE;
339 len -= (IO_PAGE_SIZE - offset);
340 offset = 0;
341 dma_npages--;
342 }
343
344 pteval = (pteval & IOPTE_PAGE) + len;
345 sg++;
346
347 /* Skip over any tail mappings we've fully mapped,
348 * adjusting pteval along the way. Stop when we
349 * detect a page crossing event.
350 */
351 while (sg < sg_end &&
352 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
353 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
354 ((pteval ^
355 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
356 pteval += sg->length;
357 sg++;
358 }
359 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
360 pteval = ~0UL;
361 } while (dma_npages != 0);
362 dma_sg++;
363 }
364
365 BUG_ON(pglist_ent == 0);
366
367 do {
368 unsigned long num;
369
370 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
371 pglist_ent);
372 entry += num;
373 pglist_ent -= num;
374 } while (pglist_ent != 0);
375
376 put_cpu();
8f6a93a1
DM		 377}
378
379static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
380{
18397944
DM		 381 struct pcidev_cookie *pcp;
382 struct pci_iommu *iommu;
383 unsigned long flags, npages, prot, devhandle;
384 u32 dma_base;
385 struct scatterlist *sgtmp;
386 long entry;
387 int used;
388
389 /* Fast path single entry scatterlists. */
390 if (nelems == 1) {
391 sglist->dma_address =
392 pci_4v_map_single(pdev,
393 (page_address(sglist->page) + sglist->offset),
394 sglist->length, direction);
395 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
396 return 0;
397 sglist->dma_length = sglist->length;
398 return 1;
399 }
400
401 pcp = pdev->sysdata;
402 iommu = pcp->pbm->iommu;
403 devhandle = pcp->pbm->devhandle;
404
405 if (unlikely(direction == PCI_DMA_NONE))
406 goto bad;
407
408 /* Step 1: Prepare scatter list. */
409 npages = prepare_sg(sglist, nelems);
410 if (unlikely(npages > PGLIST_NENTS))
411 goto bad;
412
413 /* Step 2: Allocate a cluster and context, if necessary. */
414 spin_lock_irqsave(&iommu->lock, flags);
415 entry = pci_arena_alloc(&iommu->arena, npages);
416 spin_unlock_irqrestore(&iommu->lock, flags);
417
418 if (unlikely(entry < 0L))
419 goto bad;
420
421 dma_base = iommu->page_table_map_base +
422 (entry << IO_PAGE_SHIFT);
423
424 /* Step 3: Normalize DMA addresses. */
425 used = nelems;
426
427 sgtmp = sglist;
428 while (used && sgtmp->dma_length) {
429 sgtmp->dma_address += dma_base;
430 sgtmp++;
431 used--;
432 }
433 used = nelems - used;
434
435 /* Step 4: Create the mappings. */
436 prot = HV_PCI_MAP_ATTR_READ;
437 if (direction != PCI_DMA_TODEVICE)
438 prot |= HV_PCI_MAP_ATTR_WRITE;
439
440 fill_sg(entry, devhandle, sglist, used, nelems, prot);
441
442 return used;
443
444bad:
445 if (printk_ratelimit())
446 WARN_ON(1);
447 return 0;
8f6a93a1
DM		 448}
449
450static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
451{
18397944
DM		 452 struct pcidev_cookie *pcp;
453 struct pci_iommu *iommu;
454 unsigned long flags, i, npages, devhandle;
455 long entry;
456 u32 bus_addr;
457
458 if (unlikely(direction == PCI_DMA_NONE)) {
459 if (printk_ratelimit())
460 WARN_ON(1);
461 }
462
463 pcp = pdev->sysdata;
464 iommu = pcp->pbm->iommu;
465 devhandle = pcp->pbm->devhandle;
466
467 bus_addr = sglist->dma_address & IO_PAGE_MASK;
468
469 for (i = 1; i < nelems; i++)
470 if (sglist[i].dma_length == 0)
471 break;
472 i--;
473 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
474 bus_addr) >> IO_PAGE_SHIFT;
475
476 entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
477
478 spin_lock_irqsave(&iommu->lock, flags);
479
480 pci_arena_free(&iommu->arena, entry, npages);
481
482 do {
483 unsigned long num;
484
485 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
486 npages);
487 entry += num;
488 npages -= num;
489 } while (npages != 0);
490
491 spin_unlock_irqrestore(&iommu->lock, flags);
8f6a93a1
DM		 492}
493
494static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
495{
18397944 496 /* Nothing to do... */
8f6a93a1
DM		 497}
498
499static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
500{
18397944 501 /* Nothing to do... */
8f6a93a1
DM		 502}
503
504struct pci_iommu_ops pci_sun4v_iommu_ops = {
505 .alloc_consistent = pci_4v_alloc_consistent,
506 .free_consistent = pci_4v_free_consistent,
507 .map_single = pci_4v_map_single,
508 .unmap_single = pci_4v_unmap_single,
509 .map_sg = pci_4v_map_sg,
510 .unmap_sg = pci_4v_unmap_sg,
511 .dma_sync_single_for_cpu = pci_4v_dma_sync_single_for_cpu,
512 .dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu,
513};
514
bade5622
DM		 515/* SUN4V PCI configuration space accessors. */
516
517static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
518 int where, int size, u32 *value)
519{
7eae642f
DM		 520 struct pci_pbm_info *pbm = bus_dev->sysdata;
521 unsigned long devhandle = pbm->devhandle;
522 unsigned int bus = bus_dev->number;
523 unsigned int device = PCI_SLOT(devfn);
524 unsigned int func = PCI_FUNC(devfn);
525 unsigned long ret;
526
527 ret = pci_sun4v_config_get(devhandle,
528 HV_PCI_DEVICE_BUILD(bus, device, func),
529 where, size);
530 switch (size) {
531 case 1:
532 *value = ret & 0xff;
533 break;
534 case 2:
535 *value = ret & 0xffff;
536 break;
537 case 4:
538 *value = ret & 0xffffffff;
539 break;
540 };
541
542
543 return PCIBIOS_SUCCESSFUL;
bade5622
DM		 544}
545
546static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
547 int where, int size, u32 value)
548{
7eae642f
DM		 549 struct pci_pbm_info *pbm = bus_dev->sysdata;
550 unsigned long devhandle = pbm->devhandle;
551 unsigned int bus = bus_dev->number;
552 unsigned int device = PCI_SLOT(devfn);
553 unsigned int func = PCI_FUNC(devfn);
554 unsigned long ret;
555
556 ret = pci_sun4v_config_put(devhandle,
557 HV_PCI_DEVICE_BUILD(bus, device, func),
558 where, size, value);
559
560 return PCIBIOS_SUCCESSFUL;
bade5622
DM		 561}
562
563static struct pci_ops pci_sun4v_ops = {
564 .read = pci_sun4v_read_pci_cfg,
565 .write = pci_sun4v_write_pci_cfg,
566};
567
568
c2609267
DM		 569static void pbm_scan_bus(struct pci_controller_info *p,
570 struct pci_pbm_info *pbm)
571{
572 struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
573
574 if (!cookie) {
575 prom_printf("%s: Critical allocation failure.\n", pbm->name);
576 prom_halt();
577 }
578
579 /* All we care about is the PBM. */
580 memset(cookie, 0, sizeof(*cookie));
581 cookie->pbm = pbm;
582
583 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
584 p->pci_ops,
585 pbm);
586 pci_fixup_host_bridge_self(pbm->pci_bus);
587 pbm->pci_bus->self->sysdata = cookie;
588
589 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
590 pci_record_assignments(pbm, pbm->pci_bus);
591 pci_assign_unassigned(pbm, pbm->pci_bus);
592 pci_fixup_irq(pbm, pbm->pci_bus);
593 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
594 pci_setup_busmastering(pbm, pbm->pci_bus);
595}
596
bade5622
DM		 597static void pci_sun4v_scan_bus(struct pci_controller_info *p)
598{
c2609267
DM		 599 if (p->pbm_A.prom_node) {
600 p->pbm_A.is_66mhz_capable =
601 prom_getbool(p->pbm_A.prom_node, "66mhz-capable");
602
603 pbm_scan_bus(p, &p->pbm_A);
604 }
605 if (p->pbm_B.prom_node) {
606 p->pbm_B.is_66mhz_capable =
607 prom_getbool(p->pbm_B.prom_node, "66mhz-capable");
608
609 pbm_scan_bus(p, &p->pbm_B);
610 }
611
612 /* XXX register error interrupt handlers XXX */
bade5622
DM		 613}
614
615static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
616 struct pci_dev *pdev,
617 unsigned int ino)
618{
619 /* XXX Implement me! XXX */
620 return 0;
621}
622
bade5622
DM		 623static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
624{
625 struct pcidev_cookie *pcp = pdev->sysdata;
626 struct pci_pbm_info *pbm = pcp->pbm;
627 struct resource *res, *root;
628 u32 reg;
629 int where, size, is_64bit;
630
631 res = &pdev->resource[resource];
632 if (resource < 6) {
633 where = PCI_BASE_ADDRESS_0 + (resource * 4);
634 } else if (resource == PCI_ROM_RESOURCE) {
635 where = pdev->rom_base_reg;
636 } else {
637 /* Somebody might have asked allocation of a non-standard resource */
638 return;
639 }
640
c2609267 641 /* XXX 64-bit MEM handling is not %100 correct... XXX */
bade5622
DM		 642 is_64bit = 0;
643 if (res->flags & IORESOURCE_IO)
644 root = &pbm->io_space;
645 else {
646 root = &pbm->mem_space;
647 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
648 == PCI_BASE_ADDRESS_MEM_TYPE_64)
649 is_64bit = 1;
650 }
651
652 size = res->end - res->start;
653 pci_read_config_dword(pdev, where, &reg);
654 reg = ((reg & size) |
655 (((u32)(res->start - root->start)) & ~size));
656 if (resource == PCI_ROM_RESOURCE) {
657 reg |= PCI_ROM_ADDRESS_ENABLE;
658 res->flags |= IORESOURCE_ROM_ENABLE;
659 }
660 pci_write_config_dword(pdev, where, reg);
661
662 /* This knows that the upper 32-bits of the address
663 * must be zero. Our PCI common layer enforces this.
664 */
665 if (is_64bit)
666 pci_write_config_dword(pdev, where + 4, 0);
667}
668
bade5622
DM		 669static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
670 struct resource *res,
671 struct resource *root)
672{
673 res->start += root->start;
674 res->end += root->start;
675}
676
677/* Use ranges property to determine where PCI MEM, I/O, and Config
678 * space are for this PCI bus module.
679 */
680static void pci_sun4v_determine_mem_io_space(struct pci_pbm_info *pbm)
681{
221b2fb8 682 int i, saw_mem, saw_io;
bade5622 683
221b2fb8 684 saw_mem = saw_io = 0;
bade5622
DM		 685 for (i = 0; i < pbm->num_pbm_ranges; i++) {
686 struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
687 unsigned long a;
688 int type;
689
690 type = (pr->child_phys_hi >> 24) & 0x3;
691 a = (((unsigned long)pr->parent_phys_hi << 32UL) |
692 ((unsigned long)pr->parent_phys_lo << 0UL));
693
694 switch (type) {
bade5622
DM		 695 case 1:
696 /* 16-bit IO space, 16MB */
697 pbm->io_space.start = a;
698 pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
699 pbm->io_space.flags = IORESOURCE_IO;
700 saw_io = 1;
701 break;
702
703 case 2:
704 /* 32-bit MEM space, 2GB */
705 pbm->mem_space.start = a;
706 pbm->mem_space.end = a + (0x80000000UL - 1UL);
707 pbm->mem_space.flags = IORESOURCE_MEM;
708 saw_mem = 1;
709 break;
710
c2609267
DM		 711 case 3:
712 /* XXX 64-bit MEM handling XXX */
713
bade5622
DM		 714 default:
715 break;
716 };
717 }
718
221b2fb8 719 if (!saw_io || !saw_mem) {
bade5622
DM		 720 prom_printf("%s: Fatal error, missing %s PBM range.\n",
721 pbm->name,
221b2fb8 722 (!saw_io ? "IO" : "MEM"));
bade5622
DM		 723 prom_halt();
724 }
725
221b2fb8 726 printk("%s: PCI IO[%lx] MEM[%lx]\n",
bade5622 727 pbm->name,
bade5622
DM		 728 pbm->io_space.start,
729 pbm->mem_space.start);
730}
731
732static void pbm_register_toplevel_resources(struct pci_controller_info *p,
733 struct pci_pbm_info *pbm)
734{
735 pbm->io_space.name = pbm->mem_space.name = pbm->name;
736
737 request_resource(&ioport_resource, &pbm->io_space);
738 request_resource(&iomem_resource, &pbm->mem_space);
739 pci_register_legacy_regions(&pbm->io_space,
740 &pbm->mem_space);
741}
742
18397944
DM		 743static void probe_existing_entries(struct pci_pbm_info *pbm,
744 struct pci_iommu *iommu)
745{
746 struct pci_iommu_arena *arena = &iommu->arena;
747 unsigned long i, devhandle;
748
749 devhandle = pbm->devhandle;
750 for (i = 0; i < arena->limit; i++) {
751 unsigned long ret, io_attrs, ra;
752
753 ret = pci_sun4v_iommu_getmap(devhandle,
754 HV_PCI_TSBID(0, i),
755 &io_attrs, &ra);
756 if (ret == HV_EOK)
757 __set_bit(i, arena->map);
758 }
759}
760
bade5622
DM		 761static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
762{
18397944
DM		 763 struct pci_iommu *iommu = pbm->iommu;
764 unsigned long num_tsb_entries, sz;
765 u32 vdma[2], dma_mask, dma_offset;
766 int err, tsbsize;
767
768 err = prom_getproperty(pbm->prom_node, "virtual-dma",
769 (char *)&vdma[0], sizeof(vdma));
770 if (err == 0 || err == -1) {
771 /* No property, use default values. */
772 vdma[0] = 0x80000000;
773 vdma[1] = 0x80000000;
774 }
775
776 dma_mask = vdma[0];
777 switch (vdma[1]) {
778 case 0x20000000:
779 dma_mask |= 0x1fffffff;
780 tsbsize = 64;
781 break;
782
783 case 0x40000000:
784 dma_mask |= 0x3fffffff;
785 tsbsize = 128;
786 break;
787
788 case 0x80000000:
789 dma_mask |= 0x7fffffff;
790 tsbsize = 128;
791 break;
792
793 default:
794 prom_printf("PCI-SUN4V: strange virtual-dma size.\n");
795 prom_halt();
796 };
797
798 num_tsb_entries = tsbsize / sizeof(iopte_t);
799
800 dma_offset = vdma[0];
801
802 /* Setup initial software IOMMU state. */
803 spin_lock_init(&iommu->lock);
804 iommu->ctx_lowest_free = 1;
805 iommu->page_table_map_base = dma_offset;
806 iommu->dma_addr_mask = dma_mask;
807
808 /* Allocate and initialize the free area map. */
809 sz = num_tsb_entries / 8;
810 sz = (sz + 7UL) & ~7UL;
811 iommu->arena.map = kmalloc(sz, GFP_KERNEL);
812 if (!iommu->arena.map) {
813 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
814 prom_halt();
815 }
816 memset(iommu->arena.map, 0, sz);
817 iommu->arena.limit = num_tsb_entries;
818
819 probe_existing_entries(pbm, iommu);
bade5622
DM		 820}
821
3833789b 822static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node, unsigned int devhandle)
bade5622
DM		 823{
824 struct pci_pbm_info *pbm;
bade5622 825 unsigned int busrange[2];
3833789b 826 int err, i;
bade5622 827
3833789b
DM		 828 if (devhandle & 0x40)
829 pbm = &p->pbm_B;
830 else
831 pbm = &p->pbm_A;
bade5622
DM		 832
833 pbm->parent = p;
834 pbm->prom_node = prom_node;
835 pbm->pci_first_slot = 1;
836
3833789b 837 pbm->devhandle = devhandle;
bade5622
DM		 838
839 sprintf(pbm->name, "SUN4V-PCI%d PBM%c",
840 p->index, (pbm == &p->pbm_A ? 'A' : 'B'));
841
842 printk("%s: devhandle[%x]\n", pbm->name, pbm->devhandle);
843
844 prom_getstring(prom_node, "name",
845 pbm->prom_name, sizeof(pbm->prom_name));
846
847 err = prom_getproperty(prom_node, "ranges",
848 (char *) pbm->pbm_ranges,
849 sizeof(pbm->pbm_ranges));
850 if (err == 0 || err == -1) {
851 prom_printf("%s: Fatal error, no ranges property.\n",
852 pbm->name);
853 prom_halt();
854 }
855
856 pbm->num_pbm_ranges =
857 (err / sizeof(struct linux_prom_pci_ranges));
858
3833789b
DM		 859 /* Mask out the top 8 bits of the ranges, leaving the real
860 * physical address.
861 */
862 for (i = 0; i < pbm->num_pbm_ranges; i++)
863 pbm->pbm_ranges[i].parent_phys_hi &= 0x0fffffff;
864
bade5622
DM		 865 pci_sun4v_determine_mem_io_space(pbm);
866 pbm_register_toplevel_resources(p, pbm);
867
868 err = prom_getproperty(prom_node, "interrupt-map",
869 (char *)pbm->pbm_intmap,
870 sizeof(pbm->pbm_intmap));
871 if (err != -1) {
872 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
873 err = prom_getproperty(prom_node, "interrupt-map-mask",
874 (char *)&pbm->pbm_intmask,
875 sizeof(pbm->pbm_intmask));
876 if (err == -1) {
877 prom_printf("%s: Fatal error, no "
878 "interrupt-map-mask.\n", pbm->name);
879 prom_halt();
880 }
881 } else {
882 pbm->num_pbm_intmap = 0;
883 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
884 }
885
886 err = prom_getproperty(prom_node, "bus-range",
887 (char *)&busrange[0],
888 sizeof(busrange));
889 if (err == 0 || err == -1) {
890 prom_printf("%s: Fatal error, no bus-range.\n", pbm->name);
891 prom_halt();
892 }
893 pbm->pci_first_busno = busrange[0];
894 pbm->pci_last_busno = busrange[1];
895
896 pci_sun4v_iommu_init(pbm);
897}
898
8f6a93a1
DM		 899void sun4v_pci_init(int node, char *model_name)
900{
bade5622
DM		 901 struct pci_controller_info *p;
902 struct pci_iommu *iommu;
3833789b
DM		 903 struct linux_prom64_registers regs;
904 unsigned int devhandle;
905
906 prom_getproperty(node, "reg", (char *)&regs, sizeof(regs));
907 devhandle = (regs.phys_addr >> 32UL) & 0x0fffffff;;
908
909 for (p = pci_controller_root; p; p = p->next) {
910 struct pci_pbm_info *pbm;
911
912 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
913 continue;
914
915 pbm = (p->pbm_A.prom_node ?
916 &p->pbm_A :
917 &p->pbm_B);
918
0b522497 919 if (pbm->devhandle == (devhandle ^ 0x40)) {
3833789b 920 pci_sun4v_pbm_init(p, node, devhandle);
0b522497
DM		 921 return;
922 }
3833789b 923 }
bade5622
DM		 924
925 p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
926 if (!p) {
927 prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
928 prom_halt();
929 }
930 memset(p, 0, sizeof(*p));
931
932 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
933 if (!iommu) {
934 prom_printf("SCHIZO: Fatal memory allocation error.\n");
935 prom_halt();
936 }
937 memset(iommu, 0, sizeof(*iommu));
938 p->pbm_A.iommu = iommu;
939
940 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
941 if (!iommu) {
942 prom_printf("SCHIZO: Fatal memory allocation error.\n");
943 prom_halt();
944 }
945 memset(iommu, 0, sizeof(*iommu));
946 p->pbm_B.iommu = iommu;
947
948 p->next = pci_controller_root;
949 pci_controller_root = p;
950
951 p->index = pci_num_controllers++;
952 p->pbms_same_domain = 0;
953
954 p->scan_bus = pci_sun4v_scan_bus;
955 p->irq_build = pci_sun4v_irq_build;
956 p->base_address_update = pci_sun4v_base_address_update;
957 p->resource_adjust = pci_sun4v_resource_adjust;
958 p->pci_ops = &pci_sun4v_ops;
959
960 /* Like PSYCHO and SCHIZO we have a 2GB aligned area
961 * for memory space.
962 */
963 pci_memspace_mask = 0x7fffffffUL;
964
3833789b 965 pci_sun4v_pbm_init(p, node, devhandle);
8f6a93a1 966}
Linux kernel - Deliverables
This page took 0.061608 seconds and 5 git commands to generate.