Commit | Line | Data |
---|---|---|
8f6a93a1 DM |
1 | /* pci_sun4v.c: SUN4V specific PCI controller support. |
2 | * | |
d284142c | 3 | * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net) |
8f6a93a1 DM |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/types.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/interrupt.h> | |
18397944 | 12 | #include <linux/percpu.h> |
35a17eb6 DM |
13 | #include <linux/irq.h> |
14 | #include <linux/msi.h> | |
59db8102 | 15 | #include <linux/log2.h> |
3822b509 | 16 | #include <linux/of_device.h> |
8f6a93a1 | 17 | |
8f6a93a1 DM |
18 | #include <asm/iommu.h> |
19 | #include <asm/irq.h> | |
8f6a93a1 | 20 | #include <asm/hypervisor.h> |
e87dc350 | 21 | #include <asm/prom.h> |
8f6a93a1 DM |
22 | |
23 | #include "pci_impl.h" | |
24 | #include "iommu_common.h" | |
25 | ||
bade5622 DM |
26 | #include "pci_sun4v.h" |
27 | ||
3822b509 DM |
28 | #define DRIVER_NAME "pci_sun4v" |
29 | #define PFX DRIVER_NAME ": " | |
30 | ||
e01c0d6d DM |
31 | static unsigned long vpci_major = 1; |
32 | static unsigned long vpci_minor = 1; | |
33 | ||
7c8f486a | 34 | #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64)) |
18397944 | 35 | |
16ce82d8 | 36 | struct iommu_batch { |
ad7ad57c | 37 | struct device *dev; /* Device mapping is for. */ |
6a32fd4d DM |
38 | unsigned long prot; /* IOMMU page protections */ |
39 | unsigned long entry; /* Index into IOTSB. */ | |
40 | u64 *pglist; /* List of physical pages */ | |
41 | unsigned long npages; /* Number of pages in list. */ | |
18397944 DM |
42 | }; |
43 | ||
ad7ad57c | 44 | static DEFINE_PER_CPU(struct iommu_batch, iommu_batch); |
6a32fd4d DM |
45 | |
46 | /* Interrupts must be disabled. */ | |
ad7ad57c | 47 | static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry) |
6a32fd4d | 48 | { |
ad7ad57c | 49 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d | 50 | |
ad7ad57c | 51 | p->dev = dev; |
6a32fd4d DM |
52 | p->prot = prot; |
53 | p->entry = entry; | |
54 | p->npages = 0; | |
55 | } | |
56 | ||
57 | /* Interrupts must be disabled. */ | |
ad7ad57c | 58 | static long iommu_batch_flush(struct iommu_batch *p) |
6a32fd4d | 59 | { |
ad7ad57c | 60 | struct pci_pbm_info *pbm = p->dev->archdata.host_controller; |
a2fb23af | 61 | unsigned long devhandle = pbm->devhandle; |
6a32fd4d DM |
62 | unsigned long prot = p->prot; |
63 | unsigned long entry = p->entry; | |
64 | u64 *pglist = p->pglist; | |
65 | unsigned long npages = p->npages; | |
66 | ||
d82965c1 | 67 | while (npages != 0) { |
6a32fd4d DM |
68 | long num; |
69 | ||
70 | num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry), | |
71 | npages, prot, __pa(pglist)); | |
72 | if (unlikely(num < 0)) { | |
73 | if (printk_ratelimit()) | |
ad7ad57c | 74 | printk("iommu_batch_flush: IOMMU map of " |
6a32fd4d DM |
75 | "[%08lx:%08lx:%lx:%lx:%lx] failed with " |
76 | "status %ld\n", | |
77 | devhandle, HV_PCI_TSBID(0, entry), | |
78 | npages, prot, __pa(pglist), num); | |
79 | return -1; | |
80 | } | |
81 | ||
82 | entry += num; | |
83 | npages -= num; | |
84 | pglist += num; | |
d82965c1 | 85 | } |
6a32fd4d DM |
86 | |
87 | p->entry = entry; | |
88 | p->npages = 0; | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
13fa14e1 DM |
93 | static inline void iommu_batch_new_entry(unsigned long entry) |
94 | { | |
95 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); | |
96 | ||
97 | if (p->entry + p->npages == entry) | |
98 | return; | |
99 | if (p->entry != ~0UL) | |
100 | iommu_batch_flush(p); | |
101 | p->entry = entry; | |
102 | } | |
103 | ||
6a32fd4d | 104 | /* Interrupts must be disabled. */ |
ad7ad57c | 105 | static inline long iommu_batch_add(u64 phys_page) |
6a32fd4d | 106 | { |
ad7ad57c | 107 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d DM |
108 | |
109 | BUG_ON(p->npages >= PGLIST_NENTS); | |
110 | ||
111 | p->pglist[p->npages++] = phys_page; | |
112 | if (p->npages == PGLIST_NENTS) | |
ad7ad57c | 113 | return iommu_batch_flush(p); |
6a32fd4d DM |
114 | |
115 | return 0; | |
116 | } | |
117 | ||
118 | /* Interrupts must be disabled. */ | |
ad7ad57c | 119 | static inline long iommu_batch_end(void) |
6a32fd4d | 120 | { |
ad7ad57c | 121 | struct iommu_batch *p = &__get_cpu_var(iommu_batch); |
6a32fd4d DM |
122 | |
123 | BUG_ON(p->npages >= PGLIST_NENTS); | |
124 | ||
ad7ad57c | 125 | return iommu_batch_flush(p); |
6a32fd4d | 126 | } |
18397944 | 127 | |
ad7ad57c DM |
128 | static void *dma_4v_alloc_coherent(struct device *dev, size_t size, |
129 | dma_addr_t *dma_addrp, gfp_t gfp) | |
8f6a93a1 | 130 | { |
7c8f486a | 131 | unsigned long flags, order, first_page, npages, n; |
c1b1a5f1 DM |
132 | struct iommu *iommu; |
133 | struct page *page; | |
18397944 DM |
134 | void *ret; |
135 | long entry; | |
c1b1a5f1 | 136 | int nid; |
18397944 DM |
137 | |
138 | size = IO_PAGE_ALIGN(size); | |
139 | order = get_order(size); | |
6a32fd4d | 140 | if (unlikely(order >= MAX_ORDER)) |
18397944 DM |
141 | return NULL; |
142 | ||
143 | npages = size >> IO_PAGE_SHIFT; | |
18397944 | 144 | |
c1b1a5f1 DM |
145 | nid = dev->archdata.numa_node; |
146 | page = alloc_pages_node(nid, gfp, order); | |
147 | if (unlikely(!page)) | |
18397944 | 148 | return NULL; |
e7a0453e | 149 | |
c1b1a5f1 | 150 | first_page = (unsigned long) page_address(page); |
18397944 DM |
151 | memset((char *)first_page, 0, PAGE_SIZE << order); |
152 | ||
ad7ad57c | 153 | iommu = dev->archdata.iommu; |
18397944 DM |
154 | |
155 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 156 | entry = iommu_range_alloc(dev, iommu, npages, NULL); |
18397944 DM |
157 | spin_unlock_irqrestore(&iommu->lock, flags); |
158 | ||
d284142c DM |
159 | if (unlikely(entry == DMA_ERROR_CODE)) |
160 | goto range_alloc_fail; | |
18397944 DM |
161 | |
162 | *dma_addrp = (iommu->page_table_map_base + | |
163 | (entry << IO_PAGE_SHIFT)); | |
164 | ret = (void *) first_page; | |
165 | first_page = __pa(first_page); | |
166 | ||
6a32fd4d | 167 | local_irq_save(flags); |
18397944 | 168 | |
ad7ad57c DM |
169 | iommu_batch_start(dev, |
170 | (HV_PCI_MAP_ATTR_READ | | |
171 | HV_PCI_MAP_ATTR_WRITE), | |
172 | entry); | |
18397944 | 173 | |
6a32fd4d | 174 | for (n = 0; n < npages; n++) { |
ad7ad57c | 175 | long err = iommu_batch_add(first_page + (n * PAGE_SIZE)); |
6a32fd4d DM |
176 | if (unlikely(err < 0L)) |
177 | goto iommu_map_fail; | |
178 | } | |
18397944 | 179 | |
ad7ad57c | 180 | if (unlikely(iommu_batch_end() < 0L)) |
6a32fd4d | 181 | goto iommu_map_fail; |
18397944 | 182 | |
6a32fd4d | 183 | local_irq_restore(flags); |
18397944 DM |
184 | |
185 | return ret; | |
6a32fd4d DM |
186 | |
187 | iommu_map_fail: | |
188 | /* Interrupts are disabled. */ | |
189 | spin_lock(&iommu->lock); | |
d284142c | 190 | iommu_range_free(iommu, *dma_addrp, npages); |
6a32fd4d DM |
191 | spin_unlock_irqrestore(&iommu->lock, flags); |
192 | ||
d284142c | 193 | range_alloc_fail: |
6a32fd4d DM |
194 | free_pages(first_page, order); |
195 | return NULL; | |
8f6a93a1 DM |
196 | } |
197 | ||
ad7ad57c DM |
198 | static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu, |
199 | dma_addr_t dvma) | |
8f6a93a1 | 200 | { |
a2fb23af | 201 | struct pci_pbm_info *pbm; |
16ce82d8 | 202 | struct iommu *iommu; |
7c8f486a DM |
203 | unsigned long flags, order, npages, entry; |
204 | u32 devhandle; | |
18397944 DM |
205 | |
206 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
ad7ad57c DM |
207 | iommu = dev->archdata.iommu; |
208 | pbm = dev->archdata.host_controller; | |
a2fb23af | 209 | devhandle = pbm->devhandle; |
18397944 DM |
210 | entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); |
211 | ||
212 | spin_lock_irqsave(&iommu->lock, flags); | |
213 | ||
d284142c | 214 | iommu_range_free(iommu, dvma, npages); |
18397944 DM |
215 | |
216 | do { | |
217 | unsigned long num; | |
218 | ||
219 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
220 | npages); | |
221 | entry += num; | |
222 | npages -= num; | |
223 | } while (npages != 0); | |
224 | ||
225 | spin_unlock_irqrestore(&iommu->lock, flags); | |
226 | ||
227 | order = get_order(size); | |
228 | if (order < 10) | |
229 | free_pages((unsigned long)cpu, order); | |
8f6a93a1 DM |
230 | } |
231 | ||
ad7ad57c DM |
232 | static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz, |
233 | enum dma_data_direction direction) | |
8f6a93a1 | 234 | { |
16ce82d8 | 235 | struct iommu *iommu; |
18397944 | 236 | unsigned long flags, npages, oaddr; |
7c8f486a | 237 | unsigned long i, base_paddr; |
6a32fd4d | 238 | u32 bus_addr, ret; |
18397944 DM |
239 | unsigned long prot; |
240 | long entry; | |
18397944 | 241 | |
ad7ad57c | 242 | iommu = dev->archdata.iommu; |
18397944 | 243 | |
ad7ad57c | 244 | if (unlikely(direction == DMA_NONE)) |
18397944 DM |
245 | goto bad; |
246 | ||
247 | oaddr = (unsigned long)ptr; | |
248 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); | |
249 | npages >>= IO_PAGE_SHIFT; | |
18397944 DM |
250 | |
251 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 252 | entry = iommu_range_alloc(dev, iommu, npages, NULL); |
18397944 DM |
253 | spin_unlock_irqrestore(&iommu->lock, flags); |
254 | ||
d284142c | 255 | if (unlikely(entry == DMA_ERROR_CODE)) |
18397944 DM |
256 | goto bad; |
257 | ||
258 | bus_addr = (iommu->page_table_map_base + | |
259 | (entry << IO_PAGE_SHIFT)); | |
260 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
261 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
262 | prot = HV_PCI_MAP_ATTR_READ; | |
ad7ad57c | 263 | if (direction != DMA_TO_DEVICE) |
18397944 DM |
264 | prot |= HV_PCI_MAP_ATTR_WRITE; |
265 | ||
6a32fd4d | 266 | local_irq_save(flags); |
18397944 | 267 | |
ad7ad57c | 268 | iommu_batch_start(dev, prot, entry); |
18397944 | 269 | |
6a32fd4d | 270 | for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) { |
ad7ad57c | 271 | long err = iommu_batch_add(base_paddr); |
6a32fd4d DM |
272 | if (unlikely(err < 0L)) |
273 | goto iommu_map_fail; | |
274 | } | |
ad7ad57c | 275 | if (unlikely(iommu_batch_end() < 0L)) |
6a32fd4d | 276 | goto iommu_map_fail; |
18397944 | 277 | |
6a32fd4d | 278 | local_irq_restore(flags); |
18397944 DM |
279 | |
280 | return ret; | |
281 | ||
282 | bad: | |
283 | if (printk_ratelimit()) | |
284 | WARN_ON(1); | |
ad7ad57c | 285 | return DMA_ERROR_CODE; |
6a32fd4d DM |
286 | |
287 | iommu_map_fail: | |
288 | /* Interrupts are disabled. */ | |
289 | spin_lock(&iommu->lock); | |
d284142c | 290 | iommu_range_free(iommu, bus_addr, npages); |
6a32fd4d DM |
291 | spin_unlock_irqrestore(&iommu->lock, flags); |
292 | ||
ad7ad57c | 293 | return DMA_ERROR_CODE; |
8f6a93a1 DM |
294 | } |
295 | ||
ad7ad57c DM |
296 | static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr, |
297 | size_t sz, enum dma_data_direction direction) | |
8f6a93a1 | 298 | { |
a2fb23af | 299 | struct pci_pbm_info *pbm; |
16ce82d8 | 300 | struct iommu *iommu; |
7c8f486a | 301 | unsigned long flags, npages; |
18397944 | 302 | long entry; |
7c8f486a | 303 | u32 devhandle; |
18397944 | 304 | |
ad7ad57c | 305 | if (unlikely(direction == DMA_NONE)) { |
18397944 DM |
306 | if (printk_ratelimit()) |
307 | WARN_ON(1); | |
308 | return; | |
309 | } | |
310 | ||
ad7ad57c DM |
311 | iommu = dev->archdata.iommu; |
312 | pbm = dev->archdata.host_controller; | |
a2fb23af | 313 | devhandle = pbm->devhandle; |
18397944 DM |
314 | |
315 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
316 | npages >>= IO_PAGE_SHIFT; | |
317 | bus_addr &= IO_PAGE_MASK; | |
318 | ||
319 | spin_lock_irqsave(&iommu->lock, flags); | |
320 | ||
d284142c | 321 | iommu_range_free(iommu, bus_addr, npages); |
18397944 | 322 | |
d284142c | 323 | entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT; |
18397944 DM |
324 | do { |
325 | unsigned long num; | |
326 | ||
327 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
328 | npages); | |
329 | entry += num; | |
330 | npages -= num; | |
331 | } while (npages != 0); | |
332 | ||
333 | spin_unlock_irqrestore(&iommu->lock, flags); | |
334 | } | |
335 | ||
ad7ad57c DM |
336 | static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist, |
337 | int nelems, enum dma_data_direction direction) | |
8f6a93a1 | 338 | { |
13fa14e1 DM |
339 | struct scatterlist *s, *outs, *segstart; |
340 | unsigned long flags, handle, prot; | |
341 | dma_addr_t dma_next = 0, dma_addr; | |
342 | unsigned int max_seg_size; | |
f0880257 | 343 | unsigned long seg_boundary_size; |
13fa14e1 | 344 | int outcount, incount, i; |
16ce82d8 | 345 | struct iommu *iommu; |
f0880257 | 346 | unsigned long base_shift; |
13fa14e1 DM |
347 | long err; |
348 | ||
349 | BUG_ON(direction == DMA_NONE); | |
18397944 | 350 | |
ad7ad57c | 351 | iommu = dev->archdata.iommu; |
13fa14e1 DM |
352 | if (nelems == 0 || !iommu) |
353 | return 0; | |
18397944 | 354 | |
13fa14e1 DM |
355 | prot = HV_PCI_MAP_ATTR_READ; |
356 | if (direction != DMA_TO_DEVICE) | |
357 | prot |= HV_PCI_MAP_ATTR_WRITE; | |
18397944 | 358 | |
13fa14e1 DM |
359 | outs = s = segstart = &sglist[0]; |
360 | outcount = 1; | |
361 | incount = nelems; | |
362 | handle = 0; | |
18397944 | 363 | |
13fa14e1 DM |
364 | /* Init first segment length for backout at failure */ |
365 | outs->dma_length = 0; | |
18397944 | 366 | |
13fa14e1 | 367 | spin_lock_irqsave(&iommu->lock, flags); |
18397944 | 368 | |
13fa14e1 | 369 | iommu_batch_start(dev, prot, ~0UL); |
18397944 | 370 | |
13fa14e1 | 371 | max_seg_size = dma_get_max_seg_size(dev); |
f0880257 FT |
372 | seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
373 | IO_PAGE_SIZE) >> IO_PAGE_SHIFT; | |
374 | base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT; | |
13fa14e1 | 375 | for_each_sg(sglist, s, nelems, i) { |
f0880257 | 376 | unsigned long paddr, npages, entry, out_entry = 0, slen; |
38192d52 | 377 | |
13fa14e1 DM |
378 | slen = s->length; |
379 | /* Sanity check */ | |
380 | if (slen == 0) { | |
381 | dma_next = 0; | |
382 | continue; | |
383 | } | |
384 | /* Allocate iommu entries for that segment */ | |
385 | paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s); | |
386 | npages = iommu_num_pages(paddr, slen); | |
387 | entry = iommu_range_alloc(dev, iommu, npages, &handle); | |
38192d52 | 388 | |
13fa14e1 DM |
389 | /* Handle failure */ |
390 | if (unlikely(entry == DMA_ERROR_CODE)) { | |
391 | if (printk_ratelimit()) | |
392 | printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx" | |
393 | " npages %lx\n", iommu, paddr, npages); | |
394 | goto iommu_map_failed; | |
395 | } | |
38192d52 | 396 | |
13fa14e1 | 397 | iommu_batch_new_entry(entry); |
38192d52 | 398 | |
13fa14e1 DM |
399 | /* Convert entry to a dma_addr_t */ |
400 | dma_addr = iommu->page_table_map_base + | |
401 | (entry << IO_PAGE_SHIFT); | |
402 | dma_addr |= (s->offset & ~IO_PAGE_MASK); | |
38192d52 | 403 | |
13fa14e1 | 404 | /* Insert into HW table */ |
38192d52 | 405 | paddr &= IO_PAGE_MASK; |
13fa14e1 | 406 | while (npages--) { |
38192d52 | 407 | err = iommu_batch_add(paddr); |
13fa14e1 | 408 | if (unlikely(err < 0L)) |
38192d52 | 409 | goto iommu_map_failed; |
13fa14e1 DM |
410 | paddr += IO_PAGE_SIZE; |
411 | } | |
412 | ||
413 | /* If we are in an open segment, try merging */ | |
414 | if (segstart != s) { | |
415 | /* We cannot merge if: | |
416 | * - allocated dma_addr isn't contiguous to previous allocation | |
417 | */ | |
418 | if ((dma_addr != dma_next) || | |
f0880257 FT |
419 | (outs->dma_length + s->length > max_seg_size) || |
420 | (is_span_boundary(out_entry, base_shift, | |
421 | seg_boundary_size, outs, s))) { | |
13fa14e1 DM |
422 | /* Can't merge: create a new segment */ |
423 | segstart = s; | |
424 | outcount++; | |
425 | outs = sg_next(outs); | |
426 | } else { | |
427 | outs->dma_length += s->length; | |
38192d52 | 428 | } |
13fa14e1 | 429 | } |
38192d52 | 430 | |
13fa14e1 DM |
431 | if (segstart == s) { |
432 | /* This is a new segment, fill entries */ | |
433 | outs->dma_address = dma_addr; | |
434 | outs->dma_length = slen; | |
f0880257 | 435 | out_entry = entry; |
38192d52 | 436 | } |
13fa14e1 DM |
437 | |
438 | /* Calculate next page pointer for contiguous check */ | |
439 | dma_next = dma_addr + slen; | |
38192d52 DM |
440 | } |
441 | ||
442 | err = iommu_batch_end(); | |
443 | ||
6a32fd4d DM |
444 | if (unlikely(err < 0L)) |
445 | goto iommu_map_failed; | |
18397944 | 446 | |
13fa14e1 | 447 | spin_unlock_irqrestore(&iommu->lock, flags); |
18397944 | 448 | |
13fa14e1 DM |
449 | if (outcount < incount) { |
450 | outs = sg_next(outs); | |
451 | outs->dma_address = DMA_ERROR_CODE; | |
452 | outs->dma_length = 0; | |
453 | } | |
454 | ||
455 | return outcount; | |
6a32fd4d DM |
456 | |
457 | iommu_map_failed: | |
13fa14e1 DM |
458 | for_each_sg(sglist, s, nelems, i) { |
459 | if (s->dma_length != 0) { | |
460 | unsigned long vaddr, npages; | |
461 | ||
462 | vaddr = s->dma_address & IO_PAGE_MASK; | |
463 | npages = iommu_num_pages(s->dma_address, s->dma_length); | |
464 | iommu_range_free(iommu, vaddr, npages); | |
465 | /* XXX demap? XXX */ | |
466 | s->dma_address = DMA_ERROR_CODE; | |
467 | s->dma_length = 0; | |
468 | } | |
469 | if (s == outs) | |
470 | break; | |
471 | } | |
6a32fd4d DM |
472 | spin_unlock_irqrestore(&iommu->lock, flags); |
473 | ||
474 | return 0; | |
8f6a93a1 DM |
475 | } |
476 | ||
ad7ad57c DM |
477 | static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist, |
478 | int nelems, enum dma_data_direction direction) | |
8f6a93a1 | 479 | { |
a2fb23af | 480 | struct pci_pbm_info *pbm; |
13fa14e1 | 481 | struct scatterlist *sg; |
16ce82d8 | 482 | struct iommu *iommu; |
13fa14e1 DM |
483 | unsigned long flags; |
484 | u32 devhandle; | |
18397944 | 485 | |
13fa14e1 | 486 | BUG_ON(direction == DMA_NONE); |
18397944 | 487 | |
ad7ad57c DM |
488 | iommu = dev->archdata.iommu; |
489 | pbm = dev->archdata.host_controller; | |
a2fb23af | 490 | devhandle = pbm->devhandle; |
18397944 | 491 | |
18397944 DM |
492 | spin_lock_irqsave(&iommu->lock, flags); |
493 | ||
13fa14e1 DM |
494 | sg = sglist; |
495 | while (nelems--) { | |
496 | dma_addr_t dma_handle = sg->dma_address; | |
497 | unsigned int len = sg->dma_length; | |
498 | unsigned long npages, entry; | |
499 | ||
500 | if (!len) | |
501 | break; | |
502 | npages = iommu_num_pages(dma_handle, len); | |
503 | iommu_range_free(iommu, dma_handle, npages); | |
504 | ||
505 | entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
506 | while (npages) { | |
507 | unsigned long num; | |
508 | ||
509 | num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry), | |
510 | npages); | |
511 | entry += num; | |
512 | npages -= num; | |
513 | } | |
18397944 | 514 | |
13fa14e1 DM |
515 | sg = sg_next(sg); |
516 | } | |
18397944 DM |
517 | |
518 | spin_unlock_irqrestore(&iommu->lock, flags); | |
8f6a93a1 DM |
519 | } |
520 | ||
ad7ad57c DM |
521 | static void dma_4v_sync_single_for_cpu(struct device *dev, |
522 | dma_addr_t bus_addr, size_t sz, | |
523 | enum dma_data_direction direction) | |
8f6a93a1 | 524 | { |
18397944 | 525 | /* Nothing to do... */ |
8f6a93a1 DM |
526 | } |
527 | ||
ad7ad57c DM |
528 | static void dma_4v_sync_sg_for_cpu(struct device *dev, |
529 | struct scatterlist *sglist, int nelems, | |
530 | enum dma_data_direction direction) | |
8f6a93a1 | 531 | { |
18397944 | 532 | /* Nothing to do... */ |
8f6a93a1 DM |
533 | } |
534 | ||
908f5162 | 535 | static const struct dma_ops sun4v_dma_ops = { |
ad7ad57c DM |
536 | .alloc_coherent = dma_4v_alloc_coherent, |
537 | .free_coherent = dma_4v_free_coherent, | |
538 | .map_single = dma_4v_map_single, | |
539 | .unmap_single = dma_4v_unmap_single, | |
540 | .map_sg = dma_4v_map_sg, | |
541 | .unmap_sg = dma_4v_unmap_sg, | |
542 | .sync_single_for_cpu = dma_4v_sync_single_for_cpu, | |
543 | .sync_sg_for_cpu = dma_4v_sync_sg_for_cpu, | |
8f6a93a1 DM |
544 | }; |
545 | ||
e822358a DM |
546 | static void __init pci_sun4v_scan_bus(struct pci_pbm_info *pbm, |
547 | struct device *parent) | |
bade5622 | 548 | { |
e87dc350 DM |
549 | struct property *prop; |
550 | struct device_node *dp; | |
551 | ||
34768bc8 DM |
552 | dp = pbm->prom_node; |
553 | prop = of_find_property(dp, "66mhz-capable", NULL); | |
554 | pbm->is_66mhz_capable = (prop != NULL); | |
e822358a | 555 | pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
c2609267 DM |
556 | |
557 | /* XXX register error interrupt handlers XXX */ | |
bade5622 DM |
558 | } |
559 | ||
4c622258 AB |
560 | static unsigned long __init probe_existing_entries(struct pci_pbm_info *pbm, |
561 | struct iommu *iommu) | |
18397944 | 562 | { |
9b3627f3 | 563 | struct iommu_arena *arena = &iommu->arena; |
e7a0453e | 564 | unsigned long i, cnt = 0; |
7c8f486a | 565 | u32 devhandle; |
18397944 DM |
566 | |
567 | devhandle = pbm->devhandle; | |
568 | for (i = 0; i < arena->limit; i++) { | |
569 | unsigned long ret, io_attrs, ra; | |
570 | ||
571 | ret = pci_sun4v_iommu_getmap(devhandle, | |
572 | HV_PCI_TSBID(0, i), | |
573 | &io_attrs, &ra); | |
e7a0453e | 574 | if (ret == HV_EOK) { |
c2a5a46b DM |
575 | if (page_in_phys_avail(ra)) { |
576 | pci_sun4v_iommu_demap(devhandle, | |
577 | HV_PCI_TSBID(0, i), 1); | |
578 | } else { | |
579 | cnt++; | |
580 | __set_bit(i, arena->map); | |
581 | } | |
e7a0453e | 582 | } |
18397944 | 583 | } |
e7a0453e DM |
584 | |
585 | return cnt; | |
18397944 DM |
586 | } |
587 | ||
3822b509 | 588 | static int __init pci_sun4v_iommu_init(struct pci_pbm_info *pbm) |
bade5622 | 589 | { |
8aef7278 | 590 | static const u32 vdma_default[] = { 0x80000000, 0x80000000 }; |
16ce82d8 | 591 | struct iommu *iommu = pbm->iommu; |
59db8102 | 592 | unsigned long num_tsb_entries, sz, tsbsize; |
8aef7278 DM |
593 | u32 dma_mask, dma_offset; |
594 | const u32 *vdma; | |
595 | ||
596 | vdma = of_get_property(pbm->prom_node, "virtual-dma", NULL); | |
597 | if (!vdma) | |
598 | vdma = vdma_default; | |
18397944 | 599 | |
59db8102 | 600 | if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) { |
3822b509 DM |
601 | printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n", |
602 | vdma[0], vdma[1]); | |
603 | return -EINVAL; | |
18397944 DM |
604 | }; |
605 | ||
59db8102 DM |
606 | dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL); |
607 | num_tsb_entries = vdma[1] / IO_PAGE_SIZE; | |
608 | tsbsize = num_tsb_entries * sizeof(iopte_t); | |
18397944 DM |
609 | |
610 | dma_offset = vdma[0]; | |
611 | ||
612 | /* Setup initial software IOMMU state. */ | |
613 | spin_lock_init(&iommu->lock); | |
614 | iommu->ctx_lowest_free = 1; | |
615 | iommu->page_table_map_base = dma_offset; | |
616 | iommu->dma_addr_mask = dma_mask; | |
617 | ||
618 | /* Allocate and initialize the free area map. */ | |
59db8102 | 619 | sz = (num_tsb_entries + 7) / 8; |
18397944 | 620 | sz = (sz + 7UL) & ~7UL; |
982c2064 | 621 | iommu->arena.map = kzalloc(sz, GFP_KERNEL); |
18397944 | 622 | if (!iommu->arena.map) { |
3822b509 DM |
623 | printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n"); |
624 | return -ENOMEM; | |
18397944 | 625 | } |
18397944 DM |
626 | iommu->arena.limit = num_tsb_entries; |
627 | ||
e7a0453e | 628 | sz = probe_existing_entries(pbm, iommu); |
c2a5a46b DM |
629 | if (sz) |
630 | printk("%s: Imported %lu TSB entries from OBP\n", | |
631 | pbm->name, sz); | |
3822b509 DM |
632 | |
633 | return 0; | |
bade5622 DM |
634 | } |
635 | ||
35a17eb6 DM |
636 | #ifdef CONFIG_PCI_MSI |
637 | struct pci_sun4v_msiq_entry { | |
638 | u64 version_type; | |
639 | #define MSIQ_VERSION_MASK 0xffffffff00000000UL | |
640 | #define MSIQ_VERSION_SHIFT 32 | |
641 | #define MSIQ_TYPE_MASK 0x00000000000000ffUL | |
642 | #define MSIQ_TYPE_SHIFT 0 | |
643 | #define MSIQ_TYPE_NONE 0x00 | |
644 | #define MSIQ_TYPE_MSG 0x01 | |
645 | #define MSIQ_TYPE_MSI32 0x02 | |
646 | #define MSIQ_TYPE_MSI64 0x03 | |
647 | #define MSIQ_TYPE_INTX 0x08 | |
648 | #define MSIQ_TYPE_NONE2 0xff | |
649 | ||
650 | u64 intx_sysino; | |
651 | u64 reserved1; | |
652 | u64 stick; | |
653 | u64 req_id; /* bus/device/func */ | |
654 | #define MSIQ_REQID_BUS_MASK 0xff00UL | |
655 | #define MSIQ_REQID_BUS_SHIFT 8 | |
656 | #define MSIQ_REQID_DEVICE_MASK 0x00f8UL | |
657 | #define MSIQ_REQID_DEVICE_SHIFT 3 | |
658 | #define MSIQ_REQID_FUNC_MASK 0x0007UL | |
659 | #define MSIQ_REQID_FUNC_SHIFT 0 | |
660 | ||
661 | u64 msi_address; | |
662 | ||
e5dd42e4 | 663 | /* The format of this value is message type dependent. |
35a17eb6 DM |
664 | * For MSI bits 15:0 are the data from the MSI packet. |
665 | * For MSI-X bits 31:0 are the data from the MSI packet. | |
666 | * For MSG, the message code and message routing code where: | |
667 | * bits 39:32 is the bus/device/fn of the msg target-id | |
668 | * bits 18:16 is the message routing code | |
669 | * bits 7:0 is the message code | |
670 | * For INTx the low order 2-bits are: | |
671 | * 00 - INTA | |
672 | * 01 - INTB | |
673 | * 10 - INTC | |
674 | * 11 - INTD | |
675 | */ | |
676 | u64 msi_data; | |
677 | ||
678 | u64 reserved2; | |
679 | }; | |
680 | ||
759f89e0 DM |
681 | static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
682 | unsigned long *head) | |
35a17eb6 | 683 | { |
759f89e0 | 684 | unsigned long err, limit; |
35a17eb6 | 685 | |
759f89e0 | 686 | err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head); |
35a17eb6 | 687 | if (unlikely(err)) |
759f89e0 | 688 | return -ENXIO; |
35a17eb6 | 689 | |
759f89e0 DM |
690 | limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); |
691 | if (unlikely(*head >= limit)) | |
692 | return -EFBIG; | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm, | |
698 | unsigned long msiqid, unsigned long *head, | |
699 | unsigned long *msi) | |
700 | { | |
701 | struct pci_sun4v_msiq_entry *ep; | |
702 | unsigned long err, type; | |
703 | ||
704 | /* Note: void pointer arithmetic, 'head' is a byte offset */ | |
705 | ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * | |
706 | (pbm->msiq_ent_count * | |
707 | sizeof(struct pci_sun4v_msiq_entry))) + | |
708 | *head); | |
709 | ||
710 | if ((ep->version_type & MSIQ_TYPE_MASK) == 0) | |
711 | return 0; | |
35a17eb6 | 712 | |
759f89e0 DM |
713 | type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT; |
714 | if (unlikely(type != MSIQ_TYPE_MSI32 && | |
715 | type != MSIQ_TYPE_MSI64)) | |
716 | return -EINVAL; | |
35a17eb6 | 717 | |
759f89e0 DM |
718 | *msi = ep->msi_data; |
719 | ||
720 | err = pci_sun4v_msi_setstate(pbm->devhandle, | |
721 | ep->msi_data /* msi_num */, | |
722 | HV_MSISTATE_IDLE); | |
723 | if (unlikely(err)) | |
724 | return -ENXIO; | |
35a17eb6 | 725 | |
759f89e0 DM |
726 | /* Clear the entry. */ |
727 | ep->version_type &= ~MSIQ_TYPE_MASK; | |
35a17eb6 | 728 | |
759f89e0 DM |
729 | (*head) += sizeof(struct pci_sun4v_msiq_entry); |
730 | if (*head >= | |
731 | (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))) | |
732 | *head = 0; | |
35a17eb6 | 733 | |
759f89e0 | 734 | return 1; |
35a17eb6 DM |
735 | } |
736 | ||
759f89e0 DM |
737 | static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, |
738 | unsigned long head) | |
35a17eb6 | 739 | { |
759f89e0 | 740 | unsigned long err; |
35a17eb6 | 741 | |
759f89e0 DM |
742 | err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head); |
743 | if (unlikely(err)) | |
744 | return -EINVAL; | |
35a17eb6 | 745 | |
759f89e0 DM |
746 | return 0; |
747 | } | |
35a17eb6 | 748 | |
759f89e0 DM |
749 | static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid, |
750 | unsigned long msi, int is_msi64) | |
751 | { | |
752 | if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid, | |
753 | (is_msi64 ? | |
754 | HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32))) | |
755 | return -ENXIO; | |
756 | if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE)) | |
757 | return -ENXIO; | |
758 | if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID)) | |
759 | return -ENXIO; | |
35a17eb6 DM |
760 | return 0; |
761 | } | |
762 | ||
759f89e0 | 763 | static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) |
35a17eb6 | 764 | { |
759f89e0 DM |
765 | unsigned long err, msiqid; |
766 | ||
767 | err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid); | |
768 | if (err) | |
769 | return -ENXIO; | |
770 | ||
771 | pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID); | |
772 | ||
773 | return 0; | |
35a17eb6 DM |
774 | } |
775 | ||
759f89e0 | 776 | static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm) |
35a17eb6 DM |
777 | { |
778 | unsigned long q_size, alloc_size, pages, order; | |
779 | int i; | |
780 | ||
781 | q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); | |
782 | alloc_size = (pbm->msiq_num * q_size); | |
783 | order = get_order(alloc_size); | |
784 | pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order); | |
785 | if (pages == 0UL) { | |
786 | printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n", | |
787 | order); | |
788 | return -ENOMEM; | |
789 | } | |
790 | memset((char *)pages, 0, PAGE_SIZE << order); | |
791 | pbm->msi_queues = (void *) pages; | |
792 | ||
793 | for (i = 0; i < pbm->msiq_num; i++) { | |
794 | unsigned long err, base = __pa(pages + (i * q_size)); | |
795 | unsigned long ret1, ret2; | |
796 | ||
797 | err = pci_sun4v_msiq_conf(pbm->devhandle, | |
798 | pbm->msiq_first + i, | |
799 | base, pbm->msiq_ent_count); | |
800 | if (err) { | |
801 | printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n", | |
802 | err); | |
803 | goto h_error; | |
804 | } | |
805 | ||
806 | err = pci_sun4v_msiq_info(pbm->devhandle, | |
807 | pbm->msiq_first + i, | |
808 | &ret1, &ret2); | |
809 | if (err) { | |
810 | printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n", | |
811 | err); | |
812 | goto h_error; | |
813 | } | |
814 | if (ret1 != base || ret2 != pbm->msiq_ent_count) { | |
815 | printk(KERN_ERR "MSI: Bogus qconf " | |
816 | "expected[%lx:%x] got[%lx:%lx]\n", | |
817 | base, pbm->msiq_ent_count, | |
818 | ret1, ret2); | |
819 | goto h_error; | |
820 | } | |
821 | } | |
822 | ||
823 | return 0; | |
824 | ||
825 | h_error: | |
826 | free_pages(pages, order); | |
827 | return -EINVAL; | |
828 | } | |
829 | ||
759f89e0 | 830 | static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm) |
35a17eb6 | 831 | { |
759f89e0 | 832 | unsigned long q_size, alloc_size, pages, order; |
35a17eb6 DM |
833 | int i; |
834 | ||
759f89e0 DM |
835 | for (i = 0; i < pbm->msiq_num; i++) { |
836 | unsigned long msiqid = pbm->msiq_first + i; | |
35a17eb6 | 837 | |
759f89e0 | 838 | (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0); |
35a17eb6 | 839 | } |
7fe3730d | 840 | |
759f89e0 DM |
841 | q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); |
842 | alloc_size = (pbm->msiq_num * q_size); | |
843 | order = get_order(alloc_size); | |
35a17eb6 | 844 | |
759f89e0 | 845 | pages = (unsigned long) pbm->msi_queues; |
35a17eb6 | 846 | |
759f89e0 | 847 | free_pages(pages, order); |
35a17eb6 | 848 | |
759f89e0 | 849 | pbm->msi_queues = NULL; |
35a17eb6 DM |
850 | } |
851 | ||
759f89e0 DM |
852 | static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm, |
853 | unsigned long msiqid, | |
854 | unsigned long devino) | |
35a17eb6 | 855 | { |
759f89e0 | 856 | unsigned int virt_irq = sun4v_build_irq(pbm->devhandle, devino); |
35a17eb6 | 857 | |
759f89e0 DM |
858 | if (!virt_irq) |
859 | return -ENOMEM; | |
35a17eb6 | 860 | |
759f89e0 DM |
861 | if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE)) |
862 | return -EINVAL; | |
863 | if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID)) | |
864 | return -EINVAL; | |
35a17eb6 | 865 | |
759f89e0 | 866 | return virt_irq; |
35a17eb6 | 867 | } |
e9870c4c | 868 | |
759f89e0 DM |
869 | static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = { |
870 | .get_head = pci_sun4v_get_head, | |
871 | .dequeue_msi = pci_sun4v_dequeue_msi, | |
872 | .set_head = pci_sun4v_set_head, | |
873 | .msi_setup = pci_sun4v_msi_setup, | |
874 | .msi_teardown = pci_sun4v_msi_teardown, | |
875 | .msiq_alloc = pci_sun4v_msiq_alloc, | |
876 | .msiq_free = pci_sun4v_msiq_free, | |
877 | .msiq_build_irq = pci_sun4v_msiq_build_irq, | |
878 | }; | |
879 | ||
e9870c4c DM |
880 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) |
881 | { | |
759f89e0 | 882 | sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops); |
e9870c4c | 883 | } |
35a17eb6 DM |
884 | #else /* CONFIG_PCI_MSI */ |
885 | static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) | |
886 | { | |
887 | } | |
888 | #endif /* !(CONFIG_PCI_MSI) */ | |
889 | ||
3822b509 | 890 | static int __init pci_sun4v_pbm_init(struct pci_controller_info *p, |
e822358a | 891 | struct of_device *op, u32 devhandle) |
bade5622 | 892 | { |
e822358a | 893 | struct device_node *dp = op->node; |
bade5622 | 894 | struct pci_pbm_info *pbm; |
3822b509 | 895 | int err; |
bade5622 | 896 | |
3833789b DM |
897 | if (devhandle & 0x40) |
898 | pbm = &p->pbm_B; | |
899 | else | |
900 | pbm = &p->pbm_A; | |
bade5622 | 901 | |
34768bc8 DM |
902 | pbm->next = pci_pbm_root; |
903 | pci_pbm_root = pbm; | |
904 | ||
c1b1a5f1 DM |
905 | pbm->numa_node = of_node_to_nid(dp); |
906 | ||
ca3dd88e DM |
907 | pbm->pci_ops = &sun4v_pci_ops; |
908 | pbm->config_space_reg_bits = 12; | |
34768bc8 | 909 | |
6c108f12 DM |
910 | pbm->index = pci_num_pbms++; |
911 | ||
bade5622 | 912 | pbm->parent = p; |
e87dc350 | 913 | pbm->prom_node = dp; |
bade5622 | 914 | |
3833789b | 915 | pbm->devhandle = devhandle; |
bade5622 | 916 | |
e87dc350 | 917 | pbm->name = dp->full_name; |
bade5622 | 918 | |
e87dc350 | 919 | printk("%s: SUN4V PCI Bus Module\n", pbm->name); |
c1b1a5f1 | 920 | printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node); |
bade5622 | 921 | |
9fd8b647 | 922 | pci_determine_mem_io_space(pbm); |
bade5622 | 923 | |
cfa0652c | 924 | pci_get_pbm_props(pbm); |
3822b509 DM |
925 | |
926 | err = pci_sun4v_iommu_init(pbm); | |
927 | if (err) | |
928 | return err; | |
929 | ||
35a17eb6 | 930 | pci_sun4v_msi_init(pbm); |
3822b509 | 931 | |
e822358a | 932 | pci_sun4v_scan_bus(pbm, &op->dev); |
3822b509 DM |
933 | |
934 | return 0; | |
bade5622 DM |
935 | } |
936 | ||
3822b509 DM |
937 | static int __devinit pci_sun4v_probe(struct of_device *op, |
938 | const struct of_device_id *match) | |
8f6a93a1 | 939 | { |
3822b509 | 940 | const struct linux_prom64_registers *regs; |
e01c0d6d | 941 | static int hvapi_negotiated = 0; |
bade5622 | 942 | struct pci_controller_info *p; |
34768bc8 | 943 | struct pci_pbm_info *pbm; |
3822b509 | 944 | struct device_node *dp; |
16ce82d8 | 945 | struct iommu *iommu; |
7c8f486a | 946 | u32 devhandle; |
d7472c38 | 947 | int i, err; |
3833789b | 948 | |
3822b509 DM |
949 | dp = op->node; |
950 | ||
e01c0d6d DM |
951 | if (!hvapi_negotiated++) { |
952 | int err = sun4v_hvapi_register(HV_GRP_PCI, | |
953 | vpci_major, | |
954 | &vpci_minor); | |
955 | ||
956 | if (err) { | |
3822b509 DM |
957 | printk(KERN_ERR PFX "Could not register hvapi, " |
958 | "err=%d\n", err); | |
959 | return err; | |
e01c0d6d | 960 | } |
3822b509 | 961 | printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n", |
e01c0d6d | 962 | vpci_major, vpci_minor); |
ad7ad57c DM |
963 | |
964 | dma_ops = &sun4v_dma_ops; | |
e01c0d6d DM |
965 | } |
966 | ||
3822b509 | 967 | regs = of_get_property(dp, "reg", NULL); |
d7472c38 | 968 | err = -ENODEV; |
3822b509 DM |
969 | if (!regs) { |
970 | printk(KERN_ERR PFX "Could not find config registers\n"); | |
d7472c38 | 971 | goto out_err; |
75c6d141 | 972 | } |
e87dc350 | 973 | devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff; |
3833789b | 974 | |
34768bc8 | 975 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { |
0b522497 | 976 | if (pbm->devhandle == (devhandle ^ 0x40)) { |
e822358a | 977 | return pci_sun4v_pbm_init(pbm->parent, op, devhandle); |
0b522497 | 978 | } |
3833789b | 979 | } |
bade5622 | 980 | |
d7472c38 | 981 | err = -ENOMEM; |
a283a525 | 982 | for_each_possible_cpu(i) { |
7c8f486a DM |
983 | unsigned long page = get_zeroed_page(GFP_ATOMIC); |
984 | ||
985 | if (!page) | |
d7472c38 | 986 | goto out_err; |
7c8f486a | 987 | |
ad7ad57c | 988 | per_cpu(iommu_batch, i).pglist = (u64 *) page; |
bade5622 | 989 | } |
7c8f486a | 990 | |
982c2064 | 991 | p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); |
3822b509 DM |
992 | if (!p) { |
993 | printk(KERN_ERR PFX "Could not allocate pci_controller_info\n"); | |
d7472c38 | 994 | goto out_err; |
3822b509 | 995 | } |
7c8f486a | 996 | |
16ce82d8 | 997 | iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); |
3822b509 DM |
998 | if (!iommu) { |
999 | printk(KERN_ERR PFX "Could not allocate pbm A iommu\n"); | |
d7472c38 | 1000 | goto out_free_controller; |
3822b509 | 1001 | } |
7c8f486a | 1002 | |
bade5622 DM |
1003 | p->pbm_A.iommu = iommu; |
1004 | ||
16ce82d8 | 1005 | iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); |
3822b509 DM |
1006 | if (!iommu) { |
1007 | printk(KERN_ERR PFX "Could not allocate pbm B iommu\n"); | |
d7472c38 | 1008 | goto out_free_iommu_A; |
3822b509 | 1009 | } |
7c8f486a | 1010 | |
bade5622 DM |
1011 | p->pbm_B.iommu = iommu; |
1012 | ||
e822358a | 1013 | return pci_sun4v_pbm_init(p, op, devhandle); |
7c8f486a | 1014 | |
d7472c38 DM |
1015 | out_free_iommu_A: |
1016 | kfree(p->pbm_A.iommu); | |
1017 | ||
1018 | out_free_controller: | |
1019 | kfree(p); | |
1020 | ||
1021 | out_err: | |
1022 | return err; | |
8f6a93a1 | 1023 | } |
3822b509 | 1024 | |
fd098316 | 1025 | static struct of_device_id __initdata pci_sun4v_match[] = { |
3822b509 DM |
1026 | { |
1027 | .name = "pci", | |
1028 | .compatible = "SUNW,sun4v-pci", | |
1029 | }, | |
1030 | {}, | |
1031 | }; | |
1032 | ||
1033 | static struct of_platform_driver pci_sun4v_driver = { | |
1034 | .name = DRIVER_NAME, | |
1035 | .match_table = pci_sun4v_match, | |
1036 | .probe = pci_sun4v_probe, | |
1037 | }; | |
1038 | ||
1039 | static int __init pci_sun4v_init(void) | |
1040 | { | |
1041 | return of_register_driver(&pci_sun4v_driver, &of_bus_type); | |
1042 | } | |
1043 | ||
1044 | subsys_initcall(pci_sun4v_init); |