[deliverable/linux.git] / arch / sparc64 / kernel / rtrap.S

/* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#define		RTRAP_PSTATE		(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
#define		RTRAP_PSTATE_IRQOFF	(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
#define		RTRAP_PSTATE_AG_IRQOFF	(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)

		/* Register %l6 keeps track of whether we are returning
		 * from a system call or not.  It is cleared if we call
		 * do_notify_resume, and it must not be otherwise modified
		 * until we fully commit to returning to userspace.
		 */

		.text
		.align			32
__handle_softirq:
		call			do_softirq
		 nop
		ba,a,pt			%xcc, __handle_softirq_continue
		 nop
__handle_preemption:
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		/* Redo sched+sig checks */
		ldx			[%g6 + TI_FLAGS], %l0
		andcc			%l0, _TIF_NEED_RESCHED, %g0

		be,pt			%xcc, 1f
		 nop
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0

1:		andcc			%l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
		be,pt			%xcc, __handle_user_windows_continue
		 nop
		mov			%l5, %o1
		mov			%l6, %o2
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o3

		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		clr			%l6
		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_user_windows_continue

		 andn			%l1, %l4, %l1
__handle_perfctrs:
		call			update_perfctrs
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldub			[%g6 + TI_WSAVED], %o2
		brz,pt			%o2, 1f
		 nop
		/* Redo userwin+sched+sig checks */
		call			fault_in_user_windows

		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, 1f

		 nop
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0
1:		andcc			%l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0

		be,pt			%xcc, __handle_perfctrs_continue
		 sethi			%hi(TSTATE_PEF), %o0
		mov			%l5, %o1
		mov			%l6, %o2
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o3
		call			do_notify_resume

		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		clr			%l6
		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		ba,pt			%xcc, __handle_perfctrs_continue

		 sethi			%hi(TSTATE_PEF), %o0
__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		mov			%l6, %o2
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o3
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		clr			%l6

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_signal_continue
		 andn			%l1, %l4, %l1

		.align			64
		.globl			rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap_clr_l6:	clr			%l6
rtrap:
#ifndef CONFIG_SMP
		sethi			%hi(per_cpu____cpu_data), %l0
		lduw			[%l0 + %lo(per_cpu____cpu_data)], %l1
#else
		sethi			%hi(per_cpu____cpu_data), %l0
		or			%l0, %lo(per_cpu____cpu_data), %l0
		lduw			[%l0 + %g5], %l1
#endif
		cmp			%l1, 0

		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		bne,pn			%icc, __handle_softirq
		 ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
__handle_softirq_continue:
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
#ifdef CONFIG_TRACE_IRQFLAGS
		brnz,pn			%l4, rtrap_no_irq_enable
		 nop
		call			trace_hardirqs_on
		 nop
		wrpr			%l4, %pil
rtrap_no_irq_enable:
#endif
		andcc			%l1, TSTATE_PRIV, %l3
		bne,pn			%icc, to_kernel
		 nop

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.  Note
		 * that we are disabling interrupts via PSTATE_IE, not using
		 * %pil.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with performance
		 * counters or user windows, we have to redo all of these
		 * sched+signal checks with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
		bne,pn			%xcc, __handle_signal
__handle_signal_continue:
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
__handle_user_windows_continue:
		ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_PERFCTR, %g0
		sethi			%hi(TSTATE_PEF), %o0
		bne,pn			%xcc, __handle_perfctrs
__handle_perfctrs_continue:
		 andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		nop
		.section		.sun4v_2insn_patch, "ax"
		.word			661b
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

		wrpr			%l2, %g0, %canrestore
		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
		 wrpr			%g0, %g0, %otherwin

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit

user_rtt_fill_fixup:
		rdpr	%cwp, %g1
		add	%g1, 1, %g1
		wrpr	%g1, 0x0, %cwp

		rdpr	%wstate, %g2
		sll	%g2, 3, %g2
		wrpr	%g2, 0x0, %wstate

		/* We know %canrestore and %otherwin are both zero.  */

		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g2
		mov	PRIMARY_CONTEXT, %g1

661:		stxa	%g2, [%g1] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g2, [%g1] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %g1
		flush	%g1

		or	%g4, FAULT_CODE_WINFIXUP, %g4
		stb	%g4, [%g6 + TI_FAULT_CODE]
		stx	%g5, [%g6 + TI_FAULT_ADDR]

		mov	%g6, %l1
		wrpr	%g0, 0x0, %tl

661:		nop
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		SET_GL(0)
		.previous

		wrpr	%g0, RTRAP_PSTATE, %pstate

		mov	%l1, %g6
		ldx	[%g6 + TI_TASK], %g4
		LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
		call	do_sparc64_fault
		 add	%sp, PTREGS_OFF, %o0
		ba,pt	%xcc, rtrap
		 nop

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 nop
		cmp			%l4, 0
		bne,pn			%xcc, kern_fpucheck
		 sethi			%hi(PREEMPT_ACTIVE), %l6
		stw			%l6, [%g6 + TI_PRE_COUNT]
		call			schedule
		 nop
		ba,pt			%xcc, rtrap
		 stw			%g0, [%g6 + TI_PRE_COUNT]
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
1da177e4 LT	1	/* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
	2	* rtrap.S: Preparing for return from trap on Sparc V9.
	3	*
	4	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	6	*/
	7
1da177e4 LT	8
	9	#include <asm/asi.h>
	10	#include <asm/pstate.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/spitfire.h>
	13	#include <asm/head.h>
	14	#include <asm/visasm.h>
	15	#include <asm/processor.h>
	16
	17	#define RTRAP_PSTATE (PSTATE_RMO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_IE)
	18	#define RTRAP_PSTATE_IRQOFF (PSTATE_RMO\|PSTATE_PEF\|PSTATE_PRIV)
	19	#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_AG)
	20
	21	/* Register %l6 keeps track of whether we are returning
	22	* from a system call or not. It is cleared if we call
	23	* do_notify_resume, and it must not be otherwise modified
	24	* until we fully commit to returning to userspace.
	25	*/
	26
	27	.text
	28	.align 32
	29	__handle_softirq:
	30	call do_softirq
	31	nop
	32	ba,a,pt %xcc, __handle_softirq_continue
	33	nop
	34	__handle_preemption:
	35	call schedule
	36	wrpr %g0, RTRAP_PSTATE, %pstate
	37	ba,pt %xcc, __handle_preemption_continue
	38	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	39
	40	__handle_user_windows:
	41	call fault_in_user_windows
	42	wrpr %g0, RTRAP_PSTATE, %pstate
	43	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	44	/* Redo sched+sig checks */
	45	ldx [%g6 + TI_FLAGS], %l0
	46	andcc %l0, _TIF_NEED_RESCHED, %g0
	47
	48	be,pt %xcc, 1f
	49	nop
	50	call schedule
	51	wrpr %g0, RTRAP_PSTATE, %pstate
	52	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	53	ldx [%g6 + TI_FLAGS], %l0
	54
2d7d5f05	55	1: andcc %l0, (_TIF_SIGPENDING \| _TIF_RESTORE_SIGMASK), %g0
1da177e4 LT	56	be,pt %xcc, __handle_user_windows_continue
1da177e4 LT	57	nop
2d7d5f05 DM	58	mov %l5, %o1
	59	mov %l6, %o2
	60	add %sp, PTREGS_OFF, %o0
	61	mov %l0, %o3
1da177e4 LT	62
	63	call do_notify_resume
	64	wrpr %g0, RTRAP_PSTATE, %pstate
	65	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	66	clr %l6
	67	/* Signal delivery can modify pt_regs tstate, so we must
	68	* reload it.
	69	*/
	70	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	71	sethi %hi(0xf << 20), %l4
	72	and %l1, %l4, %l4
	73	ba,pt %xcc, __handle_user_windows_continue
	74
	75	andn %l1, %l4, %l1
	76	__handle_perfctrs:
	77	call update_perfctrs
	78	wrpr %g0, RTRAP_PSTATE, %pstate
	79	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	80	ldub [%g6 + TI_WSAVED], %o2
	81	brz,pt %o2, 1f
	82	nop
	83	/* Redo userwin+sched+sig checks */
	84	call fault_in_user_windows
	85
	86	wrpr %g0, RTRAP_PSTATE, %pstate
	87	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	88	ldx [%g6 + TI_FLAGS], %l0
	89	andcc %l0, _TIF_NEED_RESCHED, %g0
	90	be,pt %xcc, 1f
	91
	92	nop
	93	call schedule
	94	wrpr %g0, RTRAP_PSTATE, %pstate
	95	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	96	ldx [%g6 + TI_FLAGS], %l0
2d7d5f05	97	1: andcc %l0, (_TIF_SIGPENDING \| _TIF_RESTORE_SIGMASK), %g0
1da177e4 LT	98
	99	be,pt %xcc, __handle_perfctrs_continue
	100	sethi %hi(TSTATE_PEF), %o0
2d7d5f05 DM	101	mov %l5, %o1
	102	mov %l6, %o2
	103	add %sp, PTREGS_OFF, %o0
	104	mov %l0, %o3
1da177e4 LT	105	call do_notify_resume
	106
	107	wrpr %g0, RTRAP_PSTATE, %pstate
	108	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	109	clr %l6
	110	/* Signal delivery can modify pt_regs tstate, so we must
	111	* reload it.
	112	*/
	113	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	114	sethi %hi(0xf << 20), %l4
	115	and %l1, %l4, %l4
	116	andn %l1, %l4, %l1
	117	ba,pt %xcc, __handle_perfctrs_continue
	118
	119	sethi %hi(TSTATE_PEF), %o0
	120	__handle_userfpu:
	121	rd %fprs, %l5
	122	andcc %l5, FPRS_FEF, %g0
	123	sethi %hi(TSTATE_PEF), %o0
	124	be,a,pn %icc, __handle_userfpu_continue
	125	andn %l1, %o0, %l1
	126	ba,a,pt %xcc, __handle_userfpu_continue
	127
	128	__handle_signal:
2d7d5f05 DM	129	mov %l5, %o1
	130	mov %l6, %o2
	131	add %sp, PTREGS_OFF, %o0
	132	mov %l0, %o3
1da177e4 LT	133	call do_notify_resume
	134	wrpr %g0, RTRAP_PSTATE, %pstate
	135	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	136	clr %l6
	137
	138	/* Signal delivery can modify pt_regs tstate, so we must
	139	* reload it.
	140	*/
	141	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	142	sethi %hi(0xf << 20), %l4
	143	and %l1, %l4, %l4
	144	ba,pt %xcc, __handle_signal_continue
	145	andn %l1, %l4, %l1
	146
	147	.align 64
	148	.globl rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
	149	rtrap_irq:
	150	rtrap_clr_l6: clr %l6
	151	rtrap:
d7ce78fd DM	152	#ifndef CONFIG_SMP
	153	sethi %hi(per_cpu____cpu_data), %l0
	154	lduw [%l0 + %lo(per_cpu____cpu_data)], %l1
	155	#else
	156	sethi %hi(per_cpu____cpu_data), %l0
	157	or %l0, %lo(per_cpu____cpu_data), %l0
	158	lduw [%l0 + %g5], %l1
	159	#endif
1da177e4 LT	160	cmp %l1, 0
	161
	162	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
	163	bne,pn %icc, __handle_softirq
	164	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	165	__handle_softirq_continue:
	166	rtrap_xcall:
	167	sethi %hi(0xf << 20), %l4
1da177e4	168	and %l1, %l4, %l4
10e26723 DM	169	andn %l1, %l4, %l1
	170	srl %l4, 20, %l4
	171	#ifdef CONFIG_TRACE_IRQFLAGS
	172	brnz,pn %l4, rtrap_no_irq_enable
	173	nop
	174	call trace_hardirqs_on
	175	nop
	176	wrpr %l4, %pil
	177	rtrap_no_irq_enable:
	178	#endif
	179	andcc %l1, TSTATE_PRIV, %l3
1da177e4	180	bne,pn %icc, to_kernel
10e26723	181	nop
1da177e4 LT	182
	183	/* We must hold IRQs off and atomically test schedule+signal
	184	* state, then hold them off all the way back to userspace.
10e26723 DM	185	* If we are returning to kernel, none of this matters. Note
	186	* that we are disabling interrupts via PSTATE_IE, not using
	187	* %pil.
1da177e4 LT	188	*
	189	* If we do not do this, there is a window where we would do
	190	* the tests, later the signal/resched event arrives but we do
	191	* not process it since we are still in kernel mode. It would
	192	* take until the next local IRQ before the signal/resched
	193	* event would be handled.
	194	*
	195	* This also means that if we have to deal with performance
	196	* counters or user windows, we have to redo all of these
	197	* sched+signal checks with IRQs disabled.
	198	*/
	199	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	200	wrpr 0, %pil
	201	__handle_preemption_continue:
	202	ldx [%g6 + TI_FLAGS], %l0
	203	sethi %hi(_TIF_USER_WORK_MASK), %o0
	204	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	205	andcc %l0, %o0, %g0
	206	sethi %hi(TSTATE_PEF), %o0
	207	be,pt %xcc, user_nowork
	208	andcc %l1, %o0, %g0
	209	andcc %l0, _TIF_NEED_RESCHED, %g0
	210	bne,pn %xcc, __handle_preemption
2d7d5f05	211	andcc %l0, (_TIF_SIGPENDING \| _TIF_RESTORE_SIGMASK), %g0
1da177e4 LT	212	bne,pn %xcc, __handle_signal
	213	__handle_signal_continue:
	214	ldub [%g6 + TI_WSAVED], %o2
	215	brnz,pn %o2, __handle_user_windows
	216	nop
	217	__handle_user_windows_continue:
	218	ldx [%g6 + TI_FLAGS], %l5
	219	andcc %l5, _TIF_PERFCTR, %g0
	220	sethi %hi(TSTATE_PEF), %o0
	221	bne,pn %xcc, __handle_perfctrs
	222	__handle_perfctrs_continue:
	223	andcc %l1, %o0, %g0
	224
	225	/* This fpdepth clear is necessary for non-syscall rtraps only */
	226	user_nowork:
	227	bne,pn %xcc, __handle_userfpu
	228	stb %g0, [%g6 + TI_FPDEPTH]
	229	__handle_userfpu_continue:
	230
	231	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	232	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	233
	234	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	235	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	236	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	237	brz,pt %l3, 1f
314981ac DM	238	mov %g6, %l2
314981ac DM	239
56fb4df6	240	/* Must do this before thread reg is clobbered below. */
ffe483d5	241	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	242	1:
74bf4312 DM	243	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	244	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	245
	246	/* Normal globals are restored, go to trap globals. */
	247	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6 DM	248	nop
af02bec6 DM	249	.section .sun4v_2insn_patch, "ax"
936f482a	250	.word 661b
af02bec6	251	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a DM	252	SET_GL(1)
	253	.previous
	254
314981ac DM	255	mov %l2, %g6
314981ac DM	256
1da177e4 LT	257	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	258	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	259
	260	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	261	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	262	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	263	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	264	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	265	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	266	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	267	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	268
	269	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	270	wr %o3, %g0, %y
1da177e4 LT	271	wrpr %l4, 0x0, %pil
	272	wrpr %g0, 0x1, %tl
	273	wrpr %l1, %g0, %tstate
	274	wrpr %l2, %g0, %tpc
	275	wrpr %o2, %g0, %tnpc
	276
	277	brnz,pn %l3, kern_rtt
	278	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	279
	280	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	281	.section .sun4v_1insn_patch, "ax"
	282	.word 661b
	283	ldxa [%l7 + %l7] ASI_MMU, %l0
	284	.previous
	285
0835ae0f DM	286	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	287	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	288	or %l0, %l1, %l0
8b11bd12 DM	289
	290	661: stxa %l0, [%l7] ASI_DMMU
	291	.section .sun4v_1insn_patch, "ax"
	292	.word 661b
	293	stxa %l0, [%l7] ASI_MMU
	294	.previous
	295
4da808c3 DM	296	sethi %hi(KERNBASE), %l7
4da808c3 DM	297	flush %l7
1da177e4 LT	298	rdpr %wstate, %l1
	299	rdpr %otherwin, %l2
	300	srl %l1, 3, %l1
	301
	302	wrpr %l2, %g0, %canrestore
	303	wrpr %l1, %g0, %wstate
314ef685 DM	304	brnz,pt %l2, user_rtt_restore
	305	wrpr %g0, %g0, %otherwin
	306
	307	ldx [%g6 + TI_FLAGS], %g3
	308	wr %g0, ASI_AIUP, %asi
	309	rdpr %cwp, %g1
	310	andcc %g3, _TIF_32BIT, %g0
	311	sub %g1, 1, %g1
	312	bne,pt %xcc, user_rtt_fill_32bit
	313	wrpr %g1, %cwp
	314	ba,a,pt %xcc, user_rtt_fill_64bit
	315
	316	user_rtt_fill_fixup:
	317	rdpr %cwp, %g1
	318	add %g1, 1, %g1
	319	wrpr %g1, 0x0, %cwp
	320
	321	rdpr %wstate, %g2
	322	sll %g2, 3, %g2
	323	wrpr %g2, 0x0, %wstate
	324
	325	/* We know %canrestore and %otherwin are both zero. */
	326
	327	sethi %hi(sparc64_kern_pri_context), %g2
	328	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
	329	mov PRIMARY_CONTEXT, %g1
8b11bd12 DM	330
	331	661: stxa %g2, [%g1] ASI_DMMU
	332	.section .sun4v_1insn_patch, "ax"
	333	.word 661b
	334	stxa %g2, [%g1] ASI_MMU
	335	.previous
	336
314ef685 DM	337	sethi %hi(KERNBASE), %g1
	338	flush %g1
	339
	340	or %g4, FAULT_CODE_WINFIXUP, %g4
	341	stb %g4, [%g6 + TI_FAULT_CODE]
	342	stx %g5, [%g6 + TI_FAULT_ADDR]
	343
	344	mov %g6, %l1
	345	wrpr %g0, 0x0, %tl
936f482a DM	346
936f482a DM	347	661: nop
df7d6aec	348	.section .sun4v_1insn_patch, "ax"
936f482a DM	349	.word 661b
	350	SET_GL(0)
	351	.previous
	352
fc504928 DM	353	wrpr %g0, RTRAP_PSTATE, %pstate
fc504928 DM	354
314ef685 DM	355	mov %l1, %g6
	356	ldx [%g6 + TI_TASK], %g4
	357	LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
	358	call do_sparc64_fault
	359	add %sp, PTREGS_OFF, %o0
	360	ba,pt %xcc, rtrap
	361	nop
	362
	363	user_rtt_pre_restore:
	364	add %g1, 1, %g1
	365	wrpr %g1, 0x0, %cwp
	366
	367	user_rtt_restore:
1da177e4 LT	368	restore
	369	rdpr %canrestore, %g1
	370	wrpr %g1, 0x0, %cleanwin
	371	retry
	372	nop
	373
314ef685 DM	374	kern_rtt: rdpr %canrestore, %g1
	375	brz,pn %g1, kern_rtt_fill
	376	nop
	377	kern_rtt_restore:
	378	restore
1da177e4	379	retry
314ef685	380
1da177e4 LT	381	to_kernel:
	382	#ifdef CONFIG_PREEMPT
	383	ldsw [%g6 + TI_PRE_COUNT], %l5
	384	brnz %l5, kern_fpucheck
	385	ldx [%g6 + TI_FLAGS], %l5
	386	andcc %l5, _TIF_NEED_RESCHED, %g0
	387	be,pt %xcc, kern_fpucheck
10e26723 DM	388	nop
10e26723 DM	389	cmp %l4, 0
1da177e4 LT	390	bne,pn %xcc, kern_fpucheck
	391	sethi %hi(PREEMPT_ACTIVE), %l6
	392	stw %l6, [%g6 + TI_PRE_COUNT]
	393	call schedule
	394	nop
	395	ba,pt %xcc, rtrap
	396	stw %g0, [%g6 + TI_PRE_COUNT]
	397	#endif
	398	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	399	brz,pt %l5, rt_continue
	400	srl %l5, 1, %o0
	401	add %g6, TI_FPSAVED, %l6
	402	ldub [%l6 + %o0], %l2
	403	sub %l5, 2, %l5
	404
	405	add %g6, TI_GSR, %o1
	406	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	407	be,pt %icc, 2f
	408	and %l2, FPRS_DL, %l6
	409	andcc %l2, FPRS_FEF, %g0
	410	be,pn %icc, 5f
	411	sll %o0, 3, %o5
	412	rd %fprs, %g1
	413
	414	wr %g1, FPRS_FEF, %fprs
	415	ldx [%o1 + %o5], %g1
	416	add %g6, TI_XFSR, %o1
1da177e4 LT	417	sll %o0, 8, %o2
	418	add %g6, TI_FPREGS, %o3
	419	brz,pn %l6, 1f
	420	add %g6, TI_FPREGS+0x40, %o4
	421
ba639933	422	membar #Sync
1da177e4 LT	423	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	424	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	425	membar #Sync
1da177e4 LT	426	1: andcc %l2, FPRS_DU, %g0
	427	be,pn %icc, 1f
	428	wr %g1, 0, %gsr
	429	add %o2, 0x80, %o2
ba639933	430	membar #Sync
1da177e4 LT	431	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	432	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	433	1: membar #Sync
	434	ldx [%o1 + %o5], %fsr
	435	2: stb %l5, [%g6 + TI_FPDEPTH]
	436	ba,pt %xcc, rt_continue
	437	nop
	438	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	439	sll %o0, 8, %o2
	440
	441	add %g6, TI_FPREGS+0x80, %o3
	442	add %g6, TI_FPREGS+0xc0, %o4
ba639933	443	membar #Sync
1da177e4 LT	444	ldda [%o3 + %o2] ASI_BLK_P, %f32
	445	ldda [%o4 + %o2] ASI_BLK_P, %f48
	446	membar #Sync
	447	wr %g0, FPRS_DU, %fprs
	448	ba,pt %xcc, rt_continue
	449	stb %l5, [%g6 + TI_FPDEPTH]