[deliverable/linux.git] / arch / sparc64 / kernel / rtrap.S

/* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */

#include <linux/config.h>

#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#define		RTRAP_PSTATE		(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
#define		RTRAP_PSTATE_IRQOFF	(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
#define		RTRAP_PSTATE_AG_IRQOFF	(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)

		/* Register %l6 keeps track of whether we are returning
		 * from a system call or not.  It is cleared if we call
		 * do_notify_resume, and it must not be otherwise modified
		 * until we fully commit to returning to userspace.
		 */

		.text
		.align			32
__handle_softirq:
		call			do_softirq
		 nop
		ba,a,pt			%xcc, __handle_softirq_continue
		 nop
__handle_preemption:
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		/* Redo sched+sig checks */
		ldx			[%g6 + TI_FLAGS], %l0
		andcc			%l0, _TIF_NEED_RESCHED, %g0

		be,pt			%xcc, 1f
		 nop
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0

1:		andcc			%l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
		be,pt			%xcc, __handle_user_windows_continue
		 nop
		mov			%l5, %o1
		mov			%l6, %o2
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o3

		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		clr			%l6
		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_user_windows_continue

		 andn			%l1, %l4, %l1
__handle_perfctrs:
		call			update_perfctrs
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldub			[%g6 + TI_WSAVED], %o2
		brz,pt			%o2, 1f
		 nop
		/* Redo userwin+sched+sig checks */
		call			fault_in_user_windows

		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, 1f

		 nop
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0
1:		andcc			%l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0

		be,pt			%xcc, __handle_perfctrs_continue
		 sethi			%hi(TSTATE_PEF), %o0
		mov			%l5, %o1
		mov			%l6, %o2
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o3
		call			do_notify_resume

		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		clr			%l6
		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		ba,pt			%xcc, __handle_perfctrs_continue

		 sethi			%hi(TSTATE_PEF), %o0
__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		mov			%l6, %o2
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o3
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		clr			%l6

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_signal_continue
		 andn			%l1, %l4, %l1

		.align			64
		.globl			rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap_clr_l6:	clr			%l6
rtrap:
#ifndef CONFIG_SMP
		sethi			%hi(per_cpu____cpu_data), %l0
		lduw			[%l0 + %lo(per_cpu____cpu_data)], %l1
#else
		sethi			%hi(per_cpu____cpu_data), %l0
		or			%l0, %lo(per_cpu____cpu_data), %l0
		lduw			[%l0 + %g5], %l1
#endif
		cmp			%l1, 0

		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		bne,pn			%icc, __handle_softirq
		 ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
__handle_softirq_continue:
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		andcc			%l1, TSTATE_PRIV, %l3
		and			%l1, %l4, %l4
		bne,pn			%icc, to_kernel
		 andn			%l1, %l4, %l1

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with performance
		 * counters or user windows, we have to redo all of these
		 * sched+signal checks with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
		bne,pn			%xcc, __handle_signal
__handle_signal_continue:
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
__handle_user_windows_continue:
		ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_PERFCTR, %g0
		sethi			%hi(TSTATE_PEF), %o0
		bne,pn			%xcc, __handle_perfctrs
__handle_perfctrs_continue:
		 andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		srl			%l4, 20, %l4
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

		wrpr			%l2, %g0, %canrestore
		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
		 wrpr			%g0, %g0, %otherwin

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit

user_rtt_fill_fixup:
		rdpr	%cwp, %g1
		add	%g1, 1, %g1
		wrpr	%g1, 0x0, %cwp

		rdpr	%wstate, %g2
		sll	%g2, 3, %g2
		wrpr	%g2, 0x0, %wstate

		/* We know %canrestore and %otherwin are both zero.  */

		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g2
		mov	PRIMARY_CONTEXT, %g1

661:		stxa	%g2, [%g1] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g2, [%g1] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %g1
		flush	%g1

		or	%g4, FAULT_CODE_WINFIXUP, %g4
		stb	%g4, [%g6 + TI_FAULT_CODE]
		stx	%g5, [%g6 + TI_FAULT_ADDR]

		mov	%g6, %l1
		wrpr	%g0, 0x0, %tl
		wrpr	%g0, RTRAP_PSTATE, %pstate

661:		nop
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		SET_GL(0)
		.previous

		mov	%l1, %g6
		ldx	[%g6 + TI_TASK], %g4
		LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
		call	do_sparc64_fault
		 add	%sp, PTREGS_OFF, %o0
		ba,pt	%xcc, rtrap
		 nop

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 srl			%l4, 20, %l5
		cmp			%l5, 0
		bne,pn			%xcc, kern_fpucheck
		 sethi			%hi(PREEMPT_ACTIVE), %l6
		stw			%l6, [%g6 + TI_PRE_COUNT]
		call			schedule
		 nop
		ba,pt			%xcc, rtrap
		 stw			%g0, [%g6 + TI_PRE_COUNT]
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
1da177e4 LT	1	/* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
	2	* rtrap.S: Preparing for return from trap on Sparc V9.
	3	*
	4	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	6	*/
	7
	8	#include <linux/config.h>
	9
	10	#include <asm/asi.h>
	11	#include <asm/pstate.h>
	12	#include <asm/ptrace.h>
	13	#include <asm/spitfire.h>
	14	#include <asm/head.h>
	15	#include <asm/visasm.h>
	16	#include <asm/processor.h>
	17
	18	#define RTRAP_PSTATE (PSTATE_RMO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_IE)
	19	#define RTRAP_PSTATE_IRQOFF (PSTATE_RMO\|PSTATE_PEF\|PSTATE_PRIV)
	20	#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_AG)
	21
	22	/* Register %l6 keeps track of whether we are returning
	23	* from a system call or not. It is cleared if we call
	24	* do_notify_resume, and it must not be otherwise modified
	25	* until we fully commit to returning to userspace.
	26	*/
	27
	28	.text
	29	.align 32
	30	__handle_softirq:
	31	call do_softirq
	32	nop
	33	ba,a,pt %xcc, __handle_softirq_continue
	34	nop
	35	__handle_preemption:
	36	call schedule
	37	wrpr %g0, RTRAP_PSTATE, %pstate
	38	ba,pt %xcc, __handle_preemption_continue
	39	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	40
	41	__handle_user_windows:
	42	call fault_in_user_windows
	43	wrpr %g0, RTRAP_PSTATE, %pstate
	44	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	45	/* Redo sched+sig checks */
	46	ldx [%g6 + TI_FLAGS], %l0
	47	andcc %l0, _TIF_NEED_RESCHED, %g0
	48
	49	be,pt %xcc, 1f
	50	nop
	51	call schedule
	52	wrpr %g0, RTRAP_PSTATE, %pstate
	53	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	54	ldx [%g6 + TI_FLAGS], %l0
	55
2d7d5f05	56	1: andcc %l0, (_TIF_SIGPENDING \| _TIF_RESTORE_SIGMASK), %g0
1da177e4 LT	57	be,pt %xcc, __handle_user_windows_continue
1da177e4 LT	58	nop
2d7d5f05 DM	59	mov %l5, %o1
	60	mov %l6, %o2
	61	add %sp, PTREGS_OFF, %o0
	62	mov %l0, %o3
1da177e4 LT	63
	64	call do_notify_resume
	65	wrpr %g0, RTRAP_PSTATE, %pstate
	66	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	67	clr %l6
	68	/* Signal delivery can modify pt_regs tstate, so we must
	69	* reload it.
	70	*/
	71	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	72	sethi %hi(0xf << 20), %l4
	73	and %l1, %l4, %l4
	74	ba,pt %xcc, __handle_user_windows_continue
	75
	76	andn %l1, %l4, %l1
	77	__handle_perfctrs:
	78	call update_perfctrs
	79	wrpr %g0, RTRAP_PSTATE, %pstate
	80	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	81	ldub [%g6 + TI_WSAVED], %o2
	82	brz,pt %o2, 1f
	83	nop
	84	/* Redo userwin+sched+sig checks */
	85	call fault_in_user_windows
	86
	87	wrpr %g0, RTRAP_PSTATE, %pstate
	88	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	89	ldx [%g6 + TI_FLAGS], %l0
	90	andcc %l0, _TIF_NEED_RESCHED, %g0
	91	be,pt %xcc, 1f
	92
	93	nop
	94	call schedule
	95	wrpr %g0, RTRAP_PSTATE, %pstate
	96	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	97	ldx [%g6 + TI_FLAGS], %l0
2d7d5f05	98	1: andcc %l0, (_TIF_SIGPENDING \| _TIF_RESTORE_SIGMASK), %g0
1da177e4 LT	99
	100	be,pt %xcc, __handle_perfctrs_continue
	101	sethi %hi(TSTATE_PEF), %o0
2d7d5f05 DM	102	mov %l5, %o1
	103	mov %l6, %o2
	104	add %sp, PTREGS_OFF, %o0
	105	mov %l0, %o3
1da177e4 LT	106	call do_notify_resume
	107
	108	wrpr %g0, RTRAP_PSTATE, %pstate
	109	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	110	clr %l6
	111	/* Signal delivery can modify pt_regs tstate, so we must
	112	* reload it.
	113	*/
	114	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	115	sethi %hi(0xf << 20), %l4
	116	and %l1, %l4, %l4
	117	andn %l1, %l4, %l1
	118	ba,pt %xcc, __handle_perfctrs_continue
	119
	120	sethi %hi(TSTATE_PEF), %o0
	121	__handle_userfpu:
	122	rd %fprs, %l5
	123	andcc %l5, FPRS_FEF, %g0
	124	sethi %hi(TSTATE_PEF), %o0
	125	be,a,pn %icc, __handle_userfpu_continue
	126	andn %l1, %o0, %l1
	127	ba,a,pt %xcc, __handle_userfpu_continue
	128
	129	__handle_signal:
2d7d5f05 DM	130	mov %l5, %o1
	131	mov %l6, %o2
	132	add %sp, PTREGS_OFF, %o0
	133	mov %l0, %o3
1da177e4 LT	134	call do_notify_resume
	135	wrpr %g0, RTRAP_PSTATE, %pstate
	136	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	137	clr %l6
	138
	139	/* Signal delivery can modify pt_regs tstate, so we must
	140	* reload it.
	141	*/
	142	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	143	sethi %hi(0xf << 20), %l4
	144	and %l1, %l4, %l4
	145	ba,pt %xcc, __handle_signal_continue
	146	andn %l1, %l4, %l1
	147
	148	.align 64
	149	.globl rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
	150	rtrap_irq:
	151	rtrap_clr_l6: clr %l6
	152	rtrap:
d7ce78fd DM	153	#ifndef CONFIG_SMP
	154	sethi %hi(per_cpu____cpu_data), %l0
	155	lduw [%l0 + %lo(per_cpu____cpu_data)], %l1
	156	#else
	157	sethi %hi(per_cpu____cpu_data), %l0
	158	or %l0, %lo(per_cpu____cpu_data), %l0
	159	lduw [%l0 + %g5], %l1
	160	#endif
1da177e4 LT	161	cmp %l1, 0
	162
	163	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
	164	bne,pn %icc, __handle_softirq
	165	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	166	__handle_softirq_continue:
	167	rtrap_xcall:
	168	sethi %hi(0xf << 20), %l4
	169	andcc %l1, TSTATE_PRIV, %l3
	170	and %l1, %l4, %l4
	171	bne,pn %icc, to_kernel
	172	andn %l1, %l4, %l1
	173
	174	/* We must hold IRQs off and atomically test schedule+signal
	175	* state, then hold them off all the way back to userspace.
	176	* If we are returning to kernel, none of this matters.
	177	*
	178	* If we do not do this, there is a window where we would do
	179	* the tests, later the signal/resched event arrives but we do
	180	* not process it since we are still in kernel mode. It would
	181	* take until the next local IRQ before the signal/resched
	182	* event would be handled.
	183	*
	184	* This also means that if we have to deal with performance
	185	* counters or user windows, we have to redo all of these
	186	* sched+signal checks with IRQs disabled.
	187	*/
	188	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	189	wrpr 0, %pil
	190	__handle_preemption_continue:
	191	ldx [%g6 + TI_FLAGS], %l0
	192	sethi %hi(_TIF_USER_WORK_MASK), %o0
	193	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	194	andcc %l0, %o0, %g0
	195	sethi %hi(TSTATE_PEF), %o0
	196	be,pt %xcc, user_nowork
	197	andcc %l1, %o0, %g0
	198	andcc %l0, _TIF_NEED_RESCHED, %g0
	199	bne,pn %xcc, __handle_preemption
2d7d5f05	200	andcc %l0, (_TIF_SIGPENDING \| _TIF_RESTORE_SIGMASK), %g0
1da177e4 LT	201	bne,pn %xcc, __handle_signal
	202	__handle_signal_continue:
	203	ldub [%g6 + TI_WSAVED], %o2
	204	brnz,pn %o2, __handle_user_windows
	205	nop
	206	__handle_user_windows_continue:
	207	ldx [%g6 + TI_FLAGS], %l5
	208	andcc %l5, _TIF_PERFCTR, %g0
	209	sethi %hi(TSTATE_PEF), %o0
	210	bne,pn %xcc, __handle_perfctrs
	211	__handle_perfctrs_continue:
	212	andcc %l1, %o0, %g0
	213
	214	/* This fpdepth clear is necessary for non-syscall rtraps only */
	215	user_nowork:
	216	bne,pn %xcc, __handle_userfpu
	217	stb %g0, [%g6 + TI_FPDEPTH]
	218	__handle_userfpu_continue:
	219
	220	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	221	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	222
	223	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	224	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	225	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	226	brz,pt %l3, 1f
314981ac DM	227	mov %g6, %l2
314981ac DM	228
56fb4df6	229	/* Must do this before thread reg is clobbered below. */
ffe483d5	230	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	231	1:
74bf4312 DM	232	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	233	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	234
	235	/* Normal globals are restored, go to trap globals. */
	236	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
df7d6aec	237	.section .sun4v_1insn_patch, "ax"
936f482a DM	238	.word 661b
	239	SET_GL(1)
	240	.previous
	241
314981ac DM	242	mov %l2, %g6
314981ac DM	243
1da177e4 LT	244	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	245	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	246
	247	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	248	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	249	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	250	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	251	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	252	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	253	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	254	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	255
	256	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	257	wr %o3, %g0, %y
	258	srl %l4, 20, %l4
	259	wrpr %l4, 0x0, %pil
	260	wrpr %g0, 0x1, %tl
	261	wrpr %l1, %g0, %tstate
	262	wrpr %l2, %g0, %tpc
	263	wrpr %o2, %g0, %tnpc
	264
	265	brnz,pn %l3, kern_rtt
	266	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	267
	268	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	269	.section .sun4v_1insn_patch, "ax"
	270	.word 661b
	271	ldxa [%l7 + %l7] ASI_MMU, %l0
	272	.previous
	273
0835ae0f DM	274	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	275	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	276	or %l0, %l1, %l0
8b11bd12 DM	277
	278	661: stxa %l0, [%l7] ASI_DMMU
	279	.section .sun4v_1insn_patch, "ax"
	280	.word 661b
	281	stxa %l0, [%l7] ASI_MMU
	282	.previous
	283
4da808c3 DM	284	sethi %hi(KERNBASE), %l7
4da808c3 DM	285	flush %l7
1da177e4 LT	286	rdpr %wstate, %l1
	287	rdpr %otherwin, %l2
	288	srl %l1, 3, %l1
	289
	290	wrpr %l2, %g0, %canrestore
	291	wrpr %l1, %g0, %wstate
314ef685 DM	292	brnz,pt %l2, user_rtt_restore
	293	wrpr %g0, %g0, %otherwin
	294
	295	ldx [%g6 + TI_FLAGS], %g3
	296	wr %g0, ASI_AIUP, %asi
	297	rdpr %cwp, %g1
	298	andcc %g3, _TIF_32BIT, %g0
	299	sub %g1, 1, %g1
	300	bne,pt %xcc, user_rtt_fill_32bit
	301	wrpr %g1, %cwp
	302	ba,a,pt %xcc, user_rtt_fill_64bit
	303
	304	user_rtt_fill_fixup:
	305	rdpr %cwp, %g1
	306	add %g1, 1, %g1
	307	wrpr %g1, 0x0, %cwp
	308
	309	rdpr %wstate, %g2
	310	sll %g2, 3, %g2
	311	wrpr %g2, 0x0, %wstate
	312
	313	/* We know %canrestore and %otherwin are both zero. */
	314
	315	sethi %hi(sparc64_kern_pri_context), %g2
	316	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
	317	mov PRIMARY_CONTEXT, %g1
8b11bd12 DM	318
	319	661: stxa %g2, [%g1] ASI_DMMU
	320	.section .sun4v_1insn_patch, "ax"
	321	.word 661b
	322	stxa %g2, [%g1] ASI_MMU
	323	.previous
	324
314ef685 DM	325	sethi %hi(KERNBASE), %g1
	326	flush %g1
	327
	328	or %g4, FAULT_CODE_WINFIXUP, %g4
	329	stb %g4, [%g6 + TI_FAULT_CODE]
	330	stx %g5, [%g6 + TI_FAULT_ADDR]
	331
	332	mov %g6, %l1
	333	wrpr %g0, 0x0, %tl
	334	wrpr %g0, RTRAP_PSTATE, %pstate
936f482a DM	335
936f482a DM	336	661: nop
df7d6aec	337	.section .sun4v_1insn_patch, "ax"
936f482a DM	338	.word 661b
	339	SET_GL(0)
	340	.previous
	341
314ef685 DM	342	mov %l1, %g6
	343	ldx [%g6 + TI_TASK], %g4
	344	LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
	345	call do_sparc64_fault
	346	add %sp, PTREGS_OFF, %o0
	347	ba,pt %xcc, rtrap
	348	nop
	349
	350	user_rtt_pre_restore:
	351	add %g1, 1, %g1
	352	wrpr %g1, 0x0, %cwp
	353
	354	user_rtt_restore:
1da177e4 LT	355	restore
	356	rdpr %canrestore, %g1
	357	wrpr %g1, 0x0, %cleanwin
	358	retry
	359	nop
	360
314ef685 DM	361	kern_rtt: rdpr %canrestore, %g1
	362	brz,pn %g1, kern_rtt_fill
	363	nop
	364	kern_rtt_restore:
	365	restore
1da177e4	366	retry
314ef685	367
1da177e4 LT	368	to_kernel:
	369	#ifdef CONFIG_PREEMPT
	370	ldsw [%g6 + TI_PRE_COUNT], %l5
	371	brnz %l5, kern_fpucheck
	372	ldx [%g6 + TI_FLAGS], %l5
	373	andcc %l5, _TIF_NEED_RESCHED, %g0
	374	be,pt %xcc, kern_fpucheck
	375	srl %l4, 20, %l5
	376	cmp %l5, 0
	377	bne,pn %xcc, kern_fpucheck
	378	sethi %hi(PREEMPT_ACTIVE), %l6
	379	stw %l6, [%g6 + TI_PRE_COUNT]
	380	call schedule
	381	nop
	382	ba,pt %xcc, rtrap
	383	stw %g0, [%g6 + TI_PRE_COUNT]
	384	#endif
	385	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	386	brz,pt %l5, rt_continue
	387	srl %l5, 1, %o0
	388	add %g6, TI_FPSAVED, %l6
	389	ldub [%l6 + %o0], %l2
	390	sub %l5, 2, %l5
	391
	392	add %g6, TI_GSR, %o1
	393	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	394	be,pt %icc, 2f
	395	and %l2, FPRS_DL, %l6
	396	andcc %l2, FPRS_FEF, %g0
	397	be,pn %icc, 5f
	398	sll %o0, 3, %o5
	399	rd %fprs, %g1
	400
	401	wr %g1, FPRS_FEF, %fprs
	402	ldx [%o1 + %o5], %g1
	403	add %g6, TI_XFSR, %o1
1da177e4 LT	404	sll %o0, 8, %o2
	405	add %g6, TI_FPREGS, %o3
	406	brz,pn %l6, 1f
	407	add %g6, TI_FPREGS+0x40, %o4
	408
ba639933	409	membar #Sync
1da177e4 LT	410	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	411	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	412	membar #Sync
1da177e4 LT	413	1: andcc %l2, FPRS_DU, %g0
	414	be,pn %icc, 1f
	415	wr %g1, 0, %gsr
	416	add %o2, 0x80, %o2
ba639933	417	membar #Sync
1da177e4 LT	418	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	419	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	420	1: membar #Sync
	421	ldx [%o1 + %o5], %fsr
	422	2: stb %l5, [%g6 + TI_FPDEPTH]
	423	ba,pt %xcc, rt_continue
	424	nop
	425	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	426	sll %o0, 8, %o2
	427
	428	add %g6, TI_FPREGS+0x80, %o3
	429	add %g6, TI_FPREGS+0xc0, %o4
ba639933	430	membar #Sync
1da177e4 LT	431	ldda [%o3 + %o2] ASI_BLK_P, %f32
	432	ldda [%o4 + %o2] ASI_BLK_P, %f48
	433	membar #Sync
	434	wr %g0, FPRS_DU, %fprs
	435	ba,pt %xcc, rt_continue
	436	stb %l5, [%g6 + TI_FPDEPTH]