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sparc: Add OF archdata propagation helper.
[deliverable/linux.git] / arch / sparc64 / kernel / sbus.c
CommitLineData
b00dc837 1/*
1da177e4
LT		 2 * sbus.c: UltraSparc SBUS controller support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7#include <linux/kernel.h>
8#include <linux/types.h>
9#include <linux/mm.h>
10#include <linux/spinlock.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14
15#include <asm/page.h>
16#include <asm/sbus.h>
17#include <asm/io.h>
18#include <asm/upa.h>
19#include <asm/cache.h>
20#include <asm/dma.h>
21#include <asm/irq.h>
25c7581b 22#include <asm/prom.h>
1da177e4
LT		 23#include <asm/starfire.h>
24
25#include "iommu_common.h"
26
1da177e4
LT		 27#define MAP_BASE ((u32)0xc0000000)
28
1da177e4
LT		 29/* Offsets from iommu_regs */
30#define SYSIO_IOMMUREG_BASE 0x2400UL
31#define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
32#define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
33#define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
34#define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
35#define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
36#define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
37#define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
38#define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
39
40#define IOMMU_DRAM_VALID (1UL << 30UL)
41
1da177e4
LT		 42/* Offsets from strbuf_regs */
43#define SYSIO_STRBUFREG_BASE 0x2800UL
44#define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
45#define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
46#define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
47#define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
48#define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
49#define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
50#define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
51
52#define STRBUF_TAG_VALID 0x02UL
53
1da177e4 54/* Enable 64-bit DVMA mode for the given device. */
63237eeb 55void sbus_set_sbus64(struct device *dev, int bursts)
1da177e4 56{
63237eeb
DM		 57 struct iommu *iommu = dev->archdata.iommu;
58 struct of_device *op = to_of_device(dev);
59 const struct linux_prom_registers *regs;
1da177e4 60 unsigned long cfg_reg;
63237eeb 61 int slot;
1da177e4
LT		 62 u64 val;
63
63237eeb
DM		 64 regs = of_get_property(op->node, "reg", NULL);
65 if (!regs) {
66 printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n",
67 op->node->full_name);
68 return;
69 }
70 slot = regs->which_io;
71
3e4d2650 72 cfg_reg = iommu->write_complete_reg;
1da177e4
LT		 73 switch (slot) {
74 case 0:
75 cfg_reg += 0x20UL;
76 break;
77 case 1:
78 cfg_reg += 0x28UL;
79 break;
80 case 2:
81 cfg_reg += 0x30UL;
82 break;
83 case 3:
84 cfg_reg += 0x38UL;
85 break;
86 case 13:
87 cfg_reg += 0x40UL;
88 break;
89 case 14:
90 cfg_reg += 0x48UL;
91 break;
92 case 15:
93 cfg_reg += 0x50UL;
94 break;
95
96 default:
97 return;
98 };
99
100 val = upa_readq(cfg_reg);
101 if (val & (1UL << 14UL)) {
102 /* Extended transfer mode already enabled. */
103 return;
104 }
105
106 val |= (1UL << 14UL);
107
108 if (bursts & DMA_BURST8)
109 val |= (1UL << 1UL);
110 if (bursts & DMA_BURST16)
111 val |= (1UL << 2UL);
112 if (bursts & DMA_BURST32)
113 val |= (1UL << 3UL);
114 if (bursts & DMA_BURST64)
115 val |= (1UL << 4UL);
116 upa_writeq(val, cfg_reg);
117}
118
1da177e4
LT		 119/* INO number to IMAP register offset for SYSIO external IRQ's.
120 * This should conform to both Sunfire/Wildfire server and Fusion
121 * desktop designs.
122 */
ec4d18f2
DM		 123#define SYSIO_IMAP_SLOT0 0x2c00UL
124#define SYSIO_IMAP_SLOT1 0x2c08UL
125#define SYSIO_IMAP_SLOT2 0x2c10UL
126#define SYSIO_IMAP_SLOT3 0x2c18UL
127#define SYSIO_IMAP_SCSI 0x3000UL
128#define SYSIO_IMAP_ETH 0x3008UL
129#define SYSIO_IMAP_BPP 0x3010UL
130#define SYSIO_IMAP_AUDIO 0x3018UL
131#define SYSIO_IMAP_PFAIL 0x3020UL
132#define SYSIO_IMAP_KMS 0x3028UL
133#define SYSIO_IMAP_FLPY 0x3030UL
134#define SYSIO_IMAP_SHW 0x3038UL
135#define SYSIO_IMAP_KBD 0x3040UL
136#define SYSIO_IMAP_MS 0x3048UL
137#define SYSIO_IMAP_SER 0x3050UL
138#define SYSIO_IMAP_TIM0 0x3060UL
139#define SYSIO_IMAP_TIM1 0x3068UL
140#define SYSIO_IMAP_UE 0x3070UL
141#define SYSIO_IMAP_CE 0x3078UL
142#define SYSIO_IMAP_SBERR 0x3080UL
143#define SYSIO_IMAP_PMGMT 0x3088UL
144#define SYSIO_IMAP_GFX 0x3090UL
145#define SYSIO_IMAP_EUPA 0x3098UL
1da177e4
LT		 146
147#define bogon ((unsigned long) -1)
148static unsigned long sysio_irq_offsets[] = {
149 /* SBUS Slot 0 --> 3, level 1 --> 7 */
150 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
151 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
152 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
153 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
154 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
155 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
156 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
157 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
158
159 /* Onboard devices (not relevant/used on SunFire). */
160 SYSIO_IMAP_SCSI,
161 SYSIO_IMAP_ETH,
162 SYSIO_IMAP_BPP,
163 bogon,
164 SYSIO_IMAP_AUDIO,
165 SYSIO_IMAP_PFAIL,
166 bogon,
167 bogon,
168 SYSIO_IMAP_KMS,
169 SYSIO_IMAP_FLPY,
170 SYSIO_IMAP_SHW,
171 SYSIO_IMAP_KBD,
172 SYSIO_IMAP_MS,
173 SYSIO_IMAP_SER,
174 bogon,
175 bogon,
176 SYSIO_IMAP_TIM0,
177 SYSIO_IMAP_TIM1,
178 bogon,
179 bogon,
180 SYSIO_IMAP_UE,
181 SYSIO_IMAP_CE,
182 SYSIO_IMAP_SBERR,
183 SYSIO_IMAP_PMGMT,
184};
185
186#undef bogon
187
84c1a13a 188#define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
1da177e4
LT		 189
190/* Convert Interrupt Mapping register pointer to associated
191 * Interrupt Clear register pointer, SYSIO specific version.
192 */
193#define SYSIO_ICLR_UNUSED0 0x3400UL
ec4d18f2
DM		 194#define SYSIO_ICLR_SLOT0 0x3408UL
195#define SYSIO_ICLR_SLOT1 0x3448UL
196#define SYSIO_ICLR_SLOT2 0x3488UL
197#define SYSIO_ICLR_SLOT3 0x34c8UL
1da177e4
LT		 198static unsigned long sysio_imap_to_iclr(unsigned long imap)
199{
200 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
201 return imap + diff;
202}
203
204unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
205{
206 struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
ad7ad57c 207 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
3e4d2650 208 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
1da177e4 209 unsigned long imap, iclr;
37cdcd9e 210 int sbus_level = 0;
1da177e4
LT		 211
212 imap = sysio_irq_offsets[ino];
213 if (imap == ((unsigned long)-1)) {
37cdcd9e
DM		 214 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
215 ino);
1da177e4
LT		 216 prom_halt();
217 }
218 imap += reg_base;
219
220 /* SYSIO inconsistency. For external SLOTS, we have to select
221 * the right ICLR register based upon the lower SBUS irq level
222 * bits.
223 */
224 if (ino >= 0x20) {
225 iclr = sysio_imap_to_iclr(imap);
226 } else {
227 int sbus_slot = (ino & 0x18)>>3;
228
229 sbus_level = ino & 0x7;
230
231 switch(sbus_slot) {
232 case 0:
233 iclr = reg_base + SYSIO_ICLR_SLOT0;
234 break;
235 case 1:
236 iclr = reg_base + SYSIO_ICLR_SLOT1;
237 break;
238 case 2:
239 iclr = reg_base + SYSIO_ICLR_SLOT2;
240 break;
241 default:
242 case 3:
243 iclr = reg_base + SYSIO_ICLR_SLOT3;
244 break;
245 };
246
247 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
248 }
e18e2a00 249 return build_irq(sbus_level, iclr, imap);
1da177e4
LT		 250}
251
252/* Error interrupt handling. */
253#define SYSIO_UE_AFSR 0x0030UL
254#define SYSIO_UE_AFAR 0x0038UL
255#define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
256#define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
257#define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
258#define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
259#define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
260#define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
261#define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
262#define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
263#define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
264#define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
265#define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
6d24c8dc 266static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
1da177e4
LT		 267{
268 struct sbus_bus *sbus = dev_id;
ad7ad57c 269 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
3e4d2650 270 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
1da177e4
LT		 271 unsigned long afsr_reg, afar_reg;
272 unsigned long afsr, afar, error_bits;
273 int reported;
274
275 afsr_reg = reg_base + SYSIO_UE_AFSR;
276 afar_reg = reg_base + SYSIO_UE_AFAR;
277
278 /* Latch error status. */
279 afsr = upa_readq(afsr_reg);
280 afar = upa_readq(afar_reg);
281
282 /* Clear primary/secondary error status bits. */
283 error_bits = afsr &
284 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
285 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
286 upa_writeq(error_bits, afsr_reg);
287
288 /* Log the error. */
289 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
290 sbus->portid,
291 (((error_bits & SYSIO_UEAFSR_PPIO) ?
292 "PIO" :
293 ((error_bits & SYSIO_UEAFSR_PDRD) ?
294 "DVMA Read" :
295 ((error_bits & SYSIO_UEAFSR_PDWR) ?
296 "DVMA Write" : "???")))));
297 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
298 sbus->portid,
299 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
300 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
301 (afsr & SYSIO_UEAFSR_MID) >> 37UL);
302 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
303 printk("SYSIO[%x]: Secondary UE errors [", sbus->portid);
304 reported = 0;
305 if (afsr & SYSIO_UEAFSR_SPIO) {
306 reported++;
307 printk("(PIO)");
308 }
309 if (afsr & SYSIO_UEAFSR_SDRD) {
310 reported++;
311 printk("(DVMA Read)");
312 }
313 if (afsr & SYSIO_UEAFSR_SDWR) {
314 reported++;
315 printk("(DVMA Write)");
316 }
317 if (!reported)
318 printk("(none)");
319 printk("]\n");
320
321 return IRQ_HANDLED;
322}
323
324#define SYSIO_CE_AFSR 0x0040UL
325#define SYSIO_CE_AFAR 0x0048UL
326#define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
327#define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
328#define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
329#define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
330#define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
331#define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
332#define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
333#define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
334#define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
335#define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
336#define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
337#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
6d24c8dc 338static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
1da177e4
LT		 339{
340 struct sbus_bus *sbus = dev_id;
ad7ad57c 341 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
3e4d2650 342 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
1da177e4
LT		 343 unsigned long afsr_reg, afar_reg;
344 unsigned long afsr, afar, error_bits;
345 int reported;
346
347 afsr_reg = reg_base + SYSIO_CE_AFSR;
348 afar_reg = reg_base + SYSIO_CE_AFAR;
349
350 /* Latch error status. */
351 afsr = upa_readq(afsr_reg);
352 afar = upa_readq(afar_reg);
353
354 /* Clear primary/secondary error status bits. */
355 error_bits = afsr &
356 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
357 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
358 upa_writeq(error_bits, afsr_reg);
359
360 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
361 sbus->portid,
362 (((error_bits & SYSIO_CEAFSR_PPIO) ?
363 "PIO" :
364 ((error_bits & SYSIO_CEAFSR_PDRD) ?
365 "DVMA Read" :
366 ((error_bits & SYSIO_CEAFSR_PDWR) ?
367 "DVMA Write" : "???")))));
368
369 /* XXX Use syndrome and afar to print out module string just like
370 * XXX UDB CE trap handler does... -DaveM
371 */
372 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
373 sbus->portid,
374 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
375 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
376 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
377 (afsr & SYSIO_CEAFSR_MID) >> 37UL);
378 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
379
380 printk("SYSIO[%x]: Secondary CE errors [", sbus->portid);
381 reported = 0;
382 if (afsr & SYSIO_CEAFSR_SPIO) {
383 reported++;
384 printk("(PIO)");
385 }
386 if (afsr & SYSIO_CEAFSR_SDRD) {
387 reported++;
388 printk("(DVMA Read)");
389 }
390 if (afsr & SYSIO_CEAFSR_SDWR) {
391 reported++;
392 printk("(DVMA Write)");
393 }
394 if (!reported)
395 printk("(none)");
396 printk("]\n");
397
398 return IRQ_HANDLED;
399}
400
401#define SYSIO_SBUS_AFSR 0x2010UL
402#define SYSIO_SBUS_AFAR 0x2018UL
403#define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
404#define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
405#define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
406#define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
407#define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
408#define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
409#define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
410#define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
411#define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
412#define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
413#define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
414#define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
6d24c8dc 415static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
1da177e4
LT		 416{
417 struct sbus_bus *sbus = dev_id;
ad7ad57c 418 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
1da177e4
LT		 419 unsigned long afsr_reg, afar_reg, reg_base;
420 unsigned long afsr, afar, error_bits;
421 int reported;
422
3e4d2650 423 reg_base = iommu->write_complete_reg - 0x2000UL;
1da177e4
LT		 424 afsr_reg = reg_base + SYSIO_SBUS_AFSR;
425 afar_reg = reg_base + SYSIO_SBUS_AFAR;
426
427 afsr = upa_readq(afsr_reg);
428 afar = upa_readq(afar_reg);
429
430 /* Clear primary/secondary error status bits. */
431 error_bits = afsr &
432 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
433 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
434 upa_writeq(error_bits, afsr_reg);
435
436 /* Log the error. */
437 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
438 sbus->portid,
439 (((error_bits & SYSIO_SBAFSR_PLE) ?
440 "Late PIO Error" :
441 ((error_bits & SYSIO_SBAFSR_PTO) ?
442 "Time Out" :
443 ((error_bits & SYSIO_SBAFSR_PBERR) ?
444 "Error Ack" : "???")))),
445 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
446 printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
447 sbus->portid,
448 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
449 (afsr & SYSIO_SBAFSR_MID) >> 37UL);
450 printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
451 printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid);
452 reported = 0;
453 if (afsr & SYSIO_SBAFSR_SLE) {
454 reported++;
455 printk("(Late PIO Error)");
456 }
457 if (afsr & SYSIO_SBAFSR_STO) {
458 reported++;
459 printk("(Time Out)");
460 }
461 if (afsr & SYSIO_SBAFSR_SBERR) {
462 reported++;
463 printk("(Error Ack)");
464 }
465 if (!reported)
466 printk("(none)");
467 printk("]\n");
468
469 /* XXX check iommu/strbuf for further error status XXX */
470
471 return IRQ_HANDLED;
472}
473
474#define ECC_CONTROL 0x0020UL
475#define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
476#define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
477#define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
478
479#define SYSIO_UE_INO 0x34
480#define SYSIO_CE_INO 0x35
481#define SYSIO_SBUSERR_INO 0x36
482
483static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
484{
ad7ad57c 485 struct iommu *iommu = sbus->ofdev.dev.archdata.iommu;
3e4d2650 486 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
1da177e4
LT		 487 unsigned int irq;
488 u64 control;
489
490 irq = sbus_build_irq(sbus, SYSIO_UE_INO);
96a496fd
DM		 491 if (request_irq(irq, sysio_ue_handler, 0,
492 "SYSIO_UE", sbus) < 0) {
1da177e4
LT		 493 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
494 sbus->portid);
495 prom_halt();
496 }
497
498 irq = sbus_build_irq(sbus, SYSIO_CE_INO);
96a496fd
DM		 499 if (request_irq(irq, sysio_ce_handler, 0,
500 "SYSIO_CE", sbus) < 0) {
1da177e4
LT		 501 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
502 sbus->portid);
503 prom_halt();
504 }
505
506 irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO);
96a496fd
DM		 507 if (request_irq(irq, sysio_sbus_error_handler, 0,
508 "SYSIO_SBERR", sbus) < 0) {
1da177e4
LT		 509 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
510 sbus->portid);
511 prom_halt();
512 }
513
514 /* Now turn the error interrupts on and also enable ECC checking. */
515 upa_writeq((SYSIO_ECNTRL_ECCEN |
516 SYSIO_ECNTRL_UEEN |
517 SYSIO_ECNTRL_CEEN),
518 reg_base + ECC_CONTROL);
519
3e4d2650 520 control = upa_readq(iommu->write_complete_reg);
1da177e4 521 control |= 0x100UL; /* SBUS Error Interrupt Enable */
3e4d2650 522 upa_writeq(control, iommu->write_complete_reg);
1da177e4
LT		 523}
524
525/* Boot time initialization. */
576c352e 526static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
1da177e4 527{
6a23acf3 528 const struct linux_prom64_registers *pr;
25c7581b 529 struct device_node *dp;
3e4d2650
DM		 530 struct iommu *iommu;
531 struct strbuf *strbuf;
532 unsigned long regs, reg_base;
1da177e4 533 u64 control;
25c7581b
DM		 534 int i;
535
536 dp = of_find_node_by_phandle(__node);
1da177e4 537
25c7581b 538 sbus->portid = of_getintprop_default(dp, "upa-portid", -1);
1da177e4 539
25c7581b
DM		 540 pr = of_get_property(dp, "reg", NULL);
541 if (!pr) {
ad7ad57c
DM		 542 prom_printf("sbus_iommu_init: Cannot map SYSIO "
543 "control registers.\n");
1da177e4
LT		 544 prom_halt();
545 }
25c7581b 546 regs = pr->phys_addr;
1da177e4 547
ad7ad57c
DM		 548 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
549 if (!iommu)
550 goto fatal_memory_error;
551 strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
552 if (!strbuf)
553 goto fatal_memory_error;
1da177e4 554
ad7ad57c
DM		 555 sbus->ofdev.dev.archdata.iommu = iommu;
556 sbus->ofdev.dev.archdata.stc = strbuf;
c1b1a5f1 557 sbus->ofdev.dev.archdata.numa_node = -1;
1da177e4 558
3e4d2650
DM		 559 reg_base = regs + SYSIO_IOMMUREG_BASE;
560 iommu->iommu_control = reg_base + IOMMU_CONTROL;
561 iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
562 iommu->iommu_flush = reg_base + IOMMU_FLUSH;
ad7ad57c
DM		 563 iommu->iommu_tags = iommu->iommu_control +
564 (IOMMU_TAGDIAG - IOMMU_CONTROL);
1da177e4 565
3e4d2650
DM		 566 reg_base = regs + SYSIO_STRBUFREG_BASE;
567 strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
568 strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
569 strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
570
571 strbuf->strbuf_enabled = 1;
1da177e4 572
3e4d2650
DM		 573 strbuf->strbuf_flushflag = (volatile unsigned long *)
574 ((((unsigned long)&strbuf->__flushflag_buf[0])
575 + 63UL)
576 & ~63UL);
577 strbuf->strbuf_flushflag_pa = (unsigned long)
578 __pa(strbuf->strbuf_flushflag);
1da177e4
LT		 579
580 /* The SYSIO SBUS control register is used for dummy reads
581 * in order to ensure write completion.
582 */
3e4d2650 583 iommu->write_complete_reg = regs + 0x2000UL;
1da177e4 584
1da177e4
LT		 585 printk("SYSIO: UPA portID %x, at %016lx\n",
586 sbus->portid, regs);
587
588 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
c1b1a5f1 589 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
ad7ad57c 590 goto fatal_memory_error;
2f3a2efd 591
3e4d2650 592 control = upa_readq(iommu->iommu_control);
1da177e4
LT		 593 control = ((7UL << 16UL) |
594 (0UL << 2UL) |
595 (1UL << 1UL) |
596 (1UL << 0UL));
3e4d2650 597 upa_writeq(control, iommu->iommu_control);
1da177e4
LT		 598
599 /* Clean out any cruft in the IOMMU using
600 * diagnostic accesses.
601 */
602 for (i = 0; i < 16; i++) {
3e4d2650
DM		 603 unsigned long dram, tag;
604
605 dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
606 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
1da177e4
LT		 607
608 dram += (unsigned long)i * 8UL;
609 tag += (unsigned long)i * 8UL;
610 upa_writeq(0, dram);
611 upa_writeq(0, tag);
612 }
3e4d2650 613 upa_readq(iommu->write_complete_reg);
1da177e4
LT		 614
615 /* Give the TSB to SYSIO. */
3e4d2650 616 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
1da177e4
LT		 617
618 /* Setup streaming buffer, DE=1 SB_EN=1 */
619 control = (1UL << 1UL) | (1UL << 0UL);
3e4d2650 620 upa_writeq(control, strbuf->strbuf_control);
1da177e4
LT		 621
622 /* Clear out the tags using diagnostics. */
623 for (i = 0; i < 16; i++) {
624 unsigned long ptag, ltag;
625
3e4d2650
DM		 626 ptag = strbuf->strbuf_control +
627 (STRBUF_PTAGDIAG - STRBUF_CONTROL);
628 ltag = strbuf->strbuf_control +
629 (STRBUF_LTAGDIAG - STRBUF_CONTROL);
1da177e4
LT		 630 ptag += (unsigned long)i * 8UL;
631 ltag += (unsigned long)i * 8UL;
632
633 upa_writeq(0UL, ptag);
634 upa_writeq(0UL, ltag);
635 }
636
637 /* Enable DVMA arbitration for all devices/slots. */
3e4d2650 638 control = upa_readq(iommu->write_complete_reg);
1da177e4 639 control |= 0x3fUL;
3e4d2650 640 upa_writeq(control, iommu->write_complete_reg);
1da177e4
LT		 641
642 /* Now some Xfire specific grot... */
643 if (this_is_starfire)
286bbe87 644 starfire_hookup(sbus->portid);
1da177e4
LT		 645
646 sysio_register_error_handlers(sbus);
ad7ad57c
DM		 647 return;
648
649fatal_memory_error:
650 prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
1da177e4 651}
8fae097d 652
576c352e
DM		 653void __init sbus_setup_iommu(struct sbus_bus *sbus, struct device_node *dp)
654{
655 sbus_iommu_init(dp->node, sbus);
656}
657
576c352e
DM		 658void __init sbus_arch_postinit(void)
659{
660 extern void firetruck_init(void);
576c352e
DM		 661
662 firetruck_init();
576c352e 663}
Linux kernel - Deliverables
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