Commit | Line | Data |
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1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
3 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/pagemap.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/smp.h> | |
13 | #include <linux/smp_lock.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/kernel_stat.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/cache.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/profile.h> | |
24 | #include <linux/bootmem.h> | |
25 | ||
26 | #include <asm/head.h> | |
27 | #include <asm/ptrace.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/tlbflush.h> | |
30 | #include <asm/mmu_context.h> | |
31 | #include <asm/cpudata.h> | |
32 | ||
33 | #include <asm/irq.h> | |
34 | #include <asm/page.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/oplib.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/timer.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/tlb.h> | |
56fb4df6 | 41 | #include <asm/sections.h> |
1da177e4 | 42 | |
1da177e4 LT |
43 | extern void calibrate_delay(void); |
44 | ||
45 | /* Please don't make this stuff initdata!!! --DaveM */ | |
46 | static unsigned char boot_cpu_id; | |
47 | ||
c12a8289 AM |
48 | cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE; |
49 | cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE; | |
1da177e4 LT |
50 | static cpumask_t smp_commenced_mask; |
51 | static cpumask_t cpu_callout_map; | |
52 | ||
53 | void smp_info(struct seq_file *m) | |
54 | { | |
55 | int i; | |
56 | ||
57 | seq_printf(m, "State:\n"); | |
58 | for (i = 0; i < NR_CPUS; i++) { | |
59 | if (cpu_online(i)) | |
60 | seq_printf(m, | |
61 | "CPU%d:\t\tonline\n", i); | |
62 | } | |
63 | } | |
64 | ||
65 | void smp_bogo(struct seq_file *m) | |
66 | { | |
67 | int i; | |
68 | ||
69 | for (i = 0; i < NR_CPUS; i++) | |
70 | if (cpu_online(i)) | |
71 | seq_printf(m, | |
72 | "Cpu%dBogo\t: %lu.%02lu\n" | |
73 | "Cpu%dClkTck\t: %016lx\n", | |
74 | i, cpu_data(i).udelay_val / (500000/HZ), | |
75 | (cpu_data(i).udelay_val / (5000/HZ)) % 100, | |
76 | i, cpu_data(i).clock_tick); | |
77 | } | |
78 | ||
79 | void __init smp_store_cpu_info(int id) | |
80 | { | |
f03b8a54 | 81 | int cpu_node, def; |
1da177e4 LT |
82 | |
83 | /* multiplier and counter set by | |
84 | smp_setup_percpu_timer() */ | |
85 | cpu_data(id).udelay_val = loops_per_jiffy; | |
86 | ||
87 | cpu_find_by_mid(id, &cpu_node); | |
88 | cpu_data(id).clock_tick = prom_getintdefault(cpu_node, | |
89 | "clock-frequency", 0); | |
90 | ||
f03b8a54 | 91 | def = ((tlb_type == hypervisor) ? (8 * 1024) : (16 * 1024)); |
80dc0d6b | 92 | cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size", |
f03b8a54 DM |
93 | def); |
94 | ||
95 | def = 32; | |
80dc0d6b | 96 | cpu_data(id).dcache_line_size = |
f03b8a54 DM |
97 | prom_getintdefault(cpu_node, "dcache-line-size", def); |
98 | ||
99 | def = 16 * 1024; | |
80dc0d6b | 100 | cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size", |
f03b8a54 DM |
101 | def); |
102 | ||
103 | def = 32; | |
80dc0d6b | 104 | cpu_data(id).icache_line_size = |
f03b8a54 DM |
105 | prom_getintdefault(cpu_node, "icache-line-size", def); |
106 | ||
107 | def = ((tlb_type == hypervisor) ? | |
108 | (3 * 1024 * 1024) : | |
109 | (4 * 1024 * 1024)); | |
80dc0d6b | 110 | cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size", |
f03b8a54 DM |
111 | def); |
112 | ||
113 | def = 64; | |
80dc0d6b | 114 | cpu_data(id).ecache_line_size = |
f03b8a54 DM |
115 | prom_getintdefault(cpu_node, "ecache-line-size", def); |
116 | ||
80dc0d6b DM |
117 | printk("CPU[%d]: Caches " |
118 | "D[sz(%d):line_sz(%d)] " | |
119 | "I[sz(%d):line_sz(%d)] " | |
120 | "E[sz(%d):line_sz(%d)]\n", | |
121 | id, | |
122 | cpu_data(id).dcache_size, cpu_data(id).dcache_line_size, | |
123 | cpu_data(id).icache_size, cpu_data(id).icache_line_size, | |
124 | cpu_data(id).ecache_size, cpu_data(id).ecache_line_size); | |
1da177e4 LT |
125 | } |
126 | ||
127 | static void smp_setup_percpu_timer(void); | |
128 | ||
129 | static volatile unsigned long callin_flag = 0; | |
130 | ||
1da177e4 LT |
131 | void __init smp_callin(void) |
132 | { | |
133 | int cpuid = hard_smp_processor_id(); | |
134 | ||
56fb4df6 | 135 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 136 | |
4a07e646 | 137 | if (tlb_type == hypervisor) |
490384e7 | 138 | sun4v_ktsb_register(); |
481295f9 | 139 | |
56fb4df6 | 140 | __flush_tlb_all(); |
1da177e4 LT |
141 | |
142 | smp_setup_percpu_timer(); | |
143 | ||
816242da DM |
144 | if (cheetah_pcache_forced_on) |
145 | cheetah_enable_pcache(); | |
146 | ||
1da177e4 LT |
147 | local_irq_enable(); |
148 | ||
149 | calibrate_delay(); | |
150 | smp_store_cpu_info(cpuid); | |
151 | callin_flag = 1; | |
152 | __asm__ __volatile__("membar #Sync\n\t" | |
153 | "flush %%g6" : : : "memory"); | |
154 | ||
155 | /* Clear this or we will die instantly when we | |
156 | * schedule back to this idler... | |
157 | */ | |
db7d9a4e | 158 | current_thread_info()->new_child = 0; |
1da177e4 LT |
159 | |
160 | /* Attach to the address space of init_task. */ | |
161 | atomic_inc(&init_mm.mm_count); | |
162 | current->active_mm = &init_mm; | |
163 | ||
164 | while (!cpu_isset(cpuid, smp_commenced_mask)) | |
4f07118f | 165 | rmb(); |
1da177e4 LT |
166 | |
167 | cpu_set(cpuid, cpu_online_map); | |
5bfb5d69 NP |
168 | |
169 | /* idle thread is expected to have preempt disabled */ | |
170 | preempt_disable(); | |
1da177e4 LT |
171 | } |
172 | ||
173 | void cpu_panic(void) | |
174 | { | |
175 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
176 | panic("SMP bolixed\n"); | |
177 | } | |
178 | ||
d369ddd2 | 179 | static unsigned long current_tick_offset __read_mostly; |
1da177e4 LT |
180 | |
181 | /* This tick register synchronization scheme is taken entirely from | |
182 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
183 | * | |
184 | * The only change I've made is to rework it so that the master | |
185 | * initiates the synchonization instead of the slave. -DaveM | |
186 | */ | |
187 | ||
188 | #define MASTER 0 | |
189 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
190 | ||
191 | #define NUM_ROUNDS 64 /* magic value */ | |
192 | #define NUM_ITERS 5 /* likewise */ | |
193 | ||
194 | static DEFINE_SPINLOCK(itc_sync_lock); | |
195 | static unsigned long go[SLAVE + 1]; | |
196 | ||
197 | #define DEBUG_TICK_SYNC 0 | |
198 | ||
199 | static inline long get_delta (long *rt, long *master) | |
200 | { | |
201 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
202 | unsigned long tcenter, t0, t1, tm; | |
203 | unsigned long i; | |
204 | ||
205 | for (i = 0; i < NUM_ITERS; i++) { | |
206 | t0 = tick_ops->get_tick(); | |
207 | go[MASTER] = 1; | |
4f07118f | 208 | membar_storeload(); |
1da177e4 | 209 | while (!(tm = go[SLAVE])) |
4f07118f | 210 | rmb(); |
1da177e4 | 211 | go[SLAVE] = 0; |
4f07118f | 212 | wmb(); |
1da177e4 LT |
213 | t1 = tick_ops->get_tick(); |
214 | ||
215 | if (t1 - t0 < best_t1 - best_t0) | |
216 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
217 | } | |
218 | ||
219 | *rt = best_t1 - best_t0; | |
220 | *master = best_tm - best_t0; | |
221 | ||
222 | /* average best_t0 and best_t1 without overflow: */ | |
223 | tcenter = (best_t0/2 + best_t1/2); | |
224 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
225 | tcenter++; | |
226 | return tcenter - best_tm; | |
227 | } | |
228 | ||
229 | void smp_synchronize_tick_client(void) | |
230 | { | |
231 | long i, delta, adj, adjust_latency = 0, done = 0; | |
232 | unsigned long flags, rt, master_time_stamp, bound; | |
233 | #if DEBUG_TICK_SYNC | |
234 | struct { | |
235 | long rt; /* roundtrip time */ | |
236 | long master; /* master's timestamp */ | |
237 | long diff; /* difference between midpoint and master's timestamp */ | |
238 | long lat; /* estimate of itc adjustment latency */ | |
239 | } t[NUM_ROUNDS]; | |
240 | #endif | |
241 | ||
242 | go[MASTER] = 1; | |
243 | ||
244 | while (go[MASTER]) | |
4f07118f | 245 | rmb(); |
1da177e4 LT |
246 | |
247 | local_irq_save(flags); | |
248 | { | |
249 | for (i = 0; i < NUM_ROUNDS; i++) { | |
250 | delta = get_delta(&rt, &master_time_stamp); | |
251 | if (delta == 0) { | |
252 | done = 1; /* let's lock on to this... */ | |
253 | bound = rt; | |
254 | } | |
255 | ||
256 | if (!done) { | |
257 | if (i > 0) { | |
258 | adjust_latency += -delta; | |
259 | adj = -delta + adjust_latency/4; | |
260 | } else | |
261 | adj = -delta; | |
262 | ||
263 | tick_ops->add_tick(adj, current_tick_offset); | |
264 | } | |
265 | #if DEBUG_TICK_SYNC | |
266 | t[i].rt = rt; | |
267 | t[i].master = master_time_stamp; | |
268 | t[i].diff = delta; | |
269 | t[i].lat = adjust_latency/4; | |
270 | #endif | |
271 | } | |
272 | } | |
273 | local_irq_restore(flags); | |
274 | ||
275 | #if DEBUG_TICK_SYNC | |
276 | for (i = 0; i < NUM_ROUNDS; i++) | |
277 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
278 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
279 | #endif | |
280 | ||
281 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles," | |
282 | "maxerr %lu cycles)\n", smp_processor_id(), delta, rt); | |
283 | } | |
284 | ||
285 | static void smp_start_sync_tick_client(int cpu); | |
286 | ||
287 | static void smp_synchronize_one_tick(int cpu) | |
288 | { | |
289 | unsigned long flags, i; | |
290 | ||
291 | go[MASTER] = 0; | |
292 | ||
293 | smp_start_sync_tick_client(cpu); | |
294 | ||
295 | /* wait for client to be ready */ | |
296 | while (!go[MASTER]) | |
4f07118f | 297 | rmb(); |
1da177e4 LT |
298 | |
299 | /* now let the client proceed into his loop */ | |
300 | go[MASTER] = 0; | |
4f07118f | 301 | membar_storeload(); |
1da177e4 LT |
302 | |
303 | spin_lock_irqsave(&itc_sync_lock, flags); | |
304 | { | |
305 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
306 | while (!go[MASTER]) | |
4f07118f | 307 | rmb(); |
1da177e4 | 308 | go[MASTER] = 0; |
4f07118f | 309 | wmb(); |
1da177e4 | 310 | go[SLAVE] = tick_ops->get_tick(); |
4f07118f | 311 | membar_storeload(); |
1da177e4 LT |
312 | } |
313 | } | |
314 | spin_unlock_irqrestore(&itc_sync_lock, flags); | |
315 | } | |
316 | ||
72aff53f DM |
317 | extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load); |
318 | ||
1da177e4 LT |
319 | extern unsigned long sparc64_cpu_startup; |
320 | ||
321 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
322 | * 32-bits (I think) so to be safe we have it read the pointer | |
323 | * contained here so we work on >4GB machines. -DaveM | |
324 | */ | |
325 | static struct thread_info *cpu_new_thread = NULL; | |
326 | ||
327 | static int __devinit smp_boot_one_cpu(unsigned int cpu) | |
328 | { | |
329 | unsigned long entry = | |
330 | (unsigned long)(&sparc64_cpu_startup); | |
331 | unsigned long cookie = | |
332 | (unsigned long)(&cpu_new_thread); | |
333 | struct task_struct *p; | |
7890f794 | 334 | int timeout, ret; |
1da177e4 LT |
335 | |
336 | p = fork_idle(cpu); | |
337 | callin_flag = 0; | |
f3169641 | 338 | cpu_new_thread = task_thread_info(p); |
1da177e4 LT |
339 | cpu_set(cpu, cpu_callout_map); |
340 | ||
7890f794 | 341 | if (tlb_type == hypervisor) { |
72aff53f DM |
342 | /* Alloc the mondo queues, cpu will load them. */ |
343 | sun4v_init_mondo_queues(0, cpu, 1, 0); | |
344 | ||
7890f794 DM |
345 | prom_startcpu_cpuid(cpu, entry, cookie); |
346 | } else { | |
347 | int cpu_node; | |
348 | ||
349 | cpu_find_by_mid(cpu, &cpu_node); | |
350 | prom_startcpu(cpu_node, entry, cookie); | |
351 | } | |
1da177e4 LT |
352 | |
353 | for (timeout = 0; timeout < 5000000; timeout++) { | |
354 | if (callin_flag) | |
355 | break; | |
356 | udelay(100); | |
357 | } | |
72aff53f | 358 | |
1da177e4 LT |
359 | if (callin_flag) { |
360 | ret = 0; | |
361 | } else { | |
362 | printk("Processor %d is stuck.\n", cpu); | |
363 | cpu_clear(cpu, cpu_callout_map); | |
364 | ret = -ENODEV; | |
365 | } | |
366 | cpu_new_thread = NULL; | |
367 | ||
368 | return ret; | |
369 | } | |
370 | ||
371 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
372 | { | |
373 | u64 result, target; | |
374 | int stuck, tmp; | |
375 | ||
376 | if (this_is_starfire) { | |
377 | /* map to real upaid */ | |
378 | cpu = (((cpu & 0x3c) << 1) | | |
379 | ((cpu & 0x40) >> 4) | | |
380 | (cpu & 0x3)); | |
381 | } | |
382 | ||
383 | target = (cpu << 14) | 0x70; | |
384 | again: | |
385 | /* Ok, this is the real Spitfire Errata #54. | |
386 | * One must read back from a UDB internal register | |
387 | * after writes to the UDB interrupt dispatch, but | |
388 | * before the membar Sync for that write. | |
389 | * So we use the high UDB control register (ASI 0x7f, | |
390 | * ADDR 0x20) for the dummy read. -DaveM | |
391 | */ | |
392 | tmp = 0x40; | |
393 | __asm__ __volatile__( | |
394 | "wrpr %1, %2, %%pstate\n\t" | |
395 | "stxa %4, [%0] %3\n\t" | |
396 | "stxa %5, [%0+%8] %3\n\t" | |
397 | "add %0, %8, %0\n\t" | |
398 | "stxa %6, [%0+%8] %3\n\t" | |
399 | "membar #Sync\n\t" | |
400 | "stxa %%g0, [%7] %3\n\t" | |
401 | "membar #Sync\n\t" | |
402 | "mov 0x20, %%g1\n\t" | |
403 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
404 | "membar #Sync" | |
405 | : "=r" (tmp) | |
406 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
407 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
408 | "r" (0x10), "0" (tmp) | |
409 | : "g1"); | |
410 | ||
411 | /* NOTE: PSTATE_IE is still clear. */ | |
412 | stuck = 100000; | |
413 | do { | |
414 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
415 | : "=r" (result) | |
416 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
417 | if (result == 0) { | |
418 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
419 | : : "r" (pstate)); | |
420 | return; | |
421 | } | |
422 | stuck -= 1; | |
423 | if (stuck == 0) | |
424 | break; | |
425 | } while (result & 0x1); | |
426 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
427 | : : "r" (pstate)); | |
428 | if (stuck == 0) { | |
429 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
430 | smp_processor_id(), result); | |
431 | } else { | |
432 | udelay(2); | |
433 | goto again; | |
434 | } | |
435 | } | |
436 | ||
437 | static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
438 | { | |
439 | u64 pstate; | |
440 | int i; | |
441 | ||
442 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
443 | for_each_cpu_mask(i, mask) | |
444 | spitfire_xcall_helper(data0, data1, data2, pstate, i); | |
445 | } | |
446 | ||
447 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
448 | * packet, but we have no use for that. However we do take advantage of | |
449 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
450 | */ | |
451 | static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
452 | { | |
453 | u64 pstate, ver; | |
92704a1c | 454 | int nack_busy_id, is_jbus; |
1da177e4 LT |
455 | |
456 | if (cpus_empty(mask)) | |
457 | return; | |
458 | ||
459 | /* Unfortunately, someone at Sun had the brilliant idea to make the | |
460 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
461 | * derivative processor. | |
462 | */ | |
463 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
464 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
465 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
466 | |
467 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
468 | ||
469 | retry: | |
470 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" | |
471 | : : "r" (pstate), "i" (PSTATE_IE)); | |
472 | ||
473 | /* Setup the dispatch data registers. */ | |
474 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
475 | "stxa %1, [%4] %6\n\t" | |
476 | "stxa %2, [%5] %6\n\t" | |
477 | "membar #Sync\n\t" | |
478 | : /* no outputs */ | |
479 | : "r" (data0), "r" (data1), "r" (data2), | |
480 | "r" (0x40), "r" (0x50), "r" (0x60), | |
481 | "i" (ASI_INTR_W)); | |
482 | ||
483 | nack_busy_id = 0; | |
484 | { | |
485 | int i; | |
486 | ||
487 | for_each_cpu_mask(i, mask) { | |
488 | u64 target = (i << 14) | 0x70; | |
489 | ||
92704a1c | 490 | if (!is_jbus) |
1da177e4 LT |
491 | target |= (nack_busy_id << 24); |
492 | __asm__ __volatile__( | |
493 | "stxa %%g0, [%0] %1\n\t" | |
494 | "membar #Sync\n\t" | |
495 | : /* no outputs */ | |
496 | : "r" (target), "i" (ASI_INTR_W)); | |
497 | nack_busy_id++; | |
498 | } | |
499 | } | |
500 | ||
501 | /* Now, poll for completion. */ | |
502 | { | |
503 | u64 dispatch_stat; | |
504 | long stuck; | |
505 | ||
506 | stuck = 100000 * nack_busy_id; | |
507 | do { | |
508 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
509 | : "=r" (dispatch_stat) | |
510 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
511 | if (dispatch_stat == 0UL) { | |
512 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
513 | : : "r" (pstate)); | |
514 | return; | |
515 | } | |
516 | if (!--stuck) | |
517 | break; | |
518 | } while (dispatch_stat & 0x5555555555555555UL); | |
519 | ||
520 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
521 | : : "r" (pstate)); | |
522 | ||
523 | if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) { | |
524 | /* Busy bits will not clear, continue instead | |
525 | * of freezing up on this cpu. | |
526 | */ | |
527 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
528 | smp_processor_id(), dispatch_stat); | |
529 | } else { | |
530 | int i, this_busy_nack = 0; | |
531 | ||
532 | /* Delay some random time with interrupts enabled | |
533 | * to prevent deadlock. | |
534 | */ | |
535 | udelay(2 * nack_busy_id); | |
536 | ||
537 | /* Clear out the mask bits for cpus which did not | |
538 | * NACK us. | |
539 | */ | |
540 | for_each_cpu_mask(i, mask) { | |
541 | u64 check_mask; | |
542 | ||
92704a1c | 543 | if (is_jbus) |
1da177e4 LT |
544 | check_mask = (0x2UL << (2*i)); |
545 | else | |
546 | check_mask = (0x2UL << | |
547 | this_busy_nack); | |
548 | if ((dispatch_stat & check_mask) == 0) | |
549 | cpu_clear(i, mask); | |
550 | this_busy_nack += 2; | |
551 | } | |
552 | ||
553 | goto retry; | |
554 | } | |
555 | } | |
556 | } | |
557 | ||
1d2f1f90 DM |
558 | /* Multi-cpu list version. */ |
559 | static int init_cpu_list(u16 *list, cpumask_t mask) | |
560 | { | |
561 | int i, cnt; | |
562 | ||
563 | cnt = 0; | |
564 | for_each_cpu_mask(i, mask) | |
565 | list[cnt++] = i; | |
566 | ||
567 | return cnt; | |
568 | } | |
569 | ||
570 | static int update_cpu_list(u16 *list, int orig_cnt, cpumask_t mask) | |
571 | { | |
572 | int i; | |
573 | ||
574 | for (i = 0; i < orig_cnt; i++) { | |
575 | if (list[i] == 0xffff) | |
576 | cpu_clear(i, mask); | |
577 | } | |
578 | ||
579 | return init_cpu_list(list, mask); | |
580 | } | |
581 | ||
a43fe0e7 DM |
582 | static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) |
583 | { | |
1d2f1f90 DM |
584 | int this_cpu = get_cpu(); |
585 | struct trap_per_cpu *tb = &trap_block[this_cpu]; | |
586 | u64 *mondo = __va(tb->cpu_mondo_block_pa); | |
587 | u16 *cpu_list = __va(tb->cpu_list_pa); | |
588 | int cnt, retries; | |
589 | ||
590 | mondo[0] = data0; | |
591 | mondo[1] = data1; | |
592 | mondo[2] = data2; | |
593 | wmb(); | |
594 | ||
595 | retries = 0; | |
596 | cnt = init_cpu_list(cpu_list, mask); | |
597 | do { | |
164c220f DM |
598 | register unsigned long func __asm__("%o5"); |
599 | register unsigned long arg0 __asm__("%o0"); | |
600 | register unsigned long arg1 __asm__("%o1"); | |
601 | register unsigned long arg2 __asm__("%o2"); | |
1d2f1f90 DM |
602 | |
603 | func = HV_FAST_CPU_MONDO_SEND; | |
604 | arg0 = cnt; | |
605 | arg1 = tb->cpu_list_pa; | |
606 | arg2 = tb->cpu_mondo_block_pa; | |
607 | ||
608 | __asm__ __volatile__("ta %8" | |
609 | : "=&r" (func), "=&r" (arg0), | |
610 | "=&r" (arg1), "=&r" (arg2) | |
611 | : "0" (func), "1" (arg0), | |
612 | "2" (arg1), "3" (arg2), | |
613 | "i" (HV_FAST_TRAP) | |
614 | : "memory"); | |
b5a37e96 | 615 | if (likely(arg0 == HV_EOK)) |
1d2f1f90 DM |
616 | break; |
617 | ||
618 | if (unlikely(++retries > 100)) { | |
619 | printk("CPU[%d]: sun4v mondo error %lu\n", | |
620 | this_cpu, func); | |
621 | break; | |
622 | } | |
623 | ||
624 | cnt = update_cpu_list(cpu_list, cnt, mask); | |
625 | ||
626 | udelay(2 * cnt); | |
627 | } while (1); | |
628 | ||
629 | put_cpu(); | |
630 | } | |
a43fe0e7 | 631 | |
1da177e4 LT |
632 | /* Send cross call to all processors mentioned in MASK |
633 | * except self. | |
634 | */ | |
635 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask) | |
636 | { | |
637 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
638 | int this_cpu = get_cpu(); | |
639 | ||
640 | cpus_and(mask, mask, cpu_online_map); | |
641 | cpu_clear(this_cpu, mask); | |
642 | ||
643 | if (tlb_type == spitfire) | |
644 | spitfire_xcall_deliver(data0, data1, data2, mask); | |
a43fe0e7 | 645 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
1da177e4 | 646 | cheetah_xcall_deliver(data0, data1, data2, mask); |
a43fe0e7 DM |
647 | else |
648 | hypervisor_xcall_deliver(data0, data1, data2, mask); | |
1da177e4 LT |
649 | /* NOTE: Caller runs local copy on master. */ |
650 | ||
651 | put_cpu(); | |
652 | } | |
653 | ||
654 | extern unsigned long xcall_sync_tick; | |
655 | ||
656 | static void smp_start_sync_tick_client(int cpu) | |
657 | { | |
658 | cpumask_t mask = cpumask_of_cpu(cpu); | |
659 | ||
660 | smp_cross_call_masked(&xcall_sync_tick, | |
661 | 0, 0, 0, mask); | |
662 | } | |
663 | ||
664 | /* Send cross call to all processors except self. */ | |
665 | #define smp_cross_call(func, ctx, data1, data2) \ | |
666 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map) | |
667 | ||
668 | struct call_data_struct { | |
669 | void (*func) (void *info); | |
670 | void *info; | |
671 | atomic_t finished; | |
672 | int wait; | |
673 | }; | |
674 | ||
675 | static DEFINE_SPINLOCK(call_lock); | |
676 | static struct call_data_struct *call_data; | |
677 | ||
678 | extern unsigned long xcall_call_function; | |
679 | ||
680 | /* | |
681 | * You must not call this function with disabled interrupts or from a | |
682 | * hardware interrupt handler or from a bottom half handler. | |
683 | */ | |
bd40791e DM |
684 | static int smp_call_function_mask(void (*func)(void *info), void *info, |
685 | int nonatomic, int wait, cpumask_t mask) | |
1da177e4 LT |
686 | { |
687 | struct call_data_struct data; | |
bd40791e | 688 | int cpus = cpus_weight(mask) - 1; |
1da177e4 LT |
689 | long timeout; |
690 | ||
691 | if (!cpus) | |
692 | return 0; | |
693 | ||
694 | /* Can deadlock when called with interrupts disabled */ | |
695 | WARN_ON(irqs_disabled()); | |
696 | ||
697 | data.func = func; | |
698 | data.info = info; | |
699 | atomic_set(&data.finished, 0); | |
700 | data.wait = wait; | |
701 | ||
702 | spin_lock(&call_lock); | |
703 | ||
704 | call_data = &data; | |
705 | ||
bd40791e | 706 | smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask); |
1da177e4 LT |
707 | |
708 | /* | |
709 | * Wait for other cpus to complete function or at | |
710 | * least snap the call data. | |
711 | */ | |
712 | timeout = 1000000; | |
713 | while (atomic_read(&data.finished) != cpus) { | |
714 | if (--timeout <= 0) | |
715 | goto out_timeout; | |
716 | barrier(); | |
717 | udelay(1); | |
718 | } | |
719 | ||
720 | spin_unlock(&call_lock); | |
721 | ||
722 | return 0; | |
723 | ||
724 | out_timeout: | |
725 | spin_unlock(&call_lock); | |
726 | printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n", | |
727 | (long) num_online_cpus() - 1L, | |
728 | (long) atomic_read(&data.finished)); | |
729 | return 0; | |
730 | } | |
731 | ||
bd40791e DM |
732 | int smp_call_function(void (*func)(void *info), void *info, |
733 | int nonatomic, int wait) | |
734 | { | |
735 | return smp_call_function_mask(func, info, nonatomic, wait, | |
736 | cpu_online_map); | |
737 | } | |
738 | ||
1da177e4 LT |
739 | void smp_call_function_client(int irq, struct pt_regs *regs) |
740 | { | |
741 | void (*func) (void *info) = call_data->func; | |
742 | void *info = call_data->info; | |
743 | ||
744 | clear_softint(1 << irq); | |
745 | if (call_data->wait) { | |
746 | /* let initiator proceed only after completion */ | |
747 | func(info); | |
748 | atomic_inc(&call_data->finished); | |
749 | } else { | |
750 | /* let initiator proceed after getting data */ | |
751 | atomic_inc(&call_data->finished); | |
752 | func(info); | |
753 | } | |
754 | } | |
755 | ||
bd40791e DM |
756 | static void tsb_sync(void *info) |
757 | { | |
758 | struct mm_struct *mm = info; | |
759 | ||
760 | if (current->active_mm == mm) | |
761 | tsb_context_switch(mm); | |
762 | } | |
763 | ||
764 | void smp_tsb_sync(struct mm_struct *mm) | |
765 | { | |
766 | smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask); | |
767 | } | |
768 | ||
1da177e4 LT |
769 | extern unsigned long xcall_flush_tlb_mm; |
770 | extern unsigned long xcall_flush_tlb_pending; | |
771 | extern unsigned long xcall_flush_tlb_kernel_range; | |
1da177e4 LT |
772 | extern unsigned long xcall_report_regs; |
773 | extern unsigned long xcall_receive_signal; | |
774 | ||
775 | #ifdef DCACHE_ALIASING_POSSIBLE | |
776 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
777 | #endif | |
778 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
779 | ||
780 | #ifdef CONFIG_DEBUG_DCFLUSH | |
781 | extern atomic_t dcpage_flushes; | |
782 | extern atomic_t dcpage_flushes_xcall; | |
783 | #endif | |
784 | ||
785 | static __inline__ void __local_flush_dcache_page(struct page *page) | |
786 | { | |
787 | #ifdef DCACHE_ALIASING_POSSIBLE | |
788 | __flush_dcache_page(page_address(page), | |
789 | ((tlb_type == spitfire) && | |
790 | page_mapping(page) != NULL)); | |
791 | #else | |
792 | if (page_mapping(page) != NULL && | |
793 | tlb_type == spitfire) | |
794 | __flush_icache_page(__pa(page_address(page))); | |
795 | #endif | |
796 | } | |
797 | ||
798 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
799 | { | |
800 | cpumask_t mask = cpumask_of_cpu(cpu); | |
a43fe0e7 DM |
801 | int this_cpu; |
802 | ||
803 | if (tlb_type == hypervisor) | |
804 | return; | |
1da177e4 LT |
805 | |
806 | #ifdef CONFIG_DEBUG_DCFLUSH | |
807 | atomic_inc(&dcpage_flushes); | |
808 | #endif | |
a43fe0e7 DM |
809 | |
810 | this_cpu = get_cpu(); | |
811 | ||
1da177e4 LT |
812 | if (cpu == this_cpu) { |
813 | __local_flush_dcache_page(page); | |
814 | } else if (cpu_online(cpu)) { | |
815 | void *pg_addr = page_address(page); | |
816 | u64 data0; | |
817 | ||
818 | if (tlb_type == spitfire) { | |
819 | data0 = | |
820 | ((u64)&xcall_flush_dcache_page_spitfire); | |
821 | if (page_mapping(page) != NULL) | |
822 | data0 |= ((u64)1 << 32); | |
823 | spitfire_xcall_deliver(data0, | |
824 | __pa(pg_addr), | |
825 | (u64) pg_addr, | |
826 | mask); | |
a43fe0e7 | 827 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
828 | #ifdef DCACHE_ALIASING_POSSIBLE |
829 | data0 = | |
830 | ((u64)&xcall_flush_dcache_page_cheetah); | |
831 | cheetah_xcall_deliver(data0, | |
832 | __pa(pg_addr), | |
833 | 0, mask); | |
834 | #endif | |
835 | } | |
836 | #ifdef CONFIG_DEBUG_DCFLUSH | |
837 | atomic_inc(&dcpage_flushes_xcall); | |
838 | #endif | |
839 | } | |
840 | ||
841 | put_cpu(); | |
842 | } | |
843 | ||
844 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
845 | { | |
846 | void *pg_addr = page_address(page); | |
847 | cpumask_t mask = cpu_online_map; | |
848 | u64 data0; | |
a43fe0e7 DM |
849 | int this_cpu; |
850 | ||
851 | if (tlb_type == hypervisor) | |
852 | return; | |
853 | ||
854 | this_cpu = get_cpu(); | |
1da177e4 LT |
855 | |
856 | cpu_clear(this_cpu, mask); | |
857 | ||
858 | #ifdef CONFIG_DEBUG_DCFLUSH | |
859 | atomic_inc(&dcpage_flushes); | |
860 | #endif | |
861 | if (cpus_empty(mask)) | |
862 | goto flush_self; | |
863 | if (tlb_type == spitfire) { | |
864 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
865 | if (page_mapping(page) != NULL) | |
866 | data0 |= ((u64)1 << 32); | |
867 | spitfire_xcall_deliver(data0, | |
868 | __pa(pg_addr), | |
869 | (u64) pg_addr, | |
870 | mask); | |
a43fe0e7 | 871 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
872 | #ifdef DCACHE_ALIASING_POSSIBLE |
873 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
874 | cheetah_xcall_deliver(data0, | |
875 | __pa(pg_addr), | |
876 | 0, mask); | |
877 | #endif | |
878 | } | |
879 | #ifdef CONFIG_DEBUG_DCFLUSH | |
880 | atomic_inc(&dcpage_flushes_xcall); | |
881 | #endif | |
882 | flush_self: | |
883 | __local_flush_dcache_page(page); | |
884 | ||
885 | put_cpu(); | |
886 | } | |
887 | ||
888 | void smp_receive_signal(int cpu) | |
889 | { | |
890 | cpumask_t mask = cpumask_of_cpu(cpu); | |
891 | ||
892 | if (cpu_online(cpu)) { | |
893 | u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff); | |
894 | ||
895 | if (tlb_type == spitfire) | |
896 | spitfire_xcall_deliver(data0, 0, 0, mask); | |
a43fe0e7 | 897 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
1da177e4 | 898 | cheetah_xcall_deliver(data0, 0, 0, mask); |
a43fe0e7 DM |
899 | else if (tlb_type == hypervisor) |
900 | hypervisor_xcall_deliver(data0, 0, 0, mask); | |
1da177e4 LT |
901 | } |
902 | } | |
903 | ||
904 | void smp_receive_signal_client(int irq, struct pt_regs *regs) | |
905 | { | |
906 | /* Just return, rtrap takes care of the rest. */ | |
907 | clear_softint(1 << irq); | |
908 | } | |
909 | ||
910 | void smp_report_regs(void) | |
911 | { | |
912 | smp_cross_call(&xcall_report_regs, 0, 0, 0); | |
913 | } | |
914 | ||
1da177e4 LT |
915 | /* We know that the window frames of the user have been flushed |
916 | * to the stack before we get here because all callers of us | |
917 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
918 | * which performs the flushw. | |
919 | * | |
920 | * The SMP TLB coherency scheme we use works as follows: | |
921 | * | |
922 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
923 | * space has (potentially) executed on, this is the heuristic | |
924 | * we use to avoid doing cross calls. | |
925 | * | |
926 | * Also, for flushing from kswapd and also for clones, we | |
927 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
928 | * | |
929 | * 2) TLB context numbers are shared globally across all processors | |
930 | * in the system, this allows us to play several games to avoid | |
931 | * cross calls. | |
932 | * | |
933 | * One invariant is that when a cpu switches to a process, and | |
934 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
935 | * current cpu's bit set, that tlb context is flushed locally. | |
936 | * | |
937 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
938 | * cross calls when we want to flush the currently running process's | |
939 | * tlb state. This is done by clearing all cpu bits except the current | |
940 | * processor's in current->active_mm->cpu_vm_mask and performing the | |
941 | * flush locally only. This will force any subsequent cpus which run | |
942 | * this task to flush the context from the local tlb if the process | |
943 | * migrates to another cpu (again). | |
944 | * | |
945 | * 3) For shared address spaces (threads) and swapping we bite the | |
946 | * bullet for most cases and perform the cross call (but only to | |
947 | * the cpus listed in cpu_vm_mask). | |
948 | * | |
949 | * The performance gain from "optimizing" away the cross call for threads is | |
950 | * questionable (in theory the big win for threads is the massive sharing of | |
951 | * address space state across processors). | |
952 | */ | |
62dbec78 DM |
953 | |
954 | /* This currently is only used by the hugetlb arch pre-fault | |
955 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
956 | * bits of the context register for an address space. | |
957 | */ | |
1da177e4 LT |
958 | void smp_flush_tlb_mm(struct mm_struct *mm) |
959 | { | |
62dbec78 DM |
960 | u32 ctx = CTX_HWBITS(mm->context); |
961 | int cpu = get_cpu(); | |
1da177e4 | 962 | |
62dbec78 DM |
963 | if (atomic_read(&mm->mm_users) == 1) { |
964 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); | |
965 | goto local_flush_and_out; | |
966 | } | |
1da177e4 | 967 | |
62dbec78 DM |
968 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
969 | ctx, 0, 0, | |
970 | mm->cpu_vm_mask); | |
1da177e4 | 971 | |
62dbec78 DM |
972 | local_flush_and_out: |
973 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 974 | |
62dbec78 | 975 | put_cpu(); |
1da177e4 LT |
976 | } |
977 | ||
978 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) | |
979 | { | |
980 | u32 ctx = CTX_HWBITS(mm->context); | |
981 | int cpu = get_cpu(); | |
982 | ||
dedeb002 | 983 | if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) |
1da177e4 | 984 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); |
dedeb002 HD |
985 | else |
986 | smp_cross_call_masked(&xcall_flush_tlb_pending, | |
987 | ctx, nr, (unsigned long) vaddrs, | |
988 | mm->cpu_vm_mask); | |
1da177e4 | 989 | |
1da177e4 LT |
990 | __flush_tlb_pending(ctx, nr, vaddrs); |
991 | ||
992 | put_cpu(); | |
993 | } | |
994 | ||
995 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
996 | { | |
997 | start &= PAGE_MASK; | |
998 | end = PAGE_ALIGN(end); | |
999 | if (start != end) { | |
1000 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
1001 | 0, start, end); | |
1002 | ||
1003 | __flush_tlb_kernel_range(start, end); | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | /* CPU capture. */ | |
1008 | /* #define CAPTURE_DEBUG */ | |
1009 | extern unsigned long xcall_capture; | |
1010 | ||
1011 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
1012 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
1013 | static unsigned long penguins_are_doing_time; | |
1014 | ||
1015 | void smp_capture(void) | |
1016 | { | |
1017 | int result = atomic_add_ret(1, &smp_capture_depth); | |
1018 | ||
1019 | if (result == 1) { | |
1020 | int ncpus = num_online_cpus(); | |
1021 | ||
1022 | #ifdef CAPTURE_DEBUG | |
1023 | printk("CPU[%d]: Sending penguins to jail...", | |
1024 | smp_processor_id()); | |
1025 | #endif | |
1026 | penguins_are_doing_time = 1; | |
4f07118f | 1027 | membar_storestore_loadstore(); |
1da177e4 LT |
1028 | atomic_inc(&smp_capture_registry); |
1029 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
1030 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 1031 | rmb(); |
1da177e4 LT |
1032 | #ifdef CAPTURE_DEBUG |
1033 | printk("done\n"); | |
1034 | #endif | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | void smp_release(void) | |
1039 | { | |
1040 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
1041 | #ifdef CAPTURE_DEBUG | |
1042 | printk("CPU[%d]: Giving pardon to " | |
1043 | "imprisoned penguins\n", | |
1044 | smp_processor_id()); | |
1045 | #endif | |
1046 | penguins_are_doing_time = 0; | |
4f07118f | 1047 | membar_storeload_storestore(); |
1da177e4 LT |
1048 | atomic_dec(&smp_capture_registry); |
1049 | } | |
1050 | } | |
1051 | ||
1052 | /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they | |
1053 | * can service tlb flush xcalls... | |
1054 | */ | |
1055 | extern void prom_world(int); | |
96c6e0d8 | 1056 | |
1da177e4 LT |
1057 | void smp_penguin_jailcell(int irq, struct pt_regs *regs) |
1058 | { | |
1da177e4 LT |
1059 | clear_softint(1 << irq); |
1060 | ||
1061 | preempt_disable(); | |
1062 | ||
1063 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
1064 | prom_world(1); |
1065 | atomic_inc(&smp_capture_registry); | |
4f07118f | 1066 | membar_storeload_storestore(); |
1da177e4 | 1067 | while (penguins_are_doing_time) |
4f07118f | 1068 | rmb(); |
1da177e4 LT |
1069 | atomic_dec(&smp_capture_registry); |
1070 | prom_world(0); | |
1071 | ||
1072 | preempt_enable(); | |
1073 | } | |
1074 | ||
1da177e4 LT |
1075 | #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier |
1076 | #define prof_counter(__cpu) cpu_data(__cpu).counter | |
1077 | ||
1078 | void smp_percpu_timer_interrupt(struct pt_regs *regs) | |
1079 | { | |
1080 | unsigned long compare, tick, pstate; | |
1081 | int cpu = smp_processor_id(); | |
1082 | int user = user_mode(regs); | |
1083 | ||
1084 | /* | |
1085 | * Check for level 14 softint. | |
1086 | */ | |
1087 | { | |
1088 | unsigned long tick_mask = tick_ops->softint_mask; | |
1089 | ||
1090 | if (!(get_softint() & tick_mask)) { | |
1091 | extern void handler_irq(int, struct pt_regs *); | |
1092 | ||
1093 | handler_irq(14, regs); | |
1094 | return; | |
1095 | } | |
1096 | clear_softint(tick_mask); | |
1097 | } | |
1098 | ||
1099 | do { | |
1100 | profile_tick(CPU_PROFILING, regs); | |
1101 | if (!--prof_counter(cpu)) { | |
1102 | irq_enter(); | |
1103 | ||
1104 | if (cpu == boot_cpu_id) { | |
1105 | kstat_this_cpu.irqs[0]++; | |
1106 | timer_tick_interrupt(regs); | |
1107 | } | |
1108 | ||
1109 | update_process_times(user); | |
1110 | ||
1111 | irq_exit(); | |
1112 | ||
1113 | prof_counter(cpu) = prof_multiplier(cpu); | |
1114 | } | |
1115 | ||
1116 | /* Guarantee that the following sequences execute | |
1117 | * uninterrupted. | |
1118 | */ | |
1119 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
1120 | "wrpr %0, %1, %%pstate" | |
1121 | : "=r" (pstate) | |
1122 | : "i" (PSTATE_IE)); | |
1123 | ||
1124 | compare = tick_ops->add_compare(current_tick_offset); | |
1125 | tick = tick_ops->get_tick(); | |
1126 | ||
1127 | /* Restore PSTATE_IE. */ | |
1128 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
1129 | : /* no outputs */ | |
1130 | : "r" (pstate)); | |
1131 | } while (time_after_eq(tick, compare)); | |
1132 | } | |
1133 | ||
1134 | static void __init smp_setup_percpu_timer(void) | |
1135 | { | |
1136 | int cpu = smp_processor_id(); | |
1137 | unsigned long pstate; | |
1138 | ||
1139 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
1140 | ||
1141 | /* Guarantee that the following sequences execute | |
1142 | * uninterrupted. | |
1143 | */ | |
1144 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
1145 | "wrpr %0, %1, %%pstate" | |
1146 | : "=r" (pstate) | |
1147 | : "i" (PSTATE_IE)); | |
1148 | ||
1149 | tick_ops->init_tick(current_tick_offset); | |
1150 | ||
1151 | /* Restore PSTATE_IE. */ | |
1152 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
1153 | : /* no outputs */ | |
1154 | : "r" (pstate)); | |
1155 | } | |
1156 | ||
1157 | void __init smp_tick_init(void) | |
1158 | { | |
1159 | boot_cpu_id = hard_smp_processor_id(); | |
1160 | current_tick_offset = timer_tick_offset; | |
1161 | ||
1162 | cpu_set(boot_cpu_id, cpu_online_map); | |
1163 | prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1; | |
1164 | } | |
1165 | ||
1166 | /* /proc/profile writes can call this, don't __init it please. */ | |
1167 | static DEFINE_SPINLOCK(prof_setup_lock); | |
1168 | ||
1169 | int setup_profiling_timer(unsigned int multiplier) | |
1170 | { | |
1171 | unsigned long flags; | |
1172 | int i; | |
1173 | ||
1174 | if ((!multiplier) || (timer_tick_offset / multiplier) < 1000) | |
1175 | return -EINVAL; | |
1176 | ||
1177 | spin_lock_irqsave(&prof_setup_lock, flags); | |
1178 | for (i = 0; i < NR_CPUS; i++) | |
1179 | prof_multiplier(i) = multiplier; | |
1180 | current_tick_offset = (timer_tick_offset / multiplier); | |
1181 | spin_unlock_irqrestore(&prof_setup_lock, flags); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
7abea921 | 1186 | /* Constrain the number of cpus to max_cpus. */ |
1da177e4 LT |
1187 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1188 | { | |
1da177e4 | 1189 | if (num_possible_cpus() > max_cpus) { |
7abea921 DM |
1190 | int instance, mid; |
1191 | ||
1da177e4 LT |
1192 | instance = 0; |
1193 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
1194 | if (mid != boot_cpu_id) { | |
1195 | cpu_clear(mid, phys_cpu_present_map); | |
1196 | if (num_possible_cpus() <= max_cpus) | |
1197 | break; | |
1198 | } | |
1199 | instance++; | |
1200 | } | |
1201 | } | |
1202 | ||
1203 | smp_store_cpu_info(boot_cpu_id); | |
1204 | } | |
1205 | ||
7abea921 DM |
1206 | /* Set this up early so that things like the scheduler can init |
1207 | * properly. We use the same cpu mask for both the present and | |
1208 | * possible cpu map. | |
1209 | */ | |
1210 | void __init smp_setup_cpu_possible_map(void) | |
1211 | { | |
1212 | int instance, mid; | |
1213 | ||
1214 | instance = 0; | |
1215 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
1216 | if (mid < NR_CPUS) | |
1217 | cpu_set(mid, phys_cpu_present_map); | |
1218 | instance++; | |
1219 | } | |
1220 | } | |
1221 | ||
1da177e4 LT |
1222 | void __devinit smp_prepare_boot_cpu(void) |
1223 | { | |
56fb4df6 DM |
1224 | int cpu = hard_smp_processor_id(); |
1225 | ||
1226 | if (cpu >= NR_CPUS) { | |
1da177e4 LT |
1227 | prom_printf("Serious problem, boot cpu id >= NR_CPUS\n"); |
1228 | prom_halt(); | |
1229 | } | |
1230 | ||
56fb4df6 DM |
1231 | current_thread_info()->cpu = cpu; |
1232 | __local_per_cpu_offset = __per_cpu_offset(cpu); | |
1da177e4 LT |
1233 | |
1234 | cpu_set(smp_processor_id(), cpu_online_map); | |
1235 | cpu_set(smp_processor_id(), phys_cpu_present_map); | |
1236 | } | |
1237 | ||
1238 | int __devinit __cpu_up(unsigned int cpu) | |
1239 | { | |
1240 | int ret = smp_boot_one_cpu(cpu); | |
1241 | ||
1242 | if (!ret) { | |
1243 | cpu_set(cpu, smp_commenced_mask); | |
1244 | while (!cpu_isset(cpu, cpu_online_map)) | |
1245 | mb(); | |
1246 | if (!cpu_isset(cpu, cpu_online_map)) { | |
1247 | ret = -ENODEV; | |
1248 | } else { | |
02fead75 DM |
1249 | /* On SUN4V, writes to %tick and %stick are |
1250 | * not allowed. | |
1251 | */ | |
1252 | if (tlb_type != hypervisor) | |
1253 | smp_synchronize_one_tick(cpu); | |
1da177e4 LT |
1254 | } |
1255 | } | |
1256 | return ret; | |
1257 | } | |
1258 | ||
1259 | void __init smp_cpus_done(unsigned int max_cpus) | |
1260 | { | |
1261 | unsigned long bogosum = 0; | |
1262 | int i; | |
1263 | ||
1264 | for (i = 0; i < NR_CPUS; i++) { | |
1265 | if (cpu_online(i)) | |
1266 | bogosum += cpu_data(i).udelay_val; | |
1267 | } | |
1268 | printk("Total of %ld processors activated " | |
1269 | "(%lu.%02lu BogoMIPS).\n", | |
1270 | (long) num_online_cpus(), | |
1271 | bogosum/(500000/HZ), | |
1272 | (bogosum/(5000/HZ))%100); | |
1273 | } | |
1274 | ||
1da177e4 LT |
1275 | void smp_send_reschedule(int cpu) |
1276 | { | |
64c7c8f8 | 1277 | smp_receive_signal(cpu); |
1da177e4 LT |
1278 | } |
1279 | ||
1280 | /* This is a nop because we capture all other cpus | |
1281 | * anyways when making the PROM active. | |
1282 | */ | |
1283 | void smp_send_stop(void) | |
1284 | { | |
1285 | } | |
1286 | ||
d369ddd2 DM |
1287 | unsigned long __per_cpu_base __read_mostly; |
1288 | unsigned long __per_cpu_shift __read_mostly; | |
1da177e4 LT |
1289 | |
1290 | EXPORT_SYMBOL(__per_cpu_base); | |
1291 | EXPORT_SYMBOL(__per_cpu_shift); | |
1292 | ||
1293 | void __init setup_per_cpu_areas(void) | |
1294 | { | |
1295 | unsigned long goal, size, i; | |
1296 | char *ptr; | |
1da177e4 LT |
1297 | |
1298 | /* Copy section for each CPU (we discard the original) */ | |
56fb4df6 | 1299 | goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES); |
1da177e4 LT |
1300 | #ifdef CONFIG_MODULES |
1301 | if (goal < PERCPU_ENOUGH_ROOM) | |
1302 | goal = PERCPU_ENOUGH_ROOM; | |
1303 | #endif | |
1304 | __per_cpu_shift = 0; | |
1305 | for (size = 1UL; size < goal; size <<= 1UL) | |
1306 | __per_cpu_shift++; | |
1307 | ||
56fb4df6 | 1308 | ptr = alloc_bootmem(size * NR_CPUS); |
1da177e4 LT |
1309 | |
1310 | __per_cpu_base = ptr - __per_cpu_start; | |
1311 | ||
1da177e4 LT |
1312 | for (i = 0; i < NR_CPUS; i++, ptr += size) |
1313 | memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start); | |
1da177e4 | 1314 | } |