[deliverable/linux.git] / arch / sparc64 / kernel / sun4v_tlb_miss.S

/* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
 *
 * Copyright (C) 2006 <davem@davemloft.net>
 */

	.text
	.align	32

	/* Load ITLB fault information into VADDR and CTX, using BASE.  */
#define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
	ldx	[BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
	ldx	[BASE + HV_FAULT_I_CTX_OFFSET], CTX;

	/* Load DTLB fault information into VADDR and CTX, using BASE.  */
#define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
	ldx	[BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
	ldx	[BASE + HV_FAULT_D_CTX_OFFSET], CTX;

	/* DEST = (VADDR >> 22)
	 *
	 * Branch to ZERO_CTX_LABEL if context is zero.
	 */
#define	COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \
	srlx	VADDR, 22, DEST; \
	brz,pn	CTX, ZERO_CTX_LABEL; \
	 nop;

	/* Create TSB pointer.  This is something like:
	 *
	 * index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
	 * tsb_base = tsb_reg & ~0x7UL;
	 * tsb_index = ((vaddr >> HASH_SHIFT) & tsb_mask);
	 * tsb_ptr = tsb_base + (tsb_index * 16);
	 */
#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \
	and	TSB_PTR, 0x7, TMP1;			\
	mov	512, TMP2;				\
	andn	TSB_PTR, 0x7, TSB_PTR;			\
	sllx	TMP2, TMP1, TMP2;			\
	srlx	VADDR, HASH_SHIFT, TMP1;		\
	sub	TMP2, 1, TMP2;				\
	and	TMP1, TMP2, TMP1;			\
	sllx	TMP1, 4, TMP1;				\
	add	TSB_PTR, TMP1, TSB_PTR;

sun4v_itlb_miss:
	/* Load MMU Miss base into %g2.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	
	/* Load UTSB reg into %g1.  */
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1

	LOAD_ITLB_INFO(%g2, %g4, %g5)
	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)

	/* Load TSB tag/pte into %g2/%g3 and compare the tag.  */
	ldda	[%g1] ASI_QUAD_LDD_PHYS_4V, %g2
	cmp	%g2, %g6
	bne,a,pn %xcc, tsb_miss_page_table_walk
	 mov	FAULT_CODE_ITLB, %g3
	andcc	%g3, _PAGE_EXEC_4V, %g0
	be,a,pn	%xcc, tsb_do_fault
	 mov	FAULT_CODE_ITLB, %g3

	/* We have a valid entry, make hypervisor call to load
	 * I-TLB and return from trap.
	 *
	 * %g3:	PTE
	 * %g4:	vaddr
	 */
sun4v_itlb_load:
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	mov	%o0, %g1		! save %o0
	mov	%o1, %g2		! save %o1
	mov	%o2, %g5		! save %o2
	mov	%o3, %g7		! save %o3
	mov	%g4, %o0		! vaddr
	ldx	[%g6 + HV_FAULT_I_CTX_OFFSET], %o1	! ctx
	mov	%g3, %o2		! PTE
	mov	HV_MMU_IMMU, %o3	! flags
	ta	HV_MMU_MAP_ADDR_TRAP
	brnz,pn	%o0, sun4v_itlb_error
	 mov	%g2, %o1		! restore %o1
	mov	%g1, %o0		! restore %o0
	mov	%g5, %o2		! restore %o2
	mov	%g7, %o3		! restore %o3

	retry

sun4v_dtlb_miss:
	/* Load MMU Miss base into %g2.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	
	/* Load UTSB reg into %g1.  */
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1

	LOAD_DTLB_INFO(%g2, %g4, %g5)
	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)

	/* Load TSB tag/pte into %g2/%g3 and compare the tag.  */
	ldda	[%g1] ASI_QUAD_LDD_PHYS_4V, %g2
	cmp	%g2, %g6
	bne,a,pn %xcc, tsb_miss_page_table_walk
	 mov	FAULT_CODE_DTLB, %g3

	/* We have a valid entry, make hypervisor call to load
	 * D-TLB and return from trap.
	 *
	 * %g3:	PTE
	 * %g4:	vaddr
	 */
sun4v_dtlb_load:
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	mov	%o0, %g1		! save %o0
	mov	%o1, %g2		! save %o1
	mov	%o2, %g5		! save %o2
	mov	%o3, %g7		! save %o3
	mov	%g4, %o0		! vaddr
	ldx	[%g6 + HV_FAULT_D_CTX_OFFSET], %o1	! ctx
	mov	%g3, %o2		! PTE
	mov	HV_MMU_DMMU, %o3	! flags
	ta	HV_MMU_MAP_ADDR_TRAP
	brnz,pn	%o0, sun4v_dtlb_error
	 mov	%g2, %o1		! restore %o1
	mov	%g1, %o0		! restore %o0
	mov	%g5, %o2		! restore %o2
	mov	%g7, %o3		! restore %o3

	retry

sun4v_dtlb_prot:
	SET_GL(1)

	/* Load MMU Miss base into %g5.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g5
	
	ldx	[%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
	rdpr	%tl, %g1
	cmp	%g1, 1
	bgu,pn	%xcc, winfix_trampoline
	 mov	FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
	ba,pt	%xcc, sparc64_realfault_common
	 nop

	/* Called from trap table:
	 * %g4:	vaddr
	 * %g5:	context
	 * %g6: TAG TARGET
	 */
sun4v_itsb_miss:
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1
	brz,pn	%g5, kvmap_itlb_4v
	 mov	FAULT_CODE_ITLB, %g3
	ba,a,pt	%xcc, sun4v_tsb_miss_common

	/* Called from trap table:
	 * %g4:	vaddr
	 * %g5:	context
	 * %g6: TAG TARGET
	 */
sun4v_dtsb_miss:
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1
	brz,pn	%g5, kvmap_dtlb_4v
	 mov	FAULT_CODE_DTLB, %g3

	/* fallthrough */

sun4v_tsb_miss_common:
	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)

	sub	%g2, TRAP_PER_CPU_FAULT_INFO, %g2

#ifdef CONFIG_HUGETLB_PAGE
	mov	SCRATCHPAD_UTSBREG2, %g5
	ldxa	[%g5] ASI_SCRATCHPAD, %g5
	cmp	%g5, -1
	be,pt	%xcc, 80f
	 nop
	COMPUTE_TSB_PTR(%g5, %g4, HPAGE_SHIFT, %g2, %g7)

	/* That clobbered %g2, reload it.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	sub	%g2, TRAP_PER_CPU_FAULT_INFO, %g2

80:	stx	%g5, [%g2 + TRAP_PER_CPU_TSB_HUGE_TEMP]
#endif

	ba,pt	%xcc, tsb_miss_page_table_walk_sun4v_fastpath
	 ldx	[%g2 + TRAP_PER_CPU_PGD_PADDR], %g7

sun4v_itlb_error:
	sethi	%hi(sun4v_err_itlb_vaddr), %g1
	stx	%g4, [%g1 + %lo(sun4v_err_itlb_vaddr)]
	sethi	%hi(sun4v_err_itlb_ctx), %g1
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	ldx	[%g6 + HV_FAULT_I_CTX_OFFSET], %o1
	stx	%o1, [%g1 + %lo(sun4v_err_itlb_ctx)]
	sethi	%hi(sun4v_err_itlb_pte), %g1
	stx	%g3, [%g1 + %lo(sun4v_err_itlb_pte)]
	sethi	%hi(sun4v_err_itlb_error), %g1
	stx	%o0, [%g1 + %lo(sun4v_err_itlb_error)]

	rdpr	%tl, %g4
	cmp	%g4, 1
	ble,pt	%icc, 1f
	 sethi	%hi(2f), %g7
	ba,pt	%xcc, etraptl1
	 or	%g7, %lo(2f), %g7

1:	ba,pt	%xcc, etrap
2:	 or	%g7, %lo(2b), %g7
	call	sun4v_itlb_error_report
	 add	%sp, PTREGS_OFF, %o0

	/* NOTREACHED */

sun4v_dtlb_error:
	sethi	%hi(sun4v_err_dtlb_vaddr), %g1
	stx	%g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)]
	sethi	%hi(sun4v_err_dtlb_ctx), %g1
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	ldx	[%g6 + HV_FAULT_D_CTX_OFFSET], %o1
	stx	%o1, [%g1 + %lo(sun4v_err_dtlb_ctx)]
	sethi	%hi(sun4v_err_dtlb_pte), %g1
	stx	%g3, [%g1 + %lo(sun4v_err_dtlb_pte)]
	sethi	%hi(sun4v_err_dtlb_error), %g1
	stx	%o0, [%g1 + %lo(sun4v_err_dtlb_error)]

	rdpr	%tl, %g4
	cmp	%g4, 1
	ble,pt	%icc, 1f
	 sethi	%hi(2f), %g7
	ba,pt	%xcc, etraptl1
	 or	%g7, %lo(2f), %g7

1:	ba,pt	%xcc, etrap
2:	 or	%g7, %lo(2b), %g7
	call	sun4v_dtlb_error_report
	 add	%sp, PTREGS_OFF, %o0

	/* NOTREACHED */

	/* Instruction Access Exception, tl0. */
sun4v_iacc:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_I_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_insn_access_exception
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

	/* Instruction Access Exception, tl1. */
sun4v_iacc_tl1:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_I_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etraptl1
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_insn_access_exception_tl1
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

	/* Data Access Exception, tl0. */
sun4v_dacc:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_data_access_exception
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

	/* Data Access Exception, tl1. */
sun4v_dacc_tl1:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etraptl1
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_data_access_exception_tl1
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

	/* Memory Address Unaligned.  */
sun4v_mna:
	/* Window fixup? */
	rdpr	%tl, %g2
	cmp	%g2, 1
	ble,pt	%icc, 1f
	 nop

	SET_GL(1)
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
	mov	HV_FAULT_TYPE_UNALIGNED, %g3
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g4
	sllx	%g3, 16, %g3
	or	%g4, %g3, %g4
	ba,pt	%xcc, winfix_mna
	 rdpr	%tpc, %g3
	/* not reached */

1:	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	mov	HV_FAULT_TYPE_UNALIGNED, %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5

	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_do_mna
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

	/* Privileged Action.  */
sun4v_privact:
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	call	do_privact
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

	/* Unaligned ldd float, tl0. */
sun4v_lddfmna:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	handle_lddfmna
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

	/* Unaligned std float, tl0. */
sun4v_stdfmna:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	handle_stdfmna
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap_clr_l6

#define BRANCH_ALWAYS	0x10680000
#define NOP		0x01000000
#define SUN4V_DO_PATCH(OLD, NEW)	\
	sethi	%hi(NEW), %g1; \
	or	%g1, %lo(NEW), %g1; \
	sethi	%hi(OLD), %g2; \
	or	%g2, %lo(OLD), %g2; \
	sub	%g1, %g2, %g1; \
	sethi	%hi(BRANCH_ALWAYS), %g3; \
	sll	%g1, 11, %g1; \
	srl	%g1, 11 + 2, %g1; \
	or	%g3, %lo(BRANCH_ALWAYS), %g3; \
	or	%g3, %g1, %g3; \
	stw	%g3, [%g2]; \
	sethi	%hi(NOP), %g3; \
	or	%g3, %lo(NOP), %g3; \
	stw	%g3, [%g2 + 0x4]; \
	flush	%g2;

	.globl	sun4v_patch_tlb_handlers
	.type	sun4v_patch_tlb_handlers,#function
sun4v_patch_tlb_handlers:
	SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
	SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
	SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
	SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
	SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
	SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
	SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
	SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
	SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
	SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
	SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
	SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
	SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
	SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
	SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
	retl
	 nop
	.size	sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers
Commit	Line	Data
d257d5da DM	1	/* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
	2	*
	3	* Copyright (C) 2006 <davem@davemloft.net>
	4	*/
	5
	6	.text
	7	.align 32
	8
36a68e77 DM	9	/* Load ITLB fault information into VADDR and CTX, using BASE. */
	10	#define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
	11	ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
	12	ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
	13
	14	/* Load DTLB fault information into VADDR and CTX, using BASE. */
	15	#define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
	16	ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
	17	ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
d257d5da	18
8b234274	19	/* DEST = (VADDR >> 22)
36a68e77	20	*
bcc28ee0	21	* Branch to ZERO_CTX_LABEL if context is zero.
d257d5da	22	*/
8b234274 DM	23	#define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \
8b234274 DM	24	srlx VADDR, 22, DEST; \
36a68e77	25	brz,pn CTX, ZERO_CTX_LABEL; \
8b234274	26	nop;
d257d5da DM	27
	28	/* Create TSB pointer. This is something like:
	29	*
	30	* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
	31	* tsb_base = tsb_reg & ~0x7UL;
dcc1e8dd	32	* tsb_index = ((vaddr >> HASH_SHIFT) & tsb_mask);
d257d5da DM	33	* tsb_ptr = tsb_base + (tsb_index * 16);
d257d5da DM	34	*/
dcc1e8dd	35	#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \
36a68e77 DM	36	and TSB_PTR, 0x7, TMP1; \
	37	mov 512, TMP2; \
	38	andn TSB_PTR, 0x7, TSB_PTR; \
	39	sllx TMP2, TMP1, TMP2; \
dcc1e8dd	40	srlx VADDR, HASH_SHIFT, TMP1; \
36a68e77 DM	41	sub TMP2, 1, TMP2; \
	42	and TMP1, TMP2, TMP1; \
	43	sllx TMP1, 4, TMP1; \
	44	add TSB_PTR, TMP1, TSB_PTR;
	45
	46	sun4v_itlb_miss:
	47	/* Load MMU Miss base into %g2. */
	48	ldxa [%g0] ASI_SCRATCHPAD, %g2
	49
	50	/* Load UTSB reg into %g1. */
	51	mov SCRATCHPAD_UTSBREG1, %g1
	52	ldxa [%g1] ASI_SCRATCHPAD, %g1
	53
	54	LOAD_ITLB_INFO(%g2, %g4, %g5)
8b234274	55	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
dcc1e8dd	56	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
d257d5da DM	57
d257d5da DM	58	/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
c7f81d42	59	ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
d257d5da	60	cmp %g2, %g6
d257d5da DM	61	bne,a,pn %xcc, tsb_miss_page_table_walk
d257d5da DM	62	mov FAULT_CODE_ITLB, %g3
45f791eb	63	andcc %g3, _PAGE_EXEC_4V, %g0
d257d5da DM	64	be,a,pn %xcc, tsb_do_fault
	65	mov FAULT_CODE_ITLB, %g3
	66
	67	/* We have a valid entry, make hypervisor call to load
	68	* I-TLB and return from trap.
	69	*
	70	* %g3: PTE
	71	* %g4: vaddr
d257d5da DM	72	*/
d257d5da DM	73	sun4v_itlb_load:
8b234274	74	ldxa [%g0] ASI_SCRATCHPAD, %g6
d257d5da DM	75	mov %o0, %g1 ! save %o0
	76	mov %o1, %g2 ! save %o1
	77	mov %o2, %g5 ! save %o2
	78	mov %o3, %g7 ! save %o3
	79	mov %g4, %o0 ! vaddr
8b234274	80	ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1 ! ctx
d257d5da DM	81	mov %g3, %o2 ! PTE
	82	mov HV_MMU_IMMU, %o3 ! flags
	83	ta HV_MMU_MAP_ADDR_TRAP
6c8927c9 DM	84	brnz,pn %o0, sun4v_itlb_error
6c8927c9 DM	85	mov %g2, %o1 ! restore %o1
d257d5da	86	mov %g1, %o0 ! restore %o0
d257d5da DM	87	mov %g5, %o2 ! restore %o2
	88	mov %g7, %o3 ! restore %o3
	89
	90	retry
	91
	92	sun4v_dtlb_miss:
12eaa328 DM	93	/* Load MMU Miss base into %g2. */
12eaa328 DM	94	ldxa [%g0] ASI_SCRATCHPAD, %g2
d257d5da DM	95
d257d5da DM	96	/* Load UTSB reg into %g1. */
12eaa328	97	mov SCRATCHPAD_UTSBREG1, %g1
459b6e62	98	ldxa [%g1] ASI_SCRATCHPAD, %g1
d257d5da	99
36a68e77	100	LOAD_DTLB_INFO(%g2, %g4, %g5)
8b234274	101	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
dcc1e8dd	102	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
d257d5da DM	103
d257d5da DM	104	/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
c7f81d42	105	ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
d257d5da DM	106	cmp %g2, %g6
d257d5da DM	107	bne,a,pn %xcc, tsb_miss_page_table_walk
92daa77e	108	mov FAULT_CODE_DTLB, %g3
d257d5da DM	109
	110	/* We have a valid entry, make hypervisor call to load
	111	* D-TLB and return from trap.
	112	*
	113	* %g3: PTE
	114	* %g4: vaddr
d257d5da DM	115	*/
d257d5da DM	116	sun4v_dtlb_load:
8b234274	117	ldxa [%g0] ASI_SCRATCHPAD, %g6
d257d5da DM	118	mov %o0, %g1 ! save %o0
	119	mov %o1, %g2 ! save %o1
	120	mov %o2, %g5 ! save %o2
	121	mov %o3, %g7 ! save %o3
	122	mov %g4, %o0 ! vaddr
8b234274	123	ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1 ! ctx
d257d5da DM	124	mov %g3, %o2 ! PTE
	125	mov HV_MMU_DMMU, %o3 ! flags
	126	ta HV_MMU_MAP_ADDR_TRAP
6c8927c9 DM	127	brnz,pn %o0, sun4v_dtlb_error
6c8927c9 DM	128	mov %g2, %o1 ! restore %o1
d257d5da	129	mov %g1, %o0 ! restore %o0
d257d5da DM	130	mov %g5, %o2 ! restore %o2
	131	mov %g7, %o3 ! restore %o3
	132
	133	retry
	134
	135	sun4v_dtlb_prot:
8b234274 DM	136	SET_GL(1)
8b234274 DM	137
24c523ec	138	/* Load MMU Miss base into %g5. */
8b234274	139	ldxa [%g0] ASI_SCRATCHPAD, %g5
d257d5da	140
8b234274	141	ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
d257d5da DM	142	rdpr %tl, %g1
d257d5da DM	143	cmp %g1, 1
8b234274	144	bgu,pn %xcc, winfix_trampoline
8b234274	145	mov FAULT_CODE_DTLB \| FAULT_CODE_WRITE, %g4
86d43258 DM	146	ba,pt %xcc, sparc64_realfault_common
86d43258 DM	147	nop
d257d5da	148
24c523ec DM	149	/* Called from trap table:
	150	* %g4: vaddr
	151	* %g5: context
	152	* %g6: TAG TARGET
aa9143b9 DM	153	*/
aa9143b9 DM	154	sun4v_itsb_miss:
459b6e62 DM	155	mov SCRATCHPAD_UTSBREG1, %g1
	156	ldxa [%g1] ASI_SCRATCHPAD, %g1
	157	brz,pn %g5, kvmap_itlb_4v
aa9143b9	158	mov FAULT_CODE_ITLB, %g3
6c8927c9	159	ba,a,pt %xcc, sun4v_tsb_miss_common
aa9143b9	160
24c523ec DM	161	/* Called from trap table:
	162	* %g4: vaddr
	163	* %g5: context
	164	* %g6: TAG TARGET
aa9143b9 DM	165	*/
aa9143b9 DM	166	sun4v_dtsb_miss:
459b6e62 DM	167	mov SCRATCHPAD_UTSBREG1, %g1
	168	ldxa [%g1] ASI_SCRATCHPAD, %g1
	169	brz,pn %g5, kvmap_dtlb_4v
	170	mov FAULT_CODE_DTLB, %g3
aa9143b9	171
24c523ec DM	172	/* fallthrough */
24c523ec DM	173
aa9143b9	174	sun4v_tsb_miss_common:
dcc1e8dd	175	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)
36a68e77	176
36a68e77	177	sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
dcc1e8dd DM	178
	179	#ifdef CONFIG_HUGETLB_PAGE
	180	mov SCRATCHPAD_UTSBREG2, %g5
	181	ldxa [%g5] ASI_SCRATCHPAD, %g5
	182	cmp %g5, -1
	183	be,pt %xcc, 80f
	184	nop
	185	COMPUTE_TSB_PTR(%g5, %g4, HPAGE_SHIFT, %g2, %g7)
	186
	187	/* That clobbered %g2, reload it. */
	188	ldxa [%g0] ASI_SCRATCHPAD, %g2
	189	sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
	190
	191	80: stx %g5, [%g2 + TRAP_PER_CPU_TSB_HUGE_TEMP]
	192	#endif
	193
36a68e77 DM	194	ba,pt %xcc, tsb_miss_page_table_walk_sun4v_fastpath
36a68e77 DM	195	ldx [%g2 + TRAP_PER_CPU_PGD_PADDR], %g7
aa9143b9	196
6c8927c9 DM	197	sun4v_itlb_error:
	198	sethi %hi(sun4v_err_itlb_vaddr), %g1
	199	stx %g4, [%g1 + %lo(sun4v_err_itlb_vaddr)]
	200	sethi %hi(sun4v_err_itlb_ctx), %g1
8b234274 DM	201	ldxa [%g0] ASI_SCRATCHPAD, %g6
8b234274 DM	202	ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1
6c8927c9 DM	203	stx %o1, [%g1 + %lo(sun4v_err_itlb_ctx)]
	204	sethi %hi(sun4v_err_itlb_pte), %g1
	205	stx %g3, [%g1 + %lo(sun4v_err_itlb_pte)]
	206	sethi %hi(sun4v_err_itlb_error), %g1
	207	stx %o0, [%g1 + %lo(sun4v_err_itlb_error)]
	208
	209	rdpr %tl, %g4
	210	cmp %g4, 1
	211	ble,pt %icc, 1f
	212	sethi %hi(2f), %g7
	213	ba,pt %xcc, etraptl1
	214	or %g7, %lo(2f), %g7
	215
	216	1: ba,pt %xcc, etrap
	217	2: or %g7, %lo(2b), %g7
	218	call sun4v_itlb_error_report
	219	add %sp, PTREGS_OFF, %o0
	220
	221	/* NOTREACHED */
	222
	223	sun4v_dtlb_error:
	224	sethi %hi(sun4v_err_dtlb_vaddr), %g1
	225	stx %g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)]
	226	sethi %hi(sun4v_err_dtlb_ctx), %g1
8b234274 DM	227	ldxa [%g0] ASI_SCRATCHPAD, %g6
8b234274 DM	228	ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1
6c8927c9 DM	229	stx %o1, [%g1 + %lo(sun4v_err_dtlb_ctx)]
	230	sethi %hi(sun4v_err_dtlb_pte), %g1
	231	stx %g3, [%g1 + %lo(sun4v_err_dtlb_pte)]
	232	sethi %hi(sun4v_err_dtlb_error), %g1
	233	stx %o0, [%g1 + %lo(sun4v_err_dtlb_error)]
	234
	235	rdpr %tl, %g4
	236	cmp %g4, 1
	237	ble,pt %icc, 1f
	238	sethi %hi(2f), %g7
	239	ba,pt %xcc, etraptl1
	240	or %g7, %lo(2f), %g7
	241
	242	1: ba,pt %xcc, etrap
	243	2: or %g7, %lo(2b), %g7
	244	call sun4v_dtlb_error_report
	245	add %sp, PTREGS_OFF, %o0
	246
	247	/* NOTREACHED */
	248
ed6b0b45 DM	249	/* Instruction Access Exception, tl0. */
ed6b0b45 DM	250	sun4v_iacc:
12eaa328 DM	251	ldxa [%g0] ASI_SCRATCHPAD, %g2
	252	ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	253	ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	254	ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
ed6b0b45 DM	255	sllx %g3, 16, %g3
	256	or %g5, %g3, %g5
	257	ba,pt %xcc, etrap
	258	rd %pc, %g7
	259	mov %l4, %o1
	260	mov %l5, %o2
	261	call sun4v_insn_access_exception
	262	add %sp, PTREGS_OFF, %o0
	263	ba,a,pt %xcc, rtrap_clr_l6
	264
	265	/* Instruction Access Exception, tl1. */
	266	sun4v_iacc_tl1:
12eaa328 DM	267	ldxa [%g0] ASI_SCRATCHPAD, %g2
	268	ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	269	ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	270	ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
ed6b0b45 DM	271	sllx %g3, 16, %g3
	272	or %g5, %g3, %g5
	273	ba,pt %xcc, etraptl1
	274	rd %pc, %g7
	275	mov %l4, %o1
	276	mov %l5, %o2
	277	call sun4v_insn_access_exception_tl1
	278	add %sp, PTREGS_OFF, %o0
	279	ba,a,pt %xcc, rtrap_clr_l6
	280
	281	/* Data Access Exception, tl0. */
	282	sun4v_dacc:
12eaa328 DM	283	ldxa [%g0] ASI_SCRATCHPAD, %g2
	284	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	285	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	286	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	287	sllx %g3, 16, %g3
	288	or %g5, %g3, %g5
	289	ba,pt %xcc, etrap
	290	rd %pc, %g7
	291	mov %l4, %o1
	292	mov %l5, %o2
	293	call sun4v_data_access_exception
	294	add %sp, PTREGS_OFF, %o0
	295	ba,a,pt %xcc, rtrap_clr_l6
	296
	297	/* Data Access Exception, tl1. */
	298	sun4v_dacc_tl1:
12eaa328 DM	299	ldxa [%g0] ASI_SCRATCHPAD, %g2
	300	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	301	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	302	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	303	sllx %g3, 16, %g3
	304	or %g5, %g3, %g5
	305	ba,pt %xcc, etraptl1
	306	rd %pc, %g7
	307	mov %l4, %o1
	308	mov %l5, %o2
	309	call sun4v_data_access_exception_tl1
	310	add %sp, PTREGS_OFF, %o0
	311	ba,a,pt %xcc, rtrap_clr_l6
	312
	313	/* Memory Address Unaligned. */
	314	sun4v_mna:
24c523ec DM	315	/* Window fixup? */
	316	rdpr %tl, %g2
	317	cmp %g2, 1
	318	ble,pt %icc, 1f
	319	nop
	320
	321	SET_GL(1)
bcc28ee0 DM	322	ldxa [%g0] ASI_SCRATCHPAD, %g2
bcc28ee0 DM	323	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
24c523ec	324	mov HV_FAULT_TYPE_UNALIGNED, %g3
bcc28ee0	325	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g4
24c523ec DM	326	sllx %g3, 16, %g3
	327	or %g4, %g3, %g4
	328	ba,pt %xcc, winfix_mna
	329	rdpr %tpc, %g3
	330	/* not reached */
	331
	332	1: ldxa [%g0] ASI_SCRATCHPAD, %g2
ed6b0b45	333	mov HV_FAULT_TYPE_UNALIGNED, %g3
12eaa328 DM	334	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
12eaa328 DM	335	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	336	sllx %g3, 16, %g3
	337	or %g5, %g3, %g5
	338
ed6b0b45 DM	339	ba,pt %xcc, etrap
	340	rd %pc, %g7
	341	mov %l4, %o1
	342	mov %l5, %o2
9f8a5b84	343	call sun4v_do_mna
ed6b0b45 DM	344	add %sp, PTREGS_OFF, %o0
	345	ba,a,pt %xcc, rtrap_clr_l6
	346
	347	/* Privileged Action. */
	348	sun4v_privact:
	349	ba,pt %xcc, etrap
	350	rd %pc, %g7
	351	call do_privact
	352	add %sp, PTREGS_OFF, %o0
	353	ba,a,pt %xcc, rtrap_clr_l6
	354
	355	/* Unaligned ldd float, tl0. */
	356	sun4v_lddfmna:
12eaa328 DM	357	ldxa [%g0] ASI_SCRATCHPAD, %g2
	358	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	359	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	360	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	361	sllx %g3, 16, %g3
	362	or %g5, %g3, %g5
	363	ba,pt %xcc, etrap
	364	rd %pc, %g7
	365	mov %l4, %o1
	366	mov %l5, %o2
	367	call handle_lddfmna
	368	add %sp, PTREGS_OFF, %o0
	369	ba,a,pt %xcc, rtrap_clr_l6
	370
	371	/* Unaligned std float, tl0. */
	372	sun4v_stdfmna:
12eaa328 DM	373	ldxa [%g0] ASI_SCRATCHPAD, %g2
	374	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	375	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	376	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	377	sllx %g3, 16, %g3
	378	or %g5, %g3, %g5
	379	ba,pt %xcc, etrap
	380	rd %pc, %g7
	381	mov %l4, %o1
	382	mov %l5, %o2
	383	call handle_stdfmna
	384	add %sp, PTREGS_OFF, %o0
	385	ba,a,pt %xcc, rtrap_clr_l6
aa9143b9	386
d257d5da DM	387	#define BRANCH_ALWAYS 0x10680000
	388	#define NOP 0x01000000
	389	#define SUN4V_DO_PATCH(OLD, NEW) \
	390	sethi %hi(NEW), %g1; \
	391	or %g1, %lo(NEW), %g1; \
	392	sethi %hi(OLD), %g2; \
	393	or %g2, %lo(OLD), %g2; \
	394	sub %g1, %g2, %g1; \
	395	sethi %hi(BRANCH_ALWAYS), %g3; \
459b6e62 DM	396	sll %g1, 11, %g1; \
459b6e62 DM	397	srl %g1, 11 + 2, %g1; \
d257d5da DM	398	or %g3, %lo(BRANCH_ALWAYS), %g3; \
	399	or %g3, %g1, %g3; \
	400	stw %g3, [%g2]; \
	401	sethi %hi(NOP), %g3; \
	402	or %g3, %lo(NOP), %g3; \
	403	stw %g3, [%g2 + 0x4]; \
	404	flush %g2;
	405
	406	.globl sun4v_patch_tlb_handlers
	407	.type sun4v_patch_tlb_handlers,#function
	408	sun4v_patch_tlb_handlers:
	409	SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
	410	SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
	411	SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
	412	SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
	413	SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
	414	SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
ed6b0b45 DM	415	SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
	416	SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
	417	SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
	418	SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
	419	SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
	420	SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
	421	SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
	422	SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
	423	SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
d257d5da DM	424	retl
	425	nop
	426	.size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers