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[SPARC64]: Get SUN4V SMP working.
[deliverable/linux.git] / arch / sparc64 / kernel / trampoline.S
CommitLineData
1da177e4
LT		 1/* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
2 * trampoline.S: Jump start slave processors on sparc64.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#include <asm/head.h>
8#include <asm/asi.h>
9#include <asm/lsu.h>
10#include <asm/dcr.h>
11#include <asm/dcu.h>
12#include <asm/pstate.h>
13#include <asm/page.h>
14#include <asm/pgtable.h>
15#include <asm/spitfire.h>
16#include <asm/processor.h>
17#include <asm/thread_info.h>
18#include <asm/mmu.h>
d82ace7d 19#include <asm/hypervisor.h>
3af6e01e 20#include <asm/cpudata.h>
1da177e4
LT		 21
22 .data
23 .align 8
24call_method:
25 .asciz "call-method"
26 .align 8
27itlb_load:
28 .asciz "SUNW,itlb-load"
29 .align 8
30dtlb_load:
31 .asciz "SUNW,dtlb-load"
32
72aff53f
DM		 33 /* XXX __cpuinit this thing XXX */
34#define TRAMP_STACK_SIZE 1024
35 .align 16
36tramp_stack:
37 .skip TRAMP_STACK_SIZE
38
1da177e4
LT		 39 .text
40 .align 8
41 .globl sparc64_cpu_startup, sparc64_cpu_startup_end
42sparc64_cpu_startup:
d82ace7d
DM		 43 BRANCH_IF_SUN4V(g1, niagara_startup)
44 BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
45 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
1da177e4
LT		 46
47 ba,pt %xcc, spitfire_startup
48 nop
49
50cheetah_plus_startup:
51 /* Preserve OBP chosen DCU and DCR register settings. */
52 ba,pt %xcc, cheetah_generic_startup
53 nop
54
55cheetah_startup:
56 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
57 wr %g1, %asr18
58
59 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
60 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
61 sllx %g5, 32, %g5
62 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
63 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
64 membar #Sync
72aff53f 65 /* fallthru */
1da177e4
LT		 66
67cheetah_generic_startup:
68 mov TSB_EXTENSION_P, %g3
69 stxa %g0, [%g3] ASI_DMMU
70 stxa %g0, [%g3] ASI_IMMU
71 membar #Sync
72
73 mov TSB_EXTENSION_S, %g3
74 stxa %g0, [%g3] ASI_DMMU
75 membar #Sync
76
77 mov TSB_EXTENSION_N, %g3
78 stxa %g0, [%g3] ASI_DMMU
79 stxa %g0, [%g3] ASI_IMMU
80 membar #Sync
d82ace7d 81 /* fallthru */
1da177e4 82
d82ace7d 83niagara_startup:
1da177e4
LT		 84 /* Disable STICK_INT interrupts. */
85 sethi %hi(0x80000000), %g5
86 sllx %g5, 32, %g5
87 wr %g5, %asr25
88
89 ba,pt %xcc, startup_continue
90 nop
91
92spitfire_startup:
93 mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
94 stxa %g1, [%g0] ASI_LSU_CONTROL
95 membar #Sync
96
97startup_continue:
1da177e4
LT		 98 sethi %hi(0x80000000), %g2
99 sllx %g2, 32, %g2
100 wr %g2, 0, %tick_cmpr
101
72aff53f
DM		 102 mov %o0, %l0
103
d82ace7d
DM		 104 BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
105
1da177e4
LT		 106 /* Call OBP by hand to lock KERNBASE into i/d tlbs.
107 * We lock 2 consequetive entries if we are 'bigkernel'.
108 */
1da177e4
LT		 109 sethi %hi(prom_entry_lock), %g2
1101: ldstub [%g2 + %lo(prom_entry_lock)], %g1
b445e26c 111 membar #StoreLoad | #StoreStore
1da177e4 112 brnz,pn %g1, 1b
b445e26c 113 nop
1da177e4
LT		 114
115 sethi %hi(p1275buf), %g2
116 or %g2, %lo(p1275buf), %g2
117 ldx [%g2 + 0x10], %l2
1da177e4
LT		 118 add %l2, -(192 + 128), %sp
119 flushw
120
121 sethi %hi(call_method), %g2
122 or %g2, %lo(call_method), %g2
123 stx %g2, [%sp + 2047 + 128 + 0x00]
124 mov 5, %g2
125 stx %g2, [%sp + 2047 + 128 + 0x08]
126 mov 1, %g2
127 stx %g2, [%sp + 2047 + 128 + 0x10]
128 sethi %hi(itlb_load), %g2
129 or %g2, %lo(itlb_load), %g2
130 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 131 sethi %hi(prom_mmu_ihandle_cache), %g2
132 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 133 stx %g2, [%sp + 2047 + 128 + 0x20]
134 sethi %hi(KERNBASE), %g2
135 stx %g2, [%sp + 2047 + 128 + 0x28]
136 sethi %hi(kern_locked_tte_data), %g2
137 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
138 stx %g2, [%sp + 2047 + 128 + 0x30]
139
140 mov 15, %g2
141 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
142
143 mov 63, %g2
1441:
145 stx %g2, [%sp + 2047 + 128 + 0x38]
146 sethi %hi(p1275buf), %g2
147 or %g2, %lo(p1275buf), %g2
148 ldx [%g2 + 0x08], %o1
149 call %o1
150 add %sp, (2047 + 128), %o0
151
152 sethi %hi(bigkernel), %g2
153 lduw [%g2 + %lo(bigkernel)], %g2
d82ace7d 154 brz,pt %g2, do_dtlb
1da177e4
LT		 155 nop
156
157 sethi %hi(call_method), %g2
158 or %g2, %lo(call_method), %g2
159 stx %g2, [%sp + 2047 + 128 + 0x00]
160 mov 5, %g2
161 stx %g2, [%sp + 2047 + 128 + 0x08]
162 mov 1, %g2
163 stx %g2, [%sp + 2047 + 128 + 0x10]
164 sethi %hi(itlb_load), %g2
165 or %g2, %lo(itlb_load), %g2
166 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 167 sethi %hi(prom_mmu_ihandle_cache), %g2
168 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 169 stx %g2, [%sp + 2047 + 128 + 0x20]
170 sethi %hi(KERNBASE + 0x400000), %g2
171 stx %g2, [%sp + 2047 + 128 + 0x28]
172 sethi %hi(kern_locked_tte_data), %g2
173 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
174 sethi %hi(0x400000), %g1
175 add %g2, %g1, %g2
176 stx %g2, [%sp + 2047 + 128 + 0x30]
177
178 mov 14, %g2
179 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
180
181 mov 62, %g2
1821:
183 stx %g2, [%sp + 2047 + 128 + 0x38]
184 sethi %hi(p1275buf), %g2
185 or %g2, %lo(p1275buf), %g2
186 ldx [%g2 + 0x08], %o1
187 call %o1
188 add %sp, (2047 + 128), %o0
189
190do_dtlb:
191 sethi %hi(call_method), %g2
192 or %g2, %lo(call_method), %g2
193 stx %g2, [%sp + 2047 + 128 + 0x00]
194 mov 5, %g2
195 stx %g2, [%sp + 2047 + 128 + 0x08]
196 mov 1, %g2
197 stx %g2, [%sp + 2047 + 128 + 0x10]
198 sethi %hi(dtlb_load), %g2
199 or %g2, %lo(dtlb_load), %g2
200 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 201 sethi %hi(prom_mmu_ihandle_cache), %g2
202 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 203 stx %g2, [%sp + 2047 + 128 + 0x20]
204 sethi %hi(KERNBASE), %g2
205 stx %g2, [%sp + 2047 + 128 + 0x28]
206 sethi %hi(kern_locked_tte_data), %g2
207 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
208 stx %g2, [%sp + 2047 + 128 + 0x30]
209
210 mov 15, %g2
211 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
212
213 mov 63, %g2
2141:
215
216 stx %g2, [%sp + 2047 + 128 + 0x38]
217 sethi %hi(p1275buf), %g2
218 or %g2, %lo(p1275buf), %g2
219 ldx [%g2 + 0x08], %o1
220 call %o1
221 add %sp, (2047 + 128), %o0
222
223 sethi %hi(bigkernel), %g2
224 lduw [%g2 + %lo(bigkernel)], %g2
d82ace7d 225 brz,pt %g2, do_unlock
1da177e4
LT		 226 nop
227
228 sethi %hi(call_method), %g2
229 or %g2, %lo(call_method), %g2
230 stx %g2, [%sp + 2047 + 128 + 0x00]
231 mov 5, %g2
232 stx %g2, [%sp + 2047 + 128 + 0x08]
233 mov 1, %g2
234 stx %g2, [%sp + 2047 + 128 + 0x10]
235 sethi %hi(dtlb_load), %g2
236 or %g2, %lo(dtlb_load), %g2
237 stx %g2, [%sp + 2047 + 128 + 0x18]
bff06d55
DM		 238 sethi %hi(prom_mmu_ihandle_cache), %g2
239 lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
1da177e4
LT		 240 stx %g2, [%sp + 2047 + 128 + 0x20]
241 sethi %hi(KERNBASE + 0x400000), %g2
242 stx %g2, [%sp + 2047 + 128 + 0x28]
243 sethi %hi(kern_locked_tte_data), %g2
244 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
245 sethi %hi(0x400000), %g1
246 add %g2, %g1, %g2
247 stx %g2, [%sp + 2047 + 128 + 0x30]
248
249 mov 14, %g2
250 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
251
252 mov 62, %g2
2531:
254
255 stx %g2, [%sp + 2047 + 128 + 0x38]
256 sethi %hi(p1275buf), %g2
257 or %g2, %lo(p1275buf), %g2
258 ldx [%g2 + 0x08], %o1
259 call %o1
260 add %sp, (2047 + 128), %o0
261
262do_unlock:
263 sethi %hi(prom_entry_lock), %g2
264 stb %g0, [%g2 + %lo(prom_entry_lock)]
265 membar #StoreStore | #StoreLoad
266
d82ace7d
DM		 267 ba,pt %xcc, after_lock_tlb
268 nop
269
270niagara_lock_tlb:
164c220f
DM		 271 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
272 sethi %hi(KERNBASE), %o0
273 clr %o1
274 sethi %hi(kern_locked_tte_data), %o2
275 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
276 mov HV_MMU_IMMU, %o3
d82ace7d
DM		 277 ta HV_FAST_TRAP
278
164c220f
DM		 279 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
280 sethi %hi(KERNBASE), %o0
281 clr %o1
282 sethi %hi(kern_locked_tte_data), %o2
283 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
284 mov HV_MMU_DMMU, %o3
d82ace7d
DM		 285 ta HV_FAST_TRAP
286
287 sethi %hi(bigkernel), %g2
288 lduw [%g2 + %lo(bigkernel)], %g2
289 brz,pt %g2, after_lock_tlb
290 nop
291
164c220f
DM		 292 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
293 sethi %hi(KERNBASE + 0x400000), %o0
294 clr %o1
295 sethi %hi(kern_locked_tte_data), %o2
296 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
297 sethi %hi(0x400000), %o3
298 add %o2, %o3, %o2
299 mov HV_MMU_IMMU, %o3
d82ace7d
DM		 300 ta HV_FAST_TRAP
301
164c220f
DM		 302 mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
303 sethi %hi(KERNBASE + 0x400000), %o0
304 clr %o1
305 sethi %hi(kern_locked_tte_data), %o2
306 ldx [%o2 + %lo(kern_locked_tte_data)], %o2
307 sethi %hi(0x400000), %o3
308 add %o2, %o3, %o2
309 mov HV_MMU_DMMU, %o3
d82ace7d
DM		 310 ta HV_FAST_TRAP
311
312after_lock_tlb:
1da177e4
LT		 313 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
314 wr %g0, 0, %fprs
315
1da177e4
LT		 316 wr %g0, ASI_P, %asi
317
318 mov PRIMARY_CONTEXT, %g7
8b11bd12
DM		 319
320661: stxa %g0, [%g7] ASI_DMMU
321 .section .sun4v_1insn_patch, "ax"
322 .word 661b
323 stxa %g0, [%g7] ASI_MMU
324 .previous
325
1da177e4
LT		 326 membar #Sync
327 mov SECONDARY_CONTEXT, %g7
8b11bd12
DM		 328
329661: stxa %g0, [%g7] ASI_DMMU
330 .section .sun4v_1insn_patch, "ax"
331 .word 661b
332 stxa %g0, [%g7] ASI_MMU
333 .previous
334
1da177e4
LT		 335 membar #Sync
336
72aff53f
DM		 337 /* Everything we do here, until we properly take over the
338 * trap table, must be done with extreme care. We cannot
339 * make any references to %g6 (current thread pointer),
340 * %g4 (current task pointer), or %g5 (base of current cpu's
341 * per-cpu area) until we properly take over the trap table
342 * from the firmware and hypervisor.
343 *
344 * Get onto temporary stack which is in the locked kernel image.
345 */
346 sethi %hi(tramp_stack), %g1
347 or %g1, %lo(tramp_stack), %g1
348 add %g1, TRAMP_STACK_SIZE, %g1
349 sub %g1, STACKFRAME_SZ + STACK_BIAS, %sp
1da177e4
LT		 350 mov 0, %fp
351
72aff53f
DM		 352 /* Put garbage in these registers to trap any access to them. */
353 set 0xdeadbeef, %g4
354 set 0xdeadbeef, %g5
355 set 0xdeadbeef, %g6
1da177e4
LT		 356
357 call init_irqwork_curcpu
358 nop
ac29c11d
DM		 359
360 sethi %hi(tlb_type), %g3
361 lduw [%g3 + %lo(tlb_type)], %g2
362 cmp %g2, 3
363 bne,pt %icc, 1f
364 nop
365
72aff53f
DM		 366 call hard_smp_processor_id
367 nop
368
369 mov %o0, %o1
370 mov 0, %o0
371 mov 0, %o2
ac29c11d 372 call sun4v_init_mondo_queues
72aff53f 373 mov 1, %o3
ac29c11d
DM		 374
3751: call init_cur_cpu_trap
72aff53f 376 ldx [%l0], %o0
1da177e4 377
0835ae0f 378 /* Start using proper page size encodings in ctx register. */
8b11bd12
DM		 379 sethi %hi(sparc64_kern_pri_context), %g3
380 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
381 mov PRIMARY_CONTEXT, %g1
382
383661: stxa %g2, [%g1] ASI_DMMU
384 .section .sun4v_1insn_patch, "ax"
385 .word 661b
386 stxa %g2, [%g1] ASI_MMU
387 .previous
388
389 membar #Sync
1da177e4 390
72aff53f
DM		 391 wrpr %g0, 0, %wstate
392
393 /* As a hack, put &init_thread_union into %g6.
394 * prom_world() loads from here to restore the %asi
395 * register.
396 */
397 sethi %hi(init_thread_union), %g6
398 or %g6, %lo(init_thread_union), %g6
1da177e4 399
12eaa328
DM		 400 sethi %hi(is_sun4v), %o0
401 lduw [%o0 + %lo(is_sun4v)], %o0
402 brz,pt %o0, 1f
403 nop
404
405 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
406 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
407 stxa %g2, [%g0] ASI_SCRATCHPAD
408
409 /* Compute physical address:
410 *
411 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
412 */
413 sethi %hi(KERNBASE), %g3
414 sub %g2, %g3, %g2
415 sethi %hi(kern_base), %g3
416 ldx [%g3 + %lo(kern_base)], %g3
417 add %g2, %g3, %o1
418
419 call prom_set_trap_table_sun4v
420 sethi %hi(sparc64_ttable_tl0), %o0
421
422 ba,pt %xcc, 2f
423 nop
424
4251: call prom_set_trap_table
1da177e4
LT		 426 sethi %hi(sparc64_ttable_tl0), %o0
427
72aff53f
DM		 4282: ldx [%l0], %g6
429 ldx [%g6 + TI_TASK], %g4
430
431 mov 1, %g5
432 sllx %g5, THREAD_SHIFT, %g5
433 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
434 add %g6, %g5, %sp
435 mov 0, %fp
436
437 rdpr %pstate, %o1
438 or %o1, PSTATE_IE, %o1
439 wrpr %o1, 0, %pstate
440
441 call smp_callin
1da177e4
LT		 442 nop
443 call cpu_idle
444 mov 0, %o0
445 call cpu_panic
446 nop
4471: b,a,pt %xcc, 1b
448
449 .align 8
450sparc64_cpu_startup_end:
Linux kernel - Deliverables
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