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sparc64: Add generic interface for registering a dimm printing handler.
[deliverable/linux.git] / arch / sparc64 / kernel / traps.c
CommitLineData
d979f179 1/* arch/sparc64/kernel/traps.c
1da177e4 2 *
4fe3ebec 3 * Copyright (C) 1995,1997,2008 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
5 */
6
7/*
8 * I like traps on v9, :))))
9 */
10
1da177e4 11#include <linux/module.h>
a2c1e064 12#include <linux/sched.h>
1da177e4 13#include <linux/kernel.h>
1da177e4
LT		 14#include <linux/signal.h>
15#include <linux/smp.h>
1da177e4
LT		 16#include <linux/mm.h>
17#include <linux/init.h>
1eeb66a1 18#include <linux/kdebug.h>
1da177e4 19
2f4dfe20 20#include <asm/smp.h>
1da177e4
LT		 21#include <asm/delay.h>
22#include <asm/system.h>
23#include <asm/ptrace.h>
24#include <asm/oplib.h>
25#include <asm/page.h>
26#include <asm/pgtable.h>
27#include <asm/unistd.h>
28#include <asm/uaccess.h>
29#include <asm/fpumacro.h>
30#include <asm/lsu.h>
31#include <asm/dcu.h>
32#include <asm/estate.h>
33#include <asm/chafsr.h>
6c52a96e 34#include <asm/sfafsr.h>
1da177e4
LT		 35#include <asm/psrcompat.h>
36#include <asm/processor.h>
37#include <asm/timer.h>
92704a1c 38#include <asm/head.h>
07f8e5f3 39#include <asm/prom.h>
881d021a 40#include <asm/memctrl.h>
1da177e4 41
99cd2201 42#include "entry.h"
4f70f7a9 43#include "kstack.h"
1da177e4
LT		 44
45/* When an irrecoverable trap occurs at tl > 0, the trap entry
46 * code logs the trap state registers at every level in the trap
47 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
48 * is as follows:
49 */
50struct tl1_traplog {
51 struct {
52 unsigned long tstate;
53 unsigned long tpc;
54 unsigned long tnpc;
55 unsigned long tt;
56 } trapstack[4];
57 unsigned long tl;
58};
59
60static void dump_tl1_traplog(struct tl1_traplog *p)
61{
3d6395cb 62 int i, limit;
1da177e4 63
04d74758
DM		 64 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
65 "dumping track stack.\n", p->tl);
3d6395cb
DM		 66
67 limit = (tlb_type == hypervisor) ? 2 : 4;
39334a4b 68 for (i = 0; i < limit; i++) {
04d74758 69 printk(KERN_EMERG
1da177e4
LT		 70 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
71 "TNPC[%016lx] TT[%lx]\n",
72 i + 1,
73 p->trapstack[i].tstate, p->trapstack[i].tpc,
74 p->trapstack[i].tnpc, p->trapstack[i].tt);
4fe3ebec 75 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
1da177e4
LT		 76 }
77}
78
1da177e4
LT		 79void bad_trap(struct pt_regs *regs, long lvl)
80{
81 char buffer[32];
82 siginfo_t info;
83
84 if (notify_die(DIE_TRAP, "bad trap", regs,
85 0, lvl, SIGTRAP) == NOTIFY_STOP)
86 return;
87
88 if (lvl < 0x100) {
89 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
90 die_if_kernel(buffer, regs);
91 }
92
93 lvl -= 0x100;
94 if (regs->tstate & TSTATE_PRIV) {
95 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
96 die_if_kernel(buffer, regs);
97 }
98 if (test_thread_flag(TIF_32BIT)) {
99 regs->tpc &= 0xffffffff;
100 regs->tnpc &= 0xffffffff;
101 }
102 info.si_signo = SIGILL;
103 info.si_errno = 0;
104 info.si_code = ILL_ILLTRP;
105 info.si_addr = (void __user *)regs->tpc;
106 info.si_trapno = lvl;
107 force_sig_info(SIGILL, &info, current);
108}
109
110void bad_trap_tl1(struct pt_regs *regs, long lvl)
111{
112 char buffer[32];
113
114 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
115 0, lvl, SIGTRAP) == NOTIFY_STOP)
116 return;
117
118 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
119
120 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
121 die_if_kernel (buffer, regs);
122}
123
124#ifdef CONFIG_DEBUG_BUGVERBOSE
125void do_BUG(const char *file, int line)
126{
127 bust_spinlocks(1);
128 printk("kernel BUG at %s:%d!\n", file, line);
129}
130#endif
131
881d021a
DM		 132static DEFINE_SPINLOCK(dimm_handler_lock);
133static dimm_printer_t dimm_handler;
134
135static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
136{
137 unsigned long flags;
138 int ret = -ENODEV;
139
140 spin_lock_irqsave(&dimm_handler_lock, flags);
141 if (dimm_handler) {
142 ret = dimm_handler(synd_code, paddr, buf, buflen);
143 } else if (tlb_type == spitfire) {
144 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
145 ret = -EINVAL;
146 else
147 ret = 0;
148 } else
149 ret = -ENODEV;
150 spin_unlock_irqrestore(&dimm_handler_lock, flags);
151
152 return ret;
153}
154
155int register_dimm_printer(dimm_printer_t func)
156{
157 unsigned long flags;
158 int ret = 0;
159
160 spin_lock_irqsave(&dimm_handler_lock, flags);
161 if (!dimm_handler)
162 dimm_handler = func;
163 else
164 ret = -EEXIST;
165 spin_unlock_irqrestore(&dimm_handler_lock, flags);
166
167 return ret;
168}
169
170void unregister_dimm_printer(dimm_printer_t func)
171{
172 unsigned long flags;
173
174 spin_lock_irqsave(&dimm_handler_lock, flags);
175 if (dimm_handler == func)
176 dimm_handler = NULL;
177 spin_unlock_irqrestore(&dimm_handler_lock, flags);
178}
179
180
6c52a96e 181void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
1da177e4
LT		 182{
183 siginfo_t info;
184
185 if (notify_die(DIE_TRAP, "instruction access exception", regs,
186 0, 0x8, SIGTRAP) == NOTIFY_STOP)
187 return;
188
189 if (regs->tstate & TSTATE_PRIV) {
6c52a96e
DM		 190 printk("spitfire_insn_access_exception: SFSR[%016lx] "
191 "SFAR[%016lx], going.\n", sfsr, sfar);
1da177e4
LT		 192 die_if_kernel("Iax", regs);
193 }
194 if (test_thread_flag(TIF_32BIT)) {
195 regs->tpc &= 0xffffffff;
196 regs->tnpc &= 0xffffffff;
197 }
198 info.si_signo = SIGSEGV;
199 info.si_errno = 0;
200 info.si_code = SEGV_MAPERR;
201 info.si_addr = (void __user *)regs->tpc;
202 info.si_trapno = 0;
203 force_sig_info(SIGSEGV, &info, current);
204}
205
6c52a96e 206void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
1da177e4
LT		 207{
208 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
209 0, 0x8, SIGTRAP) == NOTIFY_STOP)
210 return;
211
212 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
6c52a96e 213 spitfire_insn_access_exception(regs, sfsr, sfar);
1da177e4
LT		 214}
215
ed6b0b45
DM		 216void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
217{
218 unsigned short type = (type_ctx >> 16);
219 unsigned short ctx = (type_ctx & 0xffff);
220 siginfo_t info;
221
222 if (notify_die(DIE_TRAP, "instruction access exception", regs,
223 0, 0x8, SIGTRAP) == NOTIFY_STOP)
224 return;
225
226 if (regs->tstate & TSTATE_PRIV) {
227 printk("sun4v_insn_access_exception: ADDR[%016lx] "
228 "CTX[%04x] TYPE[%04x], going.\n",
229 addr, ctx, type);
230 die_if_kernel("Iax", regs);
231 }
232
233 if (test_thread_flag(TIF_32BIT)) {
234 regs->tpc &= 0xffffffff;
235 regs->tnpc &= 0xffffffff;
236 }
237 info.si_signo = SIGSEGV;
238 info.si_errno = 0;
239 info.si_code = SEGV_MAPERR;
240 info.si_addr = (void __user *) addr;
241 info.si_trapno = 0;
242 force_sig_info(SIGSEGV, &info, current);
243}
244
245void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
246{
247 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
248 0, 0x8, SIGTRAP) == NOTIFY_STOP)
249 return;
250
251 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
252 sun4v_insn_access_exception(regs, addr, type_ctx);
253}
254
6c52a96e 255void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
1da177e4
LT		 256{
257 siginfo_t info;
258
259 if (notify_die(DIE_TRAP, "data access exception", regs,
260 0, 0x30, SIGTRAP) == NOTIFY_STOP)
261 return;
262
263 if (regs->tstate & TSTATE_PRIV) {
264 /* Test if this comes from uaccess places. */
8cf14af0 265 const struct exception_table_entry *entry;
1da177e4 266
8cf14af0
DM		 267 entry = search_exception_tables(regs->tpc);
268 if (entry) {
269 /* Ouch, somebody is trying VM hole tricks on us... */
1da177e4
LT		 270#ifdef DEBUG_EXCEPTIONS
271 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
8cf14af0
DM		 272 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
273 regs->tpc, entry->fixup);
1da177e4 274#endif
8cf14af0 275 regs->tpc = entry->fixup;
1da177e4 276 regs->tnpc = regs->tpc + 4;
1da177e4
LT		 277 return;
278 }
279 /* Shit... */
6c52a96e
DM		 280 printk("spitfire_data_access_exception: SFSR[%016lx] "
281 "SFAR[%016lx], going.\n", sfsr, sfar);
1da177e4
LT		 282 die_if_kernel("Dax", regs);
283 }
284
285 info.si_signo = SIGSEGV;
286 info.si_errno = 0;
287 info.si_code = SEGV_MAPERR;
288 info.si_addr = (void __user *)sfar;
289 info.si_trapno = 0;
290 force_sig_info(SIGSEGV, &info, current);
291}
292
6c52a96e 293void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
bde4e4ee
DM		 294{
295 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
296 0, 0x30, SIGTRAP) == NOTIFY_STOP)
297 return;
298
299 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
6c52a96e 300 spitfire_data_access_exception(regs, sfsr, sfar);
bde4e4ee
DM		 301}
302
ed6b0b45
DM		 303void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
304{
305 unsigned short type = (type_ctx >> 16);
306 unsigned short ctx = (type_ctx & 0xffff);
307 siginfo_t info;
308
309 if (notify_die(DIE_TRAP, "data access exception", regs,
310 0, 0x8, SIGTRAP) == NOTIFY_STOP)
311 return;
312
313 if (regs->tstate & TSTATE_PRIV) {
314 printk("sun4v_data_access_exception: ADDR[%016lx] "
315 "CTX[%04x] TYPE[%04x], going.\n",
316 addr, ctx, type);
55555633 317 die_if_kernel("Dax", regs);
ed6b0b45
DM		 318 }
319
320 if (test_thread_flag(TIF_32BIT)) {
321 regs->tpc &= 0xffffffff;
322 regs->tnpc &= 0xffffffff;
323 }
324 info.si_signo = SIGSEGV;
325 info.si_errno = 0;
326 info.si_code = SEGV_MAPERR;
327 info.si_addr = (void __user *) addr;
328 info.si_trapno = 0;
329 force_sig_info(SIGSEGV, &info, current);
330}
331
332void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
333{
334 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
335 0, 0x8, SIGTRAP) == NOTIFY_STOP)
336 return;
337
338 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
339 sun4v_data_access_exception(regs, addr, type_ctx);
340}
341
1da177e4
LT		 342#ifdef CONFIG_PCI
343/* This is really pathetic... */
344extern volatile int pci_poke_in_progress;
345extern volatile int pci_poke_cpu;
346extern volatile int pci_poke_faulted;
347#endif
348
349/* When access exceptions happen, we must do this. */
350static void spitfire_clean_and_reenable_l1_caches(void)
351{
352 unsigned long va;
353
354 if (tlb_type != spitfire)
355 BUG();
356
357 /* Clean 'em. */
358 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
359 spitfire_put_icache_tag(va, 0x0);
360 spitfire_put_dcache_tag(va, 0x0);
361 }
362
363 /* Re-enable in LSU. */
364 __asm__ __volatile__("flush %%g6\n\t"
365 "membar #Sync\n\t"
366 "stxa %0, [%%g0] %1\n\t"
367 "membar #Sync"
368 : /* no outputs */
369 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
370 LSU_CONTROL_IM | LSU_CONTROL_DM),
371 "i" (ASI_LSU_CONTROL)
372 : "memory");
373}
374
6c52a96e 375static void spitfire_enable_estate_errors(void)
1da177e4 376{
6c52a96e
DM		 377 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
378 "membar #Sync"
379 : /* no outputs */
380 : "r" (ESTATE_ERR_ALL),
381 "i" (ASI_ESTATE_ERROR_EN));
1da177e4
LT		 382}
383
384static char ecc_syndrome_table[] = {
385 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
386 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
387 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
388 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
389 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
390 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
391 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
392 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
393 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
394 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
395 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
396 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
397 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
398 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
399 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
400 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
401 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
402 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
403 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
404 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
405 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
406 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
407 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
408 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
409 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
410 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
411 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
412 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
413 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
414 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
415 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
416 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
417};
418
1da177e4
LT		 419static char *syndrome_unknown = "<Unknown>";
420
6c52a96e 421static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
1da177e4 422{
6c52a96e
DM		 423 unsigned short scode;
424 char memmod_str[64], *p;
1da177e4 425
6c52a96e
DM		 426 if (udbl & bit) {
427 scode = ecc_syndrome_table[udbl & 0xff];
881d021a 428 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
1da177e4
LT		 429 p = syndrome_unknown;
430 else
431 p = memmod_str;
432 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
433 "Memory Module \"%s\"\n",
434 smp_processor_id(), scode, p);
435 }
436
6c52a96e
DM		 437 if (udbh & bit) {
438 scode = ecc_syndrome_table[udbh & 0xff];
881d021a 439 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
1da177e4
LT		 440 p = syndrome_unknown;
441 else
442 p = memmod_str;
443 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
444 "Memory Module \"%s\"\n",
445 smp_processor_id(), scode, p);
446 }
6c52a96e
DM		 447
448}
449
450static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
451{
452
453 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
454 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
455 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
456
457 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
458
459 /* We always log it, even if someone is listening for this
460 * trap.
461 */
462 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
463 0, TRAP_TYPE_CEE, SIGTRAP);
464
465 /* The Correctable ECC Error trap does not disable I/D caches. So
466 * we only have to restore the ESTATE Error Enable register.
467 */
468 spitfire_enable_estate_errors();
469}
470
471static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
472{
473 siginfo_t info;
474
475 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
476 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
477 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
478
479 /* XXX add more human friendly logging of the error status
480 * XXX as is implemented for cheetah
481 */
482
483 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
484
485 /* We always log it, even if someone is listening for this
486 * trap.
487 */
488 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
489 0, tt, SIGTRAP);
490
491 if (regs->tstate & TSTATE_PRIV) {
492 if (tl1)
493 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
494 die_if_kernel("UE", regs);
495 }
496
497 /* XXX need more intelligent processing here, such as is implemented
498 * XXX for cheetah errors, in fact if the E-cache still holds the
499 * XXX line with bad parity this will loop
500 */
501
502 spitfire_clean_and_reenable_l1_caches();
503 spitfire_enable_estate_errors();
504
505 if (test_thread_flag(TIF_32BIT)) {
506 regs->tpc &= 0xffffffff;
507 regs->tnpc &= 0xffffffff;
508 }
509 info.si_signo = SIGBUS;
510 info.si_errno = 0;
511 info.si_code = BUS_OBJERR;
512 info.si_addr = (void *)0;
513 info.si_trapno = 0;
514 force_sig_info(SIGBUS, &info, current);
515}
516
517void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
518{
519 unsigned long afsr, tt, udbh, udbl;
520 int tl1;
521
522 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
523 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
524 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
525 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
526 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
527
528#ifdef CONFIG_PCI
529 if (tt == TRAP_TYPE_DAE &&
530 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
531 spitfire_clean_and_reenable_l1_caches();
532 spitfire_enable_estate_errors();
533
534 pci_poke_faulted = 1;
535 regs->tnpc = regs->tpc + 4;
536 return;
537 }
538#endif
539
540 if (afsr & SFAFSR_UE)
541 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
542
543 if (tt == TRAP_TYPE_CEE) {
544 /* Handle the case where we took a CEE trap, but ACK'd
545 * only the UE state in the UDB error registers.
546 */
547 if (afsr & SFAFSR_UE) {
548 if (udbh & UDBE_CE) {
549 __asm__ __volatile__(
550 "stxa %0, [%1] %2\n\t"
551 "membar #Sync"
552 : /* no outputs */
553 : "r" (udbh & UDBE_CE),
554 "r" (0x0), "i" (ASI_UDB_ERROR_W));
555 }
556 if (udbl & UDBE_CE) {
557 __asm__ __volatile__(
558 "stxa %0, [%1] %2\n\t"
559 "membar #Sync"
560 : /* no outputs */
561 : "r" (udbl & UDBE_CE),
562 "r" (0x18), "i" (ASI_UDB_ERROR_W));
563 }
564 }
565
566 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
567 }
1da177e4
LT		 568}
569
816242da
DM		 570int cheetah_pcache_forced_on;
571
572void cheetah_enable_pcache(void)
573{
574 unsigned long dcr;
575
576 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
577 smp_processor_id());
578
579 __asm__ __volatile__("ldxa [%%g0] %1, %0"
580 : "=r" (dcr)
581 : "i" (ASI_DCU_CONTROL_REG));
582 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
583 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
584 "membar #Sync"
585 : /* no outputs */
586 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
587}
588
1da177e4
LT		 589/* Cheetah error trap handling. */
590static unsigned long ecache_flush_physbase;
591static unsigned long ecache_flush_linesize;
592static unsigned long ecache_flush_size;
593
1da177e4
LT		 594/* This table is ordered in priority of errors and matches the
595 * AFAR overwrite policy as well.
596 */
597
598struct afsr_error_table {
599 unsigned long mask;
600 const char *name;
601};
602
603static const char CHAFSR_PERR_msg[] =
604 "System interface protocol error";
605static const char CHAFSR_IERR_msg[] =
606 "Internal processor error";
607static const char CHAFSR_ISAP_msg[] =
608 "System request parity error on incoming addresss";
609static const char CHAFSR_UCU_msg[] =
610 "Uncorrectable E-cache ECC error for ifetch/data";
611static const char CHAFSR_UCC_msg[] =
612 "SW Correctable E-cache ECC error for ifetch/data";
613static const char CHAFSR_UE_msg[] =
614 "Uncorrectable system bus data ECC error for read";
615static const char CHAFSR_EDU_msg[] =
616 "Uncorrectable E-cache ECC error for stmerge/blkld";
617static const char CHAFSR_EMU_msg[] =
618 "Uncorrectable system bus MTAG error";
619static const char CHAFSR_WDU_msg[] =
620 "Uncorrectable E-cache ECC error for writeback";
621static const char CHAFSR_CPU_msg[] =
622 "Uncorrectable ECC error for copyout";
623static const char CHAFSR_CE_msg[] =
624 "HW corrected system bus data ECC error for read";
625static const char CHAFSR_EDC_msg[] =
626 "HW corrected E-cache ECC error for stmerge/blkld";
627static const char CHAFSR_EMC_msg[] =
628 "HW corrected system bus MTAG ECC error";
629static const char CHAFSR_WDC_msg[] =
630 "HW corrected E-cache ECC error for writeback";
631static const char CHAFSR_CPC_msg[] =
632 "HW corrected ECC error for copyout";
633static const char CHAFSR_TO_msg[] =
634 "Unmapped error from system bus";
635static const char CHAFSR_BERR_msg[] =
636 "Bus error response from system bus";
637static const char CHAFSR_IVC_msg[] =
638 "HW corrected system bus data ECC error for ivec read";
639static const char CHAFSR_IVU_msg[] =
640 "Uncorrectable system bus data ECC error for ivec read";
641static struct afsr_error_table __cheetah_error_table[] = {
642 { CHAFSR_PERR, CHAFSR_PERR_msg },
643 { CHAFSR_IERR, CHAFSR_IERR_msg },
644 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
645 { CHAFSR_UCU, CHAFSR_UCU_msg },
646 { CHAFSR_UCC, CHAFSR_UCC_msg },
647 { CHAFSR_UE, CHAFSR_UE_msg },
648 { CHAFSR_EDU, CHAFSR_EDU_msg },
649 { CHAFSR_EMU, CHAFSR_EMU_msg },
650 { CHAFSR_WDU, CHAFSR_WDU_msg },
651 { CHAFSR_CPU, CHAFSR_CPU_msg },
652 { CHAFSR_CE, CHAFSR_CE_msg },
653 { CHAFSR_EDC, CHAFSR_EDC_msg },
654 { CHAFSR_EMC, CHAFSR_EMC_msg },
655 { CHAFSR_WDC, CHAFSR_WDC_msg },
656 { CHAFSR_CPC, CHAFSR_CPC_msg },
657 { CHAFSR_TO, CHAFSR_TO_msg },
658 { CHAFSR_BERR, CHAFSR_BERR_msg },
659 /* These two do not update the AFAR. */
660 { CHAFSR_IVC, CHAFSR_IVC_msg },
661 { CHAFSR_IVU, CHAFSR_IVU_msg },
662 { 0, NULL },
663};
664static const char CHPAFSR_DTO_msg[] =
665 "System bus unmapped error for prefetch/storequeue-read";
666static const char CHPAFSR_DBERR_msg[] =
667 "System bus error for prefetch/storequeue-read";
668static const char CHPAFSR_THCE_msg[] =
669 "Hardware corrected E-cache Tag ECC error";
670static const char CHPAFSR_TSCE_msg[] =
671 "SW handled correctable E-cache Tag ECC error";
672static const char CHPAFSR_TUE_msg[] =
673 "Uncorrectable E-cache Tag ECC error";
674static const char CHPAFSR_DUE_msg[] =
675 "System bus uncorrectable data ECC error due to prefetch/store-fill";
676static struct afsr_error_table __cheetah_plus_error_table[] = {
677 { CHAFSR_PERR, CHAFSR_PERR_msg },
678 { CHAFSR_IERR, CHAFSR_IERR_msg },
679 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
680 { CHAFSR_UCU, CHAFSR_UCU_msg },
681 { CHAFSR_UCC, CHAFSR_UCC_msg },
682 { CHAFSR_UE, CHAFSR_UE_msg },
683 { CHAFSR_EDU, CHAFSR_EDU_msg },
684 { CHAFSR_EMU, CHAFSR_EMU_msg },
685 { CHAFSR_WDU, CHAFSR_WDU_msg },
686 { CHAFSR_CPU, CHAFSR_CPU_msg },
687 { CHAFSR_CE, CHAFSR_CE_msg },
688 { CHAFSR_EDC, CHAFSR_EDC_msg },
689 { CHAFSR_EMC, CHAFSR_EMC_msg },
690 { CHAFSR_WDC, CHAFSR_WDC_msg },
691 { CHAFSR_CPC, CHAFSR_CPC_msg },
692 { CHAFSR_TO, CHAFSR_TO_msg },
693 { CHAFSR_BERR, CHAFSR_BERR_msg },
694 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
695 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
696 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
697 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
698 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
699 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
700 /* These two do not update the AFAR. */
701 { CHAFSR_IVC, CHAFSR_IVC_msg },
702 { CHAFSR_IVU, CHAFSR_IVU_msg },
703 { 0, NULL },
704};
705static const char JPAFSR_JETO_msg[] =
706 "System interface protocol error, hw timeout caused";
707static const char JPAFSR_SCE_msg[] =
708 "Parity error on system snoop results";
709static const char JPAFSR_JEIC_msg[] =
710 "System interface protocol error, illegal command detected";
711static const char JPAFSR_JEIT_msg[] =
712 "System interface protocol error, illegal ADTYPE detected";
713static const char JPAFSR_OM_msg[] =
714 "Out of range memory error has occurred";
715static const char JPAFSR_ETP_msg[] =
716 "Parity error on L2 cache tag SRAM";
717static const char JPAFSR_UMS_msg[] =
718 "Error due to unsupported store";
719static const char JPAFSR_RUE_msg[] =
720 "Uncorrectable ECC error from remote cache/memory";
721static const char JPAFSR_RCE_msg[] =
722 "Correctable ECC error from remote cache/memory";
723static const char JPAFSR_BP_msg[] =
724 "JBUS parity error on returned read data";
725static const char JPAFSR_WBP_msg[] =
726 "JBUS parity error on data for writeback or block store";
727static const char JPAFSR_FRC_msg[] =
728 "Foreign read to DRAM incurring correctable ECC error";
729static const char JPAFSR_FRU_msg[] =
730 "Foreign read to DRAM incurring uncorrectable ECC error";
731static struct afsr_error_table __jalapeno_error_table[] = {
732 { JPAFSR_JETO, JPAFSR_JETO_msg },
733 { JPAFSR_SCE, JPAFSR_SCE_msg },
734 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
735 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
736 { CHAFSR_PERR, CHAFSR_PERR_msg },
737 { CHAFSR_IERR, CHAFSR_IERR_msg },
738 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
739 { CHAFSR_UCU, CHAFSR_UCU_msg },
740 { CHAFSR_UCC, CHAFSR_UCC_msg },
741 { CHAFSR_UE, CHAFSR_UE_msg },
742 { CHAFSR_EDU, CHAFSR_EDU_msg },
743 { JPAFSR_OM, JPAFSR_OM_msg },
744 { CHAFSR_WDU, CHAFSR_WDU_msg },
745 { CHAFSR_CPU, CHAFSR_CPU_msg },
746 { CHAFSR_CE, CHAFSR_CE_msg },
747 { CHAFSR_EDC, CHAFSR_EDC_msg },
748 { JPAFSR_ETP, JPAFSR_ETP_msg },
749 { CHAFSR_WDC, CHAFSR_WDC_msg },
750 { CHAFSR_CPC, CHAFSR_CPC_msg },
751 { CHAFSR_TO, CHAFSR_TO_msg },
752 { CHAFSR_BERR, CHAFSR_BERR_msg },
753 { JPAFSR_UMS, JPAFSR_UMS_msg },
754 { JPAFSR_RUE, JPAFSR_RUE_msg },
755 { JPAFSR_RCE, JPAFSR_RCE_msg },
756 { JPAFSR_BP, JPAFSR_BP_msg },
757 { JPAFSR_WBP, JPAFSR_WBP_msg },
758 { JPAFSR_FRC, JPAFSR_FRC_msg },
759 { JPAFSR_FRU, JPAFSR_FRU_msg },
760 /* These two do not update the AFAR. */
761 { CHAFSR_IVU, CHAFSR_IVU_msg },
762 { 0, NULL },
763};
764static struct afsr_error_table *cheetah_error_table;
765static unsigned long cheetah_afsr_errors;
766
1da177e4
LT		 767struct cheetah_err_info *cheetah_error_log;
768
d979f179 769static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
1da177e4
LT		 770{
771 struct cheetah_err_info *p;
772 int cpu = smp_processor_id();
773
774 if (!cheetah_error_log)
775 return NULL;
776
777 p = cheetah_error_log + (cpu * 2);
778 if ((afsr & CHAFSR_TL1) != 0UL)
779 p++;
780
781 return p;
782}
783
784extern unsigned int tl0_icpe[], tl1_icpe[];
785extern unsigned int tl0_dcpe[], tl1_dcpe[];
786extern unsigned int tl0_fecc[], tl1_fecc[];
787extern unsigned int tl0_cee[], tl1_cee[];
788extern unsigned int tl0_iae[], tl1_iae[];
789extern unsigned int tl0_dae[], tl1_dae[];
790extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
791extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
792extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
793extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
794extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
795
796void __init cheetah_ecache_flush_init(void)
797{
798 unsigned long largest_size, smallest_linesize, order, ver;
5cbc3073 799 int i, sz;
1da177e4
LT		 800
801 /* Scan all cpu device tree nodes, note two values:
802 * 1) largest E-cache size
803 * 2) smallest E-cache line size
804 */
805 largest_size = 0UL;
806 smallest_linesize = ~0UL;
807
5cbc3073 808 for (i = 0; i < NR_CPUS; i++) {
1da177e4
LT		 809 unsigned long val;
810
5cbc3073
DM		 811 val = cpu_data(i).ecache_size;
812 if (!val)
813 continue;
814
1da177e4
LT		 815 if (val > largest_size)
816 largest_size = val;
5cbc3073
DM		 817
818 val = cpu_data(i).ecache_line_size;
1da177e4
LT		 819 if (val < smallest_linesize)
820 smallest_linesize = val;
5cbc3073 821
1da177e4
LT		 822 }
823
824 if (largest_size == 0UL || smallest_linesize == ~0UL) {
825 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
826 "parameters.\n");
827 prom_halt();
828 }
829
830 ecache_flush_size = (2 * largest_size);
831 ecache_flush_linesize = smallest_linesize;
832
10147570 833 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
1da177e4 834
10147570 835 if (ecache_flush_physbase == ~0UL) {
1da177e4 836 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
10147570
DM		 837 "contiguous physical memory.\n",
838 ecache_flush_size);
1da177e4
LT		 839 prom_halt();
840 }
841
842 /* Now allocate error trap reporting scoreboard. */
07f8e5f3 843 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
1da177e4 844 for (order = 0; order < MAX_ORDER; order++) {
07f8e5f3 845 if ((PAGE_SIZE << order) >= sz)
1da177e4
LT		 846 break;
847 }
848 cheetah_error_log = (struct cheetah_err_info *)
849 __get_free_pages(GFP_KERNEL, order);
850 if (!cheetah_error_log) {
851 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
07f8e5f3 852 "error logging scoreboard (%d bytes).\n", sz);
1da177e4
LT		 853 prom_halt();
854 }
855 memset(cheetah_error_log, 0, PAGE_SIZE << order);
856
857 /* Mark all AFSRs as invalid so that the trap handler will
858 * log new new information there.
859 */
860 for (i = 0; i < 2 * NR_CPUS; i++)
861 cheetah_error_log[i].afsr = CHAFSR_INVALID;
862
863 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
92704a1c
DM		 864 if ((ver >> 32) == __JALAPENO_ID ||
865 (ver >> 32) == __SERRANO_ID) {
1da177e4
LT		 866 cheetah_error_table = &__jalapeno_error_table[0];
867 cheetah_afsr_errors = JPAFSR_ERRORS;
868 } else if ((ver >> 32) == 0x003e0015) {
869 cheetah_error_table = &__cheetah_plus_error_table[0];
870 cheetah_afsr_errors = CHPAFSR_ERRORS;
871 } else {
872 cheetah_error_table = &__cheetah_error_table[0];
873 cheetah_afsr_errors = CHAFSR_ERRORS;
874 }
875
876 /* Now patch trap tables. */
877 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
878 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
879 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
880 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
881 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
882 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
883 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
884 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
885 if (tlb_type == cheetah_plus) {
886 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
887 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
888 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
889 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
890 }
891 flushi(PAGE_OFFSET);
892}
893
894static void cheetah_flush_ecache(void)
895{
896 unsigned long flush_base = ecache_flush_physbase;
897 unsigned long flush_linesize = ecache_flush_linesize;
898 unsigned long flush_size = ecache_flush_size;
899
900 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
901 " bne,pt %%xcc, 1b\n\t"
902 " ldxa [%2 + %0] %3, %%g0\n\t"
903 : "=&r" (flush_size)
904 : "0" (flush_size), "r" (flush_base),
905 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
906}
907
908static void cheetah_flush_ecache_line(unsigned long physaddr)
909{
910 unsigned long alias;
911
912 physaddr &= ~(8UL - 1UL);
913 physaddr = (ecache_flush_physbase +
914 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
915 alias = physaddr + (ecache_flush_size >> 1UL);
916 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
917 "ldxa [%1] %2, %%g0\n\t"
918 "membar #Sync"
919 : /* no outputs */
920 : "r" (physaddr), "r" (alias),
921 "i" (ASI_PHYS_USE_EC));
922}
923
924/* Unfortunately, the diagnostic access to the I-cache tags we need to
925 * use to clear the thing interferes with I-cache coherency transactions.
926 *
927 * So we must only flush the I-cache when it is disabled.
928 */
929static void __cheetah_flush_icache(void)
930{
80dc0d6b
DM		 931 unsigned int icache_size, icache_line_size;
932 unsigned long addr;
933
934 icache_size = local_cpu_data().icache_size;
935 icache_line_size = local_cpu_data().icache_line_size;
1da177e4
LT		 936
937 /* Clear the valid bits in all the tags. */
80dc0d6b 938 for (addr = 0; addr < icache_size; addr += icache_line_size) {
1da177e4
LT		 939 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
940 "membar #Sync"
941 : /* no outputs */
80dc0d6b
DM		 942 : "r" (addr | (2 << 3)),
943 "i" (ASI_IC_TAG));
1da177e4
LT		 944 }
945}
946
947static void cheetah_flush_icache(void)
948{
949 unsigned long dcu_save;
950
951 /* Save current DCU, disable I-cache. */
952 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
953 "or %0, %2, %%g1\n\t"
954 "stxa %%g1, [%%g0] %1\n\t"
955 "membar #Sync"
956 : "=r" (dcu_save)
957 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
958 : "g1");
959
960 __cheetah_flush_icache();
961
962 /* Restore DCU register */
963 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
964 "membar #Sync"
965 : /* no outputs */
966 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
967}
968
969static void cheetah_flush_dcache(void)
970{
80dc0d6b
DM		 971 unsigned int dcache_size, dcache_line_size;
972 unsigned long addr;
973
974 dcache_size = local_cpu_data().dcache_size;
975 dcache_line_size = local_cpu_data().dcache_line_size;
1da177e4 976
80dc0d6b 977 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1da177e4
LT		 978 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
979 "membar #Sync"
980 : /* no outputs */
80dc0d6b 981 : "r" (addr), "i" (ASI_DCACHE_TAG));
1da177e4
LT		 982 }
983}
984
985/* In order to make the even parity correct we must do two things.
986 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
987 * Next, we clear out all 32-bytes of data for that line. Data of
988 * all-zero + tag parity value of zero == correct parity.
989 */
990static void cheetah_plus_zap_dcache_parity(void)
991{
80dc0d6b
DM		 992 unsigned int dcache_size, dcache_line_size;
993 unsigned long addr;
994
995 dcache_size = local_cpu_data().dcache_size;
996 dcache_line_size = local_cpu_data().dcache_line_size;
1da177e4 997
80dc0d6b
DM		 998 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
999 unsigned long tag = (addr >> 14);
1000 unsigned long line;
1da177e4
LT		 1001
1002 __asm__ __volatile__("membar #Sync\n\t"
1003 "stxa %0, [%1] %2\n\t"
1004 "membar #Sync"
1005 : /* no outputs */
80dc0d6b 1006 : "r" (tag), "r" (addr),
1da177e4 1007 "i" (ASI_DCACHE_UTAG));
80dc0d6b 1008 for (line = addr; line < addr + dcache_line_size; line += 8)
1da177e4
LT		 1009 __asm__ __volatile__("membar #Sync\n\t"
1010 "stxa %%g0, [%0] %1\n\t"
1011 "membar #Sync"
1012 : /* no outputs */
80dc0d6b
DM		 1013 : "r" (line),
1014 "i" (ASI_DCACHE_DATA));
1da177e4
LT		 1015 }
1016}
1017
1018/* Conversion tables used to frob Cheetah AFSR syndrome values into
1019 * something palatable to the memory controller driver get_unumber
1020 * routine.
1021 */
1022#define MT0 137
1023#define MT1 138
1024#define MT2 139
1025#define NONE 254
1026#define MTC0 140
1027#define MTC1 141
1028#define MTC2 142
1029#define MTC3 143
1030#define C0 128
1031#define C1 129
1032#define C2 130
1033#define C3 131
1034#define C4 132
1035#define C5 133
1036#define C6 134
1037#define C7 135
1038#define C8 136
1039#define M2 144
1040#define M3 145
1041#define M4 146
1042#define M 147
1043static unsigned char cheetah_ecc_syntab[] = {
1044/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1045/*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1046/*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1047/*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1048/*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1049/*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1050/*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1051/*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1052/*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1053/*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1054/*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1055/*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1056/*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1057/*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1058/*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1059/*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1060/*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1061/*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1062/*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1063/*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1064/*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1065/*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1066/*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1067/*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1068/*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1069/*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1070/*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1071/*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1072/*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1073/*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1074/*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1075/*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1076};
1077static unsigned char cheetah_mtag_syntab[] = {
1078 NONE, MTC0,
1079 MTC1, NONE,
1080 MTC2, NONE,
1081 NONE, MT0,
1082 MTC3, NONE,
1083 NONE, MT1,
1084 NONE, MT2,
1085 NONE, NONE
1086};
1087
1088/* Return the highest priority error conditon mentioned. */
d979f179 1089static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1da177e4
LT		 1090{
1091 unsigned long tmp = 0;
1092 int i;
1093
1094 for (i = 0; cheetah_error_table[i].mask; i++) {
1095 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1096 return tmp;
1097 }
1098 return tmp;
1099}
1100
1101static const char *cheetah_get_string(unsigned long bit)
1102{
1103 int i;
1104
1105 for (i = 0; cheetah_error_table[i].mask; i++) {
1106 if ((bit & cheetah_error_table[i].mask) != 0UL)
1107 return cheetah_error_table[i].name;
1108 }
1109 return "???";
1110}
1111
1da177e4
LT		 1112static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1113 unsigned long afsr, unsigned long afar, int recoverable)
1114{
1115 unsigned long hipri;
1116 char unum[256];
1117
1118 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1119 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1120 afsr, afar,
1121 (afsr & CHAFSR_TL1) ? 1 : 0);
955c054f 1122 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1da177e4 1123 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
955c054f 1124 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
5af47db7
DM		 1125 printk("%s" "ERROR(%d): ",
1126 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
4fe3ebec 1127 printk("TPC<%pS>\n", (void *) regs->tpc);
1da177e4
LT		 1128 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1129 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1130 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1131 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1132 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1133 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1134 hipri = cheetah_get_hipri(afsr);
1135 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1136 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1137 hipri, cheetah_get_string(hipri));
1138
1139 /* Try to get unumber if relevant. */
1140#define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1141 CHAFSR_CPC | CHAFSR_CPU | \
1142 CHAFSR_UE | CHAFSR_CE | \
1143 CHAFSR_EDC | CHAFSR_EDU | \
1144 CHAFSR_UCC | CHAFSR_UCU | \
1145 CHAFSR_WDU | CHAFSR_WDC)
1146#define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1147 if (afsr & ESYND_ERRORS) {
1148 int syndrome;
1149 int ret;
1150
1151 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1152 syndrome = cheetah_ecc_syntab[syndrome];
881d021a 1153 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1da177e4
LT		 1154 if (ret != -1)
1155 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1156 (recoverable ? KERN_WARNING : KERN_CRIT),
1157 smp_processor_id(), unum);
1158 } else if (afsr & MSYND_ERRORS) {
1159 int syndrome;
1160 int ret;
1161
1162 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1163 syndrome = cheetah_mtag_syntab[syndrome];
881d021a 1164 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1da177e4
LT		 1165 if (ret != -1)
1166 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1167 (recoverable ? KERN_WARNING : KERN_CRIT),
1168 smp_processor_id(), unum);
1169 }
1170
1171 /* Now dump the cache snapshots. */
1172 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1173 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1174 (int) info->dcache_index,
1175 info->dcache_tag,
1176 info->dcache_utag,
1177 info->dcache_stag);
1178 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1179 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1180 info->dcache_data[0],
1181 info->dcache_data[1],
1182 info->dcache_data[2],
1183 info->dcache_data[3]);
1184 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1185 "u[%016lx] l[%016lx]\n",
1186 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1187 (int) info->icache_index,
1188 info->icache_tag,
1189 info->icache_utag,
1190 info->icache_stag,
1191 info->icache_upper,
1192 info->icache_lower);
1193 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1194 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1195 info->icache_data[0],
1196 info->icache_data[1],
1197 info->icache_data[2],
1198 info->icache_data[3]);
1199 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1200 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1201 info->icache_data[4],
1202 info->icache_data[5],
1203 info->icache_data[6],
1204 info->icache_data[7]);
1205 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1206 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1207 (int) info->ecache_index, info->ecache_tag);
1208 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1209 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1210 info->ecache_data[0],
1211 info->ecache_data[1],
1212 info->ecache_data[2],
1213 info->ecache_data[3]);
1214
1215 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1216 while (afsr != 0UL) {
1217 unsigned long bit = cheetah_get_hipri(afsr);
1218
1219 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1220 (recoverable ? KERN_WARNING : KERN_CRIT),
1221 bit, cheetah_get_string(bit));
1222
1223 afsr &= ~bit;
1224 }
1225
1226 if (!recoverable)
1227 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1228}
1229
1230static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1231{
1232 unsigned long afsr, afar;
1233 int ret = 0;
1234
1235 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1236 : "=r" (afsr)
1237 : "i" (ASI_AFSR));
1238 if ((afsr & cheetah_afsr_errors) != 0) {
1239 if (logp != NULL) {
1240 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1241 : "=r" (afar)
1242 : "i" (ASI_AFAR));
1243 logp->afsr = afsr;
1244 logp->afar = afar;
1245 }
1246 ret = 1;
1247 }
1248 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1249 "membar #Sync\n\t"
1250 : : "r" (afsr), "i" (ASI_AFSR));
1251
1252 return ret;
1253}
1254
1255void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1256{
1257 struct cheetah_err_info local_snapshot, *p;
1258 int recoverable;
1259
1260 /* Flush E-cache */
1261 cheetah_flush_ecache();
1262
1263 p = cheetah_get_error_log(afsr);
1264 if (!p) {
1265 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1266 afsr, afar);
1267 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1268 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1269 prom_halt();
1270 }
1271
1272 /* Grab snapshot of logged error. */
1273 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1274
1275 /* If the current trap snapshot does not match what the
1276 * trap handler passed along into our args, big trouble.
1277 * In such a case, mark the local copy as invalid.
1278 *
1279 * Else, it matches and we mark the afsr in the non-local
1280 * copy as invalid so we may log new error traps there.
1281 */
1282 if (p->afsr != afsr || p->afar != afar)
1283 local_snapshot.afsr = CHAFSR_INVALID;
1284 else
1285 p->afsr = CHAFSR_INVALID;
1286
1287 cheetah_flush_icache();
1288 cheetah_flush_dcache();
1289
1290 /* Re-enable I-cache/D-cache */
1291 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1292 "or %%g1, %1, %%g1\n\t"
1293 "stxa %%g1, [%%g0] %0\n\t"
1294 "membar #Sync"
1295 : /* no outputs */
1296 : "i" (ASI_DCU_CONTROL_REG),
1297 "i" (DCU_DC | DCU_IC)
1298 : "g1");
1299
1300 /* Re-enable error reporting */
1301 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1302 "or %%g1, %1, %%g1\n\t"
1303 "stxa %%g1, [%%g0] %0\n\t"
1304 "membar #Sync"
1305 : /* no outputs */
1306 : "i" (ASI_ESTATE_ERROR_EN),
1307 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1308 : "g1");
1309
1310 /* Decide if we can continue after handling this trap and
1311 * logging the error.
1312 */
1313 recoverable = 1;
1314 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1315 recoverable = 0;
1316
1317 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1318 * error was logged while we had error reporting traps disabled.
1319 */
1320 if (cheetah_recheck_errors(&local_snapshot)) {
1321 unsigned long new_afsr = local_snapshot.afsr;
1322
1323 /* If we got a new asynchronous error, die... */
1324 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1325 CHAFSR_WDU | CHAFSR_CPU |
1326 CHAFSR_IVU | CHAFSR_UE |
1327 CHAFSR_BERR | CHAFSR_TO))
1328 recoverable = 0;
1329 }
1330
1331 /* Log errors. */
1332 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1333
1334 if (!recoverable)
1335 panic("Irrecoverable Fast-ECC error trap.\n");
1336
1337 /* Flush E-cache to kick the error trap handlers out. */
1338 cheetah_flush_ecache();
1339}
1340
1341/* Try to fix a correctable error by pushing the line out from
1342 * the E-cache. Recheck error reporting registers to see if the
1343 * problem is intermittent.
1344 */
1345static int cheetah_fix_ce(unsigned long physaddr)
1346{
1347 unsigned long orig_estate;
1348 unsigned long alias1, alias2;
1349 int ret;
1350
1351 /* Make sure correctable error traps are disabled. */
1352 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1353 "andn %0, %1, %%g1\n\t"
1354 "stxa %%g1, [%%g0] %2\n\t"
1355 "membar #Sync"
1356 : "=&r" (orig_estate)
1357 : "i" (ESTATE_ERROR_CEEN),
1358 "i" (ASI_ESTATE_ERROR_EN)
1359 : "g1");
1360
1361 /* We calculate alias addresses that will force the
1362 * cache line in question out of the E-cache. Then
1363 * we bring it back in with an atomic instruction so
1364 * that we get it in some modified/exclusive state,
1365 * then we displace it again to try and get proper ECC
1366 * pushed back into the system.
1367 */
1368 physaddr &= ~(8UL - 1UL);
1369 alias1 = (ecache_flush_physbase +
1370 (physaddr & ((ecache_flush_size >> 1) - 1)));
1371 alias2 = alias1 + (ecache_flush_size >> 1);
1372 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1373 "ldxa [%1] %3, %%g0\n\t"
1374 "casxa [%2] %3, %%g0, %%g0\n\t"
1375 "membar #StoreLoad | #StoreStore\n\t"
1376 "ldxa [%0] %3, %%g0\n\t"
1377 "ldxa [%1] %3, %%g0\n\t"
1378 "membar #Sync"
1379 : /* no outputs */
1380 : "r" (alias1), "r" (alias2),
1381 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1382
1383 /* Did that trigger another error? */
1384 if (cheetah_recheck_errors(NULL)) {
1385 /* Try one more time. */
1386 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1387 "membar #Sync"
1388 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1389 if (cheetah_recheck_errors(NULL))
1390 ret = 2;
1391 else
1392 ret = 1;
1393 } else {
1394 /* No new error, intermittent problem. */
1395 ret = 0;
1396 }
1397
1398 /* Restore error enables. */
1399 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1400 "membar #Sync"
1401 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1402
1403 return ret;
1404}
1405
1406/* Return non-zero if PADDR is a valid physical memory address. */
1407static int cheetah_check_main_memory(unsigned long paddr)
1408{
10147570 1409 unsigned long vaddr = PAGE_OFFSET + paddr;
1da177e4 1410
13edad7a 1411 if (vaddr > (unsigned long) high_memory)
ed3ffaf7
DM		 1412 return 0;
1413
10147570 1414 return kern_addr_valid(vaddr);
1da177e4
LT		 1415}
1416
1417void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1418{
1419 struct cheetah_err_info local_snapshot, *p;
1420 int recoverable, is_memory;
1421
1422 p = cheetah_get_error_log(afsr);
1423 if (!p) {
1424 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1425 afsr, afar);
1426 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1427 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1428 prom_halt();
1429 }
1430
1431 /* Grab snapshot of logged error. */
1432 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1433
1434 /* If the current trap snapshot does not match what the
1435 * trap handler passed along into our args, big trouble.
1436 * In such a case, mark the local copy as invalid.
1437 *
1438 * Else, it matches and we mark the afsr in the non-local
1439 * copy as invalid so we may log new error traps there.
1440 */
1441 if (p->afsr != afsr || p->afar != afar)
1442 local_snapshot.afsr = CHAFSR_INVALID;
1443 else
1444 p->afsr = CHAFSR_INVALID;
1445
1446 is_memory = cheetah_check_main_memory(afar);
1447
1448 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1449 /* XXX Might want to log the results of this operation
1450 * XXX somewhere... -DaveM
1451 */
1452 cheetah_fix_ce(afar);
1453 }
1454
1455 {
1456 int flush_all, flush_line;
1457
1458 flush_all = flush_line = 0;
1459 if ((afsr & CHAFSR_EDC) != 0UL) {
1460 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1461 flush_line = 1;
1462 else
1463 flush_all = 1;
1464 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1465 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1466 flush_line = 1;
1467 else
1468 flush_all = 1;
1469 }
1470
1471 /* Trap handler only disabled I-cache, flush it. */
1472 cheetah_flush_icache();
1473
1474 /* Re-enable I-cache */
1475 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1476 "or %%g1, %1, %%g1\n\t"
1477 "stxa %%g1, [%%g0] %0\n\t"
1478 "membar #Sync"
1479 : /* no outputs */
1480 : "i" (ASI_DCU_CONTROL_REG),
1481 "i" (DCU_IC)
1482 : "g1");
1483
1484 if (flush_all)
1485 cheetah_flush_ecache();
1486 else if (flush_line)
1487 cheetah_flush_ecache_line(afar);
1488 }
1489
1490 /* Re-enable error reporting */
1491 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1492 "or %%g1, %1, %%g1\n\t"
1493 "stxa %%g1, [%%g0] %0\n\t"
1494 "membar #Sync"
1495 : /* no outputs */
1496 : "i" (ASI_ESTATE_ERROR_EN),
1497 "i" (ESTATE_ERROR_CEEN)
1498 : "g1");
1499
1500 /* Decide if we can continue after handling this trap and
1501 * logging the error.
1502 */
1503 recoverable = 1;
1504 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1505 recoverable = 0;
1506
1507 /* Re-check AFSR/AFAR */
1508 (void) cheetah_recheck_errors(&local_snapshot);
1509
1510 /* Log errors. */
1511 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1512
1513 if (!recoverable)
1514 panic("Irrecoverable Correctable-ECC error trap.\n");
1515}
1516
1517void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1518{
1519 struct cheetah_err_info local_snapshot, *p;
1520 int recoverable, is_memory;
1521
1522#ifdef CONFIG_PCI
1523 /* Check for the special PCI poke sequence. */
1524 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1525 cheetah_flush_icache();
1526 cheetah_flush_dcache();
1527
1528 /* Re-enable I-cache/D-cache */
1529 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1530 "or %%g1, %1, %%g1\n\t"
1531 "stxa %%g1, [%%g0] %0\n\t"
1532 "membar #Sync"
1533 : /* no outputs */
1534 : "i" (ASI_DCU_CONTROL_REG),
1535 "i" (DCU_DC | DCU_IC)
1536 : "g1");
1537
1538 /* Re-enable error reporting */
1539 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1540 "or %%g1, %1, %%g1\n\t"
1541 "stxa %%g1, [%%g0] %0\n\t"
1542 "membar #Sync"
1543 : /* no outputs */
1544 : "i" (ASI_ESTATE_ERROR_EN),
1545 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1546 : "g1");
1547
1548 (void) cheetah_recheck_errors(NULL);
1549
1550 pci_poke_faulted = 1;
1551 regs->tpc += 4;
1552 regs->tnpc = regs->tpc + 4;
1553 return;
1554 }
1555#endif
1556
1557 p = cheetah_get_error_log(afsr);
1558 if (!p) {
1559 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1560 afsr, afar);
1561 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1562 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1563 prom_halt();
1564 }
1565
1566 /* Grab snapshot of logged error. */
1567 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1568
1569 /* If the current trap snapshot does not match what the
1570 * trap handler passed along into our args, big trouble.
1571 * In such a case, mark the local copy as invalid.
1572 *
1573 * Else, it matches and we mark the afsr in the non-local
1574 * copy as invalid so we may log new error traps there.
1575 */
1576 if (p->afsr != afsr || p->afar != afar)
1577 local_snapshot.afsr = CHAFSR_INVALID;
1578 else
1579 p->afsr = CHAFSR_INVALID;
1580
1581 is_memory = cheetah_check_main_memory(afar);
1582
1583 {
1584 int flush_all, flush_line;
1585
1586 flush_all = flush_line = 0;
1587 if ((afsr & CHAFSR_EDU) != 0UL) {
1588 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1589 flush_line = 1;
1590 else
1591 flush_all = 1;
1592 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1593 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1594 flush_line = 1;
1595 else
1596 flush_all = 1;
1597 }
1598
1599 cheetah_flush_icache();
1600 cheetah_flush_dcache();
1601
1602 /* Re-enable I/D caches */
1603 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1604 "or %%g1, %1, %%g1\n\t"
1605 "stxa %%g1, [%%g0] %0\n\t"
1606 "membar #Sync"
1607 : /* no outputs */
1608 : "i" (ASI_DCU_CONTROL_REG),
1609 "i" (DCU_IC | DCU_DC)
1610 : "g1");
1611
1612 if (flush_all)
1613 cheetah_flush_ecache();
1614 else if (flush_line)
1615 cheetah_flush_ecache_line(afar);
1616 }
1617
1618 /* Re-enable error reporting */
1619 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1620 "or %%g1, %1, %%g1\n\t"
1621 "stxa %%g1, [%%g0] %0\n\t"
1622 "membar #Sync"
1623 : /* no outputs */
1624 : "i" (ASI_ESTATE_ERROR_EN),
1625 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1626 : "g1");
1627
1628 /* Decide if we can continue after handling this trap and
1629 * logging the error.
1630 */
1631 recoverable = 1;
1632 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1633 recoverable = 0;
1634
1635 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1636 * error was logged while we had error reporting traps disabled.
1637 */
1638 if (cheetah_recheck_errors(&local_snapshot)) {
1639 unsigned long new_afsr = local_snapshot.afsr;
1640
1641 /* If we got a new asynchronous error, die... */
1642 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1643 CHAFSR_WDU | CHAFSR_CPU |
1644 CHAFSR_IVU | CHAFSR_UE |
1645 CHAFSR_BERR | CHAFSR_TO))
1646 recoverable = 0;
1647 }
1648
1649 /* Log errors. */
1650 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1651
1652 /* "Recoverable" here means we try to yank the page from ever
1653 * being newly used again. This depends upon a few things:
1654 * 1) Must be main memory, and AFAR must be valid.
1655 * 2) If we trapped from user, OK.
1656 * 3) Else, if we trapped from kernel we must find exception
1657 * table entry (ie. we have to have been accessing user
1658 * space).
1659 *
1660 * If AFAR is not in main memory, or we trapped from kernel
1661 * and cannot find an exception table entry, it is unacceptable
1662 * to try and continue.
1663 */
1664 if (recoverable && is_memory) {
1665 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1666 /* OK, usermode access. */
1667 recoverable = 1;
1668 } else {
8cf14af0 1669 const struct exception_table_entry *entry;
1da177e4 1670
8cf14af0
DM		 1671 entry = search_exception_tables(regs->tpc);
1672 if (entry) {
1da177e4
LT		 1673 /* OK, kernel access to userspace. */
1674 recoverable = 1;
1675
1676 } else {
1677 /* BAD, privileged state is corrupted. */
1678 recoverable = 0;
1679 }
1680
1681 if (recoverable) {
1682 if (pfn_valid(afar >> PAGE_SHIFT))
1683 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1684 else
1685 recoverable = 0;
1686
1687 /* Only perform fixup if we still have a
1688 * recoverable condition.
1689 */
1690 if (recoverable) {
8cf14af0 1691 regs->tpc = entry->fixup;
1da177e4 1692 regs->tnpc = regs->tpc + 4;
1da177e4
LT		 1693 }
1694 }
1695 }
1696 } else {
1697 recoverable = 0;
1698 }
1699
1700 if (!recoverable)
1701 panic("Irrecoverable deferred error trap.\n");
1702}
1703
1704/* Handle a D/I cache parity error trap. TYPE is encoded as:
1705 *
1706 * Bit0: 0=dcache,1=icache
1707 * Bit1: 0=recoverable,1=unrecoverable
1708 *
1709 * The hardware has disabled both the I-cache and D-cache in
1710 * the %dcr register.
1711 */
1712void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1713{
1714 if (type & 0x1)
1715 __cheetah_flush_icache();
1716 else
1717 cheetah_plus_zap_dcache_parity();
1718 cheetah_flush_dcache();
1719
1720 /* Re-enable I-cache/D-cache */
1721 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1722 "or %%g1, %1, %%g1\n\t"
1723 "stxa %%g1, [%%g0] %0\n\t"
1724 "membar #Sync"
1725 : /* no outputs */
1726 : "i" (ASI_DCU_CONTROL_REG),
1727 "i" (DCU_DC | DCU_IC)
1728 : "g1");
1729
1730 if (type & 0x2) {
1731 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1732 smp_processor_id(),
1733 (type & 0x1) ? 'I' : 'D',
1734 regs->tpc);
4fe3ebec 1735 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1da177e4
LT		 1736 panic("Irrecoverable Cheetah+ parity error.");
1737 }
1738
1739 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1740 smp_processor_id(),
1741 (type & 0x1) ? 'I' : 'D',
1742 regs->tpc);
4fe3ebec 1743 printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1da177e4
LT		 1744}
1745
5b0c0572
DM		 1746struct sun4v_error_entry {
1747 u64 err_handle;
1748 u64 err_stick;
1749
1750 u32 err_type;
1751#define SUN4V_ERR_TYPE_UNDEFINED 0
1752#define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1753#define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1754#define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1755#define SUN4V_ERR_TYPE_WARNING_RES 4
1756
1757 u32 err_attrs;
1758#define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1759#define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1760#define SUN4V_ERR_ATTRS_PIO 0x00000004
1761#define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1762#define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1763#define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1764#define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1765#define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1766
1767 u64 err_raddr;
1768 u32 err_size;
1769 u16 err_cpu;
1770 u16 err_pad;
1771};
1772
1773static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1774static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1775
1776static const char *sun4v_err_type_to_str(u32 type)
1777{
1778 switch (type) {
1779 case SUN4V_ERR_TYPE_UNDEFINED:
1780 return "undefined";
1781 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1782 return "uncorrected resumable";
1783 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1784 return "precise nonresumable";
1785 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1786 return "deferred nonresumable";
1787 case SUN4V_ERR_TYPE_WARNING_RES:
1788 return "warning resumable";
1789 default:
1790 return "unknown";
1791 };
1792}
1793
5224e6cc 1794static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
5b0c0572
DM		 1795{
1796 int cnt;
1797
1798 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1799 printk("%s: err_handle[%lx] err_stick[%lx] err_type[%08x:%s]\n",
1800 pfx,
1801 ent->err_handle, ent->err_stick,
1802 ent->err_type,
1803 sun4v_err_type_to_str(ent->err_type));
1804 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1805 pfx,
1806 ent->err_attrs,
1807 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1808 "processor" : ""),
1809 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1810 "memory" : ""),
1811 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1812 "pio" : ""),
1813 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1814 "integer-regs" : ""),
1815 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1816 "fpu-regs" : ""),
1817 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1818 "user" : ""),
1819 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1820 "privileged" : ""),
1821 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1822 "queue-full" : ""));
1823 printk("%s: err_raddr[%016lx] err_size[%u] err_cpu[%u]\n",
1824 pfx,
1825 ent->err_raddr, ent->err_size, ent->err_cpu);
1826
dbf3e950 1827 show_regs(regs);
5224e6cc 1828
5b0c0572
DM		 1829 if ((cnt = atomic_read(ocnt)) != 0) {
1830 atomic_set(ocnt, 0);
1831 wmb();
1832 printk("%s: Queue overflowed %d times.\n",
1833 pfx, cnt);
1834 }
1835}
1836
1837/* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1838 * Log the event and clear the first word of the entry.
1839 */
1840void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1841{
1842 struct sun4v_error_entry *ent, local_copy;
1843 struct trap_per_cpu *tb;
1844 unsigned long paddr;
1845 int cpu;
1846
1847 cpu = get_cpu();
1848
1849 tb = &trap_block[cpu];
1850 paddr = tb->resum_kernel_buf_pa + offset;
1851 ent = __va(paddr);
1852
1853 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1854
1855 /* We have a local copy now, so release the entry. */
1856 ent->err_handle = 0;
1857 wmb();
1858
1859 put_cpu();
1860
a2c1e064
DM		 1861 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1862 /* If err_type is 0x4, it's a powerdown request. Do
1863 * not do the usual resumable error log because that
1864 * makes it look like some abnormal error.
1865 */
1866 printk(KERN_INFO "Power down request...\n");
1867 kill_cad_pid(SIGINT, 1);
1868 return;
1869 }
1870
5224e6cc 1871 sun4v_log_error(regs, &local_copy, cpu,
5b0c0572
DM		 1872 KERN_ERR "RESUMABLE ERROR",
1873 &sun4v_resum_oflow_cnt);
1874}
1875
1876/* If we try to printk() we'll probably make matters worse, by trying
1877 * to retake locks this cpu already holds or causing more errors. So
1878 * just bump a counter, and we'll report these counter bumps above.
1879 */
1880void sun4v_resum_overflow(struct pt_regs *regs)
1881{
1882 atomic_inc(&sun4v_resum_oflow_cnt);
1883}
1884
1885/* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1886 * Log the event, clear the first word of the entry, and die.
1887 */
1888void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1889{
1890 struct sun4v_error_entry *ent, local_copy;
1891 struct trap_per_cpu *tb;
1892 unsigned long paddr;
1893 int cpu;
1894
1895 cpu = get_cpu();
1896
1897 tb = &trap_block[cpu];
1898 paddr = tb->nonresum_kernel_buf_pa + offset;
1899 ent = __va(paddr);
1900
1901 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1902
1903 /* We have a local copy now, so release the entry. */
1904 ent->err_handle = 0;
1905 wmb();
1906
1907 put_cpu();
1908
1909#ifdef CONFIG_PCI
1910 /* Check for the special PCI poke sequence. */
1911 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1912 pci_poke_faulted = 1;
1913 regs->tpc += 4;
1914 regs->tnpc = regs->tpc + 4;
1915 return;
1916 }
1917#endif
1918
5224e6cc 1919 sun4v_log_error(regs, &local_copy, cpu,
5b0c0572
DM		 1920 KERN_EMERG "NON-RESUMABLE ERROR",
1921 &sun4v_nonresum_oflow_cnt);
1922
1923 panic("Non-resumable error.");
1924}
1925
1926/* If we try to printk() we'll probably make matters worse, by trying
1927 * to retake locks this cpu already holds or causing more errors. So
1928 * just bump a counter, and we'll report these counter bumps above.
1929 */
1930void sun4v_nonresum_overflow(struct pt_regs *regs)
1931{
1932 /* XXX Actually even this can make not that much sense. Perhaps
1933 * XXX we should just pull the plug and panic directly from here?
1934 */
1935 atomic_inc(&sun4v_nonresum_oflow_cnt);
1936}
1937
6c8927c9
DM		 1938unsigned long sun4v_err_itlb_vaddr;
1939unsigned long sun4v_err_itlb_ctx;
1940unsigned long sun4v_err_itlb_pte;
1941unsigned long sun4v_err_itlb_error;
1942
1943void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1944{
1945 if (tl > 1)
1946 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1947
04d74758
DM		 1948 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1949 regs->tpc, tl);
4fe3ebec 1950 printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
6320bceb 1951 printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
4fe3ebec
DM		 1952 printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
1953 (void *) regs->u_regs[UREG_I7]);
04d74758
DM		 1954 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1955 "pte[%lx] error[%lx]\n",
6c8927c9
DM		 1956 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1957 sun4v_err_itlb_pte, sun4v_err_itlb_error);
04d74758 1958
6c8927c9
DM		 1959 prom_halt();
1960}
1961
1962unsigned long sun4v_err_dtlb_vaddr;
1963unsigned long sun4v_err_dtlb_ctx;
1964unsigned long sun4v_err_dtlb_pte;
1965unsigned long sun4v_err_dtlb_error;
1966
1967void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1968{
1969 if (tl > 1)
1970 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1971
04d74758
DM		 1972 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1973 regs->tpc, tl);
4fe3ebec 1974 printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
6320bceb 1975 printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
4fe3ebec
DM		 1976 printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
1977 (void *) regs->u_regs[UREG_I7]);
04d74758
DM		 1978 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1979 "pte[%lx] error[%lx]\n",
6c8927c9
DM		 1980 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1981 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
04d74758 1982
6c8927c9
DM		 1983 prom_halt();
1984}
1985
2a3a5f5d
DM		 1986void hypervisor_tlbop_error(unsigned long err, unsigned long op)
1987{
1988 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
1989 err, op);
1990}
1991
1992void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
1993{
1994 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
1995 err, op);
1996}
1997
1da177e4
LT		 1998void do_fpe_common(struct pt_regs *regs)
1999{
2000 if (regs->tstate & TSTATE_PRIV) {
2001 regs->tpc = regs->tnpc;
2002 regs->tnpc += 4;
2003 } else {
2004 unsigned long fsr = current_thread_info()->xfsr[0];
2005 siginfo_t info;
2006
2007 if (test_thread_flag(TIF_32BIT)) {
2008 regs->tpc &= 0xffffffff;
2009 regs->tnpc &= 0xffffffff;
2010 }
2011 info.si_signo = SIGFPE;
2012 info.si_errno = 0;
2013 info.si_addr = (void __user *)regs->tpc;
2014 info.si_trapno = 0;
2015 info.si_code = __SI_FAULT;
2016 if ((fsr & 0x1c000) == (1 << 14)) {
2017 if (fsr & 0x10)
2018 info.si_code = FPE_FLTINV;
2019 else if (fsr & 0x08)
2020 info.si_code = FPE_FLTOVF;
2021 else if (fsr & 0x04)
2022 info.si_code = FPE_FLTUND;
2023 else if (fsr & 0x02)
2024 info.si_code = FPE_FLTDIV;
2025 else if (fsr & 0x01)
2026 info.si_code = FPE_FLTRES;
2027 }
2028 force_sig_info(SIGFPE, &info, current);
2029 }
2030}
2031
2032void do_fpieee(struct pt_regs *regs)
2033{
2034 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2035 0, 0x24, SIGFPE) == NOTIFY_STOP)
2036 return;
2037
2038 do_fpe_common(regs);
2039}
2040
2041extern int do_mathemu(struct pt_regs *, struct fpustate *);
2042
2043void do_fpother(struct pt_regs *regs)
2044{
2045 struct fpustate *f = FPUSTATE;
2046 int ret = 0;
2047
2048 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2049 0, 0x25, SIGFPE) == NOTIFY_STOP)
2050 return;
2051
2052 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2053 case (2 << 14): /* unfinished_FPop */
2054 case (3 << 14): /* unimplemented_FPop */
2055 ret = do_mathemu(regs, f);
2056 break;
2057 }
2058 if (ret)
2059 return;
2060 do_fpe_common(regs);
2061}
2062
2063void do_tof(struct pt_regs *regs)
2064{
2065 siginfo_t info;
2066
2067 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2068 0, 0x26, SIGEMT) == NOTIFY_STOP)
2069 return;
2070
2071 if (regs->tstate & TSTATE_PRIV)
2072 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2073 if (test_thread_flag(TIF_32BIT)) {
2074 regs->tpc &= 0xffffffff;
2075 regs->tnpc &= 0xffffffff;
2076 }
2077 info.si_signo = SIGEMT;
2078 info.si_errno = 0;
2079 info.si_code = EMT_TAGOVF;
2080 info.si_addr = (void __user *)regs->tpc;
2081 info.si_trapno = 0;
2082 force_sig_info(SIGEMT, &info, current);
2083}
2084
2085void do_div0(struct pt_regs *regs)
2086{
2087 siginfo_t info;
2088
2089 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2090 0, 0x28, SIGFPE) == NOTIFY_STOP)
2091 return;
2092
2093 if (regs->tstate & TSTATE_PRIV)
2094 die_if_kernel("TL0: Kernel divide by zero.", regs);
2095 if (test_thread_flag(TIF_32BIT)) {
2096 regs->tpc &= 0xffffffff;
2097 regs->tnpc &= 0xffffffff;
2098 }
2099 info.si_signo = SIGFPE;
2100 info.si_errno = 0;
2101 info.si_code = FPE_INTDIV;
2102 info.si_addr = (void __user *)regs->tpc;
2103 info.si_trapno = 0;
2104 force_sig_info(SIGFPE, &info, current);
2105}
2106
99cd2201 2107static void instruction_dump(unsigned int *pc)
1da177e4
LT		 2108{
2109 int i;
2110
2111 if ((((unsigned long) pc) & 3))
2112 return;
2113
2114 printk("Instruction DUMP:");
2115 for (i = -3; i < 6; i++)
2116 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2117 printk("\n");
2118}
2119
99cd2201 2120static void user_instruction_dump(unsigned int __user *pc)
1da177e4
LT		 2121{
2122 int i;
2123 unsigned int buf[9];
2124
2125 if ((((unsigned long) pc) & 3))
2126 return;
2127
2128 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2129 return;
2130
2131 printk("Instruction DUMP:");
2132 for (i = 0; i < 9; i++)
2133 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2134 printk("\n");
2135}
2136
2137void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2138{
77c664fa 2139 unsigned long fp, thread_base, ksp;
c1f193a7 2140 struct thread_info *tp;
1da177e4
LT		 2141 int count = 0;
2142
2143 ksp = (unsigned long) _ksp;
c1f193a7
DM		 2144 if (!tsk)
2145 tsk = current;
2146 tp = task_thread_info(tsk);
2147 if (ksp == 0UL) {
2148 if (tsk == current)
2149 asm("mov %%fp, %0" : "=r" (ksp));
2150 else
2151 ksp = tp->ksp;
2152 }
1da177e4
LT		 2153 if (tp == current_thread_info())
2154 flushw_all();
2155
2156 fp = ksp + STACK_BIAS;
2157 thread_base = (unsigned long) tp;
2158
4fe3ebec 2159 printk("Call Trace:\n");
1da177e4 2160 do {
14d2c68b 2161 struct sparc_stackf *sf;
77c664fa
DM		 2162 struct pt_regs *regs;
2163 unsigned long pc;
2164
4f70f7a9 2165 if (!kstack_valid(tp, fp))
1da177e4 2166 break;
14d2c68b
DM		 2167 sf = (struct sparc_stackf *) fp;
2168 regs = (struct pt_regs *) (sf + 1);
77c664fa 2169
4f70f7a9 2170 if (kstack_is_trap_frame(tp, regs)) {
14d2c68b
DM		 2171 if (!(regs->tstate & TSTATE_PRIV))
2172 break;
77c664fa
DM		 2173 pc = regs->tpc;
2174 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2175 } else {
14d2c68b
DM		 2176 pc = sf->callers_pc;
2177 fp = (unsigned long)sf->fp + STACK_BIAS;
77c664fa
DM		 2178 }
2179
4fe3ebec 2180 printk(" [%016lx] %pS\n", pc, (void *) pc);
1da177e4 2181 } while (++count < 16);
1da177e4
LT		 2182}
2183
2184void dump_stack(void)
2185{
c1f193a7 2186 show_stack(current, NULL);
1da177e4
LT		 2187}
2188
2189EXPORT_SYMBOL(dump_stack);
2190
2191static inline int is_kernel_stack(struct task_struct *task,
2192 struct reg_window *rw)
2193{
2194 unsigned long rw_addr = (unsigned long) rw;
2195 unsigned long thread_base, thread_end;
2196
2197 if (rw_addr < PAGE_OFFSET) {
2198 if (task != &init_task)
2199 return 0;
2200 }
2201
ee3eea16 2202 thread_base = (unsigned long) task_stack_page(task);
1da177e4
LT		 2203 thread_end = thread_base + sizeof(union thread_union);
2204 if (rw_addr >= thread_base &&
2205 rw_addr < thread_end &&
2206 !(rw_addr & 0x7UL))
2207 return 1;
2208
2209 return 0;
2210}
2211
2212static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2213{
2214 unsigned long fp = rw->ins[6];
2215
2216 if (!fp)
2217 return NULL;
2218
2219 return (struct reg_window *) (fp + STACK_BIAS);
2220}
2221
2222void die_if_kernel(char *str, struct pt_regs *regs)
2223{
2224 static int die_counter;
1da177e4
LT		 2225 int count = 0;
2226
2227 /* Amuse the user. */
2228 printk(
2229" \\|/ ____ \\|/\n"
2230" \"@'/ .. \\`@\"\n"
2231" /_| \\__/ |_\\\n"
2232" \\__U_/\n");
2233
19c5870c 2234 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
1da177e4
LT		 2235 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2236 __asm__ __volatile__("flushw");
dbf3e950 2237 show_regs(regs);
bcdcd8e7 2238 add_taint(TAINT_DIE);
1da177e4
LT		 2239 if (regs->tstate & TSTATE_PRIV) {
2240 struct reg_window *rw = (struct reg_window *)
2241 (regs->u_regs[UREG_FP] + STACK_BIAS);
2242
2243 /* Stop the back trace when we hit userland or we
2244 * find some badly aligned kernel stack.
2245 */
2246 while (rw &&
2247 count++ < 30&&
2248 is_kernel_stack(current, rw)) {
4fe3ebec
DM		 2249 printk("Caller[%016lx]: %pS\n", rw->ins[7],
2250 (void *) rw->ins[7]);
1da177e4
LT		 2251
2252 rw = kernel_stack_up(rw);
2253 }
2254 instruction_dump ((unsigned int *) regs->tpc);
2255 } else {
2256 if (test_thread_flag(TIF_32BIT)) {
2257 regs->tpc &= 0xffffffff;
2258 regs->tnpc &= 0xffffffff;
2259 }
2260 user_instruction_dump ((unsigned int __user *) regs->tpc);
2261 }
1da177e4
LT		 2262 if (regs->tstate & TSTATE_PRIV)
2263 do_exit(SIGKILL);
2264 do_exit(SIGSEGV);
2265}
2266
6e7726e1
DM		 2267#define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2268#define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2269
1da177e4
LT		 2270extern int handle_popc(u32 insn, struct pt_regs *regs);
2271extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
6e7726e1 2272extern int vis_emul(struct pt_regs *, unsigned int);
1da177e4
LT		 2273
2274void do_illegal_instruction(struct pt_regs *regs)
2275{
2276 unsigned long pc = regs->tpc;
2277 unsigned long tstate = regs->tstate;
2278 u32 insn;
2279 siginfo_t info;
2280
2281 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2282 0, 0x10, SIGILL) == NOTIFY_STOP)
2283 return;
2284
2285 if (tstate & TSTATE_PRIV)
2286 die_if_kernel("Kernel illegal instruction", regs);
2287 if (test_thread_flag(TIF_32BIT))
2288 pc = (u32)pc;
2289 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2290 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2291 if (handle_popc(insn, regs))
2292 return;
2293 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2294 if (handle_ldf_stq(insn, regs))
2295 return;
0c51ed93 2296 } else if (tlb_type == hypervisor) {
6e7726e1
DM		 2297 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2298 if (!vis_emul(regs, insn))
2299 return;
2300 } else {
2301 struct fpustate *f = FPUSTATE;
0c51ed93 2302
6e7726e1
DM		 2303 /* XXX maybe verify XFSR bits like
2304 * XXX do_fpother() does?
2305 */
2306 if (do_mathemu(regs, f))
2307 return;
2308 }
1da177e4
LT		 2309 }
2310 }
2311 info.si_signo = SIGILL;
2312 info.si_errno = 0;
2313 info.si_code = ILL_ILLOPC;
2314 info.si_addr = (void __user *)pc;
2315 info.si_trapno = 0;
2316 force_sig_info(SIGILL, &info, current);
2317}
2318
ed6b0b45
DM		 2319extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2320
1da177e4
LT		 2321void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2322{
2323 siginfo_t info;
2324
2325 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2326 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2327 return;
2328
2329 if (regs->tstate & TSTATE_PRIV) {
ed6b0b45 2330 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
1da177e4
LT		 2331 return;
2332 }
2333 info.si_signo = SIGBUS;
2334 info.si_errno = 0;
2335 info.si_code = BUS_ADRALN;
2336 info.si_addr = (void __user *)sfar;
2337 info.si_trapno = 0;
2338 force_sig_info(SIGBUS, &info, current);
2339}
2340
9f8a5b84 2341void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
ed6b0b45
DM		 2342{
2343 siginfo_t info;
2344
2345 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2346 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2347 return;
2348
2349 if (regs->tstate & TSTATE_PRIV) {
2350 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2351 return;
2352 }
2353 info.si_signo = SIGBUS;
2354 info.si_errno = 0;
2355 info.si_code = BUS_ADRALN;
2356 info.si_addr = (void __user *) addr;
2357 info.si_trapno = 0;
2358 force_sig_info(SIGBUS, &info, current);
2359}
2360
1da177e4
LT		 2361void do_privop(struct pt_regs *regs)
2362{
2363 siginfo_t info;
2364
2365 if (notify_die(DIE_TRAP, "privileged operation", regs,
2366 0, 0x11, SIGILL) == NOTIFY_STOP)
2367 return;
2368
2369 if (test_thread_flag(TIF_32BIT)) {
2370 regs->tpc &= 0xffffffff;
2371 regs->tnpc &= 0xffffffff;
2372 }
2373 info.si_signo = SIGILL;
2374 info.si_errno = 0;
2375 info.si_code = ILL_PRVOPC;
2376 info.si_addr = (void __user *)regs->tpc;
2377 info.si_trapno = 0;
2378 force_sig_info(SIGILL, &info, current);
2379}
2380
2381void do_privact(struct pt_regs *regs)
2382{
2383 do_privop(regs);
2384}
2385
2386/* Trap level 1 stuff or other traps we should never see... */
2387void do_cee(struct pt_regs *regs)
2388{
2389 die_if_kernel("TL0: Cache Error Exception", regs);
2390}
2391
2392void do_cee_tl1(struct pt_regs *regs)
2393{
2394 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2395 die_if_kernel("TL1: Cache Error Exception", regs);
2396}
2397
2398void do_dae_tl1(struct pt_regs *regs)
2399{
2400 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2401 die_if_kernel("TL1: Data Access Exception", regs);
2402}
2403
2404void do_iae_tl1(struct pt_regs *regs)
2405{
2406 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2407 die_if_kernel("TL1: Instruction Access Exception", regs);
2408}
2409
2410void do_div0_tl1(struct pt_regs *regs)
2411{
2412 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2413 die_if_kernel("TL1: DIV0 Exception", regs);
2414}
2415
2416void do_fpdis_tl1(struct pt_regs *regs)
2417{
2418 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2419 die_if_kernel("TL1: FPU Disabled", regs);
2420}
2421
2422void do_fpieee_tl1(struct pt_regs *regs)
2423{
2424 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2425 die_if_kernel("TL1: FPU IEEE Exception", regs);
2426}
2427
2428void do_fpother_tl1(struct pt_regs *regs)
2429{
2430 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2431 die_if_kernel("TL1: FPU Other Exception", regs);
2432}
2433
2434void do_ill_tl1(struct pt_regs *regs)
2435{
2436 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2437 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2438}
2439
2440void do_irq_tl1(struct pt_regs *regs)
2441{
2442 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2443 die_if_kernel("TL1: IRQ Exception", regs);
2444}
2445
2446void do_lddfmna_tl1(struct pt_regs *regs)
2447{
2448 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2449 die_if_kernel("TL1: LDDF Exception", regs);
2450}
2451
2452void do_stdfmna_tl1(struct pt_regs *regs)
2453{
2454 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2455 die_if_kernel("TL1: STDF Exception", regs);
2456}
2457
2458void do_paw(struct pt_regs *regs)
2459{
2460 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2461}
2462
2463void do_paw_tl1(struct pt_regs *regs)
2464{
2465 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2466 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2467}
2468
2469void do_vaw(struct pt_regs *regs)
2470{
2471 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2472}
2473
2474void do_vaw_tl1(struct pt_regs *regs)
2475{
2476 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2477 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2478}
2479
2480void do_tof_tl1(struct pt_regs *regs)
2481{
2482 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2483 die_if_kernel("TL1: Tag Overflow Exception", regs);
2484}
2485
2486void do_getpsr(struct pt_regs *regs)
2487{
2488 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2489 regs->tpc = regs->tnpc;
2490 regs->tnpc += 4;
2491 if (test_thread_flag(TIF_32BIT)) {
2492 regs->tpc &= 0xffffffff;
2493 regs->tnpc &= 0xffffffff;
2494 }
2495}
2496
56fb4df6
DM		 2497struct trap_per_cpu trap_block[NR_CPUS];
2498
2499/* This can get invoked before sched_init() so play it super safe
2500 * and use hard_smp_processor_id().
2501 */
72aff53f 2502void init_cur_cpu_trap(struct thread_info *t)
56fb4df6
DM		 2503{
2504 int cpu = hard_smp_processor_id();
2505 struct trap_per_cpu *p = &trap_block[cpu];
2506
72aff53f 2507 p->thread = t;
56fb4df6
DM		 2508 p->pgd_paddr = 0;
2509}
2510
1da177e4 2511extern void thread_info_offsets_are_bolixed_dave(void);
56fb4df6 2512extern void trap_per_cpu_offsets_are_bolixed_dave(void);
dcc1e8dd 2513extern void tsb_config_offsets_are_bolixed_dave(void);
1da177e4
LT		 2514
2515/* Only invoked on boot processor. */
2516void __init trap_init(void)
2517{
2518 /* Compile time sanity check. */
2519 if (TI_TASK != offsetof(struct thread_info, task) ||
2520 TI_FLAGS != offsetof(struct thread_info, flags) ||
2521 TI_CPU != offsetof(struct thread_info, cpu) ||
2522 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2523 TI_KSP != offsetof(struct thread_info, ksp) ||
2524 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2525 TI_KREGS != offsetof(struct thread_info, kregs) ||
2526 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2527 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2528 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2529 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2530 TI_GSR != offsetof(struct thread_info, gsr) ||
2531 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2532 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2533 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2534 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2535 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2536 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
1da177e4 2537 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
db7d9a4e
DM		 2538 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2539 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
a3f99858
DM		 2540 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2541 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2542 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
1da177e4
LT		 2543 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2544 (TI_FPREGS & (64 - 1)))
2545 thread_info_offsets_are_bolixed_dave();
2546
56fb4df6 2547 if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
e088ad7c
DM		 2548 (TRAP_PER_CPU_PGD_PADDR !=
2549 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2550 (TRAP_PER_CPU_CPU_MONDO_PA !=
2551 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2552 (TRAP_PER_CPU_DEV_MONDO_PA !=
2553 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2554 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2555 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
5b0c0572
DM		 2556 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2557 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
e088ad7c
DM		 2558 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2559 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
5b0c0572
DM		 2560 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2561 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
e088ad7c 2562 (TRAP_PER_CPU_FAULT_INFO !=
1d2f1f90
DM		 2563 offsetof(struct trap_per_cpu, fault_info)) ||
2564 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2565 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2566 (TRAP_PER_CPU_CPU_LIST_PA !=
dcc1e8dd
DM		 2567 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2568 (TRAP_PER_CPU_TSB_HUGE !=
2569 offsetof(struct trap_per_cpu, tsb_huge)) ||
2570 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
fd0504c3 2571 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
eb2d8d60
DM		 2572 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2573 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
5cbc3073
DM		 2574 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2575 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2576 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2577 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2578 (TRAP_PER_CPU_RESUM_QMASK !=
2579 offsetof(struct trap_per_cpu, resum_qmask)) ||
2580 (TRAP_PER_CPU_NONRESUM_QMASK !=
2581 offsetof(struct trap_per_cpu, nonresum_qmask)))
56fb4df6
DM		 2582 trap_per_cpu_offsets_are_bolixed_dave();
2583
dcc1e8dd
DM		 2584 if ((TSB_CONFIG_TSB !=
2585 offsetof(struct tsb_config, tsb)) ||
2586 (TSB_CONFIG_RSS_LIMIT !=
2587 offsetof(struct tsb_config, tsb_rss_limit)) ||
2588 (TSB_CONFIG_NENTRIES !=
2589 offsetof(struct tsb_config, tsb_nentries)) ||
2590 (TSB_CONFIG_REG_VAL !=
2591 offsetof(struct tsb_config, tsb_reg_val)) ||
2592 (TSB_CONFIG_MAP_VADDR !=
2593 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2594 (TSB_CONFIG_MAP_PTE !=
2595 offsetof(struct tsb_config, tsb_map_pte)))
2596 tsb_config_offsets_are_bolixed_dave();
2597
1da177e4
LT		 2598 /* Attach to the address space of init_task. On SMP we
2599 * do this in smp.c:smp_callin for other cpus.
2600 */
2601 atomic_inc(&init_mm.mm_count);
2602 current->active_mm = &init_mm;
2603}
Linux kernel - Deliverables
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