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[SPARC64]: More SUN4V cpu mondo bug fixing.
[deliverable/linux.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
c4bce90e 9#include <linux/module.h>
1da177e4
LT		 10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/slab.h>
18#include <linux/initrd.h>
19#include <linux/swap.h>
20#include <linux/pagemap.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
1da177e4
LT		 26
27#include <asm/head.h>
28#include <asm/system.h>
29#include <asm/page.h>
30#include <asm/pgalloc.h>
31#include <asm/pgtable.h>
32#include <asm/oplib.h>
33#include <asm/iommu.h>
34#include <asm/io.h>
35#include <asm/uaccess.h>
36#include <asm/mmu_context.h>
37#include <asm/tlbflush.h>
38#include <asm/dma.h>
39#include <asm/starfire.h>
40#include <asm/tlb.h>
41#include <asm/spitfire.h>
42#include <asm/sections.h>
517af332 43#include <asm/tsb.h>
481295f9 44#include <asm/hypervisor.h>
1da177e4
LT		 45
46extern void device_scan(void);
47
9cc3a1ac
DM		 48#define MAX_PHYS_ADDRESS (1UL << 42UL)
49#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50#define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
52
53unsigned long kern_linear_pte_xor[2] __read_mostly;
54
55/* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
58 */
59unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
60
d7744a09
DM		 61/* A special kernel TSB for 4MB and 256MB linear mappings. */
62struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
63
13edad7a
DM		 64#define MAX_BANKS 32
65
66static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
67static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
68static int pavail_ents __initdata;
69static int pavail_rescan_ents __initdata;
70
71static int cmp_p64(const void *a, const void *b)
72{
73 const struct linux_prom64_registers *x = a, *y = b;
74
75 if (x->phys_addr > y->phys_addr)
76 return 1;
77 if (x->phys_addr < y->phys_addr)
78 return -1;
79 return 0;
80}
81
82static void __init read_obp_memory(const char *property,
83 struct linux_prom64_registers *regs,
84 int *num_ents)
85{
86 int node = prom_finddevice("/memory");
87 int prop_size = prom_getproplen(node, property);
88 int ents, ret, i;
89
90 ents = prop_size / sizeof(struct linux_prom64_registers);
91 if (ents > MAX_BANKS) {
92 prom_printf("The machine has more %s property entries than "
93 "this kernel can support (%d).\n",
94 property, MAX_BANKS);
95 prom_halt();
96 }
97
98 ret = prom_getproperty(node, property, (char *) regs, prop_size);
99 if (ret == -1) {
100 prom_printf("Couldn't get %s property from /memory.\n");
101 prom_halt();
102 }
103
104 *num_ents = ents;
10147570 105
13edad7a
DM		 106 /* Sanitize what we got from the firmware, by page aligning
107 * everything.
108 */
109 for (i = 0; i < ents; i++) {
110 unsigned long base, size;
111
112 base = regs[i].phys_addr;
113 size = regs[i].reg_size;
10147570 114
13edad7a
DM		 115 size &= PAGE_MASK;
116 if (base & ~PAGE_MASK) {
117 unsigned long new_base = PAGE_ALIGN(base);
118
119 size -= new_base - base;
120 if ((long) size < 0L)
121 size = 0UL;
122 base = new_base;
123 }
124 regs[i].phys_addr = base;
125 regs[i].reg_size = size;
126 }
c9c10830 127 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 128 cmp_p64, NULL);
129}
1da177e4 130
2bdb3cb2 131unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4
LT		 132
133/* Ugly, but necessary... -DaveM */
1ac4f5eb
DM		 134unsigned long phys_base __read_mostly;
135unsigned long kern_base __read_mostly;
136unsigned long kern_size __read_mostly;
137unsigned long pfn_base __read_mostly;
1da177e4 138
1da177e4
LT		 139/* get_new_mmu_context() uses "cache + 1". */
140DEFINE_SPINLOCK(ctx_alloc_lock);
141unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
142#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
143unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
144
145/* References to special section boundaries */
146extern char _start[], _end[];
147
148/* Initial ramdisk setup */
149extern unsigned long sparc_ramdisk_image64;
150extern unsigned int sparc_ramdisk_image;
151extern unsigned int sparc_ramdisk_size;
152
1ac4f5eb 153struct page *mem_map_zero __read_mostly;
1da177e4 154
0835ae0f
DM		 155unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
156
157unsigned long sparc64_kern_pri_context __read_mostly;
158unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
159unsigned long sparc64_kern_sec_context __read_mostly;
160
1da177e4
LT		 161int bigkernel = 0;
162
3c936465 163kmem_cache_t *pgtable_cache __read_mostly;
1da177e4 164
3c936465
DM		 165static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
166{
167 clear_page(addr);
168}
05e28f9d 169
3c936465 170void pgtable_cache_init(void)
1da177e4 171{
3c936465
DM		 172 pgtable_cache = kmem_cache_create("pgtable_cache",
173 PAGE_SIZE, PAGE_SIZE,
174 SLAB_HWCACHE_ALIGN |
175 SLAB_MUST_HWCACHE_ALIGN,
176 zero_ctor,
177 NULL);
178 if (!pgtable_cache) {
179 prom_printf("pgtable_cache_init(): Could not create!\n");
180 prom_halt();
1da177e4 181 }
1da177e4
LT		 182}
183
184#ifdef CONFIG_DEBUG_DCFLUSH
185atomic_t dcpage_flushes = ATOMIC_INIT(0);
186#ifdef CONFIG_SMP
187atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
188#endif
189#endif
190
7a591cfe 191inline void flush_dcache_page_impl(struct page *page)
1da177e4 192{
7a591cfe 193 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 194#ifdef CONFIG_DEBUG_DCFLUSH
195 atomic_inc(&dcpage_flushes);
196#endif
197
198#ifdef DCACHE_ALIASING_POSSIBLE
199 __flush_dcache_page(page_address(page),
200 ((tlb_type == spitfire) &&
201 page_mapping(page) != NULL));
202#else
203 if (page_mapping(page) != NULL &&
204 tlb_type == spitfire)
205 __flush_icache_page(__pa(page_address(page)));
206#endif
207}
208
209#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 210#define PG_dcache_cpu_shift 24
211#define PG_dcache_cpu_mask (256 - 1)
212
213#if NR_CPUS > 256
214#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
215#endif
1da177e4
LT		 216
217#define dcache_dirty_cpu(page) \
48b0e548 218 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 219
220static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
221{
222 unsigned long mask = this_cpu;
48b0e548
DM		 223 unsigned long non_cpu_bits;
224
225 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
226 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
227
1da177e4
LT		 228 __asm__ __volatile__("1:\n\t"
229 "ldx [%2], %%g7\n\t"
230 "and %%g7, %1, %%g1\n\t"
231 "or %%g1, %0, %%g1\n\t"
232 "casx [%2], %%g7, %%g1\n\t"
233 "cmp %%g7, %%g1\n\t"
b445e26c 234 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 235 "bne,pn %%xcc, 1b\n\t"
b445e26c 236 " nop"
1da177e4
LT		 237 : /* no outputs */
238 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
239 : "g1", "g7");
240}
241
242static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
243{
244 unsigned long mask = (1UL << PG_dcache_dirty);
245
246 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
247 "1:\n\t"
248 "ldx [%2], %%g7\n\t"
48b0e548 249 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 250 "and %%g1, %3, %%g1\n\t"
251 "cmp %%g1, %0\n\t"
252 "bne,pn %%icc, 2f\n\t"
253 " andn %%g7, %1, %%g1\n\t"
254 "casx [%2], %%g7, %%g1\n\t"
255 "cmp %%g7, %%g1\n\t"
b445e26c 256 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 257 "bne,pn %%xcc, 1b\n\t"
b445e26c 258 " nop\n"
1da177e4
LT		 259 "2:"
260 : /* no outputs */
261 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 262 "i" (PG_dcache_cpu_mask),
263 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 264 : "g1", "g7");
265}
266
517af332
DM		 267static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
268{
269 unsigned long tsb_addr = (unsigned long) ent;
270
3b3ab2eb 271 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 272 tsb_addr = __pa(tsb_addr);
273
274 __tsb_insert(tsb_addr, tag, pte);
275}
276
c4bce90e
DM		 277unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
278unsigned long _PAGE_SZBITS __read_mostly;
279
1da177e4
LT		 280void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
281{
bd40791e 282 struct mm_struct *mm;
7a591cfe
DM		 283
284 if (tlb_type != hypervisor) {
285 unsigned long pfn = pte_pfn(pte);
286 unsigned long pg_flags;
287 struct page *page;
288
289 if (pfn_valid(pfn) &&
290 (page = pfn_to_page(pfn), page_mapping(page)) &&
291 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
292 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
293 PG_dcache_cpu_mask);
294 int this_cpu = get_cpu();
295
296 /* This is just to optimize away some function calls
297 * in the SMP case.
298 */
299 if (cpu == this_cpu)
300 flush_dcache_page_impl(page);
301 else
302 smp_flush_dcache_page_impl(page, cpu);
303
304 clear_dcache_dirty_cpu(page, cpu);
305
306 put_cpu();
307 }
1da177e4 308 }
bd40791e
DM		 309
310 mm = vma->vm_mm;
b70c0fa1
DM		 311 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
312 struct tsb *tsb;
313 unsigned long tag;
314
315 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
316 (mm->context.tsb_nentries - 1UL)];
8b234274 317 tag = (address >> 22UL);
b70c0fa1
DM		 318 tsb_insert(tsb, tag, pte_val(pte));
319 }
1da177e4
LT		 320}
321
322void flush_dcache_page(struct page *page)
323{
a9546f59
DM		 324 struct address_space *mapping;
325 int this_cpu;
1da177e4 326
7a591cfe
DM		 327 if (tlb_type == hypervisor)
328 return;
329
a9546f59
DM		 330 /* Do not bother with the expensive D-cache flush if it
331 * is merely the zero page. The 'bigcore' testcase in GDB
332 * causes this case to run millions of times.
333 */
334 if (page == ZERO_PAGE(0))
335 return;
336
337 this_cpu = get_cpu();
338
339 mapping = page_mapping(page);
1da177e4 340 if (mapping && !mapping_mapped(mapping)) {
a9546f59 341 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 342 if (dirty) {
a9546f59
DM		 343 int dirty_cpu = dcache_dirty_cpu(page);
344
1da177e4
LT		 345 if (dirty_cpu == this_cpu)
346 goto out;
347 smp_flush_dcache_page_impl(page, dirty_cpu);
348 }
349 set_dcache_dirty(page, this_cpu);
350 } else {
351 /* We could delay the flush for the !page_mapping
352 * case too. But that case is for exec env/arg
353 * pages and those are %99 certainly going to get
354 * faulted into the tlb (and thus flushed) anyways.
355 */
356 flush_dcache_page_impl(page);
357 }
358
359out:
360 put_cpu();
361}
362
05e14cb3 363void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 364{
a43fe0e7 365 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 366 if (tlb_type == spitfire) {
367 unsigned long kaddr;
368
369 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
370 __flush_icache_page(__get_phys(kaddr));
371 }
372}
373
374unsigned long page_to_pfn(struct page *page)
375{
376 return (unsigned long) ((page - mem_map) + pfn_base);
377}
378
379struct page *pfn_to_page(unsigned long pfn)
380{
381 return (mem_map + (pfn - pfn_base));
382}
383
384void show_mem(void)
385{
386 printk("Mem-info:\n");
387 show_free_areas();
388 printk("Free swap: %6ldkB\n",
389 nr_swap_pages << (PAGE_SHIFT-10));
390 printk("%ld pages of RAM\n", num_physpages);
391 printk("%d free pages\n", nr_free_pages());
1da177e4
LT		 392}
393
394void mmu_info(struct seq_file *m)
395{
396 if (tlb_type == cheetah)
397 seq_printf(m, "MMU Type\t: Cheetah\n");
398 else if (tlb_type == cheetah_plus)
399 seq_printf(m, "MMU Type\t: Cheetah+\n");
400 else if (tlb_type == spitfire)
401 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 402 else if (tlb_type == hypervisor)
403 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 404 else
405 seq_printf(m, "MMU Type\t: ???\n");
406
407#ifdef CONFIG_DEBUG_DCFLUSH
408 seq_printf(m, "DCPageFlushes\t: %d\n",
409 atomic_read(&dcpage_flushes));
410#ifdef CONFIG_SMP
411 seq_printf(m, "DCPageFlushesXC\t: %d\n",
412 atomic_read(&dcpage_flushes_xcall));
413#endif /* CONFIG_SMP */
414#endif /* CONFIG_DEBUG_DCFLUSH */
415}
416
417struct linux_prom_translation {
418 unsigned long virt;
419 unsigned long size;
420 unsigned long data;
421};
c9c10830
DM		 422
423/* Exported for kernel TLB miss handling in ktlb.S */
424struct linux_prom_translation prom_trans[512] __read_mostly;
425unsigned int prom_trans_ents __read_mostly;
1da177e4 426
1da177e4
LT		 427/* Exported for SMP bootup purposes. */
428unsigned long kern_locked_tte_data;
429
c9c10830
DM		 430/* The obp translations are saved based on 8k pagesize, since obp can
431 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 432 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 433 */
5085b4a5
DM		 434static inline int in_obp_range(unsigned long vaddr)
435{
436 return (vaddr >= LOW_OBP_ADDRESS &&
437 vaddr < HI_OBP_ADDRESS);
438}
439
c9c10830 440static int cmp_ptrans(const void *a, const void *b)
405599bd 441{
c9c10830 442 const struct linux_prom_translation *x = a, *y = b;
405599bd 443
c9c10830
DM		 444 if (x->virt > y->virt)
445 return 1;
446 if (x->virt < y->virt)
447 return -1;
448 return 0;
405599bd
DM		 449}
450
c9c10830 451/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 452static void __init read_obp_translations(void)
405599bd 453{
c9c10830 454 int n, node, ents, first, last, i;
1da177e4
LT		 455
456 node = prom_finddevice("/virtual-memory");
457 n = prom_getproplen(node, "translations");
405599bd 458 if (unlikely(n == 0 || n == -1)) {
b206fc4c 459 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 460 prom_halt();
461 }
405599bd
DM		 462 if (unlikely(n > sizeof(prom_trans))) {
463 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 464 prom_halt();
465 }
405599bd 466
b206fc4c 467 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 468 (char *)&prom_trans[0],
469 sizeof(prom_trans))) == -1) {
b206fc4c 470 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 471 prom_halt();
472 }
9ad98c5b 473
b206fc4c 474 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 475
c9c10830
DM		 476 ents = n;
477
478 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
479 cmp_ptrans, NULL);
480
481 /* Now kick out all the non-OBP entries. */
482 for (i = 0; i < ents; i++) {
483 if (in_obp_range(prom_trans[i].virt))
484 break;
485 }
486 first = i;
487 for (; i < ents; i++) {
488 if (!in_obp_range(prom_trans[i].virt))
489 break;
490 }
491 last = i;
492
493 for (i = 0; i < (last - first); i++) {
494 struct linux_prom_translation *src = &prom_trans[i + first];
495 struct linux_prom_translation *dest = &prom_trans[i];
496
497 *dest = *src;
498 }
499 for (; i < ents; i++) {
500 struct linux_prom_translation *dest = &prom_trans[i];
501 dest->virt = dest->size = dest->data = 0x0UL;
502 }
503
504 prom_trans_ents = last - first;
505
506 if (tlb_type == spitfire) {
507 /* Clear diag TTE bits. */
508 for (i = 0; i < prom_trans_ents; i++)
509 prom_trans[i].data &= ~0x0003fe0000000000UL;
510 }
405599bd 511}
1da177e4 512
d82ace7d
DM		 513static void __init hypervisor_tlb_lock(unsigned long vaddr,
514 unsigned long pte,
515 unsigned long mmu)
516{
164c220f
DM		 517 register unsigned long func asm("%o5");
518 register unsigned long arg0 asm("%o0");
519 register unsigned long arg1 asm("%o1");
520 register unsigned long arg2 asm("%o2");
521 register unsigned long arg3 asm("%o3");
d82ace7d
DM		 522
523 func = HV_FAST_MMU_MAP_PERM_ADDR;
524 arg0 = vaddr;
525 arg1 = 0;
526 arg2 = pte;
527 arg3 = mmu;
528 __asm__ __volatile__("ta 0x80"
529 : "=&r" (func), "=&r" (arg0),
530 "=&r" (arg1), "=&r" (arg2),
531 "=&r" (arg3)
532 : "0" (func), "1" (arg0), "2" (arg1),
533 "3" (arg2), "4" (arg3));
12e126ad
DM		 534 if (arg0 != 0) {
535 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
536 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
537 prom_halt();
538 }
d82ace7d
DM		 539}
540
c4bce90e
DM		 541static unsigned long kern_large_tte(unsigned long paddr);
542
898cf0ec 543static void __init remap_kernel(void)
405599bd
DM		 544{
545 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 546 int tlb_ent = sparc64_highest_locked_tlbent();
547
1da177e4 548 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 549 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 550 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 551
552 kern_locked_tte_data = tte_data;
553
d82ace7d
DM		 554 /* Now lock us into the TLBs via Hypervisor or OBP. */
555 if (tlb_type == hypervisor) {
556 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
557 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
558 if (bigkernel) {
559 tte_vaddr += 0x400000;
560 tte_data += 0x400000;
561 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
562 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
563 }
564 } else {
565 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
566 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
567 if (bigkernel) {
568 tlb_ent -= 1;
569 prom_dtlb_load(tlb_ent,
570 tte_data + 0x400000,
571 tte_vaddr + 0x400000);
572 prom_itlb_load(tlb_ent,
573 tte_data + 0x400000,
574 tte_vaddr + 0x400000);
575 }
576 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
1da177e4 577 }
0835ae0f
DM		 578 if (tlb_type == cheetah_plus) {
579 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
580 CTX_CHEETAH_PLUS_NUC);
581 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
582 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
583 }
405599bd 584}
1da177e4 585
405599bd 586
c9c10830 587static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 588{
589 read_obp_translations();
405599bd
DM		 590
591 /* Now fixup OBP's idea about where we really are mapped. */
592 prom_printf("Remapping the kernel... ");
593 remap_kernel();
1da177e4 594 prom_printf("done.\n");
1da177e4
LT		 595}
596
1da177e4
LT		 597void prom_world(int enter)
598{
1da177e4
LT		 599 if (!enter)
600 set_fs((mm_segment_t) { get_thread_current_ds() });
601
3487d1d4 602 __asm__ __volatile__("flushw");
1da177e4
LT		 603}
604
605#ifdef DCACHE_ALIASING_POSSIBLE
606void __flush_dcache_range(unsigned long start, unsigned long end)
607{
608 unsigned long va;
609
610 if (tlb_type == spitfire) {
611 int n = 0;
612
613 for (va = start; va < end; va += 32) {
614 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
615 if (++n >= 512)
616 break;
617 }
a43fe0e7 618 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 619 start = __pa(start);
620 end = __pa(end);
621 for (va = start; va < end; va += 32)
622 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
623 "membar #Sync"
624 : /* no outputs */
625 : "r" (va),
626 "i" (ASI_DCACHE_INVALIDATE));
627 }
628}
629#endif /* DCACHE_ALIASING_POSSIBLE */
630
1da177e4
LT		 631/* Caller does TLB context flushing on local CPU if necessary.
632 * The caller also ensures that CTX_VALID(mm->context) is false.
633 *
634 * We must be careful about boundary cases so that we never
635 * let the user have CTX 0 (nucleus) or we ever use a CTX
636 * version of zero (and thus NO_CONTEXT would not be caught
637 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 638 *
639 * Always invoked with interrupts disabled.
1da177e4
LT		 640 */
641void get_new_mmu_context(struct mm_struct *mm)
642{
643 unsigned long ctx, new_ctx;
644 unsigned long orig_pgsz_bits;
a0663a79 645 int new_version;
1da177e4
LT		 646
647 spin_lock(&ctx_alloc_lock);
648 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
649 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
650 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 651 new_version = 0;
1da177e4
LT		 652 if (new_ctx >= (1 << CTX_NR_BITS)) {
653 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
654 if (new_ctx >= ctx) {
655 int i;
656 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
657 CTX_FIRST_VERSION;
658 if (new_ctx == 1)
659 new_ctx = CTX_FIRST_VERSION;
660
661 /* Don't call memset, for 16 entries that's just
662 * plain silly...
663 */
664 mmu_context_bmap[0] = 3;
665 mmu_context_bmap[1] = 0;
666 mmu_context_bmap[2] = 0;
667 mmu_context_bmap[3] = 0;
668 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
669 mmu_context_bmap[i + 0] = 0;
670 mmu_context_bmap[i + 1] = 0;
671 mmu_context_bmap[i + 2] = 0;
672 mmu_context_bmap[i + 3] = 0;
673 }
a0663a79 674 new_version = 1;
1da177e4
LT		 675 goto out;
676 }
677 }
678 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
679 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
680out:
681 tlb_context_cache = new_ctx;
682 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
683 spin_unlock(&ctx_alloc_lock);
a0663a79
DM		 684
685 if (unlikely(new_version))
686 smp_new_mmu_context_version();
1da177e4
LT		 687}
688
1da177e4
LT		 689void sparc_ultra_dump_itlb(void)
690{
691 int slot;
692
693 if (tlb_type == spitfire) {
694 printk ("Contents of itlb: ");
695 for (slot = 0; slot < 14; slot++) printk (" ");
696 printk ("%2x:%016lx,%016lx\n",
697 0,
698 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
699 for (slot = 1; slot < 64; slot+=3) {
700 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
701 slot,
702 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
703 slot+1,
704 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
705 slot+2,
706 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
707 }
708 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
709 printk ("Contents of itlb0:\n");
710 for (slot = 0; slot < 16; slot+=2) {
711 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
712 slot,
713 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
714 slot+1,
715 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
716 }
717 printk ("Contents of itlb2:\n");
718 for (slot = 0; slot < 128; slot+=2) {
719 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
720 slot,
721 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
722 slot+1,
723 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
724 }
725 }
726}
727
728void sparc_ultra_dump_dtlb(void)
729{
730 int slot;
731
732 if (tlb_type == spitfire) {
733 printk ("Contents of dtlb: ");
734 for (slot = 0; slot < 14; slot++) printk (" ");
735 printk ("%2x:%016lx,%016lx\n", 0,
736 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
737 for (slot = 1; slot < 64; slot+=3) {
738 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
739 slot,
740 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
741 slot+1,
742 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
743 slot+2,
744 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
745 }
746 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
747 printk ("Contents of dtlb0:\n");
748 for (slot = 0; slot < 16; slot+=2) {
749 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
750 slot,
751 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
752 slot+1,
753 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
754 }
755 printk ("Contents of dtlb2:\n");
756 for (slot = 0; slot < 512; slot+=2) {
757 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
758 slot,
759 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
760 slot+1,
761 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
762 }
763 if (tlb_type == cheetah_plus) {
764 printk ("Contents of dtlb3:\n");
765 for (slot = 0; slot < 512; slot+=2) {
766 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
767 slot,
768 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
769 slot+1,
770 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
771 }
772 }
773 }
774}
775
776extern unsigned long cmdline_memory_size;
777
778unsigned long __init bootmem_init(unsigned long *pages_avail)
779{
780 unsigned long bootmap_size, start_pfn, end_pfn;
781 unsigned long end_of_phys_memory = 0UL;
782 unsigned long bootmap_pfn, bytes_avail, size;
783 int i;
784
785#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 786 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 787#endif
788
789 bytes_avail = 0UL;
13edad7a
DM		 790 for (i = 0; i < pavail_ents; i++) {
791 end_of_phys_memory = pavail[i].phys_addr +
792 pavail[i].reg_size;
793 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 794 if (cmdline_memory_size) {
795 if (bytes_avail > cmdline_memory_size) {
796 unsigned long slack = bytes_avail - cmdline_memory_size;
797
798 bytes_avail -= slack;
799 end_of_phys_memory -= slack;
800
13edad7a
DM		 801 pavail[i].reg_size -= slack;
802 if ((long)pavail[i].reg_size <= 0L) {
803 pavail[i].phys_addr = 0xdeadbeefUL;
804 pavail[i].reg_size = 0UL;
805 pavail_ents = i;
1da177e4 806 } else {
13edad7a
DM		 807 pavail[i+1].reg_size = 0Ul;
808 pavail[i+1].phys_addr = 0xdeadbeefUL;
809 pavail_ents = i + 1;
1da177e4
LT		 810 }
811 break;
812 }
813 }
814 }
815
816 *pages_avail = bytes_avail >> PAGE_SHIFT;
817
818 /* Start with page aligned address of last symbol in kernel
819 * image. The kernel is hard mapped below PAGE_OFFSET in a
820 * 4MB locked TLB translation.
821 */
822 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
823
824 bootmap_pfn = start_pfn;
825
826 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
827
828#ifdef CONFIG_BLK_DEV_INITRD
829 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
830 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
831 unsigned long ramdisk_image = sparc_ramdisk_image ?
832 sparc_ramdisk_image : sparc_ramdisk_image64;
833 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
834 ramdisk_image -= KERNBASE;
835 initrd_start = ramdisk_image + phys_base;
836 initrd_end = initrd_start + sparc_ramdisk_size;
837 if (initrd_end > end_of_phys_memory) {
838 printk(KERN_CRIT "initrd extends beyond end of memory "
839 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
840 initrd_end, end_of_phys_memory);
841 initrd_start = 0;
842 }
843 if (initrd_start) {
844 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
845 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
846 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
847 }
848 }
849#endif
850 /* Initialize the boot-time allocator. */
851 max_pfn = max_low_pfn = end_pfn;
852 min_low_pfn = pfn_base;
853
854#ifdef CONFIG_DEBUG_BOOTMEM
855 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
856 min_low_pfn, bootmap_pfn, max_low_pfn);
857#endif
858 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
859
1da177e4
LT		 860 /* Now register the available physical memory with the
861 * allocator.
862 */
13edad7a 863 for (i = 0; i < pavail_ents; i++) {
1da177e4 864#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 865 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
866 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 867#endif
13edad7a 868 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 869 }
870
871#ifdef CONFIG_BLK_DEV_INITRD
872 if (initrd_start) {
873 size = initrd_end - initrd_start;
874
875 /* Resert the initrd image area. */
876#ifdef CONFIG_DEBUG_BOOTMEM
877 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
878 initrd_start, initrd_end);
879#endif
880 reserve_bootmem(initrd_start, size);
881 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
882
883 initrd_start += PAGE_OFFSET;
884 initrd_end += PAGE_OFFSET;
885 }
886#endif
887 /* Reserve the kernel text/data/bss. */
888#ifdef CONFIG_DEBUG_BOOTMEM
889 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
890#endif
891 reserve_bootmem(kern_base, kern_size);
892 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
893
894 /* Reserve the bootmem map. We do not account for it
895 * in pages_avail because we will release that memory
896 * in free_all_bootmem.
897 */
898 size = bootmap_size;
899#ifdef CONFIG_DEBUG_BOOTMEM
900 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
901 (bootmap_pfn << PAGE_SHIFT), size);
902#endif
903 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
904 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
905
906 return end_pfn;
907}
908
9cc3a1ac
DM		 909static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
910static int pall_ents __initdata;
911
56425306
DM		 912#ifdef CONFIG_DEBUG_PAGEALLOC
913static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
914{
915 unsigned long vstart = PAGE_OFFSET + pstart;
916 unsigned long vend = PAGE_OFFSET + pend;
917 unsigned long alloc_bytes = 0UL;
918
919 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 920 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 921 vstart, vend);
922 prom_halt();
923 }
924
925 while (vstart < vend) {
926 unsigned long this_end, paddr = __pa(vstart);
927 pgd_t *pgd = pgd_offset_k(vstart);
928 pud_t *pud;
929 pmd_t *pmd;
930 pte_t *pte;
931
932 pud = pud_offset(pgd, vstart);
933 if (pud_none(*pud)) {
934 pmd_t *new;
935
936 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
937 alloc_bytes += PAGE_SIZE;
938 pud_populate(&init_mm, pud, new);
939 }
940
941 pmd = pmd_offset(pud, vstart);
942 if (!pmd_present(*pmd)) {
943 pte_t *new;
944
945 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
946 alloc_bytes += PAGE_SIZE;
947 pmd_populate_kernel(&init_mm, pmd, new);
948 }
949
950 pte = pte_offset_kernel(pmd, vstart);
951 this_end = (vstart + PMD_SIZE) & PMD_MASK;
952 if (this_end > vend)
953 this_end = vend;
954
955 while (vstart < this_end) {
956 pte_val(*pte) = (paddr | pgprot_val(prot));
957
958 vstart += PAGE_SIZE;
959 paddr += PAGE_SIZE;
960 pte++;
961 }
962 }
963
964 return alloc_bytes;
965}
966
56425306 967extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 968#endif /* CONFIG_DEBUG_PAGEALLOC */
969
970static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
971{
972 const unsigned long shift_256MB = 28;
973 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
974 const unsigned long size_256MB = (1UL << shift_256MB);
975
976 while (start < end) {
977 long remains;
978
979 if (start & mask_256MB) {
980 start = (start + size_256MB) & ~mask_256MB;
981 continue;
982 }
983
984 remains = end - start;
985 while (remains >= size_256MB) {
986 unsigned long index = start >> shift_256MB;
987
988 __set_bit(index, kpte_linear_bitmap);
989
990 start += size_256MB;
991 remains -= size_256MB;
992 }
993 }
994}
56425306
DM		 995
996static void __init kernel_physical_mapping_init(void)
997{
9cc3a1ac
DM		 998 unsigned long i;
999#ifdef CONFIG_DEBUG_PAGEALLOC
1000 unsigned long mem_alloced = 0UL;
1001#endif
56425306 1002
13edad7a
DM		 1003 read_obp_memory("reg", &pall[0], &pall_ents);
1004
1005 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1006 unsigned long phys_start, phys_end;
1007
13edad7a
DM		 1008 phys_start = pall[i].phys_addr;
1009 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1010
1011 mark_kpte_bitmap(phys_start, phys_end);
1012
1013#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1014 mem_alloced += kernel_map_range(phys_start, phys_end,
1015 PAGE_KERNEL);
9cc3a1ac 1016#endif
56425306
DM		 1017 }
1018
9cc3a1ac 1019#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1020 printk("Allocated %ld bytes for kernel page tables.\n",
1021 mem_alloced);
1022
1023 kvmap_linear_patch[0] = 0x01000000; /* nop */
1024 flushi(&kvmap_linear_patch[0]);
1025
1026 __flush_tlb_all();
9cc3a1ac 1027#endif
56425306
DM		 1028}
1029
9cc3a1ac 1030#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1031void kernel_map_pages(struct page *page, int numpages, int enable)
1032{
1033 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1034 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1035
1036 kernel_map_range(phys_start, phys_end,
1037 (enable ? PAGE_KERNEL : __pgprot(0)));
1038
74bf4312
DM		 1039 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1040 PAGE_OFFSET + phys_end);
1041
56425306
DM		 1042 /* we should perform an IPI and flush all tlbs,
1043 * but that can deadlock->flush only current cpu.
1044 */
1045 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1046 PAGE_OFFSET + phys_end);
1047}
1048#endif
1049
10147570
DM		 1050unsigned long __init find_ecache_flush_span(unsigned long size)
1051{
0836a0eb
DM		 1052 int i;
1053
13edad7a
DM		 1054 for (i = 0; i < pavail_ents; i++) {
1055 if (pavail[i].reg_size >= size)
1056 return pavail[i].phys_addr;
0836a0eb
DM		 1057 }
1058
13edad7a 1059 return ~0UL;
0836a0eb
DM		 1060}
1061
517af332
DM		 1062static void __init tsb_phys_patch(void)
1063{
d257d5da 1064 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1065 struct tsb_phys_patch_entry *p;
1066
d257d5da
DM		 1067 pquad = &__tsb_ldquad_phys_patch;
1068 while (pquad < &__tsb_ldquad_phys_patch_end) {
1069 unsigned long addr = pquad->addr;
1070
1071 if (tlb_type == hypervisor)
1072 *(unsigned int *) addr = pquad->sun4v_insn;
1073 else
1074 *(unsigned int *) addr = pquad->sun4u_insn;
1075 wmb();
1076 __asm__ __volatile__("flush %0"
1077 : /* no outputs */
1078 : "r" (addr));
1079
1080 pquad++;
1081 }
1082
517af332
DM		 1083 p = &__tsb_phys_patch;
1084 while (p < &__tsb_phys_patch_end) {
1085 unsigned long addr = p->addr;
1086
1087 *(unsigned int *) addr = p->insn;
1088 wmb();
1089 __asm__ __volatile__("flush %0"
1090 : /* no outputs */
1091 : "r" (addr));
1092
1093 p++;
1094 }
1095}
1096
490384e7
DM		 1097/* Don't mark as init, we give this to the Hypervisor. */
1098static struct hv_tsb_descr ktsb_descr[2];
1099extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1100
1101static void __init sun4v_ktsb_init(void)
1102{
1103 unsigned long ktsb_pa;
1104
d7744a09 1105 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1106 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1107
1108 switch (PAGE_SIZE) {
1109 case 8 * 1024:
1110 default:
1111 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1112 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1113 break;
1114
1115 case 64 * 1024:
1116 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1117 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1118 break;
1119
1120 case 512 * 1024:
1121 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1122 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1123 break;
1124
1125 case 4 * 1024 * 1024:
1126 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1127 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1128 break;
1129 };
1130
3f19a84e 1131 ktsb_descr[0].assoc = 1;
490384e7
DM		 1132 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1133 ktsb_descr[0].ctx_idx = 0;
1134 ktsb_descr[0].tsb_base = ktsb_pa;
1135 ktsb_descr[0].resv = 0;
1136
d7744a09
DM		 1137 /* Second KTSB for 4MB/256MB mappings. */
1138 ktsb_pa = (kern_base +
1139 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1140
1141 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1142 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1143 HV_PGSZ_MASK_256MB);
1144 ktsb_descr[1].assoc = 1;
1145 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1146 ktsb_descr[1].ctx_idx = 0;
1147 ktsb_descr[1].tsb_base = ktsb_pa;
1148 ktsb_descr[1].resv = 0;
490384e7
DM		 1149}
1150
1151void __cpuinit sun4v_ktsb_register(void)
1152{
1153 register unsigned long func asm("%o5");
1154 register unsigned long arg0 asm("%o0");
1155 register unsigned long arg1 asm("%o1");
1156 unsigned long pa;
1157
1158 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1159
1160 func = HV_FAST_MMU_TSB_CTX0;
d7744a09 1161 arg0 = 2;
490384e7
DM		 1162 arg1 = pa;
1163 __asm__ __volatile__("ta %6"
1164 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1165 : "0" (func), "1" (arg0), "2" (arg1),
1166 "i" (HV_FAST_TRAP));
1167}
1168
1da177e4
LT		 1169/* paging_init() sets up the page tables */
1170
1171extern void cheetah_ecache_flush_init(void);
d257d5da 1172extern void sun4v_patch_tlb_handlers(void);
1da177e4
LT		 1173
1174static unsigned long last_valid_pfn;
56425306 1175pgd_t swapper_pg_dir[2048];
1da177e4 1176
c4bce90e
DM		 1177static void sun4u_pgprot_init(void);
1178static void sun4v_pgprot_init(void);
1179
1da177e4
LT		 1180void __init paging_init(void)
1181{
2bdb3cb2 1182 unsigned long end_pfn, pages_avail, shift;
0836a0eb
DM		 1183 unsigned long real_end, i;
1184
481295f9
DM		 1185 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1186 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1187
d7744a09 1188 /* Invalidate both kernel TSBs. */
8b234274 1189 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d7744a09 1190 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
8b234274 1191
c4bce90e
DM		 1192 if (tlb_type == hypervisor)
1193 sun4v_pgprot_init();
1194 else
1195 sun4u_pgprot_init();
1196
d257d5da
DM		 1197 if (tlb_type == cheetah_plus ||
1198 tlb_type == hypervisor)
517af332
DM		 1199 tsb_phys_patch();
1200
490384e7 1201 if (tlb_type == hypervisor) {
d257d5da 1202 sun4v_patch_tlb_handlers();
490384e7
DM		 1203 sun4v_ktsb_init();
1204 }
d257d5da 1205
13edad7a
DM		 1206 /* Find available physical memory... */
1207 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1208
1209 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1210 for (i = 0; i < pavail_ents; i++)
1211 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1212
0836a0eb
DM		 1213 pfn_base = phys_base >> PAGE_SHIFT;
1214
1da177e4
LT		 1215 set_bit(0, mmu_context_bmap);
1216
2bdb3cb2
DM		 1217 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1218
1da177e4
LT		 1219 real_end = (unsigned long)_end;
1220 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1221 bigkernel = 1;
2bdb3cb2
DM		 1222 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1223 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1224 prom_halt();
1da177e4 1225 }
2bdb3cb2
DM		 1226
1227 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1228 * work.
1229 */
1230 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1231
56425306 1232 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1233
1234 /* Now can init the kernel/bad page tables. */
1235 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1236 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1237
c9c10830 1238 inherit_prom_mappings();
5085b4a5 1239
a8b900d8
DM		 1240 /* Ok, we can use our TLB miss and window trap handlers safely. */
1241 setup_tba();
1da177e4 1242
c9c10830 1243 __flush_tlb_all();
9ad98c5b 1244
490384e7
DM		 1245 if (tlb_type == hypervisor)
1246 sun4v_ktsb_register();
1247
2bdb3cb2
DM		 1248 /* Setup bootmem... */
1249 pages_avail = 0;
1250 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1251
56425306 1252 kernel_physical_mapping_init();
56425306 1253
1da177e4
LT		 1254 {
1255 unsigned long zones_size[MAX_NR_ZONES];
1256 unsigned long zholes_size[MAX_NR_ZONES];
1257 unsigned long npages;
1258 int znum;
1259
1260 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1261 zones_size[znum] = zholes_size[znum] = 0;
1262
1263 npages = end_pfn - pfn_base;
1264 zones_size[ZONE_DMA] = npages;
1265 zholes_size[ZONE_DMA] = npages - pages_avail;
1266
1267 free_area_init_node(0, &contig_page_data, zones_size,
1268 phys_base >> PAGE_SHIFT, zholes_size);
1269 }
1270
1271 device_scan();
1272}
1273
1da177e4
LT		 1274static void __init taint_real_pages(void)
1275{
1da177e4
LT		 1276 int i;
1277
13edad7a 1278 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1279
13edad7a 1280 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1281 * reserve the lost portions in the bootmem maps.
1282 */
13edad7a 1283 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1284 unsigned long old_start, old_end;
1285
13edad7a 1286 old_start = pavail[i].phys_addr;
1da177e4 1287 old_end = old_start +
13edad7a 1288 pavail[i].reg_size;
1da177e4
LT		 1289 while (old_start < old_end) {
1290 int n;
1291
13edad7a 1292 for (n = 0; pavail_rescan_ents; n++) {
1da177e4
LT		 1293 unsigned long new_start, new_end;
1294
13edad7a
DM		 1295 new_start = pavail_rescan[n].phys_addr;
1296 new_end = new_start +
1297 pavail_rescan[n].reg_size;
1da177e4
LT		 1298
1299 if (new_start <= old_start &&
1300 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1301 set_bit(old_start >> 22,
1302 sparc64_valid_addr_bitmap);
1da177e4
LT		 1303 goto do_next_page;
1304 }
1305 }
1306 reserve_bootmem(old_start, PAGE_SIZE);
1307
1308 do_next_page:
1309 old_start += PAGE_SIZE;
1310 }
1311 }
1312}
1313
1314void __init mem_init(void)
1315{
1316 unsigned long codepages, datapages, initpages;
1317 unsigned long addr, last;
1318 int i;
1319
1320 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1321 i += 1;
2bdb3cb2 1322 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1323 if (sparc64_valid_addr_bitmap == NULL) {
1324 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1325 prom_halt();
1326 }
1327 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1328
1329 addr = PAGE_OFFSET + kern_base;
1330 last = PAGE_ALIGN(kern_size) + addr;
1331 while (addr < last) {
1332 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1333 addr += PAGE_SIZE;
1334 }
1335
1336 taint_real_pages();
1337
1338 max_mapnr = last_valid_pfn - pfn_base;
1339 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1340
1341#ifdef CONFIG_DEBUG_BOOTMEM
1342 prom_printf("mem_init: Calling free_all_bootmem().\n");
1343#endif
1344 totalram_pages = num_physpages = free_all_bootmem() - 1;
1345
1346 /*
1347 * Set up the zero page, mark it reserved, so that page count
1348 * is not manipulated when freeing the page from user ptes.
1349 */
1350 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1351 if (mem_map_zero == NULL) {
1352 prom_printf("paging_init: Cannot alloc zero page.\n");
1353 prom_halt();
1354 }
1355 SetPageReserved(mem_map_zero);
1356
1357 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1358 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1359 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1360 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1361 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1362 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1363
1364 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1365 nr_free_pages() << (PAGE_SHIFT-10),
1366 codepages << (PAGE_SHIFT-10),
1367 datapages << (PAGE_SHIFT-10),
1368 initpages << (PAGE_SHIFT-10),
1369 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1370
1371 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1372 cheetah_ecache_flush_init();
1373}
1374
898cf0ec 1375void free_initmem(void)
1da177e4
LT		 1376{
1377 unsigned long addr, initend;
1378
1379 /*
1380 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1381 */
1382 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1383 initend = (unsigned long)(__init_end) & PAGE_MASK;
1384 for (; addr < initend; addr += PAGE_SIZE) {
1385 unsigned long page;
1386 struct page *p;
1387
1388 page = (addr +
1389 ((unsigned long) __va(kern_base)) -
1390 ((unsigned long) KERNBASE));
1391 memset((void *)addr, 0xcc, PAGE_SIZE);
1392 p = virt_to_page(page);
1393
1394 ClearPageReserved(p);
1395 set_page_count(p, 1);
1396 __free_page(p);
1397 num_physpages++;
1398 totalram_pages++;
1399 }
1400}
1401
1402#ifdef CONFIG_BLK_DEV_INITRD
1403void free_initrd_mem(unsigned long start, unsigned long end)
1404{
1405 if (start < end)
1406 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1407 for (; start < end; start += PAGE_SIZE) {
1408 struct page *p = virt_to_page(start);
1409
1410 ClearPageReserved(p);
1411 set_page_count(p, 1);
1412 __free_page(p);
1413 num_physpages++;
1414 totalram_pages++;
1415 }
1416}
1417#endif
c4bce90e 1418
c4bce90e
DM		 1419#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1420#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1421#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1422#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1423#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1424#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1425
1426pgprot_t PAGE_KERNEL __read_mostly;
1427EXPORT_SYMBOL(PAGE_KERNEL);
1428
1429pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1430pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1431
1432pgprot_t PAGE_SHARED __read_mostly;
1433EXPORT_SYMBOL(PAGE_SHARED);
1434
c4bce90e
DM		 1435pgprot_t PAGE_EXEC __read_mostly;
1436unsigned long pg_iobits __read_mostly;
1437
1438unsigned long _PAGE_IE __read_mostly;
b2bef442 1439
c4bce90e 1440unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1441EXPORT_SYMBOL(_PAGE_E);
1442
c4bce90e 1443unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1444EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e
DM		 1445
1446static void prot_init_common(unsigned long page_none,
1447 unsigned long page_shared,
1448 unsigned long page_copy,
1449 unsigned long page_readonly,
1450 unsigned long page_exec_bit)
1451{
1452 PAGE_COPY = __pgprot(page_copy);
0f15952a 1453 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1454
1455 protection_map[0x0] = __pgprot(page_none);
1456 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1457 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1458 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1459 protection_map[0x4] = __pgprot(page_readonly);
1460 protection_map[0x5] = __pgprot(page_readonly);
1461 protection_map[0x6] = __pgprot(page_copy);
1462 protection_map[0x7] = __pgprot(page_copy);
1463 protection_map[0x8] = __pgprot(page_none);
1464 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1465 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1466 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1467 protection_map[0xc] = __pgprot(page_readonly);
1468 protection_map[0xd] = __pgprot(page_readonly);
1469 protection_map[0xe] = __pgprot(page_shared);
1470 protection_map[0xf] = __pgprot(page_shared);
1471}
1472
1473static void __init sun4u_pgprot_init(void)
1474{
1475 unsigned long page_none, page_shared, page_copy, page_readonly;
1476 unsigned long page_exec_bit;
1477
1478 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1479 _PAGE_CACHE_4U | _PAGE_P_4U |
1480 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1481 _PAGE_EXEC_4U);
1482 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1483 _PAGE_CACHE_4U | _PAGE_P_4U |
1484 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1485 _PAGE_EXEC_4U | _PAGE_L_4U);
1486 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1487
1488 _PAGE_IE = _PAGE_IE_4U;
1489 _PAGE_E = _PAGE_E_4U;
1490 _PAGE_CACHE = _PAGE_CACHE_4U;
1491
1492 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1493 __ACCESS_BITS_4U | _PAGE_E_4U);
1494
9cc3a1ac 1495 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1496 0xfffff80000000000;
9cc3a1ac
DM		 1497 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1498 _PAGE_P_4U | _PAGE_W_4U);
1499
1500 /* XXX Should use 256MB on Panther. XXX */
1501 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1502
1503 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1504 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1505 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1506 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1507
1508
1509 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1510 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1511 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1512 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1513 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1514 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1515 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1516
1517 page_exec_bit = _PAGE_EXEC_4U;
1518
1519 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1520 page_exec_bit);
1521}
1522
1523static void __init sun4v_pgprot_init(void)
1524{
1525 unsigned long page_none, page_shared, page_copy, page_readonly;
1526 unsigned long page_exec_bit;
1527
1528 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1529 _PAGE_CACHE_4V | _PAGE_P_4V |
1530 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1531 _PAGE_EXEC_4V);
1532 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1533 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1534
1535 _PAGE_IE = _PAGE_IE_4V;
1536 _PAGE_E = _PAGE_E_4V;
1537 _PAGE_CACHE = _PAGE_CACHE_4V;
1538
9cc3a1ac
DM		 1539 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1540 0xfffff80000000000;
1541 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1542 _PAGE_P_4V | _PAGE_W_4V);
1543
1544 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1545 0xfffff80000000000;
9cc3a1ac
DM		 1546 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1547 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1548
1549 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1550 __ACCESS_BITS_4V | _PAGE_E_4V);
1551
1552 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1553 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1554 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1555 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1556 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1557
1558 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1559 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1560 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1561 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1562 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1563 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1564 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1565
1566 page_exec_bit = _PAGE_EXEC_4V;
1567
1568 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1569 page_exec_bit);
1570}
1571
1572unsigned long pte_sz_bits(unsigned long sz)
1573{
1574 if (tlb_type == hypervisor) {
1575 switch (sz) {
1576 case 8 * 1024:
1577 default:
1578 return _PAGE_SZ8K_4V;
1579 case 64 * 1024:
1580 return _PAGE_SZ64K_4V;
1581 case 512 * 1024:
1582 return _PAGE_SZ512K_4V;
1583 case 4 * 1024 * 1024:
1584 return _PAGE_SZ4MB_4V;
1585 };
1586 } else {
1587 switch (sz) {
1588 case 8 * 1024:
1589 default:
1590 return _PAGE_SZ8K_4U;
1591 case 64 * 1024:
1592 return _PAGE_SZ64K_4U;
1593 case 512 * 1024:
1594 return _PAGE_SZ512K_4U;
1595 case 4 * 1024 * 1024:
1596 return _PAGE_SZ4MB_4U;
1597 };
1598 }
1599}
1600
1601pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1602{
1603 pte_t pte;
cf627156
DM		 1604
1605 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1606 pte_val(pte) |= (((unsigned long)space) << 32);
1607 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1608
cf627156 1609 return pte;
c4bce90e
DM		 1610}
1611
1612static unsigned long kern_large_tte(unsigned long paddr)
1613{
1614 unsigned long val;
1615
1616 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1617 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1618 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1619 if (tlb_type == hypervisor)
1620 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1621 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1622 _PAGE_EXEC_4V | _PAGE_W_4V);
1623
1624 return val | paddr;
1625}
1626
1627/*
1628 * Translate PROM's mapping we capture at boot time into physical address.
1629 * The second parameter is only set from prom_callback() invocations.
1630 */
1631unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1632{
1633 unsigned long mask;
1634 int i;
1635
1636 mask = _PAGE_PADDR_4U;
1637 if (tlb_type == hypervisor)
1638 mask = _PAGE_PADDR_4V;
1639
1640 for (i = 0; i < prom_trans_ents; i++) {
1641 struct linux_prom_translation *p = &prom_trans[i];
1642
1643 if (promva >= p->virt &&
1644 promva < (p->virt + p->size)) {
1645 unsigned long base = p->data & mask;
1646
1647 if (error)
1648 *error = 0;
1649 return base + (promva & (8192 - 1));
1650 }
1651 }
1652 if (error)
1653 *error = 1;
1654 return 0UL;
1655}
1656
1657/* XXX We should kill off this ugly thing at so me point. XXX */
1658unsigned long sun4u_get_pte(unsigned long addr)
1659{
1660 pgd_t *pgdp;
1661 pud_t *pudp;
1662 pmd_t *pmdp;
1663 pte_t *ptep;
1664 unsigned long mask = _PAGE_PADDR_4U;
1665
1666 if (tlb_type == hypervisor)
1667 mask = _PAGE_PADDR_4V;
1668
1669 if (addr >= PAGE_OFFSET)
1670 return addr & mask;
1671
1672 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1673 return prom_virt_to_phys(addr, NULL);
1674
1675 pgdp = pgd_offset_k(addr);
1676 pudp = pud_offset(pgdp, addr);
1677 pmdp = pmd_offset(pudp, addr);
1678 ptep = pte_offset_kernel(pmdp, addr);
1679
1680 return pte_val(*ptep) & mask;
1681}
1682
1683/* If not locked, zap it. */
1684void __flush_tlb_all(void)
1685{
1686 unsigned long pstate;
1687 int i;
1688
1689 __asm__ __volatile__("flushw\n\t"
1690 "rdpr %%pstate, %0\n\t"
1691 "wrpr %0, %1, %%pstate"
1692 : "=r" (pstate)
1693 : "i" (PSTATE_IE));
1694 if (tlb_type == spitfire) {
1695 for (i = 0; i < 64; i++) {
1696 /* Spitfire Errata #32 workaround */
1697 /* NOTE: Always runs on spitfire, so no
1698 * cheetah+ page size encodings.
1699 */
1700 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1701 "flush %%g6"
1702 : /* No outputs */
1703 : "r" (0),
1704 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1705
1706 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1707 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1708 "membar #Sync"
1709 : /* no outputs */
1710 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1711 spitfire_put_dtlb_data(i, 0x0UL);
1712 }
1713
1714 /* Spitfire Errata #32 workaround */
1715 /* NOTE: Always runs on spitfire, so no
1716 * cheetah+ page size encodings.
1717 */
1718 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1719 "flush %%g6"
1720 : /* No outputs */
1721 : "r" (0),
1722 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1723
1724 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1725 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1726 "membar #Sync"
1727 : /* no outputs */
1728 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1729 spitfire_put_itlb_data(i, 0x0UL);
1730 }
1731 }
1732 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1733 cheetah_flush_dtlb_all();
1734 cheetah_flush_itlb_all();
1735 }
1736 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1737 : : "r" (pstate));
1738}
Linux kernel - Deliverables
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