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[SPARC64]: Only use bypass accesses to INO buckets.
[deliverable/linux.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
c9cf5528 20#include <linux/poison.h>
1da177e4
LT		 21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
5cbc3073 26#include <linux/percpu.h>
1da177e4
LT		 27
28#include <asm/head.h>
29#include <asm/system.h>
30#include <asm/page.h>
31#include <asm/pgalloc.h>
32#include <asm/pgtable.h>
33#include <asm/oplib.h>
34#include <asm/iommu.h>
35#include <asm/io.h>
36#include <asm/uaccess.h>
37#include <asm/mmu_context.h>
38#include <asm/tlbflush.h>
39#include <asm/dma.h>
40#include <asm/starfire.h>
41#include <asm/tlb.h>
42#include <asm/spitfire.h>
43#include <asm/sections.h>
517af332 44#include <asm/tsb.h>
481295f9 45#include <asm/hypervisor.h>
372b07bb 46#include <asm/prom.h>
22d6a1cb 47#include <asm/sstate.h>
5cbc3073 48#include <asm/mdesc.h>
1da177e4 49
9cc3a1ac
DM		 50#define MAX_PHYS_ADDRESS (1UL << 42UL)
51#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
52#define KPTE_BITMAP_BYTES \
53 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
54
55unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57/* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
d1acb421 63#ifndef CONFIG_DEBUG_PAGEALLOC
2d9e2763
DM		 64/* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 69#endif
d7744a09 70
13edad7a
DM		 71#define MAX_BANKS 32
72
73static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
74static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
75static int pavail_ents __initdata;
76static int pavail_rescan_ents __initdata;
77
78static int cmp_p64(const void *a, const void *b)
79{
80 const struct linux_prom64_registers *x = a, *y = b;
81
82 if (x->phys_addr > y->phys_addr)
83 return 1;
84 if (x->phys_addr < y->phys_addr)
85 return -1;
86 return 0;
87}
88
89static void __init read_obp_memory(const char *property,
90 struct linux_prom64_registers *regs,
91 int *num_ents)
92{
93 int node = prom_finddevice("/memory");
94 int prop_size = prom_getproplen(node, property);
95 int ents, ret, i;
96
97 ents = prop_size / sizeof(struct linux_prom64_registers);
98 if (ents > MAX_BANKS) {
99 prom_printf("The machine has more %s property entries than "
100 "this kernel can support (%d).\n",
101 property, MAX_BANKS);
102 prom_halt();
103 }
104
105 ret = prom_getproperty(node, property, (char *) regs, prop_size);
106 if (ret == -1) {
107 prom_printf("Couldn't get %s property from /memory.\n");
108 prom_halt();
109 }
110
13edad7a
DM		 111 /* Sanitize what we got from the firmware, by page aligning
112 * everything.
113 */
114 for (i = 0; i < ents; i++) {
115 unsigned long base, size;
116
117 base = regs[i].phys_addr;
118 size = regs[i].reg_size;
10147570 119
13edad7a
DM		 120 size &= PAGE_MASK;
121 if (base & ~PAGE_MASK) {
122 unsigned long new_base = PAGE_ALIGN(base);
123
124 size -= new_base - base;
125 if ((long) size < 0L)
126 size = 0UL;
127 base = new_base;
128 }
0015d3d6
DM		 129 if (size == 0UL) {
130 /* If it is empty, simply get rid of it.
131 * This simplifies the logic of the other
132 * functions that process these arrays.
133 */
134 memmove(&regs[i], &regs[i + 1],
135 (ents - i - 1) * sizeof(regs[0]));
486ad10a 136 i--;
0015d3d6
DM		 137 ents--;
138 continue;
486ad10a 139 }
0015d3d6
DM		 140 regs[i].phys_addr = base;
141 regs[i].reg_size = size;
486ad10a
DM		 142 }
143
144 *num_ents = ents;
145
c9c10830 146 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 147 cmp_p64, NULL);
148}
1da177e4 149
2bdb3cb2 150unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4 151
d1112018 152/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 153unsigned long kern_base __read_mostly;
154unsigned long kern_size __read_mostly;
1da177e4 155
1da177e4
LT		 156/* Initial ramdisk setup */
157extern unsigned long sparc_ramdisk_image64;
158extern unsigned int sparc_ramdisk_image;
159extern unsigned int sparc_ramdisk_size;
160
1ac4f5eb 161struct page *mem_map_zero __read_mostly;
1da177e4 162
0835ae0f
DM		 163unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
164
165unsigned long sparc64_kern_pri_context __read_mostly;
166unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
167unsigned long sparc64_kern_sec_context __read_mostly;
168
1da177e4
LT		 169int bigkernel = 0;
170
1da177e4
LT		 171#ifdef CONFIG_DEBUG_DCFLUSH
172atomic_t dcpage_flushes = ATOMIC_INIT(0);
173#ifdef CONFIG_SMP
174atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
175#endif
176#endif
177
7a591cfe 178inline void flush_dcache_page_impl(struct page *page)
1da177e4 179{
7a591cfe 180 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 181#ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_inc(&dcpage_flushes);
183#endif
184
185#ifdef DCACHE_ALIASING_POSSIBLE
186 __flush_dcache_page(page_address(page),
187 ((tlb_type == spitfire) &&
188 page_mapping(page) != NULL));
189#else
190 if (page_mapping(page) != NULL &&
191 tlb_type == spitfire)
192 __flush_icache_page(__pa(page_address(page)));
193#endif
194}
195
196#define PG_dcache_dirty PG_arch_1
22adb358
DM		 197#define PG_dcache_cpu_shift 32UL
198#define PG_dcache_cpu_mask \
199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 200
201#define dcache_dirty_cpu(page) \
48b0e548 202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 203
204static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
205{
206 unsigned long mask = this_cpu;
48b0e548
DM		 207 unsigned long non_cpu_bits;
208
209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
211
1da177e4
LT		 212 __asm__ __volatile__("1:\n\t"
213 "ldx [%2], %%g7\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
217 "cmp %%g7, %%g1\n\t"
b445e26c 218 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 219 "bne,pn %%xcc, 1b\n\t"
b445e26c 220 " nop"
1da177e4
LT		 221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224}
225
226static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227{
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
48b0e548 233 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
b445e26c 240 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 241 "bne,pn %%xcc, 1b\n\t"
b445e26c 242 " nop\n"
1da177e4
LT		 243 "2:"
244 : /* no outputs */
245 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 246 "i" (PG_dcache_cpu_mask),
247 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 248 : "g1", "g7");
249}
250
517af332
DM		 251static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
252{
253 unsigned long tsb_addr = (unsigned long) ent;
254
3b3ab2eb 255 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 256 tsb_addr = __pa(tsb_addr);
257
258 __tsb_insert(tsb_addr, tag, pte);
259}
260
c4bce90e
DM		 261unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
262unsigned long _PAGE_SZBITS __read_mostly;
263
1da177e4
LT		 264void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
265{
bd40791e 266 struct mm_struct *mm;
74ae9987 267 struct tsb *tsb;
7a1ac526 268 unsigned long tag, flags;
dcc1e8dd 269 unsigned long tsb_index, tsb_hash_shift;
7a591cfe
DM		 270
271 if (tlb_type != hypervisor) {
272 unsigned long pfn = pte_pfn(pte);
273 unsigned long pg_flags;
274 struct page *page;
275
276 if (pfn_valid(pfn) &&
277 (page = pfn_to_page(pfn), page_mapping(page)) &&
278 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
279 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
280 PG_dcache_cpu_mask);
281 int this_cpu = get_cpu();
282
283 /* This is just to optimize away some function calls
284 * in the SMP case.
285 */
286 if (cpu == this_cpu)
287 flush_dcache_page_impl(page);
288 else
289 smp_flush_dcache_page_impl(page, cpu);
290
291 clear_dcache_dirty_cpu(page, cpu);
292
293 put_cpu();
294 }
1da177e4 295 }
bd40791e
DM		 296
297 mm = vma->vm_mm;
7a1ac526 298
dcc1e8dd
DM		 299 tsb_index = MM_TSB_BASE;
300 tsb_hash_shift = PAGE_SHIFT;
301
7a1ac526
DM		 302 spin_lock_irqsave(&mm->context.lock, flags);
303
dcc1e8dd
DM		 304#ifdef CONFIG_HUGETLB_PAGE
305 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
306 if ((tlb_type == hypervisor &&
307 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
308 (tlb_type != hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
310 tsb_index = MM_TSB_HUGE;
311 tsb_hash_shift = HPAGE_SHIFT;
312 }
313 }
314#endif
315
316 tsb = mm->context.tsb_block[tsb_index].tsb;
317 tsb += ((address >> tsb_hash_shift) &
318 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 319 tag = (address >> 22UL);
320 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 321
322 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 323}
324
325void flush_dcache_page(struct page *page)
326{
a9546f59
DM		 327 struct address_space *mapping;
328 int this_cpu;
1da177e4 329
7a591cfe
DM		 330 if (tlb_type == hypervisor)
331 return;
332
a9546f59
DM		 333 /* Do not bother with the expensive D-cache flush if it
334 * is merely the zero page. The 'bigcore' testcase in GDB
335 * causes this case to run millions of times.
336 */
337 if (page == ZERO_PAGE(0))
338 return;
339
340 this_cpu = get_cpu();
341
342 mapping = page_mapping(page);
1da177e4 343 if (mapping && !mapping_mapped(mapping)) {
a9546f59 344 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 345 if (dirty) {
a9546f59
DM		 346 int dirty_cpu = dcache_dirty_cpu(page);
347
1da177e4
LT		 348 if (dirty_cpu == this_cpu)
349 goto out;
350 smp_flush_dcache_page_impl(page, dirty_cpu);
351 }
352 set_dcache_dirty(page, this_cpu);
353 } else {
354 /* We could delay the flush for the !page_mapping
355 * case too. But that case is for exec env/arg
356 * pages and those are %99 certainly going to get
357 * faulted into the tlb (and thus flushed) anyways.
358 */
359 flush_dcache_page_impl(page);
360 }
361
362out:
363 put_cpu();
364}
365
05e14cb3 366void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 367{
a43fe0e7 368 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 369 if (tlb_type == spitfire) {
370 unsigned long kaddr;
371
a94aa253
DM		 372 /* This code only runs on Spitfire cpus so this is
373 * why we can assume _PAGE_PADDR_4U.
374 */
375 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
376 unsigned long paddr, mask = _PAGE_PADDR_4U;
377
378 if (kaddr >= PAGE_OFFSET)
379 paddr = kaddr & mask;
380 else {
381 pgd_t *pgdp = pgd_offset_k(kaddr);
382 pud_t *pudp = pud_offset(pgdp, kaddr);
383 pmd_t *pmdp = pmd_offset(pudp, kaddr);
384 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
385
386 paddr = pte_val(*ptep) & mask;
387 }
388 __flush_icache_page(paddr);
389 }
1da177e4
LT		 390 }
391}
392
1da177e4
LT		 393void show_mem(void)
394{
5be4a963
DM		 395 unsigned long total = 0, reserved = 0;
396 unsigned long shared = 0, cached = 0;
397 pg_data_t *pgdat;
398
28256ca2 399 printk(KERN_INFO "Mem-info:\n");
1da177e4 400 show_free_areas();
28256ca2 401 printk(KERN_INFO "Free swap: %6ldkB\n",
1da177e4 402 nr_swap_pages << (PAGE_SHIFT-10));
5be4a963
DM		 403 for_each_online_pgdat(pgdat) {
404 unsigned long i, flags;
405
406 pgdat_resize_lock(pgdat, &flags);
407 for (i = 0; i < pgdat->node_spanned_pages; i++) {
408 struct page *page = pgdat_page_nr(pgdat, i);
409 total++;
410 if (PageReserved(page))
411 reserved++;
412 else if (PageSwapCache(page))
413 cached++;
414 else if (page_count(page))
415 shared += page_count(page) - 1;
416 }
417 pgdat_resize_unlock(pgdat, &flags);
418 }
419
420 printk(KERN_INFO "%lu pages of RAM\n", total);
421 printk(KERN_INFO "%lu reserved pages\n", reserved);
422 printk(KERN_INFO "%lu pages shared\n", shared);
423 printk(KERN_INFO "%lu pages swap cached\n", cached);
424
425 printk(KERN_INFO "%lu pages dirty\n",
426 global_page_state(NR_FILE_DIRTY));
427 printk(KERN_INFO "%lu pages writeback\n",
428 global_page_state(NR_WRITEBACK));
429 printk(KERN_INFO "%lu pages mapped\n",
430 global_page_state(NR_FILE_MAPPED));
431 printk(KERN_INFO "%lu pages slab\n",
432 global_page_state(NR_SLAB_RECLAIMABLE) +
433 global_page_state(NR_SLAB_UNRECLAIMABLE));
434 printk(KERN_INFO "%lu pages pagetables\n",
435 global_page_state(NR_PAGETABLE));
1da177e4
LT		 436}
437
438void mmu_info(struct seq_file *m)
439{
440 if (tlb_type == cheetah)
441 seq_printf(m, "MMU Type\t: Cheetah\n");
442 else if (tlb_type == cheetah_plus)
443 seq_printf(m, "MMU Type\t: Cheetah+\n");
444 else if (tlb_type == spitfire)
445 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 446 else if (tlb_type == hypervisor)
447 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 448 else
449 seq_printf(m, "MMU Type\t: ???\n");
450
451#ifdef CONFIG_DEBUG_DCFLUSH
452 seq_printf(m, "DCPageFlushes\t: %d\n",
453 atomic_read(&dcpage_flushes));
454#ifdef CONFIG_SMP
455 seq_printf(m, "DCPageFlushesXC\t: %d\n",
456 atomic_read(&dcpage_flushes_xcall));
457#endif /* CONFIG_SMP */
458#endif /* CONFIG_DEBUG_DCFLUSH */
459}
460
a94aa253
DM		 461struct linux_prom_translation {
462 unsigned long virt;
463 unsigned long size;
464 unsigned long data;
465};
466
467/* Exported for kernel TLB miss handling in ktlb.S */
468struct linux_prom_translation prom_trans[512] __read_mostly;
469unsigned int prom_trans_ents __read_mostly;
470
1da177e4
LT		 471/* Exported for SMP bootup purposes. */
472unsigned long kern_locked_tte_data;
473
c9c10830
DM		 474/* The obp translations are saved based on 8k pagesize, since obp can
475 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 476 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 477 */
5085b4a5
DM		 478static inline int in_obp_range(unsigned long vaddr)
479{
480 return (vaddr >= LOW_OBP_ADDRESS &&
481 vaddr < HI_OBP_ADDRESS);
482}
483
c9c10830 484static int cmp_ptrans(const void *a, const void *b)
405599bd 485{
c9c10830 486 const struct linux_prom_translation *x = a, *y = b;
405599bd 487
c9c10830
DM		 488 if (x->virt > y->virt)
489 return 1;
490 if (x->virt < y->virt)
491 return -1;
492 return 0;
405599bd
DM		 493}
494
c9c10830 495/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 496static void __init read_obp_translations(void)
405599bd 497{
c9c10830 498 int n, node, ents, first, last, i;
1da177e4
LT		 499
500 node = prom_finddevice("/virtual-memory");
501 n = prom_getproplen(node, "translations");
405599bd 502 if (unlikely(n == 0 || n == -1)) {
b206fc4c 503 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 504 prom_halt();
505 }
405599bd
DM		 506 if (unlikely(n > sizeof(prom_trans))) {
507 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 508 prom_halt();
509 }
405599bd 510
b206fc4c 511 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 512 (char *)&prom_trans[0],
513 sizeof(prom_trans))) == -1) {
b206fc4c 514 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 515 prom_halt();
516 }
9ad98c5b 517
b206fc4c 518 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 519
c9c10830
DM		 520 ents = n;
521
522 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
523 cmp_ptrans, NULL);
524
525 /* Now kick out all the non-OBP entries. */
526 for (i = 0; i < ents; i++) {
527 if (in_obp_range(prom_trans[i].virt))
528 break;
529 }
530 first = i;
531 for (; i < ents; i++) {
532 if (!in_obp_range(prom_trans[i].virt))
533 break;
534 }
535 last = i;
536
537 for (i = 0; i < (last - first); i++) {
538 struct linux_prom_translation *src = &prom_trans[i + first];
539 struct linux_prom_translation *dest = &prom_trans[i];
540
541 *dest = *src;
542 }
543 for (; i < ents; i++) {
544 struct linux_prom_translation *dest = &prom_trans[i];
545 dest->virt = dest->size = dest->data = 0x0UL;
546 }
547
548 prom_trans_ents = last - first;
549
550 if (tlb_type == spitfire) {
551 /* Clear diag TTE bits. */
552 for (i = 0; i < prom_trans_ents; i++)
553 prom_trans[i].data &= ~0x0003fe0000000000UL;
554 }
405599bd 555}
1da177e4 556
d82ace7d
DM		 557static void __init hypervisor_tlb_lock(unsigned long vaddr,
558 unsigned long pte,
559 unsigned long mmu)
560{
7db35f31
DM		 561 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
562
563 if (ret != 0) {
12e126ad 564 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
7db35f31 565 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 566 prom_halt();
567 }
d82ace7d
DM		 568}
569
c4bce90e
DM		 570static unsigned long kern_large_tte(unsigned long paddr);
571
898cf0ec 572static void __init remap_kernel(void)
405599bd
DM		 573{
574 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 575 int tlb_ent = sparc64_highest_locked_tlbent();
576
1da177e4 577 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 578 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 579 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 580
581 kern_locked_tte_data = tte_data;
582
d82ace7d
DM		 583 /* Now lock us into the TLBs via Hypervisor or OBP. */
584 if (tlb_type == hypervisor) {
585 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
586 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
587 if (bigkernel) {
588 tte_vaddr += 0x400000;
589 tte_data += 0x400000;
590 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
591 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
592 }
593 } else {
594 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
595 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
596 if (bigkernel) {
597 tlb_ent -= 1;
598 prom_dtlb_load(tlb_ent,
599 tte_data + 0x400000,
600 tte_vaddr + 0x400000);
601 prom_itlb_load(tlb_ent,
602 tte_data + 0x400000,
603 tte_vaddr + 0x400000);
604 }
605 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
1da177e4 606 }
0835ae0f
DM		 607 if (tlb_type == cheetah_plus) {
608 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
609 CTX_CHEETAH_PLUS_NUC);
610 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
611 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
612 }
405599bd 613}
1da177e4 614
405599bd 615
c9c10830 616static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 617{
618 read_obp_translations();
405599bd
DM		 619
620 /* Now fixup OBP's idea about where we really are mapped. */
621 prom_printf("Remapping the kernel... ");
622 remap_kernel();
1da177e4 623 prom_printf("done.\n");
1da177e4
LT		 624}
625
1da177e4
LT		 626void prom_world(int enter)
627{
1da177e4
LT		 628 if (!enter)
629 set_fs((mm_segment_t) { get_thread_current_ds() });
630
3487d1d4 631 __asm__ __volatile__("flushw");
1da177e4
LT		 632}
633
1da177e4
LT		 634void __flush_dcache_range(unsigned long start, unsigned long end)
635{
636 unsigned long va;
637
638 if (tlb_type == spitfire) {
639 int n = 0;
640
641 for (va = start; va < end; va += 32) {
642 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
643 if (++n >= 512)
644 break;
645 }
a43fe0e7 646 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 647 start = __pa(start);
648 end = __pa(end);
649 for (va = start; va < end; va += 32)
650 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
651 "membar #Sync"
652 : /* no outputs */
653 : "r" (va),
654 "i" (ASI_DCACHE_INVALIDATE));
655 }
656}
1da177e4 657
85f1e1f6
DM		 658/* get_new_mmu_context() uses "cache + 1". */
659DEFINE_SPINLOCK(ctx_alloc_lock);
660unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
661#define MAX_CTX_NR (1UL << CTX_NR_BITS)
662#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
663DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
664
1da177e4
LT		 665/* Caller does TLB context flushing on local CPU if necessary.
666 * The caller also ensures that CTX_VALID(mm->context) is false.
667 *
668 * We must be careful about boundary cases so that we never
669 * let the user have CTX 0 (nucleus) or we ever use a CTX
670 * version of zero (and thus NO_CONTEXT would not be caught
671 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 672 *
673 * Always invoked with interrupts disabled.
1da177e4
LT		 674 */
675void get_new_mmu_context(struct mm_struct *mm)
676{
677 unsigned long ctx, new_ctx;
678 unsigned long orig_pgsz_bits;
a77754b4 679 unsigned long flags;
a0663a79 680 int new_version;
1da177e4 681
a77754b4 682 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 683 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
684 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
685 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 686 new_version = 0;
1da177e4
LT		 687 if (new_ctx >= (1 << CTX_NR_BITS)) {
688 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
689 if (new_ctx >= ctx) {
690 int i;
691 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
692 CTX_FIRST_VERSION;
693 if (new_ctx == 1)
694 new_ctx = CTX_FIRST_VERSION;
695
696 /* Don't call memset, for 16 entries that's just
697 * plain silly...
698 */
699 mmu_context_bmap[0] = 3;
700 mmu_context_bmap[1] = 0;
701 mmu_context_bmap[2] = 0;
702 mmu_context_bmap[3] = 0;
703 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
704 mmu_context_bmap[i + 0] = 0;
705 mmu_context_bmap[i + 1] = 0;
706 mmu_context_bmap[i + 2] = 0;
707 mmu_context_bmap[i + 3] = 0;
708 }
a0663a79 709 new_version = 1;
1da177e4
LT		 710 goto out;
711 }
712 }
713 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
714 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
715out:
716 tlb_context_cache = new_ctx;
717 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 718 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 719
720 if (unlikely(new_version))
721 smp_new_mmu_context_version();
1da177e4
LT		 722}
723
d1112018
DM		 724/* Find a free area for the bootmem map, avoiding the kernel image
725 * and the initial ramdisk.
726 */
727static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
728 unsigned long end_pfn)
1da177e4 729{
d1112018
DM		 730 unsigned long avoid_start, avoid_end, bootmap_size;
731 int i;
732
39964653
DM		 733 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
734 bootmap_size <<= PAGE_SHIFT;
d1112018
DM		 735
736 avoid_start = avoid_end = 0;
737#ifdef CONFIG_BLK_DEV_INITRD
738 avoid_start = initrd_start;
739 avoid_end = PAGE_ALIGN(initrd_end);
740#endif
741
742#ifdef CONFIG_DEBUG_BOOTMEM
743 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
744 kern_base, PAGE_ALIGN(kern_base + kern_size),
745 avoid_start, avoid_end);
746#endif
747 for (i = 0; i < pavail_ents; i++) {
748 unsigned long start, end;
749
750 start = pavail[i].phys_addr;
751 end = start + pavail[i].reg_size;
752
753 while (start < end) {
754 if (start >= kern_base &&
755 start < PAGE_ALIGN(kern_base + kern_size)) {
756 start = PAGE_ALIGN(kern_base + kern_size);
757 continue;
758 }
759 if (start >= avoid_start && start < avoid_end) {
760 start = avoid_end;
761 continue;
762 }
763
764 if ((end - start) < bootmap_size)
765 break;
766
767 if (start < kern_base &&
768 (start + bootmap_size) > kern_base) {
769 start = PAGE_ALIGN(kern_base + kern_size);
770 continue;
771 }
772
773 if (start < avoid_start &&
774 (start + bootmap_size) > avoid_start) {
775 start = avoid_end;
776 continue;
777 }
778
779 /* OK, it doesn't overlap anything, use it. */
780#ifdef CONFIG_DEBUG_BOOTMEM
781 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
782 start >> PAGE_SHIFT, start);
783#endif
784 return start >> PAGE_SHIFT;
785 }
786 }
787
788 prom_printf("Cannot find free area for bootmap, aborting.\n");
789 prom_halt();
790}
791
6fc5bae7
DM		 792static void __init trim_pavail(unsigned long *cur_size_p,
793 unsigned long *end_of_phys_p)
794{
795 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
796 unsigned long avoid_start, avoid_end;
797 int i;
798
799 to_trim = PAGE_ALIGN(to_trim);
800
801 avoid_start = avoid_end = 0;
802#ifdef CONFIG_BLK_DEV_INITRD
803 avoid_start = initrd_start;
804 avoid_end = PAGE_ALIGN(initrd_end);
805#endif
806
807 /* Trim some pavail[] entries in order to satisfy the
808 * requested "mem=xxx" kernel command line specification.
809 *
810 * We must not trim off the kernel image area nor the
811 * initial ramdisk range (if any). Also, we must not trim
812 * any pavail[] entry down to zero in order to preserve
813 * the invariant that all pavail[] entries have a non-zero
814 * size which is assumed by all of the code in here.
815 */
816 for (i = 0; i < pavail_ents; i++) {
817 unsigned long start, end, kern_end;
818 unsigned long trim_low, trim_high, n;
819
820 kern_end = PAGE_ALIGN(kern_base + kern_size);
821
822 trim_low = start = pavail[i].phys_addr;
823 trim_high = end = start + pavail[i].reg_size;
824
825 if (kern_base >= start &&
826 kern_base < end) {
827 trim_low = kern_base;
828 if (kern_end >= end)
829 continue;
830 }
831 if (kern_end >= start &&
832 kern_end < end) {
833 trim_high = kern_end;
834 }
835 if (avoid_start &&
836 avoid_start >= start &&
837 avoid_start < end) {
838 if (trim_low > avoid_start)
839 trim_low = avoid_start;
840 if (avoid_end >= end)
841 continue;
842 }
843 if (avoid_end &&
844 avoid_end >= start &&
845 avoid_end < end) {
846 if (trim_high < avoid_end)
847 trim_high = avoid_end;
848 }
849
850 if (trim_high <= trim_low)
851 continue;
852
853 if (trim_low == start && trim_high == end) {
854 /* Whole chunk is available for trimming.
855 * Trim all except one page, in order to keep
856 * entry non-empty.
857 */
858 n = (end - start) - PAGE_SIZE;
859 if (n > to_trim)
860 n = to_trim;
861
862 if (n) {
863 pavail[i].phys_addr += n;
864 pavail[i].reg_size -= n;
865 to_trim -= n;
866 }
867 } else {
868 n = (trim_low - start);
869 if (n > to_trim)
870 n = to_trim;
871
872 if (n) {
873 pavail[i].phys_addr += n;
874 pavail[i].reg_size -= n;
875 to_trim -= n;
876 }
877 if (to_trim) {
878 n = end - trim_high;
879 if (n > to_trim)
880 n = to_trim;
881 if (n) {
882 pavail[i].reg_size -= n;
883 to_trim -= n;
884 }
885 }
886 }
887
888 if (!to_trim)
889 break;
890 }
891
892 /* Recalculate. */
893 *cur_size_p = 0UL;
894 for (i = 0; i < pavail_ents; i++) {
895 *end_of_phys_p = pavail[i].phys_addr +
896 pavail[i].reg_size;
897 *cur_size_p += pavail[i].reg_size;
898 }
899}
900
f1cfdb55
DM		 901/* About pages_avail, this is the value we will use to calculate
902 * the zholes_size[] argument given to free_area_init_node(). The
903 * page allocator uses this to calculate nr_kernel_pages,
904 * nr_all_pages and zone->present_pages. On NUMA it is used
905 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
906 *
907 * So this number should really be set to what the page allocator
908 * actually ends up with. This means:
909 * 1) It should include bootmem map pages, we'll release those.
910 * 2) It should not include the kernel image, except for the
911 * __init sections which we will also release.
912 * 3) It should include the initrd image, since we'll release
913 * that too.
914 */
d1112018
DM		 915static unsigned long __init bootmem_init(unsigned long *pages_avail,
916 unsigned long phys_base)
917{
918 unsigned long bootmap_size, end_pfn;
1da177e4
LT		 919 unsigned long end_of_phys_memory = 0UL;
920 unsigned long bootmap_pfn, bytes_avail, size;
921 int i;
922
923#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 924 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 925#endif
926
927 bytes_avail = 0UL;
13edad7a
DM		 928 for (i = 0; i < pavail_ents; i++) {
929 end_of_phys_memory = pavail[i].phys_addr +
930 pavail[i].reg_size;
931 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 932 }
933
6fc5bae7
DM		 934 /* Determine the location of the initial ramdisk before trying
935 * to honor the "mem=xxx" command line argument. We must know
936 * where the kernel image and the ramdisk image are so that we
937 * do not trim those two areas from the physical memory map.
938 */
1da177e4
LT		 939
940#ifdef CONFIG_BLK_DEV_INITRD
941 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
942 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
943 unsigned long ramdisk_image = sparc_ramdisk_image ?
944 sparc_ramdisk_image : sparc_ramdisk_image64;
715a0ecc 945 ramdisk_image -= KERNBASE;
1da177e4
LT		 946 initrd_start = ramdisk_image + phys_base;
947 initrd_end = initrd_start + sparc_ramdisk_size;
948 if (initrd_end > end_of_phys_memory) {
949 printk(KERN_CRIT "initrd extends beyond end of memory "
950 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
951 initrd_end, end_of_phys_memory);
952 initrd_start = 0;
d1112018 953 initrd_end = 0;
1da177e4
LT		 954 }
955 }
956#endif
6fc5bae7
DM		 957
958 if (cmdline_memory_size &&
959 bytes_avail > cmdline_memory_size)
960 trim_pavail(&bytes_avail,
961 &end_of_phys_memory);
962
963 *pages_avail = bytes_avail >> PAGE_SHIFT;
964
965 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
966
1da177e4
LT		 967 /* Initialize the boot-time allocator. */
968 max_pfn = max_low_pfn = end_pfn;
d1112018
DM		 969 min_low_pfn = (phys_base >> PAGE_SHIFT);
970
971 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1da177e4
LT		 972
973#ifdef CONFIG_DEBUG_BOOTMEM
974 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
975 min_low_pfn, bootmap_pfn, max_low_pfn);
976#endif
d1112018 977 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
17b0e199 978 min_low_pfn, end_pfn);
1da177e4 979
1da177e4
LT		 980 /* Now register the available physical memory with the
981 * allocator.
982 */
13edad7a 983 for (i = 0; i < pavail_ents; i++) {
1da177e4 984#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 985 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
986 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 987#endif
13edad7a 988 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 989 }
990
991#ifdef CONFIG_BLK_DEV_INITRD
992 if (initrd_start) {
993 size = initrd_end - initrd_start;
994
e5dd42e4 995 /* Reserve the initrd image area. */
1da177e4
LT		 996#ifdef CONFIG_DEBUG_BOOTMEM
997 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
998 initrd_start, initrd_end);
999#endif
1000 reserve_bootmem(initrd_start, size);
1da177e4
LT		 1001
1002 initrd_start += PAGE_OFFSET;
1003 initrd_end += PAGE_OFFSET;
1004 }
1005#endif
1006 /* Reserve the kernel text/data/bss. */
1007#ifdef CONFIG_DEBUG_BOOTMEM
1008 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1009#endif
1010 reserve_bootmem(kern_base, kern_size);
1011 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1012
f1cfdb55
DM		 1013 /* Add back in the initmem pages. */
1014 size = ((unsigned long)(__init_end) & PAGE_MASK) -
1015 PAGE_ALIGN((unsigned long)__init_begin);
1016 *pages_avail += size >> PAGE_SHIFT;
1017
1da177e4
LT		 1018 /* Reserve the bootmem map. We do not account for it
1019 * in pages_avail because we will release that memory
1020 * in free_all_bootmem.
1021 */
1022 size = bootmap_size;
1023#ifdef CONFIG_DEBUG_BOOTMEM
1024 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1025 (bootmap_pfn << PAGE_SHIFT), size);
1026#endif
1027 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1da177e4 1028
d1112018
DM		 1029 for (i = 0; i < pavail_ents; i++) {
1030 unsigned long start_pfn, end_pfn;
1031
1032 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1033 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1034#ifdef CONFIG_DEBUG_BOOTMEM
1035 prom_printf("memory_present(0, %lx, %lx)\n",
1036 start_pfn, end_pfn);
1037#endif
1038 memory_present(0, start_pfn, end_pfn);
1039 }
1040
1041 sparse_init();
1042
1da177e4
LT		 1043 return end_pfn;
1044}
1045
9cc3a1ac
DM		 1046static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1047static int pall_ents __initdata;
1048
56425306
DM		 1049#ifdef CONFIG_DEBUG_PAGEALLOC
1050static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1051{
1052 unsigned long vstart = PAGE_OFFSET + pstart;
1053 unsigned long vend = PAGE_OFFSET + pend;
1054 unsigned long alloc_bytes = 0UL;
1055
1056 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1057 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1058 vstart, vend);
1059 prom_halt();
1060 }
1061
1062 while (vstart < vend) {
1063 unsigned long this_end, paddr = __pa(vstart);
1064 pgd_t *pgd = pgd_offset_k(vstart);
1065 pud_t *pud;
1066 pmd_t *pmd;
1067 pte_t *pte;
1068
1069 pud = pud_offset(pgd, vstart);
1070 if (pud_none(*pud)) {
1071 pmd_t *new;
1072
1073 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1074 alloc_bytes += PAGE_SIZE;
1075 pud_populate(&init_mm, pud, new);
1076 }
1077
1078 pmd = pmd_offset(pud, vstart);
1079 if (!pmd_present(*pmd)) {
1080 pte_t *new;
1081
1082 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1083 alloc_bytes += PAGE_SIZE;
1084 pmd_populate_kernel(&init_mm, pmd, new);
1085 }
1086
1087 pte = pte_offset_kernel(pmd, vstart);
1088 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1089 if (this_end > vend)
1090 this_end = vend;
1091
1092 while (vstart < this_end) {
1093 pte_val(*pte) = (paddr | pgprot_val(prot));
1094
1095 vstart += PAGE_SIZE;
1096 paddr += PAGE_SIZE;
1097 pte++;
1098 }
1099 }
1100
1101 return alloc_bytes;
1102}
1103
56425306 1104extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1105#endif /* CONFIG_DEBUG_PAGEALLOC */
1106
1107static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1108{
1109 const unsigned long shift_256MB = 28;
1110 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1111 const unsigned long size_256MB = (1UL << shift_256MB);
1112
1113 while (start < end) {
1114 long remains;
1115
f7c00338
DM		 1116 remains = end - start;
1117 if (remains < size_256MB)
1118 break;
1119
9cc3a1ac
DM		 1120 if (start & mask_256MB) {
1121 start = (start + size_256MB) & ~mask_256MB;
1122 continue;
1123 }
1124
9cc3a1ac
DM		 1125 while (remains >= size_256MB) {
1126 unsigned long index = start >> shift_256MB;
1127
1128 __set_bit(index, kpte_linear_bitmap);
1129
1130 start += size_256MB;
1131 remains -= size_256MB;
1132 }
1133 }
1134}
56425306
DM		 1135
1136static void __init kernel_physical_mapping_init(void)
1137{
9cc3a1ac
DM		 1138 unsigned long i;
1139#ifdef CONFIG_DEBUG_PAGEALLOC
1140 unsigned long mem_alloced = 0UL;
1141#endif
56425306 1142
13edad7a
DM		 1143 read_obp_memory("reg", &pall[0], &pall_ents);
1144
1145 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1146 unsigned long phys_start, phys_end;
1147
13edad7a
DM		 1148 phys_start = pall[i].phys_addr;
1149 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1150
1151 mark_kpte_bitmap(phys_start, phys_end);
1152
1153#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1154 mem_alloced += kernel_map_range(phys_start, phys_end,
1155 PAGE_KERNEL);
9cc3a1ac 1156#endif
56425306
DM		 1157 }
1158
9cc3a1ac 1159#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1160 printk("Allocated %ld bytes for kernel page tables.\n",
1161 mem_alloced);
1162
1163 kvmap_linear_patch[0] = 0x01000000; /* nop */
1164 flushi(&kvmap_linear_patch[0]);
1165
1166 __flush_tlb_all();
9cc3a1ac 1167#endif
56425306
DM		 1168}
1169
9cc3a1ac 1170#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1171void kernel_map_pages(struct page *page, int numpages, int enable)
1172{
1173 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1174 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1175
1176 kernel_map_range(phys_start, phys_end,
1177 (enable ? PAGE_KERNEL : __pgprot(0)));
1178
74bf4312
DM		 1179 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1180 PAGE_OFFSET + phys_end);
1181
56425306
DM		 1182 /* we should perform an IPI and flush all tlbs,
1183 * but that can deadlock->flush only current cpu.
1184 */
1185 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1186 PAGE_OFFSET + phys_end);
1187}
1188#endif
1189
10147570
DM		 1190unsigned long __init find_ecache_flush_span(unsigned long size)
1191{
0836a0eb
DM		 1192 int i;
1193
13edad7a
DM		 1194 for (i = 0; i < pavail_ents; i++) {
1195 if (pavail[i].reg_size >= size)
1196 return pavail[i].phys_addr;
0836a0eb
DM		 1197 }
1198
13edad7a 1199 return ~0UL;
0836a0eb
DM		 1200}
1201
517af332
DM		 1202static void __init tsb_phys_patch(void)
1203{
d257d5da 1204 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1205 struct tsb_phys_patch_entry *p;
1206
d257d5da
DM		 1207 pquad = &__tsb_ldquad_phys_patch;
1208 while (pquad < &__tsb_ldquad_phys_patch_end) {
1209 unsigned long addr = pquad->addr;
1210
1211 if (tlb_type == hypervisor)
1212 *(unsigned int *) addr = pquad->sun4v_insn;
1213 else
1214 *(unsigned int *) addr = pquad->sun4u_insn;
1215 wmb();
1216 __asm__ __volatile__("flush %0"
1217 : /* no outputs */
1218 : "r" (addr));
1219
1220 pquad++;
1221 }
1222
517af332
DM		 1223 p = &__tsb_phys_patch;
1224 while (p < &__tsb_phys_patch_end) {
1225 unsigned long addr = p->addr;
1226
1227 *(unsigned int *) addr = p->insn;
1228 wmb();
1229 __asm__ __volatile__("flush %0"
1230 : /* no outputs */
1231 : "r" (addr));
1232
1233 p++;
1234 }
1235}
1236
490384e7 1237/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1238#ifndef CONFIG_DEBUG_PAGEALLOC
1239#define NUM_KTSB_DESCR 2
1240#else
1241#define NUM_KTSB_DESCR 1
1242#endif
1243static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1244extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1245
1246static void __init sun4v_ktsb_init(void)
1247{
1248 unsigned long ktsb_pa;
1249
d7744a09 1250 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1251 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1252
1253 switch (PAGE_SIZE) {
1254 case 8 * 1024:
1255 default:
1256 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1257 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1258 break;
1259
1260 case 64 * 1024:
1261 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1262 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1263 break;
1264
1265 case 512 * 1024:
1266 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1267 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1268 break;
1269
1270 case 4 * 1024 * 1024:
1271 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1272 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1273 break;
1274 };
1275
3f19a84e 1276 ktsb_descr[0].assoc = 1;
490384e7
DM		 1277 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1278 ktsb_descr[0].ctx_idx = 0;
1279 ktsb_descr[0].tsb_base = ktsb_pa;
1280 ktsb_descr[0].resv = 0;
1281
d1acb421 1282#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09
DM		 1283 /* Second KTSB for 4MB/256MB mappings. */
1284 ktsb_pa = (kern_base +
1285 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1286
1287 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1288 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1289 HV_PGSZ_MASK_256MB);
1290 ktsb_descr[1].assoc = 1;
1291 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1292 ktsb_descr[1].ctx_idx = 0;
1293 ktsb_descr[1].tsb_base = ktsb_pa;
1294 ktsb_descr[1].resv = 0;
d1acb421 1295#endif
490384e7
DM		 1296}
1297
1298void __cpuinit sun4v_ktsb_register(void)
1299{
7db35f31 1300 unsigned long pa, ret;
490384e7
DM		 1301
1302 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1303
7db35f31
DM		 1304 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1305 if (ret != 0) {
1306 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1307 "errors with %lx\n", pa, ret);
1308 prom_halt();
1309 }
490384e7
DM		 1310}
1311
1da177e4
LT		 1312/* paging_init() sets up the page tables */
1313
1314extern void cheetah_ecache_flush_init(void);
d257d5da 1315extern void sun4v_patch_tlb_handlers(void);
1da177e4 1316
5cbc3073
DM		 1317extern void cpu_probe(void);
1318extern void central_probe(void);
1319
1da177e4 1320static unsigned long last_valid_pfn;
56425306 1321pgd_t swapper_pg_dir[2048];
1da177e4 1322
c4bce90e
DM		 1323static void sun4u_pgprot_init(void);
1324static void sun4v_pgprot_init(void);
1325
1da177e4
LT		 1326void __init paging_init(void)
1327{
d1112018 1328 unsigned long end_pfn, pages_avail, shift, phys_base;
0836a0eb
DM		 1329 unsigned long real_end, i;
1330
22adb358
DM		 1331 /* These build time checkes make sure that the dcache_dirty_cpu()
1332 * page->flags usage will work.
1333 *
1334 * When a page gets marked as dcache-dirty, we store the
1335 * cpu number starting at bit 32 in the page->flags. Also,
1336 * functions like clear_dcache_dirty_cpu use the cpu mask
1337 * in 13-bit signed-immediate instruction fields.
1338 */
1339 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1340 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1341 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1342 BUILD_BUG_ON(NR_CPUS > 4096);
1343
481295f9
DM		 1344 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1345 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1346
22d6a1cb
DM		 1347 sstate_booting();
1348
d7744a09 1349 /* Invalidate both kernel TSBs. */
8b234274 1350 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1351#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1352 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1353#endif
8b234274 1354
c4bce90e
DM		 1355 if (tlb_type == hypervisor)
1356 sun4v_pgprot_init();
1357 else
1358 sun4u_pgprot_init();
1359
d257d5da
DM		 1360 if (tlb_type == cheetah_plus ||
1361 tlb_type == hypervisor)
517af332
DM		 1362 tsb_phys_patch();
1363
490384e7 1364 if (tlb_type == hypervisor) {
d257d5da 1365 sun4v_patch_tlb_handlers();
490384e7
DM		 1366 sun4v_ktsb_init();
1367 }
d257d5da 1368
13edad7a
DM		 1369 /* Find available physical memory... */
1370 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1371
1372 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1373 for (i = 0; i < pavail_ents; i++)
1374 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1375
1da177e4
LT		 1376 set_bit(0, mmu_context_bmap);
1377
2bdb3cb2
DM		 1378 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1379
1da177e4
LT		 1380 real_end = (unsigned long)_end;
1381 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1382 bigkernel = 1;
2bdb3cb2
DM		 1383 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1384 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1385 prom_halt();
1da177e4 1386 }
2bdb3cb2
DM		 1387
1388 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1389 * work.
1390 */
1391 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1392
56425306 1393 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1394
1395 /* Now can init the kernel/bad page tables. */
1396 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1397 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1398
c9c10830 1399 inherit_prom_mappings();
5085b4a5 1400
a8b900d8
DM		 1401 /* Ok, we can use our TLB miss and window trap handlers safely. */
1402 setup_tba();
1da177e4 1403
c9c10830 1404 __flush_tlb_all();
9ad98c5b 1405
490384e7
DM		 1406 if (tlb_type == hypervisor)
1407 sun4v_ktsb_register();
1408
2bdb3cb2
DM		 1409 /* Setup bootmem... */
1410 pages_avail = 0;
d1112018
DM		 1411 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1412
17b0e199 1413 max_mapnr = last_valid_pfn;
2bdb3cb2 1414
56425306 1415 kernel_physical_mapping_init();
56425306 1416
5cbc3073
DM		 1417 real_setup_per_cpu_areas();
1418
372b07bb
DM		 1419 prom_build_devicetree();
1420
5cbc3073
DM		 1421 if (tlb_type == hypervisor)
1422 sun4v_mdesc_init();
1423
1da177e4
LT		 1424 {
1425 unsigned long zones_size[MAX_NR_ZONES];
1426 unsigned long zholes_size[MAX_NR_ZONES];
1da177e4
LT		 1427 int znum;
1428
1429 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1430 zones_size[znum] = zholes_size[znum] = 0;
1431
1b51d3a0
DM		 1432 zones_size[ZONE_NORMAL] = end_pfn;
1433 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1da177e4
LT		 1434
1435 free_area_init_node(0, &contig_page_data, zones_size,
17b0e199
DM		 1436 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1437 zholes_size);
1da177e4
LT		 1438 }
1439
5cbc3073
DM		 1440 prom_printf("Booting Linux...\n");
1441
1442 central_probe();
1443 cpu_probe();
1da177e4
LT		 1444}
1445
1da177e4
LT		 1446static void __init taint_real_pages(void)
1447{
1da177e4
LT		 1448 int i;
1449
13edad7a 1450 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1451
13edad7a 1452 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1453 * reserve the lost portions in the bootmem maps.
1454 */
13edad7a 1455 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1456 unsigned long old_start, old_end;
1457
13edad7a 1458 old_start = pavail[i].phys_addr;
1da177e4 1459 old_end = old_start +
13edad7a 1460 pavail[i].reg_size;
1da177e4
LT		 1461 while (old_start < old_end) {
1462 int n;
1463
c2a5a46b 1464 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1465 unsigned long new_start, new_end;
1466
13edad7a
DM		 1467 new_start = pavail_rescan[n].phys_addr;
1468 new_end = new_start +
1469 pavail_rescan[n].reg_size;
1da177e4
LT		 1470
1471 if (new_start <= old_start &&
1472 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1473 set_bit(old_start >> 22,
1474 sparc64_valid_addr_bitmap);
1da177e4
LT		 1475 goto do_next_page;
1476 }
1477 }
1478 reserve_bootmem(old_start, PAGE_SIZE);
1479
1480 do_next_page:
1481 old_start += PAGE_SIZE;
1482 }
1483 }
1484}
1485
c2a5a46b
DM		 1486int __init page_in_phys_avail(unsigned long paddr)
1487{
1488 int i;
1489
1490 paddr &= PAGE_MASK;
1491
1492 for (i = 0; i < pavail_rescan_ents; i++) {
1493 unsigned long start, end;
1494
1495 start = pavail_rescan[i].phys_addr;
1496 end = start + pavail_rescan[i].reg_size;
1497
1498 if (paddr >= start && paddr < end)
1499 return 1;
1500 }
1501 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1502 return 1;
1503#ifdef CONFIG_BLK_DEV_INITRD
1504 if (paddr >= __pa(initrd_start) &&
1505 paddr < __pa(PAGE_ALIGN(initrd_end)))
1506 return 1;
1507#endif
1508
1509 return 0;
1510}
1511
1da177e4
LT		 1512void __init mem_init(void)
1513{
1514 unsigned long codepages, datapages, initpages;
1515 unsigned long addr, last;
1516 int i;
1517
1518 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1519 i += 1;
2bdb3cb2 1520 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1521 if (sparc64_valid_addr_bitmap == NULL) {
1522 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1523 prom_halt();
1524 }
1525 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1526
1527 addr = PAGE_OFFSET + kern_base;
1528 last = PAGE_ALIGN(kern_size) + addr;
1529 while (addr < last) {
1530 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1531 addr += PAGE_SIZE;
1532 }
1533
1534 taint_real_pages();
1535
1da177e4
LT		 1536 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1537
1538#ifdef CONFIG_DEBUG_BOOTMEM
1539 prom_printf("mem_init: Calling free_all_bootmem().\n");
1540#endif
f1cfdb55
DM		 1541
1542 /* We subtract one to account for the mem_map_zero page
1543 * allocated below.
1544 */
1da177e4
LT		 1545 totalram_pages = num_physpages = free_all_bootmem() - 1;
1546
1547 /*
1548 * Set up the zero page, mark it reserved, so that page count
1549 * is not manipulated when freeing the page from user ptes.
1550 */
1551 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1552 if (mem_map_zero == NULL) {
1553 prom_printf("paging_init: Cannot alloc zero page.\n");
1554 prom_halt();
1555 }
1556 SetPageReserved(mem_map_zero);
1557
1558 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1559 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1560 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1561 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1562 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1563 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1564
96177299 1565 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 1566 nr_free_pages() << (PAGE_SHIFT-10),
1567 codepages << (PAGE_SHIFT-10),
1568 datapages << (PAGE_SHIFT-10),
1569 initpages << (PAGE_SHIFT-10),
1570 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1571
1572 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1573 cheetah_ecache_flush_init();
1574}
1575
898cf0ec 1576void free_initmem(void)
1da177e4
LT		 1577{
1578 unsigned long addr, initend;
1579
1580 /*
1581 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1582 */
1583 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1584 initend = (unsigned long)(__init_end) & PAGE_MASK;
1585 for (; addr < initend; addr += PAGE_SIZE) {
1586 unsigned long page;
1587 struct page *p;
1588
1589 page = (addr +
1590 ((unsigned long) __va(kern_base)) -
1591 ((unsigned long) KERNBASE));
c9cf5528 1592 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4
LT		 1593 p = virt_to_page(page);
1594
1595 ClearPageReserved(p);
7835e98b 1596 init_page_count(p);
1da177e4
LT		 1597 __free_page(p);
1598 num_physpages++;
1599 totalram_pages++;
1600 }
1601}
1602
1603#ifdef CONFIG_BLK_DEV_INITRD
1604void free_initrd_mem(unsigned long start, unsigned long end)
1605{
1606 if (start < end)
1607 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1608 for (; start < end; start += PAGE_SIZE) {
1609 struct page *p = virt_to_page(start);
1610
1611 ClearPageReserved(p);
7835e98b 1612 init_page_count(p);
1da177e4
LT		 1613 __free_page(p);
1614 num_physpages++;
1615 totalram_pages++;
1616 }
1617}
1618#endif
c4bce90e 1619
c4bce90e
DM		 1620#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1621#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1622#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1623#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1624#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1625#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1626
1627pgprot_t PAGE_KERNEL __read_mostly;
1628EXPORT_SYMBOL(PAGE_KERNEL);
1629
1630pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1631pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1632
1633pgprot_t PAGE_SHARED __read_mostly;
1634EXPORT_SYMBOL(PAGE_SHARED);
1635
c4bce90e
DM		 1636pgprot_t PAGE_EXEC __read_mostly;
1637unsigned long pg_iobits __read_mostly;
1638
1639unsigned long _PAGE_IE __read_mostly;
987c74fc 1640EXPORT_SYMBOL(_PAGE_IE);
b2bef442 1641
c4bce90e 1642unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1643EXPORT_SYMBOL(_PAGE_E);
1644
c4bce90e 1645unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1646EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e
DM		 1647
1648static void prot_init_common(unsigned long page_none,
1649 unsigned long page_shared,
1650 unsigned long page_copy,
1651 unsigned long page_readonly,
1652 unsigned long page_exec_bit)
1653{
1654 PAGE_COPY = __pgprot(page_copy);
0f15952a 1655 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1656
1657 protection_map[0x0] = __pgprot(page_none);
1658 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1659 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1660 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1661 protection_map[0x4] = __pgprot(page_readonly);
1662 protection_map[0x5] = __pgprot(page_readonly);
1663 protection_map[0x6] = __pgprot(page_copy);
1664 protection_map[0x7] = __pgprot(page_copy);
1665 protection_map[0x8] = __pgprot(page_none);
1666 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1667 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1668 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1669 protection_map[0xc] = __pgprot(page_readonly);
1670 protection_map[0xd] = __pgprot(page_readonly);
1671 protection_map[0xe] = __pgprot(page_shared);
1672 protection_map[0xf] = __pgprot(page_shared);
1673}
1674
1675static void __init sun4u_pgprot_init(void)
1676{
1677 unsigned long page_none, page_shared, page_copy, page_readonly;
1678 unsigned long page_exec_bit;
1679
1680 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1681 _PAGE_CACHE_4U | _PAGE_P_4U |
1682 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1683 _PAGE_EXEC_4U);
1684 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1685 _PAGE_CACHE_4U | _PAGE_P_4U |
1686 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1687 _PAGE_EXEC_4U | _PAGE_L_4U);
1688 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1689
1690 _PAGE_IE = _PAGE_IE_4U;
1691 _PAGE_E = _PAGE_E_4U;
1692 _PAGE_CACHE = _PAGE_CACHE_4U;
1693
1694 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1695 __ACCESS_BITS_4U | _PAGE_E_4U);
1696
d1acb421
DM		 1697#ifdef CONFIG_DEBUG_PAGEALLOC
1698 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1699 0xfffff80000000000;
1700#else
9cc3a1ac 1701 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1702 0xfffff80000000000;
d1acb421 1703#endif
9cc3a1ac
DM		 1704 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1705 _PAGE_P_4U | _PAGE_W_4U);
1706
1707 /* XXX Should use 256MB on Panther. XXX */
1708 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1709
1710 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1711 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1712 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1713 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1714
1715
1716 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1717 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1718 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1719 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1720 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1721 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1722 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1723
1724 page_exec_bit = _PAGE_EXEC_4U;
1725
1726 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1727 page_exec_bit);
1728}
1729
1730static void __init sun4v_pgprot_init(void)
1731{
1732 unsigned long page_none, page_shared, page_copy, page_readonly;
1733 unsigned long page_exec_bit;
1734
1735 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1736 _PAGE_CACHE_4V | _PAGE_P_4V |
1737 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1738 _PAGE_EXEC_4V);
1739 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1740 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1741
1742 _PAGE_IE = _PAGE_IE_4V;
1743 _PAGE_E = _PAGE_E_4V;
1744 _PAGE_CACHE = _PAGE_CACHE_4V;
1745
d1acb421
DM		 1746#ifdef CONFIG_DEBUG_PAGEALLOC
1747 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1748 0xfffff80000000000;
1749#else
9cc3a1ac
DM		 1750 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1751 0xfffff80000000000;
d1acb421 1752#endif
9cc3a1ac
DM		 1753 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1754 _PAGE_P_4V | _PAGE_W_4V);
1755
d1acb421
DM		 1756#ifdef CONFIG_DEBUG_PAGEALLOC
1757 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1758 0xfffff80000000000;
1759#else
9cc3a1ac 1760 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1761 0xfffff80000000000;
d1acb421 1762#endif
9cc3a1ac
DM		 1763 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1764 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1765
1766 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1767 __ACCESS_BITS_4V | _PAGE_E_4V);
1768
1769 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1770 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1771 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1772 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1773 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1774
1775 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1776 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1777 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1778 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1779 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1780 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1781 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1782
1783 page_exec_bit = _PAGE_EXEC_4V;
1784
1785 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1786 page_exec_bit);
1787}
1788
1789unsigned long pte_sz_bits(unsigned long sz)
1790{
1791 if (tlb_type == hypervisor) {
1792 switch (sz) {
1793 case 8 * 1024:
1794 default:
1795 return _PAGE_SZ8K_4V;
1796 case 64 * 1024:
1797 return _PAGE_SZ64K_4V;
1798 case 512 * 1024:
1799 return _PAGE_SZ512K_4V;
1800 case 4 * 1024 * 1024:
1801 return _PAGE_SZ4MB_4V;
1802 };
1803 } else {
1804 switch (sz) {
1805 case 8 * 1024:
1806 default:
1807 return _PAGE_SZ8K_4U;
1808 case 64 * 1024:
1809 return _PAGE_SZ64K_4U;
1810 case 512 * 1024:
1811 return _PAGE_SZ512K_4U;
1812 case 4 * 1024 * 1024:
1813 return _PAGE_SZ4MB_4U;
1814 };
1815 }
1816}
1817
1818pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1819{
1820 pte_t pte;
cf627156
DM		 1821
1822 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1823 pte_val(pte) |= (((unsigned long)space) << 32);
1824 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1825
cf627156 1826 return pte;
c4bce90e
DM		 1827}
1828
1829static unsigned long kern_large_tte(unsigned long paddr)
1830{
1831 unsigned long val;
1832
1833 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1834 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1835 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1836 if (tlb_type == hypervisor)
1837 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1838 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1839 _PAGE_EXEC_4V | _PAGE_W_4V);
1840
1841 return val | paddr;
1842}
1843
c4bce90e
DM		 1844/* If not locked, zap it. */
1845void __flush_tlb_all(void)
1846{
1847 unsigned long pstate;
1848 int i;
1849
1850 __asm__ __volatile__("flushw\n\t"
1851 "rdpr %%pstate, %0\n\t"
1852 "wrpr %0, %1, %%pstate"
1853 : "=r" (pstate)
1854 : "i" (PSTATE_IE));
1855 if (tlb_type == spitfire) {
1856 for (i = 0; i < 64; i++) {
1857 /* Spitfire Errata #32 workaround */
1858 /* NOTE: Always runs on spitfire, so no
1859 * cheetah+ page size encodings.
1860 */
1861 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1862 "flush %%g6"
1863 : /* No outputs */
1864 : "r" (0),
1865 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1866
1867 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1868 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1869 "membar #Sync"
1870 : /* no outputs */
1871 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1872 spitfire_put_dtlb_data(i, 0x0UL);
1873 }
1874
1875 /* Spitfire Errata #32 workaround */
1876 /* NOTE: Always runs on spitfire, so no
1877 * cheetah+ page size encodings.
1878 */
1879 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1880 "flush %%g6"
1881 : /* No outputs */
1882 : "r" (0),
1883 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1884
1885 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1886 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1887 "membar #Sync"
1888 : /* no outputs */
1889 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1890 spitfire_put_itlb_data(i, 0x0UL);
1891 }
1892 }
1893 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1894 cheetah_flush_dtlb_all();
1895 cheetah_flush_itlb_all();
1896 }
1897 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1898 : : "r" (pstate));
1899}
88d70794
DM		 1900
1901#ifdef CONFIG_MEMORY_HOTPLUG
1902
1903void online_page(struct page *page)
1904{
1905 ClearPageReserved(page);
fcab1e51
NP		 1906 init_page_count(page);
1907 __free_page(page);
88d70794
DM		 1908 totalram_pages++;
1909 num_physpages++;
1910}
1911
1912int remove_memory(u64 start, u64 size)
1913{
1914 return -EINVAL;
1915}
1916
1917#endif /* CONFIG_MEMORY_HOTPLUG */
Linux kernel - Deliverables
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