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867e359b CM |
1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #ifndef _ASM_TILE_PCI_H | |
16 | #define _ASM_TILE_PCI_H | |
17 | ||
41bb38fc | 18 | #include <linux/dma-mapping.h> |
f02cbbe6 | 19 | #include <linux/pci.h> |
12962267 | 20 | #include <linux/numa.h> |
84550121 | 21 | #include <asm-generic/pci_iomap.h> |
f02cbbe6 | 22 | |
12962267 CM |
23 | #ifndef __tilegx__ |
24 | ||
f02cbbe6 CM |
25 | /* |
26 | * Structure of a PCI controller (host bridge) | |
27 | */ | |
28 | struct pci_controller { | |
29 | int index; /* PCI domain number */ | |
30 | struct pci_bus *root_bus; | |
31 | ||
f02cbbe6 CM |
32 | int last_busno; |
33 | ||
34 | int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */ | |
35 | int hv_mem_fd; /* fd to Hypervisor for MMIO operations */ | |
36 | ||
37 | struct pci_ops *ops; | |
38 | ||
39 | int irq_base; /* Base IRQ from the Hypervisor */ | |
40 | int plx_gen1; /* flag for PLX Gen 1 configuration */ | |
41 | ||
42 | /* Address ranges that are routed to this controller/bridge. */ | |
43 | struct resource mem_resources[3]; | |
44 | }; | |
867e359b | 45 | |
12962267 CM |
46 | /* |
47 | * This flag tells if the platform is TILEmpower that needs | |
48 | * special configuration for the PLX switch chip. | |
49 | */ | |
50 | extern int tile_plx_gen1; | |
51 | ||
52 | static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} | |
53 | ||
54 | #define TILE_NUM_PCIE 2 | |
55 | ||
41bb38fc CM |
56 | /* |
57 | * The hypervisor maps the entirety of CPA-space as bus addresses, so | |
58 | * bus addresses are physical addresses. The networking and block | |
59 | * device layers use this boolean for bounce buffer decisions. | |
60 | */ | |
61 | #define PCI_DMA_BUS_IS_PHYS 1 | |
62 | ||
63 | /* generic pci stuff */ | |
64 | #include <asm-generic/pci.h> | |
65 | ||
12962267 CM |
66 | #else |
67 | ||
68 | #include <asm/page.h> | |
69 | #include <gxio/trio.h> | |
70 | ||
71 | /** | |
72 | * We reserve the hugepage-size address range at the top of the 64-bit address | |
73 | * space to serve as the PCI window, emulating the BAR0 space of an endpoint | |
74 | * device. This window is used by the chip-to-chip applications running on | |
75 | * the RC node. The reason for carving out this window is that Mem-Maps that | |
76 | * back up this window will not overlap with those that map the real physical | |
77 | * memory. | |
78 | */ | |
79 | #define PCIE_HOST_BAR0_SIZE HPAGE_SIZE | |
80 | #define PCIE_HOST_BAR0_START HPAGE_MASK | |
81 | ||
82 | /** | |
83 | * The first PAGE_SIZE of the above "BAR" window is mapped to the | |
84 | * gxpci_host_regs structure. | |
85 | */ | |
86 | #define PCIE_HOST_REGS_SIZE PAGE_SIZE | |
87 | ||
88 | /* | |
89 | * This is the PCI address where the Mem-Map interrupt regions start. | |
90 | * We use the 2nd to the last huge page of the 64-bit address space. | |
91 | * The last huge page is used for the rootcomplex "bar", for C2C purpose. | |
92 | */ | |
93 | #define MEM_MAP_INTR_REGIONS_BASE (HPAGE_MASK - HPAGE_SIZE) | |
94 | ||
95 | /* | |
96 | * Each Mem-Map interrupt region occupies 4KB. | |
97 | */ | |
41bb38fc CM |
98 | #define MEM_MAP_INTR_REGION_SIZE (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT) |
99 | ||
100 | /* | |
101 | * Allocate the PCI BAR window right below 4GB. | |
102 | */ | |
103 | #define TILE_PCI_BAR_WINDOW_TOP (1ULL << 32) | |
104 | ||
105 | /* | |
106 | * Allocate 1GB for the PCI BAR window. | |
107 | */ | |
108 | #define TILE_PCI_BAR_WINDOW_SIZE (1 << 30) | |
109 | ||
110 | /* | |
111 | * This is the highest bus address targeting the host memory that | |
112 | * can be generated by legacy PCI devices with 32-bit or less | |
113 | * DMA capability, dictated by the BAR window size and location. | |
114 | */ | |
115 | #define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \ | |
116 | (TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1) | |
117 | ||
118 | /* | |
119 | * We shift the PCI bus range for all the physical memory up by the whole PA | |
120 | * range. The corresponding CPA of an incoming PCI request will be the PCI | |
121 | * address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies | |
122 | * that the 64-bit capable devices will be given DMA addresses as | |
123 | * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit | |
124 | * devices, we create a separate map region that handles the low | |
125 | * 4GB. | |
126 | */ | |
127 | #define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH()) | |
128 | ||
129 | /* | |
f6d2ce00 CM |
130 | * Start of the PCI memory resource, which starts at the end of the |
131 | * maximum system physical RAM address. | |
41bb38fc | 132 | */ |
f6d2ce00 | 133 | #define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH()) |
12962267 CM |
134 | |
135 | /* | |
136 | * Structure of a PCI controller (host bridge) on Gx. | |
137 | */ | |
138 | struct pci_controller { | |
139 | ||
140 | /* Pointer back to the TRIO that this PCIe port is connected to. */ | |
141 | gxio_trio_context_t *trio; | |
142 | int mac; /* PCIe mac index on the TRIO shim */ | |
143 | int trio_index; /* Index of TRIO shim that contains the MAC. */ | |
144 | ||
145 | int pio_mem_index; /* PIO region index for memory access */ | |
146 | ||
cf89c426 CM |
147 | #ifdef CONFIG_TILE_PCI_IO |
148 | int pio_io_index; /* PIO region index for I/O space access */ | |
149 | #endif | |
150 | ||
12962267 CM |
151 | /* |
152 | * Mem-Map regions for all the memory controllers so that Linux can | |
153 | * map all of its physical memory space to the PCI bus. | |
154 | */ | |
155 | int mem_maps[MAX_NUMNODES]; | |
156 | ||
157 | int index; /* PCI domain number */ | |
158 | struct pci_bus *root_bus; | |
159 | ||
cf89c426 CM |
160 | /* PCI I/O space resource for this controller. */ |
161 | struct resource io_space; | |
162 | char io_space_name[32]; | |
163 | ||
f6d2ce00 CM |
164 | /* PCI memory space resource for this controller. */ |
165 | struct resource mem_space; | |
166 | char mem_space_name[32]; | |
167 | ||
41bb38fc CM |
168 | uint64_t mem_offset; /* cpu->bus memory mapping offset. */ |
169 | ||
f6d2ce00 | 170 | int first_busno; |
12962267 CM |
171 | |
172 | struct pci_ops *ops; | |
173 | ||
174 | /* Table that maps the INTx numbers to Linux irq numbers. */ | |
175 | int irq_intx_table[4]; | |
12962267 CM |
176 | }; |
177 | ||
178 | extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES]; | |
179 | extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; | |
1c43649a | 180 | extern int num_trio_shims; |
12962267 CM |
181 | |
182 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *); | |
183 | ||
867e359b | 184 | /* |
41bb38fc CM |
185 | * The PCI address space does not equal the physical memory address |
186 | * space (we have an IOMMU). The IDE and SCSI device layers use this | |
187 | * boolean for bounce buffer decisions. | |
867e359b | 188 | */ |
41bb38fc CM |
189 | #define PCI_DMA_BUS_IS_PHYS 0 |
190 | ||
191 | #endif /* __tilegx__ */ | |
867e359b | 192 | |
05ef1b79 CM |
193 | int __init tile_pci_init(void); |
194 | int __init pcibios_init(void); | |
867e359b | 195 | |
b881bc46 | 196 | void pcibios_fixup_bus(struct pci_bus *bus); |
867e359b | 197 | |
867e359b CM |
198 | #define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index) |
199 | ||
200 | /* | |
201 | * This decides whether to display the domain number in /proc. | |
202 | */ | |
203 | static inline int pci_proc_domain(struct pci_bus *bus) | |
204 | { | |
205 | return 1; | |
206 | } | |
207 | ||
208 | /* | |
f02cbbe6 CM |
209 | * pcibios_assign_all_busses() tells whether or not the bus numbers |
210 | * should be reassigned, in case the BIOS didn't do it correctly, or | |
211 | * in case we don't have a BIOS and we want to let Linux do it. | |
867e359b | 212 | */ |
f02cbbe6 CM |
213 | static inline int pcibios_assign_all_busses(void) |
214 | { | |
215 | return 1; | |
216 | } | |
867e359b | 217 | |
867e359b | 218 | #define PCIBIOS_MIN_MEM 0 |
cf89c426 CM |
219 | /* Minimum PCI I/O address, starting at the page boundary. */ |
220 | #define PCIBIOS_MIN_IO PAGE_SIZE | |
867e359b | 221 | |
f02cbbe6 CM |
222 | /* Use any cpu for PCI. */ |
223 | #define cpumask_of_pcibus(bus) cpu_online_mask | |
867e359b CM |
224 | |
225 | /* implement the pci_ DMA API in terms of the generic device dma_ one */ | |
226 | #include <asm-generic/pci-dma-compat.h> | |
227 | ||
867e359b | 228 | #endif /* _ASM_TILE_PCI_H */ |