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4875f69f CM |
1 | /* |
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | /** | |
16 | * Interface definitions for the mpipe driver. | |
17 | */ | |
18 | ||
19 | #ifndef _SYS_HV_DRV_MPIPE_INTF_H | |
20 | #define _SYS_HV_DRV_MPIPE_INTF_H | |
21 | ||
22 | #include <arch/mpipe.h> | |
23 | #include <arch/mpipe_constants.h> | |
24 | ||
25 | ||
f3286a3a CM |
26 | /** Number of mPIPE instances supported */ |
27 | #define HV_MPIPE_INSTANCE_MAX (2) | |
28 | ||
4875f69f CM |
29 | /** Number of buffer stacks (32). */ |
30 | #define HV_MPIPE_NUM_BUFFER_STACKS \ | |
31 | (MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH) | |
32 | ||
33 | /** Number of NotifRings (256). */ | |
34 | #define HV_MPIPE_NUM_NOTIF_RINGS (MPIPE_NUM_NOTIF_RINGS) | |
35 | ||
36 | /** Number of NotifGroups (32). */ | |
37 | #define HV_MPIPE_NUM_NOTIF_GROUPS (MPIPE_NUM_NOTIF_GROUPS) | |
38 | ||
39 | /** Number of buckets (4160). */ | |
40 | #define HV_MPIPE_NUM_BUCKETS (MPIPE_NUM_BUCKETS) | |
41 | ||
42 | /** Number of "lo" buckets (4096). */ | |
43 | #define HV_MPIPE_NUM_LO_BUCKETS 4096 | |
44 | ||
45 | /** Number of "hi" buckets (64). */ | |
46 | #define HV_MPIPE_NUM_HI_BUCKETS \ | |
47 | (HV_MPIPE_NUM_BUCKETS - HV_MPIPE_NUM_LO_BUCKETS) | |
48 | ||
49 | /** Number of edma rings (24). */ | |
50 | #define HV_MPIPE_NUM_EDMA_RINGS \ | |
51 | (MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH) | |
52 | ||
53 | ||
54 | ||
55 | ||
56 | /** A flag bit indicating a fixed resource allocation. */ | |
57 | #define HV_MPIPE_ALLOC_FIXED 0x01 | |
58 | ||
59 | /** Offset for the config register MMIO region. */ | |
60 | #define HV_MPIPE_CONFIG_MMIO_OFFSET \ | |
61 | (MPIPE_MMIO_ADDR__REGION_VAL_CFG << MPIPE_MMIO_ADDR__REGION_SHIFT) | |
62 | ||
63 | /** Size of the config register MMIO region. */ | |
64 | #define HV_MPIPE_CONFIG_MMIO_SIZE (64 * 1024) | |
65 | ||
66 | /** Offset for the config register MMIO region. */ | |
67 | #define HV_MPIPE_FAST_MMIO_OFFSET \ | |
68 | (MPIPE_MMIO_ADDR__REGION_VAL_IDMA << MPIPE_MMIO_ADDR__REGION_SHIFT) | |
69 | ||
70 | /** Size of the fast register MMIO region (IDMA, EDMA, buffer stack). */ | |
71 | #define HV_MPIPE_FAST_MMIO_SIZE \ | |
72 | ((MPIPE_MMIO_ADDR__REGION_VAL_BSM + 1 - MPIPE_MMIO_ADDR__REGION_VAL_IDMA) \ | |
73 | << MPIPE_MMIO_ADDR__REGION_SHIFT) | |
74 | ||
75 | ||
76 | /* | |
77 | * Each type of resource allocation comes in quantized chunks, where | |
78 | * XXX_BITS is the number of chunks, and XXX_RES_PER_BIT is the number | |
79 | * of resources in each chunk. | |
80 | */ | |
81 | ||
82 | /** Number of buffer stack chunks available (32). */ | |
83 | #define HV_MPIPE_ALLOC_BUFFER_STACKS_BITS \ | |
84 | MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH | |
85 | ||
86 | /** Granularity of buffer stack allocation (1). */ | |
87 | #define HV_MPIPE_ALLOC_BUFFER_STACKS_RES_PER_BIT \ | |
88 | (HV_MPIPE_NUM_BUFFER_STACKS / HV_MPIPE_ALLOC_BUFFER_STACKS_BITS) | |
89 | ||
90 | /** Number of NotifRing chunks available (32). */ | |
91 | #define HV_MPIPE_ALLOC_NOTIF_RINGS_BITS \ | |
92 | MPIPE_MMIO_INIT_DAT_GX36_0__NOTIF_RING_MASK_WIDTH | |
93 | ||
94 | /** Granularity of NotifRing allocation (8). */ | |
95 | #define HV_MPIPE_ALLOC_NOTIF_RINGS_RES_PER_BIT \ | |
96 | (HV_MPIPE_NUM_NOTIF_RINGS / HV_MPIPE_ALLOC_NOTIF_RINGS_BITS) | |
97 | ||
98 | /** Number of NotifGroup chunks available (32). */ | |
99 | #define HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS \ | |
100 | HV_MPIPE_NUM_NOTIF_GROUPS | |
101 | ||
102 | /** Granularity of NotifGroup allocation (1). */ | |
103 | #define HV_MPIPE_ALLOC_NOTIF_GROUPS_RES_PER_BIT \ | |
104 | (HV_MPIPE_NUM_NOTIF_GROUPS / HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS) | |
105 | ||
106 | /** Number of lo bucket chunks available (16). */ | |
107 | #define HV_MPIPE_ALLOC_LO_BUCKETS_BITS \ | |
108 | MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_LO_WIDTH | |
109 | ||
110 | /** Granularity of lo bucket allocation (256). */ | |
111 | #define HV_MPIPE_ALLOC_LO_BUCKETS_RES_PER_BIT \ | |
112 | (HV_MPIPE_NUM_LO_BUCKETS / HV_MPIPE_ALLOC_LO_BUCKETS_BITS) | |
113 | ||
114 | /** Number of hi bucket chunks available (16). */ | |
115 | #define HV_MPIPE_ALLOC_HI_BUCKETS_BITS \ | |
116 | MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_HI_WIDTH | |
117 | ||
118 | /** Granularity of hi bucket allocation (4). */ | |
119 | #define HV_MPIPE_ALLOC_HI_BUCKETS_RES_PER_BIT \ | |
120 | (HV_MPIPE_NUM_HI_BUCKETS / HV_MPIPE_ALLOC_HI_BUCKETS_BITS) | |
121 | ||
122 | /** Number of eDMA ring chunks available (24). */ | |
123 | #define HV_MPIPE_ALLOC_EDMA_RINGS_BITS \ | |
124 | MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH | |
125 | ||
126 | /** Granularity of eDMA ring allocation (1). */ | |
127 | #define HV_MPIPE_ALLOC_EDMA_RINGS_RES_PER_BIT \ | |
128 | (HV_MPIPE_NUM_EDMA_RINGS / HV_MPIPE_ALLOC_EDMA_RINGS_BITS) | |
129 | ||
130 | ||
131 | ||
132 | ||
133 | /** Bit vector encoding which NotifRings are in a NotifGroup. */ | |
134 | typedef struct | |
135 | { | |
136 | /** The actual bits. */ | |
137 | uint64_t ring_mask[4]; | |
138 | ||
139 | } gxio_mpipe_notif_group_bits_t; | |
140 | ||
141 | ||
142 | /** Another name for MPIPE_LBL_INIT_DAT_BSTS_TBL_t. */ | |
143 | typedef MPIPE_LBL_INIT_DAT_BSTS_TBL_t gxio_mpipe_bucket_info_t; | |
144 | ||
145 | ||
146 | ||
147 | /** Eight buffer stack ids. */ | |
148 | typedef struct | |
149 | { | |
150 | /** The stacks. */ | |
151 | uint8_t stacks[8]; | |
152 | ||
153 | } gxio_mpipe_rules_stacks_t; | |
154 | ||
155 | ||
156 | /** A destination mac address. */ | |
157 | typedef struct | |
158 | { | |
159 | /** The octets. */ | |
160 | uint8_t octets[6]; | |
161 | ||
162 | } gxio_mpipe_rules_dmac_t; | |
163 | ||
164 | ||
165 | /** A vlan. */ | |
166 | typedef uint16_t gxio_mpipe_rules_vlan_t; | |
167 | ||
168 | ||
169 | ||
170 | /** Maximum number of characters in a link name. */ | |
171 | #define GXIO_MPIPE_LINK_NAME_LEN 32 | |
172 | ||
173 | ||
174 | /** Structure holding a link name. Only needed, and only typedef'ed, | |
175 | * because the IORPC stub generator only handles types which are single | |
176 | * words coming before the parameter name. */ | |
177 | typedef struct | |
178 | { | |
179 | /** The name itself. */ | |
180 | char name[GXIO_MPIPE_LINK_NAME_LEN]; | |
181 | } | |
182 | _gxio_mpipe_link_name_t; | |
183 | ||
184 | /** Maximum number of characters in a symbol name. */ | |
185 | #define GXIO_MPIPE_SYMBOL_NAME_LEN 128 | |
186 | ||
187 | ||
188 | /** Structure holding a symbol name. Only needed, and only typedef'ed, | |
189 | * because the IORPC stub generator only handles types which are single | |
190 | * words coming before the parameter name. */ | |
191 | typedef struct | |
192 | { | |
193 | /** The name itself. */ | |
194 | char name[GXIO_MPIPE_SYMBOL_NAME_LEN]; | |
195 | } | |
196 | _gxio_mpipe_symbol_name_t; | |
197 | ||
198 | ||
199 | /** Structure holding a MAC address. */ | |
200 | typedef struct | |
201 | { | |
202 | /** The address. */ | |
203 | uint8_t mac[6]; | |
204 | } | |
205 | _gxio_mpipe_link_mac_t; | |
206 | ||
207 | ||
208 | ||
209 | /** Request shared data permission -- that is, the ability to send and | |
210 | * receive packets -- on the specified link. Other processes may also | |
211 | * request shared data permission on the same link. | |
212 | * | |
213 | * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA, | |
35b90a29 | 214 | * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
215 | * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed. |
216 | */ | |
217 | #define GXIO_MPIPE_LINK_DATA 0x00000001UL | |
218 | ||
219 | /** Do not request data permission on the specified link. | |
220 | * | |
221 | * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA, | |
35b90a29 | 222 | * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
223 | * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed. |
224 | */ | |
225 | #define GXIO_MPIPE_LINK_NO_DATA 0x00000002UL | |
226 | ||
227 | /** Request exclusive data permission -- that is, the ability to send and | |
228 | * receive packets -- on the specified link. No other processes may | |
229 | * request data permission on this link, and if any process already has | |
230 | * data permission on it, this open will fail. | |
231 | * | |
232 | * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA, | |
35b90a29 | 233 | * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
234 | * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed. |
235 | */ | |
236 | #define GXIO_MPIPE_LINK_EXCL_DATA 0x00000004UL | |
237 | ||
238 | /** Request shared stats permission -- that is, the ability to read and write | |
239 | * registers which contain link statistics, and to get link attributes -- | |
240 | * on the specified link. Other processes may also request shared stats | |
241 | * permission on the same link. | |
242 | * | |
243 | * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS, | |
35b90a29 | 244 | * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
245 | * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed. |
246 | */ | |
247 | #define GXIO_MPIPE_LINK_STATS 0x00000008UL | |
248 | ||
249 | /** Do not request stats permission on the specified link. | |
250 | * | |
251 | * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS, | |
35b90a29 | 252 | * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
253 | * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed. |
254 | */ | |
255 | #define GXIO_MPIPE_LINK_NO_STATS 0x00000010UL | |
256 | ||
257 | /** Request exclusive stats permission -- that is, the ability to read and | |
258 | * write registers which contain link statistics, and to get link | |
259 | * attributes -- on the specified link. No other processes may request | |
260 | * stats permission on this link, and if any process already | |
261 | * has stats permission on it, this open will fail. | |
262 | * | |
263 | * Requesting exclusive stats permission is normally a very bad idea, since | |
264 | * it prevents programs like mpipe-stat from providing information on this | |
265 | * link. Applications should only do this if they use MAC statistics | |
266 | * registers, and cannot tolerate any of the clear-on-read registers being | |
267 | * reset by other statistics programs. | |
268 | * | |
269 | * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS, | |
35b90a29 | 270 | * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
271 | * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed. |
272 | */ | |
273 | #define GXIO_MPIPE_LINK_EXCL_STATS 0x00000020UL | |
274 | ||
275 | /** Request shared control permission -- that is, the ability to modify link | |
276 | * attributes, and read and write MAC and MDIO registers -- on the | |
277 | * specified link. Other processes may also request shared control | |
278 | * permission on the same link. | |
279 | * | |
280 | * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL, | |
35b90a29 | 281 | * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
282 | * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed. |
283 | */ | |
284 | #define GXIO_MPIPE_LINK_CTL 0x00000040UL | |
285 | ||
286 | /** Do not request control permission on the specified link. | |
287 | * | |
288 | * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL, | |
35b90a29 | 289 | * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
290 | * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed. |
291 | */ | |
292 | #define GXIO_MPIPE_LINK_NO_CTL 0x00000080UL | |
293 | ||
294 | /** Request exclusive control permission -- that is, the ability to modify | |
295 | * link attributes, and read and write MAC and MDIO registers -- on the | |
296 | * specified link. No other processes may request control permission on | |
297 | * this link, and if any process already has control permission on it, | |
298 | * this open will fail. | |
299 | * | |
300 | * Requesting exclusive control permission is not always a good idea, since | |
301 | * it prevents programs like mpipe-link from configuring the link. | |
302 | * | |
303 | * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL, | |
35b90a29 | 304 | * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
305 | * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed. |
306 | */ | |
307 | #define GXIO_MPIPE_LINK_EXCL_CTL 0x00000100UL | |
308 | ||
309 | /** Set the desired state of the link to up, allowing any speeds which are | |
310 | * supported by the link hardware, as part of this open operation; do not | |
311 | * change the desired state of the link when it is closed or the process | |
312 | * exits. No more than one of ::GXIO_MPIPE_LINK_AUTO_UP, | |
313 | * ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or | |
35b90a29 | 314 | * ::GXIO_MPIPE_LINK_AUTO_NONE may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
315 | * call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed. |
316 | */ | |
317 | #define GXIO_MPIPE_LINK_AUTO_UP 0x00000200UL | |
318 | ||
319 | /** Set the desired state of the link to up, allowing any speeds which are | |
320 | * supported by the link hardware, as part of this open operation; when the | |
321 | * link is closed or this process exits, if no other process has the link | |
322 | * open, set the desired state of the link to down. No more than one of | |
323 | * ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN, | |
324 | * ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be | |
35b90a29 | 325 | * specified in a gxio_mpipe_link_open() call. If none are specified, |
4875f69f CM |
326 | * ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed. |
327 | */ | |
328 | #define GXIO_MPIPE_LINK_AUTO_UPDOWN 0x00000400UL | |
329 | ||
330 | /** Do not change the desired state of the link as part of the open | |
331 | * operation; when the link is closed or this process exits, if no other | |
332 | * process has the link open, set the desired state of the link to down. | |
333 | * No more than one of ::GXIO_MPIPE_LINK_AUTO_UP, | |
334 | * ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or | |
35b90a29 | 335 | * ::GXIO_MPIPE_LINK_AUTO_NONE may be specified in a gxio_mpipe_link_open() |
4875f69f CM |
336 | * call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed. |
337 | */ | |
338 | #define GXIO_MPIPE_LINK_AUTO_DOWN 0x00000800UL | |
339 | ||
340 | /** Do not change the desired state of the link as part of the open | |
341 | * operation; do not change the desired state of the link when it is | |
342 | * closed or the process exits. No more than one of | |
343 | * ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN, | |
344 | * ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be | |
35b90a29 | 345 | * specified in a gxio_mpipe_link_open() call. If none are specified, |
4875f69f CM |
346 | * ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed. |
347 | */ | |
348 | #define GXIO_MPIPE_LINK_AUTO_NONE 0x00001000UL | |
349 | ||
350 | /** Request that this open call not complete until the network link is up. | |
351 | * The process will wait as long as necessary for this to happen; | |
352 | * applications which wish to abandon waiting for the link after a | |
353 | * specific time period should not specify this flag when opening a link, | |
354 | * but should instead call gxio_mpipe_link_wait() afterward. The link | |
355 | * must be opened with stats permission. Note that this flag by itself | |
356 | * does not change the desired link state; if other open flags or previous | |
357 | * link state changes have not requested a desired state of up, the open | |
358 | * call will never complete. This flag is not available to kernel | |
359 | * clients. | |
360 | */ | |
361 | #define GXIO_MPIPE_LINK_WAIT 0x00002000UL | |
362 | ||
363 | ||
364 | /* | |
365 | * Note: link attributes must fit in 24 bits, since we use the top 8 bits | |
366 | * of the IORPC offset word for the channel number. | |
367 | */ | |
368 | ||
369 | /** Determine whether jumbo frames may be received. If this attribute's | |
370 | * value value is nonzero, the MAC will accept frames of up to 10240 bytes. | |
371 | * If the value is zero, the MAC will only accept frames of up to 1544 | |
372 | * bytes. The default value is zero. */ | |
373 | #define GXIO_MPIPE_LINK_RECEIVE_JUMBO 0x010000 | |
374 | ||
375 | /** Determine whether to send pause frames on this link if the mPIPE packet | |
376 | * FIFO is nearly full. If the value is zero, pause frames are not sent. | |
377 | * If the value is nonzero, it is the delay value which will be sent in any | |
378 | * pause frames which are output, in units of 512 bit times. | |
379 | * | |
380 | * Bear in mind that in almost all circumstances, the mPIPE packet FIFO | |
381 | * will never fill up, since mPIPE will empty it as fast as or faster than | |
382 | * the incoming data rate, by either delivering or dropping packets. The | |
383 | * only situation in which this is not true is if the memory and cache | |
384 | * subsystem is extremely heavily loaded, and mPIPE cannot perform DMA of | |
385 | * packet data to memory in a timely fashion. In particular, pause frames | |
386 | * will <em>not</em> be sent if packets cannot be delivered because | |
387 | * NotifRings are full, buckets are full, or buffers are not available in | |
388 | * a buffer stack. */ | |
389 | #define GXIO_MPIPE_LINK_SEND_PAUSE 0x020000 | |
390 | ||
391 | /** Determine whether to suspend output on the receipt of pause frames. | |
392 | * If the value is nonzero, mPIPE shim will suspend output on the link's | |
393 | * channel when a pause frame is received. If the value is zero, pause | |
394 | * frames will be ignored. The default value is zero. */ | |
395 | #define GXIO_MPIPE_LINK_RECEIVE_PAUSE 0x030000 | |
396 | ||
397 | /** Interface MAC address. The value is a 6-byte MAC address, in the least | |
398 | * significant 48 bits of the value; in other words, an address which would | |
399 | * be printed as '12:34:56:78:90:AB' in IEEE 802 canonical format would | |
400 | * be returned as 0x12345678ab. | |
401 | * | |
402 | * Depending upon the overall system design, a MAC address may or may not | |
403 | * be available for each interface. Note that the interface's MAC address | |
404 | * does not limit the packets received on its channel, although the | |
405 | * classifier's rules could be configured to do that. Similarly, the MAC | |
406 | * address is not used when transmitting packets, although applications | |
407 | * could certainly decide to use the assigned address as a source MAC | |
408 | * address when doing so. This attribute may only be retrieved with | |
409 | * gxio_mpipe_link_get_attr(); it may not be modified. | |
410 | */ | |
411 | #define GXIO_MPIPE_LINK_MAC 0x040000 | |
412 | ||
413 | /** Determine whether to discard egress packets on link down. If this value | |
414 | * is nonzero, packets sent on this link while the link is down will be | |
415 | * discarded. If this value is zero, no packets will be sent on this link | |
416 | * while it is down. The default value is one. */ | |
417 | #define GXIO_MPIPE_LINK_DISCARD_IF_DOWN 0x050000 | |
418 | ||
419 | /** Possible link state. The value is a combination of link state flags, | |
420 | * ORed together, that indicate link modes which are actually supported by | |
421 | * the hardware. This attribute may only be retrieved with | |
422 | * gxio_mpipe_link_get_attr(); it may not be modified. */ | |
423 | #define GXIO_MPIPE_LINK_POSSIBLE_STATE 0x060000 | |
424 | ||
425 | /** Current link state. The value is a combination of link state flags, | |
426 | * ORed together, that indicate the current state of the hardware. If the | |
427 | * link is down, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will be zero; | |
428 | * if the link is up, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will | |
429 | * result in exactly one of the speed values, indicating the current speed. | |
430 | * This attribute may only be retrieved with gxio_mpipe_link_get_attr(); it | |
431 | * may not be modified. */ | |
432 | #define GXIO_MPIPE_LINK_CURRENT_STATE 0x070000 | |
433 | ||
434 | /** Desired link state. The value is a conbination of flags, which specify | |
435 | * the desired state for the link. With gxio_mpipe_link_set_attr(), this | |
436 | * will, in the background, attempt to bring up the link using whichever of | |
437 | * the requested flags are reasonable, or take down the link if the flags | |
438 | * are zero. The actual link up or down operation may happen after this | |
439 | * call completes. If the link state changes in the future, the system | |
440 | * will continue to try to get back to the desired link state; for | |
441 | * instance, if the link is brought up successfully, and then the network | |
442 | * cable is disconnected, the link will go down. However, the desired | |
443 | * state of the link is still up, so if the cable is reconnected, the link | |
444 | * will be brought up again. | |
445 | * | |
446 | * With gxio_mpipe_link_set_attr(), this will indicate the desired state | |
447 | * for the link, as set with a previous gxio_mpipe_link_set_attr() call, | |
448 | * or implicitly by a gxio_mpipe_link_open() or link close operation. | |
449 | * This may not reflect the current state of the link; to get that, use | |
450 | * ::GXIO_MPIPE_LINK_CURRENT_STATE. | |
451 | */ | |
452 | #define GXIO_MPIPE_LINK_DESIRED_STATE 0x080000 | |
453 | ||
454 | ||
455 | ||
456 | /** Link can run, should run, or is running at 10 Mbps. */ | |
457 | #define GXIO_MPIPE_LINK_10M 0x0000000000000001UL | |
458 | ||
459 | /** Link can run, should run, or is running at 100 Mbps. */ | |
460 | #define GXIO_MPIPE_LINK_100M 0x0000000000000002UL | |
461 | ||
462 | /** Link can run, should run, or is running at 1 Gbps. */ | |
463 | #define GXIO_MPIPE_LINK_1G 0x0000000000000004UL | |
464 | ||
465 | /** Link can run, should run, or is running at 10 Gbps. */ | |
466 | #define GXIO_MPIPE_LINK_10G 0x0000000000000008UL | |
467 | ||
468 | /** Link can run, should run, or is running at 20 Gbps. */ | |
469 | #define GXIO_MPIPE_LINK_20G 0x0000000000000010UL | |
470 | ||
471 | /** Link can run, should run, or is running at 25 Gbps. */ | |
472 | #define GXIO_MPIPE_LINK_25G 0x0000000000000020UL | |
473 | ||
474 | /** Link can run, should run, or is running at 50 Gbps. */ | |
475 | #define GXIO_MPIPE_LINK_50G 0x0000000000000040UL | |
476 | ||
477 | /** Link should run at the highest speed supported by the link and by | |
478 | * the device connected to the link. Only usable as a value for | |
479 | * the link's desired state; never returned as a value for the current | |
480 | * or possible states. */ | |
481 | #define GXIO_MPIPE_LINK_ANYSPEED 0x0000000000000800UL | |
482 | ||
483 | /** All legal link speeds. This value is provided for use in extracting | |
484 | * the speed-related subset of the link state flags; it is not intended | |
485 | * to be set directly as a value for one of the GXIO_MPIPE_LINK_xxx_STATE | |
486 | * attributes. A link is up or is requested to be up if its current or | |
487 | * desired state, respectively, ANDED with this value, is nonzero. */ | |
488 | #define GXIO_MPIPE_LINK_SPEED_MASK 0x0000000000000FFFUL | |
489 | ||
490 | /** Link can run, should run, or is running in MAC loopback mode. This | |
491 | * loops transmitted packets back to the receiver, inside the Tile | |
492 | * Processor. */ | |
493 | #define GXIO_MPIPE_LINK_LOOP_MAC 0x0000000000001000UL | |
494 | ||
495 | /** Link can run, should run, or is running in PHY loopback mode. This | |
496 | * loops transmitted packets back to the receiver, inside the external | |
497 | * PHY chip. */ | |
498 | #define GXIO_MPIPE_LINK_LOOP_PHY 0x0000000000002000UL | |
499 | ||
500 | /** Link can run, should run, or is running in external loopback mode. | |
501 | * This requires that an external loopback plug be installed on the | |
502 | * Ethernet port. Note that only some links require that this be | |
503 | * configured via the gxio_mpipe_link routines; other links can do | |
504 | * external loopack with the plug and no special configuration. */ | |
505 | #define GXIO_MPIPE_LINK_LOOP_EXT 0x0000000000004000UL | |
506 | ||
507 | /** All legal loopback types. */ | |
508 | #define GXIO_MPIPE_LINK_LOOP_MASK 0x000000000000F000UL | |
509 | ||
510 | /** Link can run, should run, or is running in full-duplex mode. | |
511 | * If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are | |
512 | * specified in a set of desired state flags, both are assumed. */ | |
513 | #define GXIO_MPIPE_LINK_FDX 0x0000000000010000UL | |
514 | ||
515 | /** Link can run, should run, or is running in half-duplex mode. | |
516 | * If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are | |
517 | * specified in a set of desired state flags, both are assumed. */ | |
518 | #define GXIO_MPIPE_LINK_HDX 0x0000000000020000UL | |
519 | ||
520 | ||
521 | /** An individual rule. */ | |
522 | typedef struct | |
523 | { | |
524 | /** The total size. */ | |
525 | uint16_t size; | |
526 | ||
527 | /** The priority. */ | |
528 | int16_t priority; | |
529 | ||
530 | /** The "headroom" in each buffer. */ | |
531 | uint8_t headroom; | |
532 | ||
533 | /** The "tailroom" in each buffer. */ | |
534 | uint8_t tailroom; | |
535 | ||
536 | /** The "capacity" of the largest buffer. */ | |
537 | uint16_t capacity; | |
538 | ||
539 | /** The mask for converting a flow hash into a bucket. */ | |
540 | uint16_t bucket_mask; | |
541 | ||
542 | /** The offset for converting a flow hash into a bucket. */ | |
543 | uint16_t bucket_first; | |
544 | ||
545 | /** The buffer stack ids. */ | |
546 | gxio_mpipe_rules_stacks_t stacks; | |
547 | ||
548 | /** The actual channels. */ | |
549 | uint32_t channel_bits; | |
550 | ||
551 | /** The number of dmacs. */ | |
552 | uint16_t num_dmacs; | |
553 | ||
554 | /** The number of vlans. */ | |
555 | uint16_t num_vlans; | |
556 | ||
557 | /** The actual dmacs and vlans. */ | |
558 | uint8_t dmacs_and_vlans[]; | |
559 | ||
560 | } gxio_mpipe_rules_rule_t; | |
561 | ||
562 | ||
563 | /** A list of classifier rules. */ | |
564 | typedef struct | |
565 | { | |
566 | /** The offset to the end of the current rule. */ | |
567 | uint16_t tail; | |
568 | ||
569 | /** The offset to the start of the current rule. */ | |
570 | uint16_t head; | |
571 | ||
572 | /** The actual rules. */ | |
573 | uint8_t rules[4096 - 4]; | |
574 | ||
575 | } gxio_mpipe_rules_list_t; | |
576 | ||
577 | ||
578 | ||
579 | ||
580 | /** mPIPE statistics structure. These counters include all relevant | |
581 | * events occurring on all links within the mPIPE shim. */ | |
582 | typedef struct | |
583 | { | |
584 | /** Number of ingress packets dropped for any reason. */ | |
585 | uint64_t ingress_drops; | |
586 | /** Number of ingress packets dropped because a buffer stack was empty. */ | |
587 | uint64_t ingress_drops_no_buf; | |
588 | /** Number of ingress packets dropped or truncated due to lack of space in | |
589 | * the iPkt buffer. */ | |
590 | uint64_t ingress_drops_ipkt; | |
591 | /** Number of ingress packets dropped by the classifier or load balancer */ | |
592 | uint64_t ingress_drops_cls_lb; | |
593 | /** Total number of ingress packets. */ | |
594 | uint64_t ingress_packets; | |
595 | /** Total number of egress packets. */ | |
596 | uint64_t egress_packets; | |
597 | /** Total number of ingress bytes. */ | |
598 | uint64_t ingress_bytes; | |
599 | /** Total number of egress bytes. */ | |
600 | uint64_t egress_bytes; | |
601 | } | |
602 | gxio_mpipe_stats_t; | |
603 | ||
604 | ||
605 | #endif /* _SYS_HV_DRV_MPIPE_INTF_H */ |