Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / arch / tile / kernel / hardwall.c
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1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/fs.h>
16#include <linux/proc_fs.h>
17#include <linux/seq_file.h>
18#include <linux/rwsem.h>
19#include <linux/kprobes.h>
20#include <linux/sched.h>
21#include <linux/hardirq.h>
22#include <linux/uaccess.h>
23#include <linux/smp.h>
24#include <linux/cdev.h>
25#include <linux/compat.h>
26#include <asm/hardwall.h>
27#include <asm/traps.h>
28#include <asm/siginfo.h>
29#include <asm/irq_regs.h>
30
31#include <arch/interrupts.h>
32#include <arch/spr_def.h>
33
34
35/*
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36 * Implement a per-cpu "hardwall" resource class such as UDN or IPI.
37 * We use "hardwall" nomenclature throughout for historical reasons.
38 * The lock here controls access to the list data structure as well as
39 * to the items on the list.
40 */
41struct hardwall_type {
42 int index;
43 int is_xdn;
44 int is_idn;
45 int disabled;
46 const char *name;
47 struct list_head list;
48 spinlock_t lock;
49 struct proc_dir_entry *proc_dir;
50};
51
52enum hardwall_index {
53 HARDWALL_UDN = 0,
54#ifndef __tilepro__
55 HARDWALL_IDN = 1,
56 HARDWALL_IPI = 2,
57#endif
58 _HARDWALL_TYPES
59};
60
61static struct hardwall_type hardwall_types[] = {
62 { /* user-space access to UDN */
63 0,
64 1,
65 0,
66 0,
67 "udn",
68 LIST_HEAD_INIT(hardwall_types[HARDWALL_UDN].list),
dd386e03 69 __SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_UDN].lock),
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70 NULL
71 },
72#ifndef __tilepro__
73 { /* user-space access to IDN */
74 1,
75 1,
76 1,
77 1, /* disabled pending hypervisor support */
78 "idn",
79 LIST_HEAD_INIT(hardwall_types[HARDWALL_IDN].list),
dd386e03 80 __SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_IDN].lock),
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81 NULL
82 },
83 { /* access to user-space IPI */
84 2,
85 0,
86 0,
87 0,
88 "ipi",
89 LIST_HEAD_INIT(hardwall_types[HARDWALL_IPI].list),
dd386e03 90 __SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_IPI].lock),
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91 NULL
92 },
93#endif
94};
95
96/*
97 * This data structure tracks the cpu data, etc., associated
98 * one-to-one with a "struct file *" from opening a hardwall device file.
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99 * Note that the file's private data points back to this structure.
100 */
101struct hardwall_info {
b8ace083 102 struct list_head list; /* for hardwall_types.list */
9f9c0382 103 struct list_head task_head; /* head of tasks in this hardwall */
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104 struct hardwall_type *type; /* type of this resource */
105 struct cpumask cpumask; /* cpus reserved */
106 int id; /* integer id for this hardwall */
107 int teardown_in_progress; /* are we tearing this one down? */
108
109 /* Remaining fields only valid for user-network resources. */
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110 int ulhc_x; /* upper left hand corner x coord */
111 int ulhc_y; /* upper left hand corner y coord */
112 int width; /* rectangle width */
113 int height; /* rectangle height */
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114#if CHIP_HAS_REV1_XDN()
115 atomic_t xdn_pending_count; /* cores in phase 1 of drain */
116#endif
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117};
118
9f9c0382 119
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120/* /proc/tile/hardwall */
121static struct proc_dir_entry *hardwall_proc_dir;
122
123/* Functions to manage files in /proc/tile/hardwall. */
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124static void hardwall_add_proc(struct hardwall_info *);
125static void hardwall_remove_proc(struct hardwall_info *);
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126
127/* Allow disabling UDN access. */
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128static int __init noudn(char *str)
129{
130 pr_info("User-space UDN access is disabled\n");
b8ace083 131 hardwall_types[HARDWALL_UDN].disabled = 1;
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132 return 0;
133}
134early_param("noudn", noudn);
135
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136#ifndef __tilepro__
137/* Allow disabling IDN access. */
138static int __init noidn(char *str)
139{
140 pr_info("User-space IDN access is disabled\n");
141 hardwall_types[HARDWALL_IDN].disabled = 1;
142 return 0;
143}
144early_param("noidn", noidn);
145
146/* Allow disabling IPI access. */
147static int __init noipi(char *str)
148{
149 pr_info("User-space IPI access is disabled\n");
150 hardwall_types[HARDWALL_IPI].disabled = 1;
151 return 0;
152}
153early_param("noipi", noipi);
154#endif
155
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156
157/*
b8ace083 158 * Low-level primitives for UDN/IDN
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159 */
160
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161#ifdef __tilepro__
162#define mtspr_XDN(hwt, name, val) \
163 do { (void)(hwt); __insn_mtspr(SPR_UDN_##name, (val)); } while (0)
164#define mtspr_MPL_XDN(hwt, name, val) \
165 do { (void)(hwt); __insn_mtspr(SPR_MPL_UDN_##name, (val)); } while (0)
166#define mfspr_XDN(hwt, name) \
167 ((void)(hwt), __insn_mfspr(SPR_UDN_##name))
168#else
169#define mtspr_XDN(hwt, name, val) \
170 do { \
171 if ((hwt)->is_idn) \
172 __insn_mtspr(SPR_IDN_##name, (val)); \
173 else \
174 __insn_mtspr(SPR_UDN_##name, (val)); \
175 } while (0)
176#define mtspr_MPL_XDN(hwt, name, val) \
177 do { \
178 if ((hwt)->is_idn) \
179 __insn_mtspr(SPR_MPL_IDN_##name, (val)); \
180 else \
181 __insn_mtspr(SPR_MPL_UDN_##name, (val)); \
182 } while (0)
183#define mfspr_XDN(hwt, name) \
184 ((hwt)->is_idn ? __insn_mfspr(SPR_IDN_##name) : __insn_mfspr(SPR_UDN_##name))
185#endif
186
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187/* Set a CPU bit if the CPU is online. */
188#define cpu_online_set(cpu, dst) do { \
189 if (cpu_online(cpu)) \
190 cpumask_set_cpu(cpu, dst); \
191} while (0)
192
193
194/* Does the given rectangle contain the given x,y coordinate? */
195static int contains(struct hardwall_info *r, int x, int y)
196{
197 return (x >= r->ulhc_x && x < r->ulhc_x + r->width) &&
198 (y >= r->ulhc_y && y < r->ulhc_y + r->height);
199}
200
201/* Compute the rectangle parameters and validate the cpumask. */
b8ace083 202static int check_rectangle(struct hardwall_info *r, struct cpumask *mask)
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203{
204 int x, y, cpu, ulhc, lrhc;
205
206 /* The first cpu is the ULHC, the last the LRHC. */
207 ulhc = find_first_bit(cpumask_bits(mask), nr_cpumask_bits);
208 lrhc = find_last_bit(cpumask_bits(mask), nr_cpumask_bits);
209
210 /* Compute the rectangle attributes from the cpus. */
211 r->ulhc_x = cpu_x(ulhc);
212 r->ulhc_y = cpu_y(ulhc);
213 r->width = cpu_x(lrhc) - r->ulhc_x + 1;
214 r->height = cpu_y(lrhc) - r->ulhc_y + 1;
215
216 /* Width and height must be positive */
217 if (r->width <= 0 || r->height <= 0)
218 return -EINVAL;
219
220 /* Confirm that the cpumask is exactly the rectangle. */
221 for (y = 0, cpu = 0; y < smp_height; ++y)
222 for (x = 0; x < smp_width; ++x, ++cpu)
223 if (cpumask_test_cpu(cpu, mask) != contains(r, x, y))
224 return -EINVAL;
225
226 /*
b8ace083 227 * Note that offline cpus can't be drained when this user network
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228 * rectangle eventually closes. We used to detect this
229 * situation and print a warning, but it annoyed users and
230 * they ignored it anyway, so now we just return without a
231 * warning.
232 */
233 return 0;
234}
235
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236/*
237 * Hardware management of hardwall setup, teardown, trapping,
238 * and enabling/disabling PL0 access to the networks.
239 */
240
241/* Bit field values to mask together for writes to SPR_XDN_DIRECTION_PROTECT */
242enum direction_protect {
243 N_PROTECT = (1 << 0),
244 E_PROTECT = (1 << 1),
245 S_PROTECT = (1 << 2),
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246 W_PROTECT = (1 << 3),
247 C_PROTECT = (1 << 4),
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248};
249
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250static inline int xdn_which_interrupt(struct hardwall_type *hwt)
251{
252#ifndef __tilepro__
253 if (hwt->is_idn)
254 return INT_IDN_FIREWALL;
255#endif
256 return INT_UDN_FIREWALL;
257}
258
259static void enable_firewall_interrupts(struct hardwall_type *hwt)
9f9c0382 260{
b8ace083 261 arch_local_irq_unmask_now(xdn_which_interrupt(hwt));
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262}
263
b8ace083 264static void disable_firewall_interrupts(struct hardwall_type *hwt)
9f9c0382 265{
b8ace083 266 arch_local_irq_mask_now(xdn_which_interrupt(hwt));
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267}
268
269/* Set up hardwall on this cpu based on the passed hardwall_info. */
b8ace083 270static void hardwall_setup_func(void *info)
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271{
272 struct hardwall_info *r = info;
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273 struct hardwall_type *hwt = r->type;
274
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275 int cpu = smp_processor_id(); /* on_each_cpu disables preemption */
276 int x = cpu_x(cpu);
277 int y = cpu_y(cpu);
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278 int bits = 0;
279 if (x == r->ulhc_x)
280 bits |= W_PROTECT;
281 if (x == r->ulhc_x + r->width - 1)
282 bits |= E_PROTECT;
283 if (y == r->ulhc_y)
284 bits |= N_PROTECT;
285 if (y == r->ulhc_y + r->height - 1)
286 bits |= S_PROTECT;
287 BUG_ON(bits == 0);
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288 mtspr_XDN(hwt, DIRECTION_PROTECT, bits);
289 enable_firewall_interrupts(hwt);
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290}
291
292/* Set up all cpus on edge of rectangle to enable/disable hardwall SPRs. */
b8ace083 293static void hardwall_protect_rectangle(struct hardwall_info *r)
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294{
295 int x, y, cpu, delta;
296 struct cpumask rect_cpus;
297
298 cpumask_clear(&rect_cpus);
299
300 /* First include the top and bottom edges */
301 cpu = r->ulhc_y * smp_width + r->ulhc_x;
302 delta = (r->height - 1) * smp_width;
303 for (x = 0; x < r->width; ++x, ++cpu) {
304 cpu_online_set(cpu, &rect_cpus);
305 cpu_online_set(cpu + delta, &rect_cpus);
306 }
307
308 /* Then the left and right edges */
309 cpu -= r->width;
310 delta = r->width - 1;
311 for (y = 0; y < r->height; ++y, cpu += smp_width) {
312 cpu_online_set(cpu, &rect_cpus);
313 cpu_online_set(cpu + delta, &rect_cpus);
314 }
315
316 /* Then tell all the cpus to set up their protection SPR */
b8ace083 317 on_each_cpu_mask(&rect_cpus, hardwall_setup_func, r, 1);
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318}
319
bc1a298f 320/* Entered from INT_xDN_FIREWALL interrupt vector with irqs disabled. */
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321void __kprobes do_hardwall_trap(struct pt_regs* regs, int fault_num)
322{
323 struct hardwall_info *rect;
b8ace083 324 struct hardwall_type *hwt;
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325 struct task_struct *p;
326 struct siginfo info;
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327 int cpu = smp_processor_id();
328 int found_processes;
9f9c0382 329 struct pt_regs *old_regs = set_irq_regs(regs);
b8ace083 330
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331 irq_enter();
332
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333 /* Figure out which network trapped. */
334 switch (fault_num) {
335#ifndef __tilepro__
336 case INT_IDN_FIREWALL:
337 hwt = &hardwall_types[HARDWALL_IDN];
338 break;
339#endif
340 case INT_UDN_FIREWALL:
341 hwt = &hardwall_types[HARDWALL_UDN];
342 break;
343 default:
344 BUG();
345 }
346 BUG_ON(hwt->disabled);
347
9f9c0382 348 /* This tile trapped a network access; find the rectangle. */
bc1a298f 349 spin_lock(&hwt->lock);
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350 list_for_each_entry(rect, &hwt->list, list) {
351 if (cpumask_test_cpu(cpu, &rect->cpumask))
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352 break;
353 }
354
355 /*
356 * It shouldn't be possible not to find this cpu on the
357 * rectangle list, since only cpus in rectangles get hardwalled.
b8ace083 358 * The hardwall is only removed after the user network is drained.
9f9c0382 359 */
b8ace083 360 BUG_ON(&rect->list == &hwt->list);
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361
362 /*
363 * If we already started teardown on this hardwall, don't worry;
364 * the abort signal has been sent and we are just waiting for things
365 * to quiesce.
366 */
367 if (rect->teardown_in_progress) {
b8ace083 368 pr_notice("cpu %d: detected %s hardwall violation %#lx"
9f9c0382 369 " while teardown already in progress\n",
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370 cpu, hwt->name,
371 (long)mfspr_XDN(hwt, DIRECTION_PROTECT));
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372 goto done;
373 }
374
375 /*
376 * Kill off any process that is activated in this rectangle.
377 * We bypass security to deliver the signal, since it must be
b8ace083 378 * one of the activated processes that generated the user network
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379 * message that caused this trap, and all the activated
380 * processes shared a single open file so are pretty tightly
381 * bound together from a security point of view to begin with.
382 */
383 rect->teardown_in_progress = 1;
384 wmb(); /* Ensure visibility of rectangle before notifying processes. */
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385 pr_notice("cpu %d: detected %s hardwall violation %#lx...\n",
386 cpu, hwt->name, (long)mfspr_XDN(hwt, DIRECTION_PROTECT));
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387 info.si_signo = SIGILL;
388 info.si_errno = 0;
389 info.si_code = ILL_HARDWALL;
390 found_processes = 0;
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391 list_for_each_entry(p, &rect->task_head,
392 thread.hardwall[hwt->index].list) {
393 BUG_ON(p->thread.hardwall[hwt->index].info != rect);
ceca3c19 394 if (!(p->flags & PF_EXITING)) {
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395 found_processes = 1;
396 pr_notice("hardwall: killing %d\n", p->pid);
ceca3c19 397 do_send_sig_info(info.si_signo, &info, p, false);
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398 }
399 }
400 if (!found_processes)
401 pr_notice("hardwall: no associated processes!\n");
402
403 done:
bc1a298f 404 spin_unlock(&hwt->lock);
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405
406 /*
407 * We have to disable firewall interrupts now, or else when we
408 * return from this handler, we will simply re-interrupt back to
409 * it. However, we can't clear the protection bits, since we
410 * haven't yet drained the network, and that would allow packets
411 * to cross out of the hardwall region.
412 */
b8ace083 413 disable_firewall_interrupts(hwt);
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414
415 irq_exit();
416 set_irq_regs(old_regs);
417}
418
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419/* Allow access from user space to the user network. */
420void grant_hardwall_mpls(struct hardwall_type *hwt)
9f9c0382 421{
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422#ifndef __tilepro__
423 if (!hwt->is_xdn) {
424 __insn_mtspr(SPR_MPL_IPI_0_SET_0, 1);
425 return;
426 }
427#endif
428 mtspr_MPL_XDN(hwt, ACCESS_SET_0, 1);
429 mtspr_MPL_XDN(hwt, AVAIL_SET_0, 1);
430 mtspr_MPL_XDN(hwt, COMPLETE_SET_0, 1);
431 mtspr_MPL_XDN(hwt, TIMER_SET_0, 1);
9f9c0382 432#if !CHIP_HAS_REV1_XDN()
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433 mtspr_MPL_XDN(hwt, REFILL_SET_0, 1);
434 mtspr_MPL_XDN(hwt, CA_SET_0, 1);
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435#endif
436}
437
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438/* Deny access from user space to the user network. */
439void restrict_hardwall_mpls(struct hardwall_type *hwt)
9f9c0382 440{
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441#ifndef __tilepro__
442 if (!hwt->is_xdn) {
443 __insn_mtspr(SPR_MPL_IPI_0_SET_1, 1);
444 return;
445 }
446#endif
447 mtspr_MPL_XDN(hwt, ACCESS_SET_1, 1);
448 mtspr_MPL_XDN(hwt, AVAIL_SET_1, 1);
449 mtspr_MPL_XDN(hwt, COMPLETE_SET_1, 1);
450 mtspr_MPL_XDN(hwt, TIMER_SET_1, 1);
9f9c0382 451#if !CHIP_HAS_REV1_XDN()
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452 mtspr_MPL_XDN(hwt, REFILL_SET_1, 1);
453 mtspr_MPL_XDN(hwt, CA_SET_1, 1);
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454#endif
455}
456
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457/* Restrict or deny as necessary for the task we're switching to. */
458void hardwall_switch_tasks(struct task_struct *prev,
459 struct task_struct *next)
460{
461 int i;
462 for (i = 0; i < HARDWALL_TYPES; ++i) {
463 if (prev->thread.hardwall[i].info != NULL) {
464 if (next->thread.hardwall[i].info == NULL)
465 restrict_hardwall_mpls(&hardwall_types[i]);
466 } else if (next->thread.hardwall[i].info != NULL) {
467 grant_hardwall_mpls(&hardwall_types[i]);
468 }
469 }
470}
471
472/* Does this task have the right to IPI the given cpu? */
473int hardwall_ipi_valid(int cpu)
474{
475#ifdef __tilegx__
476 struct hardwall_info *info =
477 current->thread.hardwall[HARDWALL_IPI].info;
478 return info && cpumask_test_cpu(cpu, &info->cpumask);
479#else
480 return 0;
481#endif
482}
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483
484/*
b8ace083 485 * Code to create, activate, deactivate, and destroy hardwall resources.
9f9c0382
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486 */
487
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488/* Create a hardwall for the given resource */
489static struct hardwall_info *hardwall_create(struct hardwall_type *hwt,
490 size_t size,
491 const unsigned char __user *bits)
9f9c0382 492{
b8ace083 493 struct hardwall_info *iter, *info;
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494 struct cpumask mask;
495 unsigned long flags;
496 int rc;
497
498 /* Reject crazy sizes out of hand, a la sys_mbind(). */
499 if (size > PAGE_SIZE)
500 return ERR_PTR(-EINVAL);
501
502 /* Copy whatever fits into a cpumask. */
503 if (copy_from_user(&mask, bits, min(sizeof(struct cpumask), size)))
504 return ERR_PTR(-EFAULT);
505
506 /*
507 * If the size was short, clear the rest of the mask;
508 * otherwise validate that the rest of the user mask was zero
509 * (we don't try hard to be efficient when validating huge masks).
510 */
511 if (size < sizeof(struct cpumask)) {
512 memset((char *)&mask + size, 0, sizeof(struct cpumask) - size);
513 } else if (size > sizeof(struct cpumask)) {
514 size_t i;
515 for (i = sizeof(struct cpumask); i < size; ++i) {
516 char c;
517 if (get_user(c, &bits[i]))
518 return ERR_PTR(-EFAULT);
519 if (c)
520 return ERR_PTR(-EINVAL);
521 }
522 }
523
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524 /* Allocate a new hardwall_info optimistically. */
525 info = kmalloc(sizeof(struct hardwall_info),
9f9c0382 526 GFP_KERNEL | __GFP_ZERO);
b8ace083 527 if (info == NULL)
1c689cbc 528 return ERR_PTR(-ENOMEM);
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529 INIT_LIST_HEAD(&info->task_head);
530 info->type = hwt;
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531
532 /* Compute the rectangle size and validate that it's plausible. */
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533 cpumask_copy(&info->cpumask, &mask);
534 info->id = find_first_bit(cpumask_bits(&mask), nr_cpumask_bits);
535 if (hwt->is_xdn) {
536 rc = check_rectangle(info, &mask);
537 if (rc != 0) {
538 kfree(info);
539 return ERR_PTR(rc);
540 }
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541 }
542
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543 /*
544 * Eliminate cpus that are not part of this Linux client.
545 * Note that this allows for configurations that we might not want to
546 * support, such as one client on every even cpu, another client on
547 * every odd cpu.
548 */
549 cpumask_and(&info->cpumask, &info->cpumask, cpu_online_mask);
550
9f9c0382 551 /* Confirm it doesn't overlap and add it to the list. */
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552 spin_lock_irqsave(&hwt->lock, flags);
553 list_for_each_entry(iter, &hwt->list, list) {
554 if (cpumask_intersects(&iter->cpumask, &info->cpumask)) {
555 spin_unlock_irqrestore(&hwt->lock, flags);
556 kfree(info);
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557 return ERR_PTR(-EBUSY);
558 }
559 }
b8ace083
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560 list_add_tail(&info->list, &hwt->list);
561 spin_unlock_irqrestore(&hwt->lock, flags);
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562
563 /* Set up appropriate hardwalling on all affected cpus. */
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564 if (hwt->is_xdn)
565 hardwall_protect_rectangle(info);
9f9c0382 566
f133ecca 567 /* Create a /proc/tile/hardwall entry. */
b8ace083 568 hardwall_add_proc(info);
f133ecca 569
b8ace083 570 return info;
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571}
572
573/* Activate a given hardwall on this cpu for this process. */
b8ace083 574static int hardwall_activate(struct hardwall_info *info)
9f9c0382 575{
b8ace083 576 int cpu;
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577 unsigned long flags;
578 struct task_struct *p = current;
579 struct thread_struct *ts = &p->thread;
b8ace083 580 struct hardwall_type *hwt;
9f9c0382 581
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582 /* Require a hardwall. */
583 if (info == NULL)
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584 return -ENODATA;
585
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586 /* Not allowed to activate a hardwall that is being torn down. */
587 if (info->teardown_in_progress)
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588 return -EINVAL;
589
590 /*
591 * Get our affinity; if we're not bound to this tile uniquely,
592 * we can't access the network registers.
593 */
594 if (cpumask_weight(&p->cpus_allowed) != 1)
595 return -EPERM;
596
b8ace083 597 /* Make sure we are bound to a cpu assigned to this resource. */
9f9c0382
CM
598 cpu = smp_processor_id();
599 BUG_ON(cpumask_first(&p->cpus_allowed) != cpu);
b8ace083 600 if (!cpumask_test_cpu(cpu, &info->cpumask))
9f9c0382
CM
601 return -EINVAL;
602
603 /* If we are already bound to this hardwall, it's a no-op. */
b8ace083
CM
604 hwt = info->type;
605 if (ts->hardwall[hwt->index].info) {
606 BUG_ON(ts->hardwall[hwt->index].info != info);
9f9c0382
CM
607 return 0;
608 }
609
b8ace083
CM
610 /* Success! This process gets to use the resource on this cpu. */
611 ts->hardwall[hwt->index].info = info;
612 spin_lock_irqsave(&hwt->lock, flags);
613 list_add(&ts->hardwall[hwt->index].list, &info->task_head);
614 spin_unlock_irqrestore(&hwt->lock, flags);
615 grant_hardwall_mpls(hwt);
616 printk(KERN_DEBUG "Pid %d (%s) activated for %s hardwall: cpu %d\n",
617 p->pid, p->comm, hwt->name, cpu);
9f9c0382
CM
618 return 0;
619}
620
621/*
b8ace083 622 * Deactivate a task's hardwall. Must hold lock for hardwall_type.
7d937719 623 * This method may be called from exit_thread(), so we don't want to
9f9c0382
CM
624 * rely on too many fields of struct task_struct still being valid.
625 * We assume the cpus_allowed, pid, and comm fields are still valid.
626 */
b8ace083
CM
627static void _hardwall_deactivate(struct hardwall_type *hwt,
628 struct task_struct *task)
9f9c0382
CM
629{
630 struct thread_struct *ts = &task->thread;
631
632 if (cpumask_weight(&task->cpus_allowed) != 1) {
b8ace083 633 pr_err("pid %d (%s) releasing %s hardwall with"
9f9c0382 634 " an affinity mask containing %d cpus!\n",
b8ace083 635 task->pid, task->comm, hwt->name,
9f9c0382
CM
636 cpumask_weight(&task->cpus_allowed));
637 BUG();
638 }
639
b8ace083
CM
640 BUG_ON(ts->hardwall[hwt->index].info == NULL);
641 ts->hardwall[hwt->index].info = NULL;
642 list_del(&ts->hardwall[hwt->index].list);
9f9c0382 643 if (task == current)
b8ace083 644 restrict_hardwall_mpls(hwt);
9f9c0382
CM
645}
646
647/* Deactivate a task's hardwall. */
b8ace083
CM
648static int hardwall_deactivate(struct hardwall_type *hwt,
649 struct task_struct *task)
9f9c0382
CM
650{
651 unsigned long flags;
652 int activated;
653
b8ace083
CM
654 spin_lock_irqsave(&hwt->lock, flags);
655 activated = (task->thread.hardwall[hwt->index].info != NULL);
9f9c0382 656 if (activated)
b8ace083
CM
657 _hardwall_deactivate(hwt, task);
658 spin_unlock_irqrestore(&hwt->lock, flags);
9f9c0382
CM
659
660 if (!activated)
661 return -EINVAL;
662
b8ace083 663 printk(KERN_DEBUG "Pid %d (%s) deactivated for %s hardwall: cpu %d\n",
bc1a298f 664 task->pid, task->comm, hwt->name, raw_smp_processor_id());
9f9c0382
CM
665 return 0;
666}
667
b8ace083
CM
668void hardwall_deactivate_all(struct task_struct *task)
669{
670 int i;
671 for (i = 0; i < HARDWALL_TYPES; ++i)
672 if (task->thread.hardwall[i].info)
673 hardwall_deactivate(&hardwall_types[i], task);
674}
675
676/* Stop the switch before draining the network. */
677static void stop_xdn_switch(void *arg)
9f9c0382
CM
678{
679#if !CHIP_HAS_REV1_XDN()
680 /* Freeze the switch and the demux. */
681 __insn_mtspr(SPR_UDN_SP_FREEZE,
682 SPR_UDN_SP_FREEZE__SP_FRZ_MASK |
683 SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK |
684 SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK);
b8ace083
CM
685#else
686 /*
687 * Drop all packets bound for the core or off the edge.
688 * We rely on the normal hardwall protection setup code
689 * to have set the low four bits to trigger firewall interrupts,
690 * and shift those bits up to trigger "drop on send" semantics,
691 * plus adding "drop on send to core" for all switches.
692 * In practice it seems the switches latch the DIRECTION_PROTECT
693 * SPR so they won't start dropping if they're already
694 * delivering the last message to the core, but it doesn't
695 * hurt to enable it here.
696 */
697 struct hardwall_type *hwt = arg;
698 unsigned long protect = mfspr_XDN(hwt, DIRECTION_PROTECT);
699 mtspr_XDN(hwt, DIRECTION_PROTECT, (protect | C_PROTECT) << 5);
9f9c0382
CM
700#endif
701}
702
b8ace083
CM
703static void empty_xdn_demuxes(struct hardwall_type *hwt)
704{
705#ifndef __tilepro__
706 if (hwt->is_idn) {
707 while (__insn_mfspr(SPR_IDN_DATA_AVAIL) & (1 << 0))
708 (void) __tile_idn0_receive();
709 while (__insn_mfspr(SPR_IDN_DATA_AVAIL) & (1 << 1))
710 (void) __tile_idn1_receive();
711 return;
712 }
713#endif
714 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 0))
715 (void) __tile_udn0_receive();
716 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 1))
717 (void) __tile_udn1_receive();
718 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 2))
719 (void) __tile_udn2_receive();
720 while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 3))
721 (void) __tile_udn3_receive();
722}
723
9f9c0382 724/* Drain all the state from a stopped switch. */
b8ace083 725static void drain_xdn_switch(void *arg)
9f9c0382 726{
b8ace083
CM
727 struct hardwall_info *info = arg;
728 struct hardwall_type *hwt = info->type;
729
730#if CHIP_HAS_REV1_XDN()
731 /*
732 * The switches have been configured to drop any messages
733 * destined for cores (or off the edge of the rectangle).
734 * But the current message may continue to be delivered,
735 * so we wait until all the cores have finished any pending
736 * messages before we stop draining.
737 */
738 int pending = mfspr_XDN(hwt, PENDING);
739 while (pending--) {
740 empty_xdn_demuxes(hwt);
741 if (hwt->is_idn)
742 __tile_idn_send(0);
743 else
744 __tile_udn_send(0);
745 }
746 atomic_dec(&info->xdn_pending_count);
747 while (atomic_read(&info->xdn_pending_count))
748 empty_xdn_demuxes(hwt);
749#else
9f9c0382
CM
750 int i;
751 int from_tile_words, ca_count;
752
753 /* Empty out the 5 switch point fifos. */
754 for (i = 0; i < 5; i++) {
755 int words, j;
756 __insn_mtspr(SPR_UDN_SP_FIFO_SEL, i);
757 words = __insn_mfspr(SPR_UDN_SP_STATE) & 0xF;
758 for (j = 0; j < words; j++)
759 (void) __insn_mfspr(SPR_UDN_SP_FIFO_DATA);
760 BUG_ON((__insn_mfspr(SPR_UDN_SP_STATE) & 0xF) != 0);
761 }
762
763 /* Dump out the 3 word fifo at top. */
764 from_tile_words = (__insn_mfspr(SPR_UDN_DEMUX_STATUS) >> 10) & 0x3;
765 for (i = 0; i < from_tile_words; i++)
766 (void) __insn_mfspr(SPR_UDN_DEMUX_WRITE_FIFO);
767
768 /* Empty out demuxes. */
b8ace083 769 empty_xdn_demuxes(hwt);
9f9c0382
CM
770
771 /* Empty out catch all. */
772 ca_count = __insn_mfspr(SPR_UDN_DEMUX_CA_COUNT);
773 for (i = 0; i < ca_count; i++)
774 (void) __insn_mfspr(SPR_UDN_CA_DATA);
775 BUG_ON(__insn_mfspr(SPR_UDN_DEMUX_CA_COUNT) != 0);
776
777 /* Clear demux logic. */
778 __insn_mtspr(SPR_UDN_DEMUX_CTL, 1);
779
780 /*
781 * Write switch state; experimentation indicates that 0xc3000
782 * is an idle switch point.
783 */
784 for (i = 0; i < 5; i++) {
785 __insn_mtspr(SPR_UDN_SP_FIFO_SEL, i);
786 __insn_mtspr(SPR_UDN_SP_STATE, 0xc3000);
787 }
788#endif
789}
790
b8ace083
CM
791/* Reset random XDN state registers at boot up and during hardwall teardown. */
792static void reset_xdn_network_state(struct hardwall_type *hwt)
9f9c0382 793{
b8ace083 794 if (hwt->disabled)
9f9c0382
CM
795 return;
796
b8ace083
CM
797 /* Clear out other random registers so we have a clean slate. */
798 mtspr_XDN(hwt, DIRECTION_PROTECT, 0);
799 mtspr_XDN(hwt, AVAIL_EN, 0);
800 mtspr_XDN(hwt, DEADLOCK_TIMEOUT, 0);
801
9f9c0382 802#if !CHIP_HAS_REV1_XDN()
b8ace083
CM
803 /* Reset UDN coordinates to their standard value */
804 {
805 unsigned int cpu = smp_processor_id();
bc1a298f
CM
806 unsigned int x = cpu_x(cpu);
807 unsigned int y = cpu_y(cpu);
b8ace083
CM
808 __insn_mtspr(SPR_UDN_TILE_COORD, (x << 18) | (y << 7));
809 }
9f9c0382
CM
810
811 /* Set demux tags to predefined values and enable them. */
812 __insn_mtspr(SPR_UDN_TAG_VALID, 0xf);
813 __insn_mtspr(SPR_UDN_TAG_0, (1 << 0));
814 __insn_mtspr(SPR_UDN_TAG_1, (1 << 1));
815 __insn_mtspr(SPR_UDN_TAG_2, (1 << 2));
816 __insn_mtspr(SPR_UDN_TAG_3, (1 << 3));
9f9c0382 817
b8ace083 818 /* Set other rev0 random registers to a clean state. */
9f9c0382
CM
819 __insn_mtspr(SPR_UDN_REFILL_EN, 0);
820 __insn_mtspr(SPR_UDN_DEMUX_QUEUE_SEL, 0);
821 __insn_mtspr(SPR_UDN_SP_FIFO_SEL, 0);
9f9c0382
CM
822
823 /* Start the switch and demux. */
9f9c0382
CM
824 __insn_mtspr(SPR_UDN_SP_FREEZE, 0);
825#endif
826}
827
b8ace083 828void reset_network_state(void)
9f9c0382 829{
b8ace083
CM
830 reset_xdn_network_state(&hardwall_types[HARDWALL_UDN]);
831#ifndef __tilepro__
832 reset_xdn_network_state(&hardwall_types[HARDWALL_IDN]);
833#endif
9f9c0382
CM
834}
835
b8ace083
CM
836/* Restart an XDN switch after draining. */
837static void restart_xdn_switch(void *arg)
9f9c0382 838{
b8ace083 839 struct hardwall_type *hwt = arg;
9f9c0382 840
b8ace083
CM
841#if CHIP_HAS_REV1_XDN()
842 /* One last drain step to avoid races with injection and draining. */
843 empty_xdn_demuxes(hwt);
844#endif
9f9c0382 845
b8ace083
CM
846 reset_xdn_network_state(hwt);
847
848 /* Disable firewall interrupts. */
849 disable_firewall_interrupts(hwt);
9f9c0382
CM
850}
851
852/* Last reference to a hardwall is gone, so clear the network. */
b8ace083 853static void hardwall_destroy(struct hardwall_info *info)
9f9c0382
CM
854{
855 struct task_struct *task;
b8ace083 856 struct hardwall_type *hwt;
9f9c0382 857 unsigned long flags;
9f9c0382 858
b8ace083
CM
859 /* Make sure this file actually represents a hardwall. */
860 if (info == NULL)
9f9c0382
CM
861 return;
862
863 /*
864 * Deactivate any remaining tasks. It's possible to race with
865 * some other thread that is exiting and hasn't yet called
866 * deactivate (when freeing its thread_info), so we carefully
867 * deactivate any remaining tasks before freeing the
868 * hardwall_info object itself.
869 */
b8ace083
CM
870 hwt = info->type;
871 info->teardown_in_progress = 1;
872 spin_lock_irqsave(&hwt->lock, flags);
873 list_for_each_entry(task, &info->task_head,
874 thread.hardwall[hwt->index].list)
875 _hardwall_deactivate(hwt, task);
876 spin_unlock_irqrestore(&hwt->lock, flags);
877
878 if (hwt->is_xdn) {
879 /* Configure the switches for draining the user network. */
880 printk(KERN_DEBUG
881 "Clearing %s hardwall rectangle %dx%d %d,%d\n",
882 hwt->name, info->width, info->height,
883 info->ulhc_x, info->ulhc_y);
884 on_each_cpu_mask(&info->cpumask, stop_xdn_switch, hwt, 1);
885
886 /* Drain the network. */
887#if CHIP_HAS_REV1_XDN()
888 atomic_set(&info->xdn_pending_count,
889 cpumask_weight(&info->cpumask));
890 on_each_cpu_mask(&info->cpumask, drain_xdn_switch, info, 0);
891#else
892 on_each_cpu_mask(&info->cpumask, drain_xdn_switch, info, 1);
893#endif
9f9c0382 894
b8ace083
CM
895 /* Restart switch and disable firewall. */
896 on_each_cpu_mask(&info->cpumask, restart_xdn_switch, hwt, 1);
897 }
9f9c0382 898
f133ecca 899 /* Remove the /proc/tile/hardwall entry. */
b8ace083
CM
900 hardwall_remove_proc(info);
901
902 /* Now free the hardwall from the list. */
903 spin_lock_irqsave(&hwt->lock, flags);
904 BUG_ON(!list_empty(&info->task_head));
905 list_del(&info->list);
906 spin_unlock_irqrestore(&hwt->lock, flags);
907 kfree(info);
9f9c0382
CM
908}
909
910
f133ecca 911static int hardwall_proc_show(struct seq_file *sf, void *v)
9f9c0382 912{
b8ace083 913 struct hardwall_info *info = sf->private;
f133ecca 914 char buf[256];
9f9c0382 915
b8ace083 916 int rc = cpulist_scnprintf(buf, sizeof(buf), &info->cpumask);
f133ecca
CM
917 buf[rc++] = '\n';
918 seq_write(sf, buf, rc);
9f9c0382
CM
919 return 0;
920}
921
f133ecca
CM
922static int hardwall_proc_open(struct inode *inode,
923 struct file *file)
924{
d9dda78b 925 return single_open(file, hardwall_proc_show, PDE_DATA(inode));
f133ecca
CM
926}
927
928static const struct file_operations hardwall_proc_fops = {
929 .open = hardwall_proc_open,
930 .read = seq_read,
931 .llseek = seq_lseek,
932 .release = single_release,
933};
934
b8ace083 935static void hardwall_add_proc(struct hardwall_info *info)
f133ecca
CM
936{
937 char buf[64];
b8ace083
CM
938 snprintf(buf, sizeof(buf), "%d", info->id);
939 proc_create_data(buf, 0444, info->type->proc_dir,
940 &hardwall_proc_fops, info);
f133ecca
CM
941}
942
b8ace083 943static void hardwall_remove_proc(struct hardwall_info *info)
f133ecca
CM
944{
945 char buf[64];
b8ace083
CM
946 snprintf(buf, sizeof(buf), "%d", info->id);
947 remove_proc_entry(buf, info->type->proc_dir);
f133ecca
CM
948}
949
d962c144
AD
950int proc_pid_hardwall(struct seq_file *m, struct pid_namespace *ns,
951 struct pid *pid, struct task_struct *task)
f133ecca 952{
b8ace083
CM
953 int i;
954 int n = 0;
955 for (i = 0; i < HARDWALL_TYPES; ++i) {
956 struct hardwall_info *info = task->thread.hardwall[i].info;
957 if (info)
d962c144 958 seq_printf(m, "%s: %d\n", info->type->name, info->id);
b8ace083
CM
959 }
960 return n;
f133ecca
CM
961}
962
963void proc_tile_hardwall_init(struct proc_dir_entry *root)
964{
b8ace083
CM
965 int i;
966 for (i = 0; i < HARDWALL_TYPES; ++i) {
967 struct hardwall_type *hwt = &hardwall_types[i];
968 if (hwt->disabled)
969 continue;
970 if (hardwall_proc_dir == NULL)
971 hardwall_proc_dir = proc_mkdir("hardwall", root);
972 hwt->proc_dir = proc_mkdir(hwt->name, hardwall_proc_dir);
973 }
f133ecca
CM
974}
975
9f9c0382
CM
976
977/*
978 * Character device support via ioctl/close.
979 */
980
981static long hardwall_ioctl(struct file *file, unsigned int a, unsigned long b)
982{
b8ace083
CM
983 struct hardwall_info *info = file->private_data;
984 int minor = iminor(file->f_mapping->host);
985 struct hardwall_type* hwt;
9f9c0382
CM
986
987 if (_IOC_TYPE(a) != HARDWALL_IOCTL_BASE)
988 return -EINVAL;
989
b8ace083
CM
990 BUILD_BUG_ON(HARDWALL_TYPES != _HARDWALL_TYPES);
991 BUILD_BUG_ON(HARDWALL_TYPES !=
992 sizeof(hardwall_types)/sizeof(hardwall_types[0]));
993
994 if (minor < 0 || minor >= HARDWALL_TYPES)
995 return -EINVAL;
996 hwt = &hardwall_types[minor];
997 WARN_ON(info && hwt != info->type);
998
9f9c0382
CM
999 switch (_IOC_NR(a)) {
1000 case _HARDWALL_CREATE:
b8ace083 1001 if (hwt->disabled)
9f9c0382 1002 return -ENOSYS;
b8ace083 1003 if (info != NULL)
9f9c0382 1004 return -EALREADY;
b8ace083
CM
1005 info = hardwall_create(hwt, _IOC_SIZE(a),
1006 (const unsigned char __user *)b);
1007 if (IS_ERR(info))
1008 return PTR_ERR(info);
1009 file->private_data = info;
9f9c0382
CM
1010 return 0;
1011
1012 case _HARDWALL_ACTIVATE:
b8ace083 1013 return hardwall_activate(info);
9f9c0382
CM
1014
1015 case _HARDWALL_DEACTIVATE:
b8ace083 1016 if (current->thread.hardwall[hwt->index].info != info)
9f9c0382 1017 return -EINVAL;
b8ace083 1018 return hardwall_deactivate(hwt, current);
9f9c0382 1019
f133ecca 1020 case _HARDWALL_GET_ID:
b8ace083 1021 return info ? info->id : -EINVAL;
f133ecca 1022
9f9c0382
CM
1023 default:
1024 return -EINVAL;
1025 }
1026}
1027
1028#ifdef CONFIG_COMPAT
1029static long hardwall_compat_ioctl(struct file *file,
1030 unsigned int a, unsigned long b)
1031{
1032 /* Sign-extend the argument so it can be used as a pointer. */
1033 return hardwall_ioctl(file, a, (unsigned long)compat_ptr(b));
1034}
1035#endif
1036
1037/* The user process closed the file; revoke access to user networks. */
1038static int hardwall_flush(struct file *file, fl_owner_t owner)
1039{
b8ace083 1040 struct hardwall_info *info = file->private_data;
9f9c0382
CM
1041 struct task_struct *task, *tmp;
1042 unsigned long flags;
1043
b8ace083 1044 if (info) {
9f9c0382
CM
1045 /*
1046 * NOTE: if multiple threads are activated on this hardwall
1047 * file, the other threads will continue having access to the
b8ace083
CM
1048 * user network until they are context-switched out and back
1049 * in again.
9f9c0382
CM
1050 *
1051 * NOTE: A NULL files pointer means the task is being torn
1052 * down, so in that case we also deactivate it.
1053 */
b8ace083
CM
1054 struct hardwall_type *hwt = info->type;
1055 spin_lock_irqsave(&hwt->lock, flags);
1056 list_for_each_entry_safe(task, tmp, &info->task_head,
1057 thread.hardwall[hwt->index].list) {
9f9c0382 1058 if (task->files == owner || task->files == NULL)
b8ace083 1059 _hardwall_deactivate(hwt, task);
9f9c0382 1060 }
b8ace083 1061 spin_unlock_irqrestore(&hwt->lock, flags);
9f9c0382
CM
1062 }
1063
1064 return 0;
1065}
1066
1067/* This hardwall is gone, so destroy it. */
1068static int hardwall_release(struct inode *inode, struct file *file)
1069{
1070 hardwall_destroy(file->private_data);
1071 return 0;
1072}
1073
1074static const struct file_operations dev_hardwall_fops = {
d02db4f8 1075 .open = nonseekable_open,
9f9c0382
CM
1076 .unlocked_ioctl = hardwall_ioctl,
1077#ifdef CONFIG_COMPAT
1078 .compat_ioctl = hardwall_compat_ioctl,
1079#endif
1080 .flush = hardwall_flush,
1081 .release = hardwall_release,
1082};
1083
1084static struct cdev hardwall_dev;
1085
1086static int __init dev_hardwall_init(void)
1087{
1088 int rc;
1089 dev_t dev;
1090
b8ace083 1091 rc = alloc_chrdev_region(&dev, 0, HARDWALL_TYPES, "hardwall");
9f9c0382
CM
1092 if (rc < 0)
1093 return rc;
1094 cdev_init(&hardwall_dev, &dev_hardwall_fops);
b8ace083 1095 rc = cdev_add(&hardwall_dev, dev, HARDWALL_TYPES);
9f9c0382
CM
1096 if (rc < 0)
1097 return rc;
1098
1099 return 0;
1100}
1101late_initcall(dev_hardwall_init);
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