Commit | Line | Data |
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eb7c792d CM |
1 | /* TILE-Gx opcode information. |
2 | * | |
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation, version 2. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * | |
16 | * | |
17 | * | |
18 | * | |
19 | */ | |
20 | ||
18aecc2b CM |
21 | /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ |
22 | #define BFD_RELOC(x) -1 | |
23 | ||
24 | /* Special registers. */ | |
25 | #define TREG_LR 55 | |
26 | #define TREG_SN 56 | |
27 | #define TREG_ZERO 63 | |
28 | ||
18aecc2b | 29 | #include <linux/stddef.h> |
eb7c792d | 30 | #include <asm/tile-desc.h> |
18aecc2b CM |
31 | |
32 | const struct tilegx_opcode tilegx_opcodes[334] = | |
33 | { | |
34 | { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0, | |
35 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
36 | }, | |
37 | { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1, | |
38 | { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } }, | |
39 | }, | |
40 | { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1, | |
41 | { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } }, | |
42 | }, | |
43 | { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1, | |
44 | { { 6, 7 }, { 8, 9 }, { 10, 11 }, { 12, 13 }, { 0, } }, | |
45 | }, | |
46 | { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1, | |
47 | { { 6, 0 }, { 8, 1 }, { 10, 2 }, { 12, 3 }, { 0, } }, | |
48 | }, | |
49 | { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1, | |
50 | { { 6, 4 }, { 8, 5 }, { 0, }, { 0, }, { 0, } }, | |
51 | }, | |
52 | { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1, | |
53 | { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } }, | |
54 | }, | |
55 | { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1, | |
56 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
57 | }, | |
58 | { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1, | |
59 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
60 | }, | |
61 | { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1, | |
62 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
63 | }, | |
64 | { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1, | |
65 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
66 | }, | |
67 | { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1, | |
68 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
69 | }, | |
70 | { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1, | |
71 | { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
72 | }, | |
73 | { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1, | |
74 | { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } }, | |
75 | }, | |
76 | { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1, | |
77 | { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } }, | |
78 | }, | |
79 | { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1, | |
80 | { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } }, | |
81 | }, | |
82 | { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1, | |
83 | { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } }, | |
84 | }, | |
85 | { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1, | |
86 | { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } }, | |
87 | }, | |
88 | { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1, | |
89 | { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } }, | |
90 | }, | |
91 | { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1, | |
92 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
93 | }, | |
94 | { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1, | |
95 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
96 | }, | |
97 | { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1, | |
98 | { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, | |
99 | }, | |
100 | { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1, | |
101 | { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } }, | |
102 | }, | |
103 | { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1, | |
104 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
105 | }, | |
106 | { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1, | |
107 | { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, | |
108 | }, | |
109 | { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1, | |
110 | { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } }, | |
111 | }, | |
112 | { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1, | |
113 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
114 | }, | |
115 | { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1, | |
116 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
117 | }, | |
118 | { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1, | |
119 | { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, | |
120 | }, | |
121 | { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1, | |
122 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
123 | }, | |
124 | { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1, | |
125 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
126 | }, | |
127 | { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1, | |
128 | { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
129 | }, | |
130 | { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1, | |
131 | { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
132 | }, | |
133 | { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1, | |
134 | { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
135 | }, | |
136 | { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1, | |
137 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
138 | }, | |
139 | { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1, | |
140 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
141 | }, | |
142 | { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1, | |
143 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
144 | }, | |
145 | { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1, | |
146 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
147 | }, | |
148 | { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1, | |
149 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
150 | }, | |
151 | { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1, | |
152 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
153 | }, | |
154 | { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1, | |
155 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
156 | }, | |
157 | { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1, | |
158 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
159 | }, | |
160 | { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1, | |
161 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
162 | }, | |
163 | { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1, | |
164 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
165 | }, | |
166 | { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1, | |
167 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
168 | }, | |
169 | { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1, | |
170 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
171 | }, | |
172 | { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1, | |
173 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
174 | }, | |
175 | { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1, | |
176 | { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } }, | |
177 | }, | |
178 | { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1, | |
179 | { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, | |
180 | }, | |
181 | { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1, | |
182 | { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, | |
183 | }, | |
184 | { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1, | |
185 | { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, | |
186 | }, | |
187 | { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1, | |
188 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
189 | }, | |
190 | { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1, | |
191 | { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, | |
192 | }, | |
193 | { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1, | |
194 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
195 | }, | |
196 | { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1, | |
197 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
198 | }, | |
199 | { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1, | |
200 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
201 | }, | |
202 | { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1, | |
203 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
204 | }, | |
205 | { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1, | |
206 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
207 | }, | |
208 | { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1, | |
209 | { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } }, | |
210 | }, | |
211 | { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1, | |
212 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
213 | }, | |
214 | { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1, | |
215 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
216 | }, | |
217 | { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1, | |
218 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
219 | }, | |
220 | { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1, | |
221 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
222 | }, | |
223 | { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1, | |
224 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
225 | }, | |
226 | { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1, | |
227 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
228 | }, | |
229 | { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1, | |
230 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
231 | }, | |
232 | { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1, | |
233 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
234 | }, | |
235 | { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1, | |
236 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
237 | }, | |
238 | { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1, | |
239 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
240 | }, | |
241 | { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1, | |
242 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
243 | }, | |
244 | { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1, | |
245 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
246 | }, | |
247 | { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1, | |
248 | { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, | |
249 | }, | |
250 | { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1, | |
251 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
252 | }, | |
253 | { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1, | |
254 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
255 | }, | |
256 | { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1, | |
257 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
258 | }, | |
259 | { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1, | |
260 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
261 | }, | |
262 | { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0, | |
263 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
264 | }, | |
265 | { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1, | |
266 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | |
267 | }, | |
268 | { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1, | |
269 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
270 | }, | |
271 | { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1, | |
272 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
273 | }, | |
274 | { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1, | |
275 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
276 | }, | |
277 | { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1, | |
278 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
279 | }, | |
280 | { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1, | |
281 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
282 | }, | |
283 | { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1, | |
284 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
285 | }, | |
286 | { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1, | |
287 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
288 | }, | |
289 | { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1, | |
290 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
291 | }, | |
292 | { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1, | |
293 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
294 | }, | |
295 | { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1, | |
296 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
297 | }, | |
298 | { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1, | |
299 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
300 | }, | |
301 | { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1, | |
302 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
303 | }, | |
304 | { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1, | |
305 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
306 | }, | |
307 | { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1, | |
308 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
309 | }, | |
310 | { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1, | |
311 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
312 | }, | |
313 | { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1, | |
314 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
315 | }, | |
316 | { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1, | |
317 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
318 | }, | |
319 | { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1, | |
320 | { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
321 | }, | |
322 | { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1, | |
323 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | |
324 | }, | |
325 | { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1, | |
326 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | |
327 | }, | |
328 | { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1, | |
329 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
330 | }, | |
331 | { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1, | |
332 | { { }, { }, { }, { }, { 0, } }, | |
333 | }, | |
334 | { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1, | |
335 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
336 | }, | |
337 | { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1, | |
338 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
339 | }, | |
340 | { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1, | |
341 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
342 | }, | |
343 | { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1, | |
344 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
345 | }, | |
346 | { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1, | |
347 | { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, | |
348 | }, | |
349 | { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1, | |
350 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
351 | }, | |
352 | { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1, | |
353 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
354 | }, | |
355 | { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1, | |
356 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | |
357 | }, | |
358 | { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1, | |
359 | { { 0, }, { }, { 0, }, { }, { 0, } }, | |
360 | }, | |
361 | { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1, | |
362 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | |
363 | }, | |
364 | { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1, | |
365 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
366 | }, | |
367 | { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1, | |
368 | { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } }, | |
369 | }, | |
370 | { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1, | |
371 | { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } }, | |
372 | }, | |
373 | { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1, | |
374 | { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } }, | |
375 | }, | |
376 | { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1, | |
377 | { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } }, | |
378 | }, | |
379 | { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1, | |
380 | { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } }, | |
381 | }, | |
382 | { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1, | |
383 | { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } }, | |
384 | }, | |
385 | { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1, | |
386 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } }, | |
387 | }, | |
388 | { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1, | |
389 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } }, | |
390 | }, | |
391 | { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1, | |
392 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
393 | }, | |
394 | { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1, | |
395 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } }, | |
396 | }, | |
397 | { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1, | |
398 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
399 | }, | |
400 | { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1, | |
401 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } }, | |
402 | }, | |
403 | { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1, | |
404 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
405 | }, | |
406 | { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1, | |
407 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } }, | |
408 | }, | |
409 | { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1, | |
410 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
411 | }, | |
412 | { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1, | |
413 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } }, | |
414 | }, | |
415 | { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1, | |
416 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
417 | }, | |
418 | { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1, | |
419 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } }, | |
420 | }, | |
421 | { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1, | |
422 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
423 | }, | |
424 | { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1, | |
425 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
426 | }, | |
427 | { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1, | |
428 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
429 | }, | |
430 | { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1, | |
431 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
432 | }, | |
433 | { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1, | |
434 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
435 | }, | |
436 | { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1, | |
437 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
438 | }, | |
439 | { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1, | |
440 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
441 | }, | |
442 | { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1, | |
443 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
444 | }, | |
445 | { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1, | |
446 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
447 | }, | |
448 | { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1, | |
449 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
450 | }, | |
451 | { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1, | |
452 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
453 | }, | |
454 | { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1, | |
455 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
456 | }, | |
457 | { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1, | |
458 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
459 | }, | |
460 | { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1, | |
461 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
462 | }, | |
463 | { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1, | |
464 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
465 | }, | |
466 | { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1, | |
467 | { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } }, | |
468 | }, | |
469 | { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1, | |
470 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
471 | }, | |
472 | { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1, | |
473 | { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } }, | |
474 | }, | |
475 | { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1, | |
476 | { { 0, }, { 8 }, { 0, }, { 12 }, { 0, } }, | |
477 | }, | |
478 | { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1, | |
479 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
480 | }, | |
481 | { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1, | |
482 | { { 0, }, { 8, 27 }, { 0, }, { 0, }, { 0, } }, | |
483 | }, | |
484 | { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1, | |
485 | { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
486 | }, | |
487 | { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1, | |
488 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
489 | }, | |
490 | { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1, | |
491 | { { 0, }, { 28, 9 }, { 0, }, { 0, }, { 0, } }, | |
492 | }, | |
493 | { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1, | |
494 | { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, | |
495 | }, | |
496 | { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1, | |
497 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
498 | }, | |
499 | { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1, | |
500 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
501 | }, | |
502 | { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1, | |
503 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
504 | }, | |
505 | { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1, | |
506 | { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, | |
507 | }, | |
508 | { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1, | |
509 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
510 | }, | |
511 | { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1, | |
512 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
513 | }, | |
514 | { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1, | |
515 | { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, | |
516 | }, | |
517 | { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1, | |
518 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
519 | }, | |
520 | { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1, | |
521 | { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, | |
522 | }, | |
523 | { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1, | |
524 | { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, | |
525 | }, | |
526 | { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1, | |
527 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
528 | }, | |
529 | { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1, | |
530 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
531 | }, | |
532 | { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1, | |
533 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
534 | }, | |
535 | { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1, | |
536 | { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, | |
537 | }, | |
538 | { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1, | |
539 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
540 | }, | |
541 | { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1, | |
542 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
543 | }, | |
544 | { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1, | |
545 | { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, | |
546 | }, | |
547 | { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1, | |
548 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
549 | }, | |
550 | { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1, | |
551 | { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, | |
552 | }, | |
553 | { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1, | |
554 | { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } }, | |
555 | }, | |
556 | { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1, | |
557 | { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } }, | |
558 | }, | |
559 | { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1, | |
560 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
561 | }, | |
562 | { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0, | |
563 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
564 | }, | |
565 | { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1, | |
566 | { { }, { }, { }, { }, { 0, } }, | |
567 | }, | |
568 | { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1, | |
569 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
570 | }, | |
571 | { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1, | |
572 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
573 | }, | |
574 | { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1, | |
575 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
576 | }, | |
577 | { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1, | |
578 | { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, | |
579 | }, | |
580 | { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1, | |
581 | { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, | |
582 | }, | |
583 | { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1, | |
584 | { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } }, | |
585 | }, | |
586 | { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1, | |
587 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
588 | }, | |
589 | { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1, | |
590 | { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, | |
591 | }, | |
592 | { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1, | |
593 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
594 | }, | |
595 | { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1, | |
596 | { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } }, | |
597 | }, | |
598 | { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1, | |
599 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
600 | }, | |
601 | { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1, | |
602 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
603 | }, | |
604 | { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1, | |
605 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
606 | }, | |
607 | { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1, | |
608 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
609 | }, | |
610 | { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1, | |
611 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
612 | }, | |
613 | { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1, | |
614 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
615 | }, | |
616 | { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1, | |
617 | { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, | |
618 | }, | |
619 | { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1, | |
620 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
621 | }, | |
622 | { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1, | |
623 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
624 | }, | |
625 | { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1, | |
626 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
627 | }, | |
628 | { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1, | |
629 | { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, | |
630 | }, | |
631 | { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1, | |
632 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
633 | }, | |
634 | { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1, | |
635 | { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } }, | |
636 | }, | |
637 | { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1, | |
638 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
639 | }, | |
640 | { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1, | |
641 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
642 | }, | |
643 | { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1, | |
644 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
645 | }, | |
646 | { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1, | |
647 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } }, | |
648 | }, | |
649 | { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1, | |
650 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } }, | |
651 | }, | |
652 | { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1, | |
653 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
654 | }, | |
655 | { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1, | |
656 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } }, | |
657 | }, | |
658 | { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1, | |
659 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
660 | }, | |
661 | { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1, | |
662 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } }, | |
663 | }, | |
664 | { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1, | |
665 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
666 | }, | |
667 | { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1, | |
668 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
669 | }, | |
670 | { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1, | |
671 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
672 | }, | |
673 | { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1, | |
674 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
675 | }, | |
676 | { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1, | |
677 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
678 | }, | |
679 | { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1, | |
680 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
681 | }, | |
682 | { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1, | |
683 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
684 | }, | |
685 | { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1, | |
686 | { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
687 | }, | |
688 | { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1, | |
689 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
690 | }, | |
691 | { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1, | |
692 | { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } }, | |
693 | }, | |
694 | { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1, | |
695 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
696 | }, | |
697 | { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1, | |
698 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
699 | }, | |
700 | { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1, | |
701 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
702 | }, | |
703 | { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0, | |
704 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
705 | }, | |
706 | { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0, | |
707 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
708 | }, | |
709 | { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0, | |
710 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
711 | }, | |
712 | { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0, | |
713 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | |
714 | }, | |
715 | { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1, | |
716 | { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, | |
717 | }, | |
718 | { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1, | |
719 | { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, | |
720 | }, | |
721 | { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1, | |
722 | { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, | |
723 | }, | |
724 | { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1, | |
725 | { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } }, | |
726 | }, | |
727 | { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1, | |
728 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
729 | }, | |
730 | { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1, | |
731 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
732 | }, | |
733 | { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1, | |
734 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
735 | }, | |
736 | { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1, | |
737 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
738 | }, | |
739 | { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1, | |
740 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
741 | }, | |
742 | { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1, | |
743 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
744 | }, | |
745 | { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1, | |
746 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
747 | }, | |
748 | { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1, | |
749 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
750 | }, | |
751 | { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1, | |
752 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
753 | }, | |
754 | { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1, | |
755 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
756 | }, | |
757 | { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1, | |
758 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
759 | }, | |
760 | { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1, | |
761 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
762 | }, | |
763 | { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1, | |
764 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
765 | }, | |
766 | { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1, | |
767 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
768 | }, | |
769 | { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1, | |
770 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
771 | }, | |
772 | { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1, | |
773 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
774 | }, | |
775 | { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1, | |
776 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
777 | }, | |
778 | { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1, | |
779 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
780 | }, | |
781 | { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1, | |
782 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
783 | }, | |
784 | { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1, | |
785 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
786 | }, | |
787 | { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1, | |
788 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
789 | }, | |
790 | { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1, | |
791 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
792 | }, | |
793 | { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1, | |
794 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
795 | }, | |
796 | { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1, | |
797 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
798 | }, | |
799 | { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1, | |
800 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
801 | }, | |
802 | { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1, | |
803 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
804 | }, | |
805 | { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1, | |
806 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
807 | }, | |
808 | { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1, | |
809 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
810 | }, | |
811 | { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1, | |
812 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
813 | }, | |
814 | { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1, | |
815 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
816 | }, | |
817 | { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1, | |
818 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
819 | }, | |
820 | { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1, | |
821 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
822 | }, | |
823 | { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1, | |
824 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
825 | }, | |
826 | { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1, | |
827 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
828 | }, | |
829 | { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1, | |
830 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
831 | }, | |
832 | { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1, | |
833 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
834 | }, | |
835 | { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1, | |
836 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
837 | }, | |
838 | { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1, | |
839 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
840 | }, | |
841 | { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1, | |
842 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
843 | }, | |
844 | { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1, | |
845 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
846 | }, | |
847 | { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1, | |
848 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
849 | }, | |
850 | { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1, | |
851 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
852 | }, | |
853 | { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1, | |
854 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
855 | }, | |
856 | { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1, | |
857 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
858 | }, | |
859 | { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1, | |
860 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
861 | }, | |
862 | { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1, | |
863 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
864 | }, | |
865 | { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1, | |
866 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
867 | }, | |
868 | { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1, | |
869 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
870 | }, | |
871 | { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1, | |
872 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
873 | }, | |
874 | { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1, | |
875 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
876 | }, | |
877 | { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1, | |
878 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
879 | }, | |
880 | { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1, | |
881 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
882 | }, | |
883 | { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1, | |
884 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
885 | }, | |
886 | { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1, | |
887 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
888 | }, | |
889 | { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1, | |
890 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
891 | }, | |
892 | { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1, | |
893 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
894 | }, | |
895 | { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1, | |
896 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
897 | }, | |
898 | { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1, | |
899 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
900 | }, | |
901 | { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1, | |
902 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
903 | }, | |
904 | { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1, | |
905 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
906 | }, | |
907 | { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1, | |
908 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
909 | }, | |
910 | { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1, | |
911 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
912 | }, | |
913 | { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1, | |
914 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
915 | }, | |
916 | { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1, | |
917 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
918 | }, | |
919 | { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1, | |
920 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
921 | }, | |
922 | { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1, | |
923 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
924 | }, | |
925 | { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1, | |
926 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
927 | }, | |
928 | { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1, | |
929 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
930 | }, | |
931 | { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1, | |
932 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
933 | }, | |
934 | { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1, | |
935 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
936 | }, | |
937 | { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1, | |
938 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
939 | }, | |
940 | { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1, | |
941 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
942 | }, | |
943 | { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1, | |
944 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
945 | }, | |
946 | { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1, | |
947 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
948 | }, | |
949 | { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1, | |
950 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
951 | }, | |
952 | { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1, | |
953 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
954 | }, | |
955 | { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1, | |
956 | { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
957 | }, | |
958 | { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1, | |
959 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
960 | }, | |
961 | { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1, | |
962 | { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | |
963 | }, | |
964 | { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1, | |
965 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
966 | }, | |
967 | { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1, | |
968 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
969 | }, | |
970 | { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1, | |
971 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
972 | }, | |
973 | { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1, | |
974 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
975 | }, | |
976 | { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1, | |
977 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
978 | }, | |
979 | { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1, | |
980 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
981 | }, | |
982 | { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1, | |
983 | { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } }, | |
984 | }, | |
985 | { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1, | |
986 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
987 | }, | |
988 | { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1, | |
989 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
990 | }, | |
991 | { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1, | |
992 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
993 | }, | |
994 | { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1, | |
995 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
996 | }, | |
997 | { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1, | |
998 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
999 | }, | |
1000 | { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1, | |
1001 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1002 | }, | |
1003 | { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1, | |
1004 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1005 | }, | |
1006 | { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1, | |
1007 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1008 | }, | |
1009 | { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1, | |
1010 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1011 | }, | |
1012 | { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1, | |
1013 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1014 | }, | |
1015 | { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1, | |
1016 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1017 | }, | |
1018 | { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1, | |
1019 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1020 | }, | |
1021 | { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1, | |
1022 | { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } }, | |
1023 | }, | |
1024 | { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1, | |
1025 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | |
1026 | }, | |
1027 | { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1, | |
1028 | { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } }, | |
1029 | }, | |
1030 | { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1, | |
1031 | { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } }, | |
1032 | }, | |
1033 | { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } }, | |
1034 | } | |
1035 | }; | |
1036 | #define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6)) | |
1037 | #define CHILD(array_index) (TILEGX_OPC_NONE + (array_index)) | |
1038 | ||
1039 | static const unsigned short decode_X0_fsm[936] = | |
1040 | { | |
1041 | BITFIELD(22, 9) /* index 0 */, | |
1042 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1043 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1044 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1045 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1046 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1047 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1048 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1049 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1050 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1051 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1052 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1053 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1054 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1055 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1056 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1057 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1058 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1059 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1060 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1061 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1062 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1063 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1064 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1065 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1066 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1067 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1068 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI, | |
1069 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1070 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1071 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1072 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1073 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1074 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1075 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1076 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1077 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1078 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1079 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1080 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1081 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1082 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1083 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1084 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE, | |
1085 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1086 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1087 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1088 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS, | |
1089 | TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU, | |
1090 | TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS, | |
1091 | TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM, | |
1092 | TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE, | |
1093 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1094 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1095 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1096 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1097 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1098 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1099 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1100 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578), | |
1101 | CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE, | |
1102 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1103 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1104 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1105 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1106 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1107 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1108 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1109 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1110 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1111 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1112 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1113 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1114 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1115 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1116 | TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671), | |
1117 | CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865), | |
1118 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1119 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1120 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1121 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1122 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1123 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1124 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1125 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1126 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1127 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1128 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1129 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1130 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1131 | TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1132 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1133 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1134 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1135 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1136 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1137 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1138 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1139 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1140 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1141 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1142 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1143 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1144 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1145 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1146 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1147 | TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1148 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1149 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1150 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1151 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1152 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1153 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1154 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1155 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1156 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1157 | CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), | |
1158 | BITFIELD(6, 2) /* index 513 */, | |
1159 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518), | |
1160 | BITFIELD(8, 2) /* index 518 */, | |
1161 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523), | |
1162 | BITFIELD(10, 2) /* index 523 */, | |
1163 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI, | |
1164 | BITFIELD(20, 2) /* index 528 */, | |
1165 | TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548), | |
1166 | BITFIELD(6, 2) /* index 533 */, | |
1167 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538), | |
1168 | BITFIELD(8, 2) /* index 538 */, | |
1169 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543), | |
1170 | BITFIELD(10, 2) /* index 543 */, | |
1171 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, | |
1172 | BITFIELD(0, 2) /* index 548 */, | |
1173 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553), | |
1174 | BITFIELD(2, 2) /* index 553 */, | |
1175 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558), | |
1176 | BITFIELD(4, 2) /* index 558 */, | |
1177 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563), | |
1178 | BITFIELD(6, 2) /* index 563 */, | |
1179 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568), | |
1180 | BITFIELD(8, 2) /* index 568 */, | |
1181 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573), | |
1182 | BITFIELD(10, 2) /* index 573 */, | |
1183 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, | |
1184 | BITFIELD(20, 2) /* index 578 */, | |
1185 | TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI, | |
1186 | BITFIELD(20, 2) /* index 583 */, | |
1187 | TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI, | |
1188 | TILEGX_OPC_V1CMPLTUI, | |
1189 | BITFIELD(20, 2) /* index 588 */, | |
1190 | TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI, | |
1191 | TILEGX_OPC_V2CMPEQI, | |
1192 | BITFIELD(20, 2) /* index 593 */, | |
1193 | TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI, | |
1194 | TILEGX_OPC_V2MINSI, | |
1195 | BITFIELD(20, 2) /* index 598 */, | |
1196 | TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1197 | BITFIELD(18, 4) /* index 603 */, | |
1198 | TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD, | |
1199 | TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ, | |
1200 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, | |
1201 | TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR, | |
1202 | BITFIELD(18, 4) /* index 620 */, | |
1203 | TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL, | |
1204 | TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2, | |
1205 | TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN, | |
1206 | TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS, | |
1207 | TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1, | |
1208 | TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS, | |
1209 | BITFIELD(18, 4) /* index 637 */, | |
1210 | TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN, | |
1211 | TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2, | |
1212 | TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2, | |
1213 | TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX, | |
1214 | TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS, | |
1215 | TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS, | |
1216 | BITFIELD(18, 4) /* index 654 */, | |
1217 | TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU, | |
1218 | TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS, | |
1219 | TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU, | |
1220 | TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU, | |
1221 | TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU, | |
1222 | TILEGX_OPC_MZ, | |
1223 | BITFIELD(18, 4) /* index 671 */, | |
1224 | TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX, | |
1225 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD, | |
1226 | TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL, | |
1227 | TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES, | |
1228 | TILEGX_OPC_SUBXSC, | |
1229 | BITFIELD(12, 2) /* index 688 */, | |
1230 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693), | |
1231 | BITFIELD(14, 2) /* index 693 */, | |
1232 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698), | |
1233 | BITFIELD(16, 2) /* index 698 */, | |
1234 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, | |
1235 | BITFIELD(18, 4) /* index 703 */, | |
1236 | TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC, | |
1237 | TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU, | |
1238 | TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU, | |
1239 | TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE, | |
1240 | TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA, | |
1241 | BITFIELD(12, 4) /* index 720 */, | |
1242 | TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757), | |
1243 | CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787), | |
1244 | CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1245 | BITFIELD(16, 2) /* index 737 */, | |
1246 | TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1247 | BITFIELD(16, 2) /* index 742 */, | |
1248 | TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1249 | BITFIELD(16, 2) /* index 747 */, | |
1250 | TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1251 | BITFIELD(16, 2) /* index 752 */, | |
1252 | TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1253 | BITFIELD(16, 2) /* index 757 */, | |
1254 | TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1255 | BITFIELD(16, 2) /* index 762 */, | |
1256 | TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1257 | BITFIELD(16, 2) /* index 767 */, | |
1258 | TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1259 | BITFIELD(16, 2) /* index 772 */, | |
1260 | TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1261 | BITFIELD(16, 2) /* index 777 */, | |
1262 | TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1263 | BITFIELD(16, 2) /* index 782 */, | |
1264 | TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1265 | BITFIELD(16, 2) /* index 787 */, | |
1266 | TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1267 | BITFIELD(16, 2) /* index 792 */, | |
1268 | TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1269 | BITFIELD(18, 4) /* index 797 */, | |
1270 | TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP, | |
1271 | TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU, | |
1272 | TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS, | |
1273 | TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU, | |
1274 | TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, | |
1275 | BITFIELD(18, 4) /* index 814 */, | |
1276 | TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, | |
1277 | TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS, | |
1278 | TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, | |
1279 | TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE, | |
1280 | TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H, | |
1281 | BITFIELD(18, 4) /* index 831 */, | |
1282 | TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, | |
1283 | TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ, | |
1284 | TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC, | |
1285 | TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS, | |
1286 | TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC, | |
1287 | BITFIELD(18, 4) /* index 848 */, | |
1288 | TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC, | |
1289 | TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H, | |
1290 | TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC, | |
1291 | TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC, | |
1292 | TILEGX_OPC_V4SUB, | |
1293 | BITFIELD(18, 3) /* index 865 */, | |
1294 | CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE, | |
1295 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1296 | BITFIELD(21, 1) /* index 874 */, | |
1297 | TILEGX_OPC_XOR, TILEGX_OPC_NONE, | |
1298 | BITFIELD(21, 1) /* index 877 */, | |
1299 | TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE, | |
1300 | BITFIELD(21, 1) /* index 880 */, | |
1301 | TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE, | |
1302 | BITFIELD(21, 1) /* index 883 */, | |
1303 | TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE, | |
1304 | BITFIELD(21, 1) /* index 886 */, | |
1305 | TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE, | |
1306 | BITFIELD(18, 4) /* index 889 */, | |
1307 | TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI, | |
1308 | TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI, | |
1309 | TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI, | |
1310 | TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1311 | TILEGX_OPC_NONE, | |
1312 | BITFIELD(0, 2) /* index 906 */, | |
1313 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1314 | CHILD(911), | |
1315 | BITFIELD(2, 2) /* index 911 */, | |
1316 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1317 | CHILD(916), | |
1318 | BITFIELD(4, 2) /* index 916 */, | |
1319 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1320 | CHILD(921), | |
1321 | BITFIELD(6, 2) /* index 921 */, | |
1322 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1323 | CHILD(926), | |
1324 | BITFIELD(8, 2) /* index 926 */, | |
1325 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1326 | CHILD(931), | |
1327 | BITFIELD(10, 2) /* index 931 */, | |
1328 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1329 | TILEGX_OPC_INFOL, | |
1330 | }; | |
1331 | ||
1332 | static const unsigned short decode_X1_fsm[1206] = | |
1333 | { | |
1334 | BITFIELD(53, 9) /* index 0 */, | |
1335 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1336 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1337 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1338 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1339 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1340 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1341 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1342 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1343 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1344 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), | |
1345 | CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI, | |
1346 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1347 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1348 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1349 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1350 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1351 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1352 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1353 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1354 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1355 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1356 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1357 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1358 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1359 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1360 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, | |
1361 | TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE, | |
1362 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1363 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1364 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1365 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1366 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1367 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1368 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1369 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT, | |
1370 | TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT, | |
1371 | TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT, | |
1372 | TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT, | |
1373 | TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST, | |
1374 | TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT, | |
1375 | TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT, | |
1376 | TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT, | |
1377 | TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578), | |
1378 | CHILD(598), CHILD(663), CHILD(683), CHILD(688), CHILD(693), CHILD(698), | |
1379 | CHILD(703), CHILD(708), CHILD(713), CHILD(718), TILEGX_OPC_NONE, | |
1380 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1381 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1382 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1383 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1384 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1385 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1386 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1387 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1388 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1389 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1390 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1391 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1392 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL, | |
1393 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, | |
1394 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, | |
1395 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, | |
1396 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, | |
1397 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, | |
1398 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, | |
1399 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, | |
1400 | TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J, | |
1401 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, | |
1402 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, | |
1403 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, | |
1404 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, | |
1405 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, | |
1406 | TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, | |
1407 | CHILD(723), CHILD(740), CHILD(772), CHILD(789), CHILD(1108), CHILD(1125), | |
1408 | CHILD(1142), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1409 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1410 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1411 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1412 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1413 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1414 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1415 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1416 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1417 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1418 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1419 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1420 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1421 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1422 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1159), TILEGX_OPC_NONE, | |
1423 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1424 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1425 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1426 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1427 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1428 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1429 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1430 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1431 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1432 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1433 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1434 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1435 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1436 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1437 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1438 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1176), CHILD(1176), CHILD(1176), | |
1439 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1440 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1441 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1442 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1443 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1444 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1445 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1446 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1447 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1448 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1449 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1450 | CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), | |
1451 | CHILD(1176), | |
1452 | BITFIELD(37, 2) /* index 513 */, | |
1453 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518), | |
1454 | BITFIELD(39, 2) /* index 518 */, | |
1455 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523), | |
1456 | BITFIELD(41, 2) /* index 523 */, | |
1457 | TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI, | |
1458 | BITFIELD(51, 2) /* index 528 */, | |
1459 | TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548), | |
1460 | BITFIELD(37, 2) /* index 533 */, | |
1461 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538), | |
1462 | BITFIELD(39, 2) /* index 538 */, | |
1463 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543), | |
1464 | BITFIELD(41, 2) /* index 543 */, | |
1465 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, | |
1466 | BITFIELD(31, 2) /* index 548 */, | |
1467 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553), | |
1468 | BITFIELD(33, 2) /* index 553 */, | |
1469 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558), | |
1470 | BITFIELD(35, 2) /* index 558 */, | |
1471 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563), | |
1472 | BITFIELD(37, 2) /* index 563 */, | |
1473 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568), | |
1474 | BITFIELD(39, 2) /* index 568 */, | |
1475 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573), | |
1476 | BITFIELD(41, 2) /* index 573 */, | |
1477 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, | |
1478 | BITFIELD(51, 2) /* index 578 */, | |
1479 | TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583), | |
1480 | BITFIELD(31, 2) /* index 583 */, | |
1481 | TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588), | |
1482 | BITFIELD(33, 2) /* index 588 */, | |
1483 | TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593), | |
1484 | BITFIELD(35, 2) /* index 593 */, | |
1485 | TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, | |
1486 | TILEGX_OPC_PREFETCH_ADD_L1_FAULT, | |
1487 | BITFIELD(51, 2) /* index 598 */, | |
1488 | CHILD(603), CHILD(618), CHILD(633), CHILD(648), | |
1489 | BITFIELD(31, 2) /* index 603 */, | |
1490 | TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608), | |
1491 | BITFIELD(33, 2) /* index 608 */, | |
1492 | TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613), | |
1493 | BITFIELD(35, 2) /* index 613 */, | |
1494 | TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, | |
1495 | TILEGX_OPC_PREFETCH_ADD_L1, | |
1496 | BITFIELD(31, 2) /* index 618 */, | |
1497 | TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623), | |
1498 | BITFIELD(33, 2) /* index 623 */, | |
1499 | TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628), | |
1500 | BITFIELD(35, 2) /* index 628 */, | |
1501 | TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, | |
1502 | TILEGX_OPC_PREFETCH_ADD_L2_FAULT, | |
1503 | BITFIELD(31, 2) /* index 633 */, | |
1504 | TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638), | |
1505 | BITFIELD(33, 2) /* index 638 */, | |
1506 | TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643), | |
1507 | BITFIELD(35, 2) /* index 643 */, | |
1508 | TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, | |
1509 | TILEGX_OPC_PREFETCH_ADD_L2, | |
1510 | BITFIELD(31, 2) /* index 648 */, | |
1511 | TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(653), | |
1512 | BITFIELD(33, 2) /* index 653 */, | |
1513 | TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(658), | |
1514 | BITFIELD(35, 2) /* index 658 */, | |
1515 | TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, | |
1516 | TILEGX_OPC_PREFETCH_ADD_L3_FAULT, | |
1517 | BITFIELD(51, 2) /* index 663 */, | |
1518 | CHILD(668), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD, | |
1519 | TILEGX_OPC_LDNT2S_ADD, | |
1520 | BITFIELD(31, 2) /* index 668 */, | |
1521 | TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(673), | |
1522 | BITFIELD(33, 2) /* index 673 */, | |
1523 | TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(678), | |
1524 | BITFIELD(35, 2) /* index 678 */, | |
1525 | TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, | |
1526 | TILEGX_OPC_PREFETCH_ADD_L3, | |
1527 | BITFIELD(51, 2) /* index 683 */, | |
1528 | TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD, | |
1529 | TILEGX_OPC_LDNT_ADD, | |
1530 | BITFIELD(51, 2) /* index 688 */, | |
1531 | TILEGX_OPC_LD_ADD, TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR, | |
1532 | BITFIELD(51, 2) /* index 693 */, | |
1533 | TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD, | |
1534 | BITFIELD(51, 2) /* index 698 */, | |
1535 | TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD, | |
1536 | TILEGX_OPC_STNT_ADD, | |
1537 | BITFIELD(51, 2) /* index 703 */, | |
1538 | TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, | |
1539 | TILEGX_OPC_V1CMPLTSI, | |
1540 | BITFIELD(51, 2) /* index 708 */, | |
1541 | TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, | |
1542 | TILEGX_OPC_V2ADDI, | |
1543 | BITFIELD(51, 2) /* index 713 */, | |
1544 | TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, | |
1545 | TILEGX_OPC_V2MAXSI, | |
1546 | BITFIELD(51, 2) /* index 718 */, | |
1547 | TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1548 | BITFIELD(49, 4) /* index 723 */, | |
1549 | TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD, | |
1550 | TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH, | |
1551 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, | |
1552 | TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4, | |
1553 | TILEGX_OPC_DBLALIGN6, | |
1554 | BITFIELD(49, 4) /* index 740 */, | |
1555 | TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4, | |
1556 | TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD, | |
1557 | TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4, | |
1558 | TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR, | |
1559 | CHILD(757), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX, | |
1560 | BITFIELD(43, 2) /* index 757 */, | |
1561 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(762), | |
1562 | BITFIELD(45, 2) /* index 762 */, | |
1563 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(767), | |
1564 | BITFIELD(47, 2) /* index 767 */, | |
1565 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, | |
1566 | BITFIELD(49, 4) /* index 772 */, | |
1567 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD, | |
1568 | TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL, | |
1569 | TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1, | |
1570 | TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2, | |
1571 | TILEGX_OPC_STNT4, | |
1572 | BITFIELD(46, 7) /* index 789 */, | |
1573 | TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, | |
1574 | TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, | |
1575 | TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, | |
1576 | TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC, | |
1577 | TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, | |
1578 | TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX, | |
1579 | TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, | |
1580 | TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, | |
1581 | TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, | |
1582 | TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(918), CHILD(927), | |
1583 | CHILD(1006), CHILD(1090), CHILD(1099), TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1584 | TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, | |
1585 | TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, | |
1586 | TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, | |
1587 | TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, | |
1588 | TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, | |
1589 | TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, | |
1590 | TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, | |
1591 | TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, | |
1592 | TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, | |
1593 | TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU, | |
1594 | TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, | |
1595 | TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, | |
1596 | TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, | |
1597 | TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, | |
1598 | TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, | |
1599 | TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, | |
1600 | TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, | |
1601 | TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE, | |
1602 | TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, | |
1603 | TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, | |
1604 | TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, | |
1605 | TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, | |
1606 | TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, | |
1607 | TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, | |
1608 | TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, | |
1609 | TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, | |
1610 | BITFIELD(43, 3) /* index 918 */, | |
1611 | TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV, | |
1612 | TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH, | |
1613 | BITFIELD(43, 3) /* index 927 */, | |
1614 | CHILD(936), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP, | |
1615 | TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(991), | |
1616 | BITFIELD(31, 2) /* index 936 */, | |
1617 | CHILD(941), CHILD(966), TILEGX_OPC_ILL, TILEGX_OPC_ILL, | |
1618 | BITFIELD(33, 2) /* index 941 */, | |
1619 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(946), | |
1620 | BITFIELD(35, 2) /* index 946 */, | |
1621 | TILEGX_OPC_ILL, CHILD(951), TILEGX_OPC_ILL, TILEGX_OPC_ILL, | |
1622 | BITFIELD(37, 2) /* index 951 */, | |
1623 | TILEGX_OPC_ILL, CHILD(956), TILEGX_OPC_ILL, TILEGX_OPC_ILL, | |
1624 | BITFIELD(39, 2) /* index 956 */, | |
1625 | TILEGX_OPC_ILL, CHILD(961), TILEGX_OPC_ILL, TILEGX_OPC_ILL, | |
1626 | BITFIELD(41, 2) /* index 961 */, | |
1627 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL, | |
1628 | BITFIELD(33, 2) /* index 966 */, | |
1629 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(971), | |
1630 | BITFIELD(35, 2) /* index 971 */, | |
1631 | TILEGX_OPC_ILL, CHILD(976), TILEGX_OPC_ILL, TILEGX_OPC_ILL, | |
1632 | BITFIELD(37, 2) /* index 976 */, | |
1633 | TILEGX_OPC_ILL, CHILD(981), TILEGX_OPC_ILL, TILEGX_OPC_ILL, | |
1634 | BITFIELD(39, 2) /* index 981 */, | |
1635 | TILEGX_OPC_ILL, CHILD(986), TILEGX_OPC_ILL, TILEGX_OPC_ILL, | |
1636 | BITFIELD(41, 2) /* index 986 */, | |
1637 | TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL, | |
1638 | BITFIELD(31, 2) /* index 991 */, | |
1639 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(996), | |
1640 | BITFIELD(33, 2) /* index 996 */, | |
1641 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1001), | |
1642 | BITFIELD(35, 2) /* index 1001 */, | |
1643 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, | |
1644 | TILEGX_OPC_PREFETCH_L1_FAULT, | |
1645 | BITFIELD(43, 3) /* index 1006 */, | |
1646 | CHILD(1015), CHILD(1030), CHILD(1045), CHILD(1060), CHILD(1075), | |
1647 | TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U, | |
1648 | BITFIELD(31, 2) /* index 1015 */, | |
1649 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1020), | |
1650 | BITFIELD(33, 2) /* index 1020 */, | |
1651 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1025), | |
1652 | BITFIELD(35, 2) /* index 1025 */, | |
1653 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH, | |
1654 | BITFIELD(31, 2) /* index 1030 */, | |
1655 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1035), | |
1656 | BITFIELD(33, 2) /* index 1035 */, | |
1657 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1040), | |
1658 | BITFIELD(35, 2) /* index 1040 */, | |
1659 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, | |
1660 | TILEGX_OPC_PREFETCH_L2_FAULT, | |
1661 | BITFIELD(31, 2) /* index 1045 */, | |
1662 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1050), | |
1663 | BITFIELD(33, 2) /* index 1050 */, | |
1664 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1055), | |
1665 | BITFIELD(35, 2) /* index 1055 */, | |
1666 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2, | |
1667 | BITFIELD(31, 2) /* index 1060 */, | |
1668 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1065), | |
1669 | BITFIELD(33, 2) /* index 1065 */, | |
1670 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1070), | |
1671 | BITFIELD(35, 2) /* index 1070 */, | |
1672 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, | |
1673 | TILEGX_OPC_PREFETCH_L3_FAULT, | |
1674 | BITFIELD(31, 2) /* index 1075 */, | |
1675 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1080), | |
1676 | BITFIELD(33, 2) /* index 1080 */, | |
1677 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1085), | |
1678 | BITFIELD(35, 2) /* index 1085 */, | |
1679 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3, | |
1680 | BITFIELD(43, 3) /* index 1090 */, | |
1681 | TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U, | |
1682 | TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF, | |
1683 | BITFIELD(43, 3) /* index 1099 */, | |
1684 | TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1, | |
1685 | TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE, | |
1686 | BITFIELD(49, 4) /* index 1108 */, | |
1687 | TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ, | |
1688 | TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, | |
1689 | TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ, | |
1690 | TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS, | |
1691 | TILEGX_OPC_V2CMPLTU, | |
1692 | BITFIELD(49, 4) /* index 1125 */, | |
1693 | TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L, | |
1694 | TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ, | |
1695 | TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC, | |
1696 | TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, | |
1697 | TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB, | |
1698 | BITFIELD(49, 4) /* index 1142 */, | |
1699 | TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H, | |
1700 | TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC, | |
1701 | TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC, | |
1702 | TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1703 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1704 | BITFIELD(49, 4) /* index 1159 */, | |
1705 | TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI, | |
1706 | TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI, | |
1707 | TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI, | |
1708 | TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1709 | TILEGX_OPC_NONE, | |
1710 | BITFIELD(31, 2) /* index 1176 */, | |
1711 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1712 | CHILD(1181), | |
1713 | BITFIELD(33, 2) /* index 1181 */, | |
1714 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1715 | CHILD(1186), | |
1716 | BITFIELD(35, 2) /* index 1186 */, | |
1717 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1718 | CHILD(1191), | |
1719 | BITFIELD(37, 2) /* index 1191 */, | |
1720 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1721 | CHILD(1196), | |
1722 | BITFIELD(39, 2) /* index 1196 */, | |
1723 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1724 | CHILD(1201), | |
1725 | BITFIELD(41, 2) /* index 1201 */, | |
1726 | TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, | |
1727 | TILEGX_OPC_INFOL, | |
1728 | }; | |
1729 | ||
1730 | static const unsigned short decode_Y0_fsm[178] = | |
1731 | { | |
1732 | BITFIELD(27, 4) /* index 0 */, | |
1733 | CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI, | |
1734 | TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123), | |
1735 | CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168), | |
1736 | CHILD(173), | |
1737 | BITFIELD(6, 2) /* index 17 */, | |
1738 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22), | |
1739 | BITFIELD(8, 2) /* index 22 */, | |
1740 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27), | |
1741 | BITFIELD(10, 2) /* index 27 */, | |
1742 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, | |
1743 | BITFIELD(0, 2) /* index 32 */, | |
1744 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37), | |
1745 | BITFIELD(2, 2) /* index 37 */, | |
1746 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42), | |
1747 | BITFIELD(4, 2) /* index 42 */, | |
1748 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47), | |
1749 | BITFIELD(6, 2) /* index 47 */, | |
1750 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52), | |
1751 | BITFIELD(8, 2) /* index 52 */, | |
1752 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57), | |
1753 | BITFIELD(10, 2) /* index 57 */, | |
1754 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, | |
1755 | BITFIELD(18, 2) /* index 62 */, | |
1756 | TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, | |
1757 | BITFIELD(15, 5) /* index 67 */, | |
1758 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, | |
1759 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, | |
1760 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, | |
1761 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, | |
1762 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, | |
1763 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, | |
1764 | TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, | |
1765 | TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100), | |
1766 | CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1767 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1768 | BITFIELD(12, 3) /* index 100 */, | |
1769 | TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP, | |
1770 | TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT, | |
1771 | TILEGX_OPC_REVBITS, | |
1772 | BITFIELD(12, 3) /* index 109 */, | |
1773 | TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1, | |
1774 | TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1775 | TILEGX_OPC_NONE, | |
1776 | BITFIELD(18, 2) /* index 118 */, | |
1777 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, | |
1778 | BITFIELD(18, 2) /* index 123 */, | |
1779 | TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX, | |
1780 | BITFIELD(18, 2) /* index 128 */, | |
1781 | TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, | |
1782 | BITFIELD(18, 2) /* index 133 */, | |
1783 | TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR, | |
1784 | BITFIELD(12, 2) /* index 138 */, | |
1785 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143), | |
1786 | BITFIELD(14, 2) /* index 143 */, | |
1787 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148), | |
1788 | BITFIELD(16, 2) /* index 148 */, | |
1789 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, | |
1790 | BITFIELD(18, 2) /* index 153 */, | |
1791 | TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU, | |
1792 | BITFIELD(18, 2) /* index 158 */, | |
1793 | TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX, | |
1794 | TILEGX_OPC_SHL3ADDX, | |
1795 | BITFIELD(18, 2) /* index 163 */, | |
1796 | TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS, | |
1797 | TILEGX_OPC_MUL_LU_LU, | |
1798 | BITFIELD(18, 2) /* index 168 */, | |
1799 | TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS, | |
1800 | TILEGX_OPC_MULA_LU_LU, | |
1801 | BITFIELD(18, 2) /* index 173 */, | |
1802 | TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, | |
1803 | }; | |
1804 | ||
1805 | static const unsigned short decode_Y1_fsm[167] = | |
1806 | { | |
1807 | BITFIELD(58, 4) /* index 0 */, | |
1808 | TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI, | |
1809 | TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122), | |
1810 | CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE, | |
1811 | BITFIELD(37, 2) /* index 17 */, | |
1812 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22), | |
1813 | BITFIELD(39, 2) /* index 22 */, | |
1814 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27), | |
1815 | BITFIELD(41, 2) /* index 27 */, | |
1816 | TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI, | |
1817 | BITFIELD(31, 2) /* index 32 */, | |
1818 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37), | |
1819 | BITFIELD(33, 2) /* index 37 */, | |
1820 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42), | |
1821 | BITFIELD(35, 2) /* index 42 */, | |
1822 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47), | |
1823 | BITFIELD(37, 2) /* index 47 */, | |
1824 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52), | |
1825 | BITFIELD(39, 2) /* index 52 */, | |
1826 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57), | |
1827 | BITFIELD(41, 2) /* index 57 */, | |
1828 | TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO, | |
1829 | BITFIELD(49, 2) /* index 62 */, | |
1830 | TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB, | |
1831 | BITFIELD(47, 4) /* index 67 */, | |
1832 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, | |
1833 | TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, | |
1834 | TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, | |
1835 | TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84), | |
1836 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, | |
1837 | BITFIELD(43, 3) /* index 84 */, | |
1838 | CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108), | |
1839 | CHILD(111), CHILD(114), | |
1840 | BITFIELD(46, 1) /* index 93 */, | |
1841 | TILEGX_OPC_NONE, TILEGX_OPC_FNOP, | |
1842 | BITFIELD(46, 1) /* index 96 */, | |
1843 | TILEGX_OPC_NONE, TILEGX_OPC_ILL, | |
1844 | BITFIELD(46, 1) /* index 99 */, | |
1845 | TILEGX_OPC_NONE, TILEGX_OPC_JALRP, | |
1846 | BITFIELD(46, 1) /* index 102 */, | |
1847 | TILEGX_OPC_NONE, TILEGX_OPC_JALR, | |
1848 | BITFIELD(46, 1) /* index 105 */, | |
1849 | TILEGX_OPC_NONE, TILEGX_OPC_JRP, | |
1850 | BITFIELD(46, 1) /* index 108 */, | |
1851 | TILEGX_OPC_NONE, TILEGX_OPC_JR, | |
1852 | BITFIELD(46, 1) /* index 111 */, | |
1853 | TILEGX_OPC_NONE, TILEGX_OPC_LNK, | |
1854 | BITFIELD(46, 1) /* index 114 */, | |
1855 | TILEGX_OPC_NONE, TILEGX_OPC_NOP, | |
1856 | BITFIELD(49, 2) /* index 117 */, | |
1857 | TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU, | |
1858 | BITFIELD(49, 2) /* index 122 */, | |
1859 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, | |
1860 | BITFIELD(49, 2) /* index 127 */, | |
1861 | TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, | |
1862 | BITFIELD(49, 2) /* index 132 */, | |
1863 | TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR, | |
1864 | BITFIELD(43, 2) /* index 137 */, | |
1865 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142), | |
1866 | BITFIELD(45, 2) /* index 142 */, | |
1867 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147), | |
1868 | BITFIELD(47, 2) /* index 147 */, | |
1869 | TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE, | |
1870 | BITFIELD(49, 2) /* index 152 */, | |
1871 | TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU, | |
1872 | BITFIELD(49, 2) /* index 157 */, | |
1873 | TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX, | |
1874 | TILEGX_OPC_SHL3ADDX, | |
1875 | BITFIELD(49, 2) /* index 162 */, | |
1876 | TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, | |
1877 | }; | |
1878 | ||
1879 | static const unsigned short decode_Y2_fsm[118] = | |
1880 | { | |
1881 | BITFIELD(62, 2) /* index 0 */, | |
1882 | TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109), | |
1883 | BITFIELD(55, 3) /* index 5 */, | |
1884 | CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40), | |
1885 | CHILD(43), | |
1886 | BITFIELD(26, 1) /* index 14 */, | |
1887 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1U, | |
1888 | BITFIELD(26, 1) /* index 17 */, | |
1889 | CHILD(20), CHILD(30), | |
1890 | BITFIELD(51, 2) /* index 20 */, | |
1891 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25), | |
1892 | BITFIELD(53, 2) /* index 25 */, | |
1893 | TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, | |
1894 | TILEGX_OPC_PREFETCH_L1_FAULT, | |
1895 | BITFIELD(51, 2) /* index 30 */, | |
1896 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35), | |
1897 | BITFIELD(53, 2) /* index 35 */, | |
1898 | TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH, | |
1899 | BITFIELD(26, 1) /* index 40 */, | |
1900 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2U, | |
1901 | BITFIELD(26, 1) /* index 43 */, | |
1902 | CHILD(46), CHILD(56), | |
1903 | BITFIELD(51, 2) /* index 46 */, | |
1904 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51), | |
1905 | BITFIELD(53, 2) /* index 51 */, | |
1906 | TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, | |
1907 | TILEGX_OPC_PREFETCH_L2_FAULT, | |
1908 | BITFIELD(51, 2) /* index 56 */, | |
1909 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61), | |
1910 | BITFIELD(53, 2) /* index 61 */, | |
1911 | TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2, | |
1912 | BITFIELD(56, 2) /* index 66 */, | |
1913 | CHILD(71), CHILD(74), CHILD(90), CHILD(93), | |
1914 | BITFIELD(26, 1) /* index 71 */, | |
1915 | TILEGX_OPC_NONE, TILEGX_OPC_LD4S, | |
1916 | BITFIELD(26, 1) /* index 74 */, | |
1917 | TILEGX_OPC_NONE, CHILD(77), | |
1918 | BITFIELD(51, 2) /* index 77 */, | |
1919 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82), | |
1920 | BITFIELD(53, 2) /* index 82 */, | |
1921 | TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87), | |
1922 | BITFIELD(55, 1) /* index 87 */, | |
1923 | TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT, | |
1924 | BITFIELD(26, 1) /* index 90 */, | |
1925 | TILEGX_OPC_LD4U, TILEGX_OPC_LD, | |
1926 | BITFIELD(26, 1) /* index 93 */, | |
1927 | CHILD(96), TILEGX_OPC_LD, | |
1928 | BITFIELD(51, 2) /* index 96 */, | |
1929 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101), | |
1930 | BITFIELD(53, 2) /* index 101 */, | |
1931 | TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106), | |
1932 | BITFIELD(55, 1) /* index 106 */, | |
1933 | TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3, | |
1934 | BITFIELD(26, 1) /* index 109 */, | |
1935 | CHILD(112), CHILD(115), | |
1936 | BITFIELD(57, 1) /* index 112 */, | |
1937 | TILEGX_OPC_ST1, TILEGX_OPC_ST4, | |
1938 | BITFIELD(57, 1) /* index 115 */, | |
1939 | TILEGX_OPC_ST2, TILEGX_OPC_ST, | |
1940 | }; | |
1941 | ||
1942 | #undef BITFIELD | |
1943 | #undef CHILD | |
1944 | const unsigned short * const | |
1945 | tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] = | |
1946 | { | |
1947 | decode_X0_fsm, | |
1948 | decode_X1_fsm, | |
1949 | decode_Y0_fsm, | |
1950 | decode_Y1_fsm, | |
1951 | decode_Y2_fsm | |
1952 | }; | |
1953 | const struct tilegx_operand tilegx_operands[35] = | |
1954 | { | |
1955 | { | |
1956 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0), | |
1957 | 8, 1, 0, 0, 0, 0, | |
1958 | create_Imm8_X0, get_Imm8_X0 | |
1959 | }, | |
1960 | { | |
1961 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1), | |
1962 | 8, 1, 0, 0, 0, 0, | |
1963 | create_Imm8_X1, get_Imm8_X1 | |
1964 | }, | |
1965 | { | |
1966 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0), | |
1967 | 8, 1, 0, 0, 0, 0, | |
1968 | create_Imm8_Y0, get_Imm8_Y0 | |
1969 | }, | |
1970 | { | |
1971 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1), | |
1972 | 8, 1, 0, 0, 0, 0, | |
1973 | create_Imm8_Y1, get_Imm8_Y1 | |
1974 | }, | |
1975 | { | |
1976 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST), | |
1977 | 16, 1, 0, 0, 0, 0, | |
1978 | create_Imm16_X0, get_Imm16_X0 | |
1979 | }, | |
1980 | { | |
1981 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST), | |
1982 | 16, 1, 0, 0, 0, 0, | |
1983 | create_Imm16_X1, get_Imm16_X1 | |
1984 | }, | |
1985 | { | |
1986 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
1987 | 6, 0, 0, 1, 0, 0, | |
1988 | create_Dest_X0, get_Dest_X0 | |
1989 | }, | |
1990 | { | |
1991 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
1992 | 6, 0, 1, 0, 0, 0, | |
1993 | create_SrcA_X0, get_SrcA_X0 | |
1994 | }, | |
1995 | { | |
1996 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
1997 | 6, 0, 0, 1, 0, 0, | |
1998 | create_Dest_X1, get_Dest_X1 | |
1999 | }, | |
2000 | { | |
2001 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2002 | 6, 0, 1, 0, 0, 0, | |
2003 | create_SrcA_X1, get_SrcA_X1 | |
2004 | }, | |
2005 | { | |
2006 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2007 | 6, 0, 0, 1, 0, 0, | |
2008 | create_Dest_Y0, get_Dest_Y0 | |
2009 | }, | |
2010 | { | |
2011 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2012 | 6, 0, 1, 0, 0, 0, | |
2013 | create_SrcA_Y0, get_SrcA_Y0 | |
2014 | }, | |
2015 | { | |
2016 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2017 | 6, 0, 0, 1, 0, 0, | |
2018 | create_Dest_Y1, get_Dest_Y1 | |
2019 | }, | |
2020 | { | |
2021 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2022 | 6, 0, 1, 0, 0, 0, | |
2023 | create_SrcA_Y1, get_SrcA_Y1 | |
2024 | }, | |
2025 | { | |
2026 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2027 | 6, 0, 1, 0, 0, 0, | |
2028 | create_SrcA_Y2, get_SrcA_Y2 | |
2029 | }, | |
2030 | { | |
2031 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2032 | 6, 0, 1, 1, 0, 0, | |
2033 | create_SrcA_X1, get_SrcA_X1 | |
2034 | }, | |
2035 | { | |
2036 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2037 | 6, 0, 1, 0, 0, 0, | |
2038 | create_SrcB_X0, get_SrcB_X0 | |
2039 | }, | |
2040 | { | |
2041 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2042 | 6, 0, 1, 0, 0, 0, | |
2043 | create_SrcB_X1, get_SrcB_X1 | |
2044 | }, | |
2045 | { | |
2046 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2047 | 6, 0, 1, 0, 0, 0, | |
2048 | create_SrcB_Y0, get_SrcB_Y0 | |
2049 | }, | |
2050 | { | |
2051 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2052 | 6, 0, 1, 0, 0, 0, | |
2053 | create_SrcB_Y1, get_SrcB_Y1 | |
2054 | }, | |
2055 | { | |
2056 | TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1), | |
2057 | 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, | |
2058 | create_BrOff_X1, get_BrOff_X1 | |
2059 | }, | |
2060 | { | |
eb7c792d | 2061 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0), |
18aecc2b CM |
2062 | 6, 0, 0, 0, 0, 0, |
2063 | create_BFStart_X0, get_BFStart_X0 | |
2064 | }, | |
2065 | { | |
eb7c792d | 2066 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0), |
18aecc2b CM |
2067 | 6, 0, 0, 0, 0, 0, |
2068 | create_BFEnd_X0, get_BFEnd_X0 | |
2069 | }, | |
2070 | { | |
2071 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2072 | 6, 0, 1, 1, 0, 0, | |
2073 | create_Dest_X0, get_Dest_X0 | |
2074 | }, | |
2075 | { | |
2076 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2077 | 6, 0, 1, 1, 0, 0, | |
2078 | create_Dest_Y0, get_Dest_Y0 | |
2079 | }, | |
2080 | { | |
2081 | TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1), | |
2082 | 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, | |
2083 | create_JumpOff_X1, get_JumpOff_X1 | |
2084 | }, | |
2085 | { | |
2086 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2087 | 6, 0, 0, 1, 0, 0, | |
2088 | create_SrcBDest_Y2, get_SrcBDest_Y2 | |
2089 | }, | |
2090 | { | |
2091 | TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1), | |
2092 | 14, 0, 0, 0, 0, 0, | |
2093 | create_MF_Imm14_X1, get_MF_Imm14_X1 | |
2094 | }, | |
2095 | { | |
2096 | TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1), | |
2097 | 14, 0, 0, 0, 0, 0, | |
2098 | create_MT_Imm14_X1, get_MT_Imm14_X1 | |
2099 | }, | |
2100 | { | |
2101 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0), | |
2102 | 6, 0, 0, 0, 0, 0, | |
2103 | create_ShAmt_X0, get_ShAmt_X0 | |
2104 | }, | |
2105 | { | |
2106 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1), | |
2107 | 6, 0, 0, 0, 0, 0, | |
2108 | create_ShAmt_X1, get_ShAmt_X1 | |
2109 | }, | |
2110 | { | |
2111 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0), | |
2112 | 6, 0, 0, 0, 0, 0, | |
2113 | create_ShAmt_Y0, get_ShAmt_Y0 | |
2114 | }, | |
2115 | { | |
2116 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1), | |
2117 | 6, 0, 0, 0, 0, 0, | |
2118 | create_ShAmt_Y1, get_ShAmt_Y1 | |
2119 | }, | |
2120 | { | |
2121 | TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE), | |
2122 | 6, 0, 1, 0, 0, 0, | |
2123 | create_SrcBDest_Y2, get_SrcBDest_Y2 | |
2124 | }, | |
2125 | { | |
2126 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1), | |
2127 | 8, 1, 0, 0, 0, 0, | |
2128 | create_Dest_Imm8_X1, get_Dest_Imm8_X1 | |
2129 | } | |
2130 | }; | |
2131 | ||
2132 | ||
2133 | ||
2134 | ||
2135 | /* Given a set of bundle bits and the lookup FSM for a specific pipe, | |
2136 | * returns which instruction the bundle contains in that pipe. | |
2137 | */ | |
2138 | static const struct tilegx_opcode * | |
2139 | find_opcode(tilegx_bundle_bits bits, const unsigned short *table) | |
2140 | { | |
2141 | int index = 0; | |
2142 | ||
2143 | while (1) | |
2144 | { | |
2145 | unsigned short bitspec = table[index]; | |
2146 | unsigned int bitfield = | |
2147 | ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6); | |
2148 | ||
2149 | unsigned short next = table[index + 1 + bitfield]; | |
2150 | if (next <= TILEGX_OPC_NONE) | |
2151 | return &tilegx_opcodes[next]; | |
2152 | ||
2153 | index = next - TILEGX_OPC_NONE; | |
2154 | } | |
2155 | } | |
2156 | ||
2157 | ||
2158 | int | |
2159 | parse_insn_tilegx(tilegx_bundle_bits bits, | |
2160 | unsigned long long pc, | |
2161 | struct tilegx_decoded_instruction | |
2162 | decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]) | |
2163 | { | |
2164 | int num_instructions = 0; | |
2165 | int pipe; | |
2166 | ||
2167 | int min_pipe, max_pipe; | |
2168 | if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0) | |
2169 | { | |
2170 | min_pipe = TILEGX_PIPELINE_X0; | |
2171 | max_pipe = TILEGX_PIPELINE_X1; | |
2172 | } | |
2173 | else | |
2174 | { | |
2175 | min_pipe = TILEGX_PIPELINE_Y0; | |
2176 | max_pipe = TILEGX_PIPELINE_Y2; | |
2177 | } | |
2178 | ||
2179 | /* For each pipe, find an instruction that fits. */ | |
2180 | for (pipe = min_pipe; pipe <= max_pipe; pipe++) | |
2181 | { | |
2182 | const struct tilegx_opcode *opc; | |
2183 | struct tilegx_decoded_instruction *d; | |
2184 | int i; | |
2185 | ||
2186 | d = &decoded[num_instructions++]; | |
2187 | opc = find_opcode (bits, tilegx_bundle_decoder_fsms[pipe]); | |
2188 | d->opcode = opc; | |
2189 | ||
2190 | /* Decode each operand, sign extending, etc. as appropriate. */ | |
2191 | for (i = 0; i < opc->num_operands; i++) | |
2192 | { | |
2193 | const struct tilegx_operand *op = | |
2194 | &tilegx_operands[opc->operands[pipe][i]]; | |
2195 | int raw_opval = op->extract (bits); | |
2196 | long long opval; | |
2197 | ||
2198 | if (op->is_signed) | |
2199 | { | |
2200 | /* Sign-extend the operand. */ | |
2201 | int shift = (int)((sizeof(int) * 8) - op->num_bits); | |
2202 | raw_opval = (raw_opval << shift) >> shift; | |
2203 | } | |
2204 | ||
2205 | /* Adjust PC-relative scaled branch offsets. */ | |
2206 | if (op->type == TILEGX_OP_TYPE_ADDRESS) | |
2207 | opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc; | |
2208 | else | |
2209 | opval = raw_opval; | |
2210 | ||
2211 | /* Record the final value. */ | |
2212 | d->operands[i] = op; | |
2213 | d->operand_values[i] = opval; | |
2214 | } | |
2215 | } | |
2216 | ||
2217 | return num_instructions; | |
2218 | } |