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867e359b CM |
1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * Support the cycle counter clocksource and tile timer clock event device. | |
15 | */ | |
16 | ||
17 | #include <linux/time.h> | |
18 | #include <linux/timex.h> | |
19 | #include <linux/clocksource.h> | |
20 | #include <linux/clockchips.h> | |
21 | #include <linux/hardirq.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/delay.h> | |
28d71741 | 25 | #include <linux/module.h> |
4a556f4f | 26 | #include <linux/timekeeper_internal.h> |
867e359b | 27 | #include <asm/irq_regs.h> |
0707ad30 | 28 | #include <asm/traps.h> |
4a556f4f | 29 | #include <asm/vdso.h> |
867e359b CM |
30 | #include <hv/hypervisor.h> |
31 | #include <arch/interrupts.h> | |
32 | #include <arch/spr_def.h> | |
33 | ||
34 | ||
35 | /* | |
36 | * Define the cycle counter clock source. | |
37 | */ | |
38 | ||
39 | /* How many cycles per second we are running at. */ | |
40 | static cycles_t cycles_per_sec __write_once; | |
41 | ||
0707ad30 | 42 | cycles_t get_clock_rate(void) |
867e359b CM |
43 | { |
44 | return cycles_per_sec; | |
45 | } | |
46 | ||
47 | #if CHIP_HAS_SPLIT_CYCLE() | |
0707ad30 | 48 | cycles_t get_cycles(void) |
867e359b CM |
49 | { |
50 | unsigned int high = __insn_mfspr(SPR_CYCLE_HIGH); | |
51 | unsigned int low = __insn_mfspr(SPR_CYCLE_LOW); | |
52 | unsigned int high2 = __insn_mfspr(SPR_CYCLE_HIGH); | |
53 | ||
54 | while (unlikely(high != high2)) { | |
55 | low = __insn_mfspr(SPR_CYCLE_LOW); | |
56 | high = high2; | |
57 | high2 = __insn_mfspr(SPR_CYCLE_HIGH); | |
58 | } | |
59 | ||
60 | return (((cycles_t)high) << 32) | low; | |
61 | } | |
28d71741 | 62 | EXPORT_SYMBOL(get_cycles); |
867e359b CM |
63 | #endif |
64 | ||
749dc6f2 CM |
65 | /* |
66 | * We use a relatively small shift value so that sched_clock() | |
67 | * won't wrap around very often. | |
68 | */ | |
69 | #define SCHED_CLOCK_SHIFT 10 | |
70 | ||
71 | static unsigned long sched_clock_mult __write_once; | |
72 | ||
0707ad30 | 73 | static cycles_t clocksource_get_cycles(struct clocksource *cs) |
867e359b CM |
74 | { |
75 | return get_cycles(); | |
76 | } | |
77 | ||
78 | static struct clocksource cycle_counter_cs = { | |
79 | .name = "cycle counter", | |
80 | .rating = 300, | |
81 | .read = clocksource_get_cycles, | |
82 | .mask = CLOCKSOURCE_MASK(64), | |
83 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
84 | }; | |
85 | ||
86 | /* | |
87 | * Called very early from setup_arch() to set cycles_per_sec. | |
88 | * We initialize it early so we can use it to set up loops_per_jiffy. | |
89 | */ | |
90 | void __init setup_clock(void) | |
91 | { | |
92 | cycles_per_sec = hv_sysconf(HV_SYSCONF_CPU_SPEED); | |
749dc6f2 CM |
93 | sched_clock_mult = |
94 | clocksource_hz2mult(cycles_per_sec, SCHED_CLOCK_SHIFT); | |
867e359b CM |
95 | } |
96 | ||
97 | void __init calibrate_delay(void) | |
98 | { | |
99 | loops_per_jiffy = get_clock_rate() / HZ; | |
100 | pr_info("Clock rate yields %lu.%02lu BogoMIPS (lpj=%lu)\n", | |
f4743673 JP |
101 | loops_per_jiffy / (500000 / HZ), |
102 | (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy); | |
867e359b CM |
103 | } |
104 | ||
105 | /* Called fairly late in init/main.c, but before we go smp. */ | |
106 | void __init time_init(void) | |
107 | { | |
108 | /* Initialize and register the clock source. */ | |
9f14517b | 109 | clocksource_register_hz(&cycle_counter_cs, cycles_per_sec); |
867e359b CM |
110 | |
111 | /* Start up the tile-timer interrupt source on the boot cpu. */ | |
112 | setup_tile_timer(); | |
113 | } | |
114 | ||
867e359b CM |
115 | /* |
116 | * Define the tile timer clock event device. The timer is driven by | |
117 | * the TILE_TIMER_CONTROL register, which consists of a 31-bit down | |
118 | * counter, plus bit 31, which signifies that the counter has wrapped | |
119 | * from zero to (2**31) - 1. The INT_TILE_TIMER interrupt will be | |
120 | * raised as long as bit 31 is set. | |
749dc6f2 CM |
121 | * |
122 | * The TILE_MINSEC value represents the largest range of real-time | |
123 | * we can possibly cover with the timer, based on MAX_TICK combined | |
124 | * with the slowest reasonable clock rate we might run at. | |
867e359b CM |
125 | */ |
126 | ||
127 | #define MAX_TICK 0x7fffffff /* we have 31 bits of countdown timer */ | |
749dc6f2 | 128 | #define TILE_MINSEC 5 /* timer covers no more than 5 seconds */ |
867e359b CM |
129 | |
130 | static int tile_timer_set_next_event(unsigned long ticks, | |
131 | struct clock_event_device *evt) | |
132 | { | |
133 | BUG_ON(ticks > MAX_TICK); | |
134 | __insn_mtspr(SPR_TILE_TIMER_CONTROL, ticks); | |
5d966115 | 135 | arch_local_irq_unmask_now(INT_TILE_TIMER); |
867e359b CM |
136 | return 0; |
137 | } | |
138 | ||
139 | /* | |
140 | * Whenever anyone tries to change modes, we just mask interrupts | |
141 | * and wait for the next event to get set. | |
142 | */ | |
38715df2 | 143 | static int tile_timer_shutdown(struct clock_event_device *evt) |
867e359b | 144 | { |
5d966115 | 145 | arch_local_irq_mask_now(INT_TILE_TIMER); |
38715df2 | 146 | return 0; |
867e359b CM |
147 | } |
148 | ||
149 | /* | |
150 | * Set min_delta_ns to 1 microsecond, since it takes about | |
151 | * that long to fire the interrupt. | |
152 | */ | |
153 | static DEFINE_PER_CPU(struct clock_event_device, tile_timer) = { | |
154 | .name = "tile timer", | |
155 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
156 | .min_delta_ns = 1000, | |
157 | .rating = 100, | |
158 | .irq = -1, | |
159 | .set_next_event = tile_timer_set_next_event, | |
38715df2 VK |
160 | .set_state_shutdown = tile_timer_shutdown, |
161 | .set_state_oneshot = tile_timer_shutdown, | |
162 | .tick_resume = tile_timer_shutdown, | |
867e359b CM |
163 | }; |
164 | ||
18f894c1 | 165 | void setup_tile_timer(void) |
867e359b | 166 | { |
b4f50191 | 167 | struct clock_event_device *evt = this_cpu_ptr(&tile_timer); |
867e359b CM |
168 | |
169 | /* Fill in fields that are speed-specific. */ | |
170 | clockevents_calc_mult_shift(evt, cycles_per_sec, TILE_MINSEC); | |
171 | evt->max_delta_ns = clockevent_delta2ns(MAX_TICK, evt); | |
172 | ||
173 | /* Mark as being for this cpu only. */ | |
174 | evt->cpumask = cpumask_of(smp_processor_id()); | |
175 | ||
176 | /* Start out with timer not firing. */ | |
5d966115 | 177 | arch_local_irq_mask_now(INT_TILE_TIMER); |
867e359b CM |
178 | |
179 | /* Register tile timer. */ | |
180 | clockevents_register_device(evt); | |
181 | } | |
182 | ||
183 | /* Called from the interrupt vector. */ | |
184 | void do_timer_interrupt(struct pt_regs *regs, int fault_num) | |
185 | { | |
186 | struct pt_regs *old_regs = set_irq_regs(regs); | |
b4f50191 | 187 | struct clock_event_device *evt = this_cpu_ptr(&tile_timer); |
867e359b CM |
188 | |
189 | /* | |
190 | * Mask the timer interrupt here, since we are a oneshot timer | |
191 | * and there are now by definition no events pending. | |
192 | */ | |
5d966115 | 193 | arch_local_irq_mask(INT_TILE_TIMER); |
867e359b CM |
194 | |
195 | /* Track time spent here in an interrupt context */ | |
196 | irq_enter(); | |
197 | ||
198 | /* Track interrupt count. */ | |
b4f50191 | 199 | __this_cpu_inc(irq_stat.irq_timer_count); |
867e359b CM |
200 | |
201 | /* Call the generic timer handler */ | |
202 | evt->event_handler(evt); | |
203 | ||
204 | /* | |
205 | * Track time spent against the current process again and | |
206 | * process any softirqs if they are waiting. | |
207 | */ | |
208 | irq_exit(); | |
209 | ||
210 | set_irq_regs(old_regs); | |
211 | } | |
212 | ||
213 | /* | |
214 | * Scheduler clock - returns current time in nanosec units. | |
215 | * Note that with LOCKDEP, this is called during lockdep_init(), and | |
216 | * we will claim that sched_clock() is zero for a little while, until | |
217 | * we run setup_clock(), above. | |
218 | */ | |
219 | unsigned long long sched_clock(void) | |
220 | { | |
221 | return clocksource_cyc2ns(get_cycles(), | |
749dc6f2 | 222 | sched_clock_mult, SCHED_CLOCK_SHIFT); |
867e359b CM |
223 | } |
224 | ||
225 | int setup_profiling_timer(unsigned int multiplier) | |
226 | { | |
227 | return -EINVAL; | |
228 | } | |
13371731 CM |
229 | |
230 | /* | |
231 | * Use the tile timer to convert nsecs to core clock cycles, relying | |
232 | * on it having the same frequency as SPR_CYCLE. | |
233 | */ | |
234 | cycles_t ns2cycles(unsigned long nsecs) | |
235 | { | |
39e8202b HA |
236 | /* |
237 | * We do not have to disable preemption here as each core has the same | |
238 | * clock frequency. | |
239 | */ | |
b4f50191 | 240 | struct clock_event_device *dev = raw_cpu_ptr(&tile_timer); |
767f3021 HA |
241 | |
242 | /* | |
243 | * as in clocksource.h and x86's timer.h, we split the calculation | |
244 | * into 2 parts to avoid unecessary overflow of the intermediate | |
245 | * value. This will not lead to any loss of precision. | |
246 | */ | |
247 | u64 quot = (u64)nsecs >> dev->shift; | |
248 | u64 rem = (u64)nsecs & ((1ULL << dev->shift) - 1); | |
249 | return quot * dev->mult + ((rem * dev->mult) >> dev->shift); | |
13371731 | 250 | } |
4a556f4f CM |
251 | |
252 | void update_vsyscall_tz(void) | |
253 | { | |
94fb1afb | 254 | write_seqcount_begin(&vdso_data->tz_seq); |
4a556f4f CM |
255 | vdso_data->tz_minuteswest = sys_tz.tz_minuteswest; |
256 | vdso_data->tz_dsttime = sys_tz.tz_dsttime; | |
94fb1afb | 257 | write_seqcount_end(&vdso_data->tz_seq); |
4a556f4f CM |
258 | } |
259 | ||
260 | void update_vsyscall(struct timekeeper *tk) | |
261 | { | |
876e7881 | 262 | if (tk->tkr_mono.clock != &cycle_counter_cs) |
4a556f4f CM |
263 | return; |
264 | ||
94fb1afb CM |
265 | write_seqcount_begin(&vdso_data->tb_seq); |
266 | ||
876e7881 PZ |
267 | vdso_data->cycle_last = tk->tkr_mono.cycle_last; |
268 | vdso_data->mask = tk->tkr_mono.mask; | |
269 | vdso_data->mult = tk->tkr_mono.mult; | |
270 | vdso_data->shift = tk->tkr_mono.shift; | |
78410af5 CM |
271 | |
272 | vdso_data->wall_time_sec = tk->xtime_sec; | |
876e7881 | 273 | vdso_data->wall_time_snsec = tk->tkr_mono.xtime_nsec; |
78410af5 CM |
274 | |
275 | vdso_data->monotonic_time_sec = tk->xtime_sec | |
276 | + tk->wall_to_monotonic.tv_sec; | |
876e7881 | 277 | vdso_data->monotonic_time_snsec = tk->tkr_mono.xtime_nsec |
78410af5 | 278 | + ((u64)tk->wall_to_monotonic.tv_nsec |
876e7881 | 279 | << tk->tkr_mono.shift); |
78410af5 | 280 | while (vdso_data->monotonic_time_snsec >= |
876e7881 | 281 | (((u64)NSEC_PER_SEC) << tk->tkr_mono.shift)) { |
78410af5 | 282 | vdso_data->monotonic_time_snsec -= |
876e7881 | 283 | ((u64)NSEC_PER_SEC) << tk->tkr_mono.shift; |
78410af5 CM |
284 | vdso_data->monotonic_time_sec++; |
285 | } | |
286 | ||
287 | vdso_data->wall_time_coarse_sec = tk->xtime_sec; | |
876e7881 PZ |
288 | vdso_data->wall_time_coarse_nsec = (long)(tk->tkr_mono.xtime_nsec >> |
289 | tk->tkr_mono.shift); | |
78410af5 CM |
290 | |
291 | vdso_data->monotonic_time_coarse_sec = | |
292 | vdso_data->wall_time_coarse_sec + tk->wall_to_monotonic.tv_sec; | |
293 | vdso_data->monotonic_time_coarse_nsec = | |
294 | vdso_data->wall_time_coarse_nsec + tk->wall_to_monotonic.tv_nsec; | |
295 | ||
296 | while (vdso_data->monotonic_time_coarse_nsec >= NSEC_PER_SEC) { | |
297 | vdso_data->monotonic_time_coarse_nsec -= NSEC_PER_SEC; | |
298 | vdso_data->monotonic_time_coarse_sec++; | |
299 | } | |
94fb1afb CM |
300 | |
301 | write_seqcount_end(&vdso_data->tb_seq); | |
4a556f4f | 302 | } |