[deliverable/linux.git] / arch / tile / mm / homecache.c

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 *
 * This code maintains the "home" for each page in the system.
 */

#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/bootmem.h>
#include <linux/rmap.h>
#include <linux/pagemap.h>
#include <linux/mutex.h>
#include <linux/interrupt.h>
#include <linux/sysctl.h>
#include <linux/pagevec.h>
#include <linux/ptrace.h>
#include <linux/timex.h>
#include <linux/cache.h>
#include <linux/smp.h>
#include <linux/module.h>
#include <linux/hugetlb.h>

#include <asm/page.h>
#include <asm/sections.h>
#include <asm/tlbflush.h>
#include <asm/pgalloc.h>
#include <asm/homecache.h>

#include <arch/sim.h>

#include "migrate.h"


#if CHIP_HAS_COHERENT_LOCAL_CACHE()

/*
 * The noallocl2 option suppresses all use of the L2 cache to cache
 * locally from a remote home.  There's no point in using it if we
 * don't have coherent local caching, though.
 */
static int __write_once noallocl2;
static int __init set_noallocl2(char *str)
{
	noallocl2 = 1;
	return 0;
}
early_param("noallocl2", set_noallocl2);

#else

#define noallocl2 0

#endif


/*
 * Update the irq_stat for cpus that we are going to interrupt
 * with TLB or cache flushes.  Also handle removing dataplane cpus
 * from the TLB flush set, and setting dataplane_tlb_state instead.
 */
static void hv_flush_update(const struct cpumask *cache_cpumask,
			    struct cpumask *tlb_cpumask,
			    unsigned long tlb_va, unsigned long tlb_length,
			    HV_Remote_ASID *asids, int asidcount)
{
	struct cpumask mask;
	int i, cpu;

	cpumask_clear(&mask);
	if (cache_cpumask)
		cpumask_or(&mask, &mask, cache_cpumask);
	if (tlb_cpumask && tlb_length) {
		cpumask_or(&mask, &mask, tlb_cpumask);
	}

	for (i = 0; i < asidcount; ++i)
		cpumask_set_cpu(asids[i].y * smp_width + asids[i].x, &mask);

	/*
	 * Don't bother to update atomically; losing a count
	 * here is not that critical.
	 */
	for_each_cpu(cpu, &mask)
		++per_cpu(irq_stat, cpu).irq_hv_flush_count;
}

/*
 * This wrapper function around hv_flush_remote() does several things:
 *
 *  - Provides a return value error-checking panic path, since
 *    there's never any good reason for hv_flush_remote() to fail.
 *  - Accepts a 32-bit PFN rather than a 64-bit PA, which generally
 *    is the type that Linux wants to pass around anyway.
 *  - Canonicalizes that lengths of zero make cpumasks NULL.
 *  - Handles deferring TLB flushes for dataplane tiles.
 *  - Tracks remote interrupts in the per-cpu irq_cpustat_t.
 *
 * Note that we have to wait until the cache flush completes before
 * updating the per-cpu last_cache_flush word, since otherwise another
 * concurrent flush can race, conclude the flush has already
 * completed, and start to use the page while it's still dirty
 * remotely (running concurrently with the actual evict, presumably).
 */
void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
		  const struct cpumask *cache_cpumask_orig,
		  HV_VirtAddr tlb_va, unsigned long tlb_length,
		  unsigned long tlb_pgsize,
		  const struct cpumask *tlb_cpumask_orig,
		  HV_Remote_ASID *asids, int asidcount)
{
	int rc;
	struct cpumask cache_cpumask_copy, tlb_cpumask_copy;
	struct cpumask *cache_cpumask, *tlb_cpumask;
	HV_PhysAddr cache_pa;
	char cache_buf[NR_CPUS*5], tlb_buf[NR_CPUS*5];

	mb();   /* provided just to simplify "magic hypervisor" mode */

	/*
	 * Canonicalize and copy the cpumasks.
	 */
	if (cache_cpumask_orig && cache_control) {
		cpumask_copy(&cache_cpumask_copy, cache_cpumask_orig);
		cache_cpumask = &cache_cpumask_copy;
	} else {
		cpumask_clear(&cache_cpumask_copy);
		cache_cpumask = NULL;
	}
	if (cache_cpumask == NULL)
		cache_control = 0;
	if (tlb_cpumask_orig && tlb_length) {
		cpumask_copy(&tlb_cpumask_copy, tlb_cpumask_orig);
		tlb_cpumask = &tlb_cpumask_copy;
	} else {
		cpumask_clear(&tlb_cpumask_copy);
		tlb_cpumask = NULL;
	}

	hv_flush_update(cache_cpumask, tlb_cpumask, tlb_va, tlb_length,
			asids, asidcount);
	cache_pa = (HV_PhysAddr)cache_pfn << PAGE_SHIFT;
	rc = hv_flush_remote(cache_pa, cache_control,
			     cpumask_bits(cache_cpumask),
			     tlb_va, tlb_length, tlb_pgsize,
			     cpumask_bits(tlb_cpumask),
			     asids, asidcount);
	if (rc == 0)
		return;
	cpumask_scnprintf(cache_buf, sizeof(cache_buf), &cache_cpumask_copy);
	cpumask_scnprintf(tlb_buf, sizeof(tlb_buf), &tlb_cpumask_copy);

	pr_err("hv_flush_remote(%#llx, %#lx, %p [%s],"
	       " %#lx, %#lx, %#lx, %p [%s], %p, %d) = %d\n",
	       cache_pa, cache_control, cache_cpumask, cache_buf,
	       (unsigned long)tlb_va, tlb_length, tlb_pgsize,
	       tlb_cpumask, tlb_buf,
	       asids, asidcount, rc);
	panic("Unsafe to continue.");
}

static void homecache_finv_page_va(void* va, int home)
{
	int cpu = get_cpu();
	if (home == cpu) {
		finv_buffer_local(va, PAGE_SIZE);
	} else if (home == PAGE_HOME_HASH) {
		finv_buffer_remote(va, PAGE_SIZE, 1);
	} else {
		BUG_ON(home < 0 || home >= NR_CPUS);
		finv_buffer_remote(va, PAGE_SIZE, 0);
	}
	put_cpu();
}

void homecache_finv_map_page(struct page *page, int home)
{
	unsigned long flags;
	unsigned long va;
	pte_t *ptep;
	pte_t pte;

	if (home == PAGE_HOME_UNCACHED)
		return;
	local_irq_save(flags);
#ifdef CONFIG_HIGHMEM
	va = __fix_to_virt(FIX_KMAP_BEGIN + kmap_atomic_idx_push() +
			   (KM_TYPE_NR * smp_processor_id()));
#else
	va = __fix_to_virt(FIX_HOMECACHE_BEGIN + smp_processor_id());
#endif
	ptep = virt_to_pte(NULL, (unsigned long)va);
	pte = pfn_pte(page_to_pfn(page), PAGE_KERNEL);
	__set_pte(ptep, pte_set_home(pte, home));
	homecache_finv_page_va((void *)va, home);
	__pte_clear(ptep);
	hv_flush_page(va, PAGE_SIZE);
#ifdef CONFIG_HIGHMEM
	kmap_atomic_idx_pop();
#endif
	local_irq_restore(flags);
}

static void homecache_finv_page_home(struct page *page, int home)
{
	if (!PageHighMem(page) && home == page_home(page))
		homecache_finv_page_va(page_address(page), home);
	else
		homecache_finv_map_page(page, home);
}

static inline bool incoherent_home(int home)
{
	return home == PAGE_HOME_IMMUTABLE || home == PAGE_HOME_INCOHERENT;
}

static void homecache_finv_page_internal(struct page *page, int force_map)
{
	int home = page_home(page);
	if (home == PAGE_HOME_UNCACHED)
		return;
	if (incoherent_home(home)) {
		int cpu;
		for_each_cpu(cpu, &cpu_cacheable_map)
			homecache_finv_map_page(page, cpu);
	} else if (force_map) {
		/* Force if, e.g., the normal mapping is migrating. */
		homecache_finv_map_page(page, home);
	} else {
		homecache_finv_page_home(page, home);
	}
	sim_validate_lines_evicted(PFN_PHYS(page_to_pfn(page)), PAGE_SIZE);
}

void homecache_finv_page(struct page *page)
{
	homecache_finv_page_internal(page, 0);
}

void homecache_evict(const struct cpumask *mask)
{
	flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
}

/* Report the home corresponding to a given PTE. */
static int pte_to_home(pte_t pte)
{
	if (hv_pte_get_nc(pte))
		return PAGE_HOME_IMMUTABLE;
	switch (hv_pte_get_mode(pte)) {
	case HV_PTE_MODE_CACHE_TILE_L3:
		return get_remote_cache_cpu(pte);
	case HV_PTE_MODE_CACHE_NO_L3:
		return PAGE_HOME_INCOHERENT;
	case HV_PTE_MODE_UNCACHED:
		return PAGE_HOME_UNCACHED;
#if CHIP_HAS_CBOX_HOME_MAP()
	case HV_PTE_MODE_CACHE_HASH_L3:
		return PAGE_HOME_HASH;
#endif
	}
	panic("Bad PTE %#llx\n", pte.val);
}

/* Update the home of a PTE if necessary (can also be used for a pgprot_t). */
pte_t pte_set_home(pte_t pte, int home)
{
	/* Check for non-linear file mapping "PTEs" and pass them through. */
	if (pte_file(pte))
		return pte;

#if CHIP_HAS_MMIO()
	/* Check for MMIO mappings and pass them through. */
	if (hv_pte_get_mode(pte) == HV_PTE_MODE_MMIO)
		return pte;
#endif


	/*
	 * Only immutable pages get NC mappings.  If we have a
	 * non-coherent PTE, but the underlying page is not
	 * immutable, it's likely the result of a forced
	 * caching setting running up against ptrace setting
	 * the page to be writable underneath.  In this case,
	 * just keep the PTE coherent.
	 */
	if (hv_pte_get_nc(pte) && home != PAGE_HOME_IMMUTABLE) {
		pte = hv_pte_clear_nc(pte);
		pr_err("non-immutable page incoherently referenced: %#llx\n",
		       pte.val);
	}

	switch (home) {

	case PAGE_HOME_UNCACHED:
		pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
		break;

	case PAGE_HOME_INCOHERENT:
		pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
		break;

	case PAGE_HOME_IMMUTABLE:
		/*
		 * We could home this page anywhere, since it's immutable,
		 * but by default just home it to follow "hash_default".
		 */
		BUG_ON(hv_pte_get_writable(pte));
		if (pte_get_forcecache(pte)) {
			/* Upgrade "force any cpu" to "No L3" for immutable. */
			if (hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_TILE_L3
			    && pte_get_anyhome(pte)) {
				pte = hv_pte_set_mode(pte,
						      HV_PTE_MODE_CACHE_NO_L3);
			}
		} else
#if CHIP_HAS_CBOX_HOME_MAP()
		if (hash_default)
			pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
		else
#endif
			pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
		pte = hv_pte_set_nc(pte);
		break;

#if CHIP_HAS_CBOX_HOME_MAP()
	case PAGE_HOME_HASH:
		pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
		break;
#endif

	default:
		BUG_ON(home < 0 || home >= NR_CPUS ||
		       !cpu_is_valid_lotar(home));
		pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_TILE_L3);
		pte = set_remote_cache_cpu(pte, home);
		break;
	}

#if CHIP_HAS_NC_AND_NOALLOC_BITS()
	if (noallocl2)
		pte = hv_pte_set_no_alloc_l2(pte);

	/* Simplify "no local and no l3" to "uncached" */
	if (hv_pte_get_no_alloc_l2(pte) && hv_pte_get_no_alloc_l1(pte) &&
	    hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_NO_L3) {
		pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
	}
#endif

	/* Checking this case here gives a better panic than from the hv. */
	BUG_ON(hv_pte_get_mode(pte) == 0);

	return pte;
}
EXPORT_SYMBOL(pte_set_home);

/*
 * The routines in this section are the "static" versions of the normal
 * dynamic homecaching routines; they just set the home cache
 * of a kernel page once, and require a full-chip cache/TLB flush,
 * so they're not suitable for anything but infrequent use.
 */

#if CHIP_HAS_CBOX_HOME_MAP()
static inline int initial_page_home(void) { return PAGE_HOME_HASH; }
#else
static inline int initial_page_home(void) { return 0; }
#endif

int page_home(struct page *page)
{
	if (PageHighMem(page)) {
		return initial_page_home();
	} else {
		unsigned long kva = (unsigned long)page_address(page);
		return pte_to_home(*virt_to_pte(NULL, kva));
	}
}
EXPORT_SYMBOL(page_home);

void homecache_change_page_home(struct page *page, int order, int home)
{
	int i, pages = (1 << order);
	unsigned long kva;

	BUG_ON(PageHighMem(page));
	BUG_ON(page_count(page) > 1);
	BUG_ON(page_mapcount(page) != 0);
	kva = (unsigned long) page_address(page);
	flush_remote(0, HV_FLUSH_EVICT_L2, &cpu_cacheable_map,
		     kva, pages * PAGE_SIZE, PAGE_SIZE, cpu_online_mask,
		     NULL, 0);

	for (i = 0; i < pages; ++i, kva += PAGE_SIZE) {
		pte_t *ptep = virt_to_pte(NULL, kva);
		pte_t pteval = *ptep;
		BUG_ON(!pte_present(pteval) || pte_huge(pteval));
		__set_pte(ptep, pte_set_home(pteval, home));
	}
}
EXPORT_SYMBOL(homecache_change_page_home);

struct page *homecache_alloc_pages(gfp_t gfp_mask,
				   unsigned int order, int home)
{
	struct page *page;
	BUG_ON(gfp_mask & __GFP_HIGHMEM);   /* must be lowmem */
	page = alloc_pages(gfp_mask, order);
	if (page)
		homecache_change_page_home(page, order, home);
	return page;
}
EXPORT_SYMBOL(homecache_alloc_pages);

struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
					unsigned int order, int home)
{
	struct page *page;
	BUG_ON(gfp_mask & __GFP_HIGHMEM);   /* must be lowmem */
	page = alloc_pages_node(nid, gfp_mask, order);
	if (page)
		homecache_change_page_home(page, order, home);
	return page;
}

void __homecache_free_pages(struct page *page, unsigned int order)
{
	if (put_page_testzero(page)) {
		homecache_change_page_home(page, order, initial_page_home());
		if (order == 0) {
			free_hot_cold_page(page, 0);
		} else {
			init_page_count(page);
			__free_pages(page, order);
		}
	}
}
EXPORT_SYMBOL(__homecache_free_pages);

void homecache_free_pages(unsigned long addr, unsigned int order)
{
	if (addr != 0) {
		VM_BUG_ON(!virt_addr_valid((void *)addr));
		__homecache_free_pages(virt_to_page((void *)addr), order);
	}
}
EXPORT_SYMBOL(homecache_free_pages);
Commit	Line	Data
867e359b CM	1	/*
	2	* Copyright 2010 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*
	14	* This code maintains the "home" for each page in the system.
	15	*/
	16
	17	#include <linux/kernel.h>
	18	#include <linux/mm.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/list.h>
	21	#include <linux/bootmem.h>
	22	#include <linux/rmap.h>
	23	#include <linux/pagemap.h>
	24	#include <linux/mutex.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/sysctl.h>
	27	#include <linux/pagevec.h>
	28	#include <linux/ptrace.h>
	29	#include <linux/timex.h>
	30	#include <linux/cache.h>
	31	#include <linux/smp.h>
c745a8a1	32	#include <linux/module.h>
621b1955	33	#include <linux/hugetlb.h>
867e359b CM	34
	35	#include <asm/page.h>
	36	#include <asm/sections.h>
	37	#include <asm/tlbflush.h>
	38	#include <asm/pgalloc.h>
	39	#include <asm/homecache.h>
	40
bf65e440 CM	41	#include <arch/sim.h>
bf65e440 CM	42
867e359b CM	43	#include "migrate.h"
	44
	45
	46	#if CHIP_HAS_COHERENT_LOCAL_CACHE()
	47
	48	/*
	49	* The noallocl2 option suppresses all use of the L2 cache to cache
	50	* locally from a remote home. There's no point in using it if we
	51	* don't have coherent local caching, though.
	52	*/
0707ad30	53	static int __write_once noallocl2;
867e359b CM	54	static int __init set_noallocl2(char *str)
	55	{
	56	noallocl2 = 1;
	57	return 0;
	58	}
	59	early_param("noallocl2", set_noallocl2);
	60
	61	#else
	62
	63	#define noallocl2 0
	64
	65	#endif
	66
867e359b	67
867e359b CM	68	/*
	69	* Update the irq_stat for cpus that we are going to interrupt
	70	* with TLB or cache flushes. Also handle removing dataplane cpus
	71	* from the TLB flush set, and setting dataplane_tlb_state instead.
	72	*/
	73	static void hv_flush_update(const struct cpumask *cache_cpumask,
	74	struct cpumask *tlb_cpumask,
	75	unsigned long tlb_va, unsigned long tlb_length,
	76	HV_Remote_ASID *asids, int asidcount)
	77	{
	78	struct cpumask mask;
	79	int i, cpu;
	80
	81	cpumask_clear(&mask);
	82	if (cache_cpumask)
	83	cpumask_or(&mask, &mask, cache_cpumask);
	84	if (tlb_cpumask && tlb_length) {
	85	cpumask_or(&mask, &mask, tlb_cpumask);
	86	}
	87
	88	for (i = 0; i < asidcount; ++i)
	89	cpumask_set_cpu(asids[i].y * smp_width + asids[i].x, &mask);
	90
	91	/*
	92	* Don't bother to update atomically; losing a count
	93	* here is not that critical.
	94	*/
	95	for_each_cpu(cpu, &mask)
	96	++per_cpu(irq_stat, cpu).irq_hv_flush_count;
	97	}
	98
	99	/*
	100	* This wrapper function around hv_flush_remote() does several things:
	101	*
	102	* - Provides a return value error-checking panic path, since
	103	* there's never any good reason for hv_flush_remote() to fail.
	104	* - Accepts a 32-bit PFN rather than a 64-bit PA, which generally
	105	* is the type that Linux wants to pass around anyway.
867e359b CM	106	* - Canonicalizes that lengths of zero make cpumasks NULL.
	107	* - Handles deferring TLB flushes for dataplane tiles.
	108	* - Tracks remote interrupts in the per-cpu irq_cpustat_t.
	109	*
	110	* Note that we have to wait until the cache flush completes before
	111	* updating the per-cpu last_cache_flush word, since otherwise another
	112	* concurrent flush can race, conclude the flush has already
	113	* completed, and start to use the page while it's still dirty
	114	* remotely (running concurrently with the actual evict, presumably).
	115	*/
	116	void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
	117	const struct cpumask *cache_cpumask_orig,
	118	HV_VirtAddr tlb_va, unsigned long tlb_length,
	119	unsigned long tlb_pgsize,
	120	const struct cpumask *tlb_cpumask_orig,
	121	HV_Remote_ASID *asids, int asidcount)
	122	{
	123	int rc;
867e359b CM	124	struct cpumask cache_cpumask_copy, tlb_cpumask_copy;
	125	struct cpumask cache_cpumask, tlb_cpumask;
	126	HV_PhysAddr cache_pa;
	127	char cache_buf[NR_CPUS5], tlb_buf[NR_CPUS5];
	128
	129	mb(); /* provided just to simplify "magic hypervisor" mode */
	130
	131	/*
	132	* Canonicalize and copy the cpumasks.
	133	*/
	134	if (cache_cpumask_orig && cache_control) {
	135	cpumask_copy(&cache_cpumask_copy, cache_cpumask_orig);
	136	cache_cpumask = &cache_cpumask_copy;
	137	} else {
	138	cpumask_clear(&cache_cpumask_copy);
	139	cache_cpumask = NULL;
	140	}
	141	if (cache_cpumask == NULL)
	142	cache_control = 0;
	143	if (tlb_cpumask_orig && tlb_length) {
	144	cpumask_copy(&tlb_cpumask_copy, tlb_cpumask_orig);
	145	tlb_cpumask = &tlb_cpumask_copy;
	146	} else {
	147	cpumask_clear(&tlb_cpumask_copy);
	148	tlb_cpumask = NULL;
	149	}
	150
	151	hv_flush_update(cache_cpumask, tlb_cpumask, tlb_va, tlb_length,
	152	asids, asidcount);
	153	cache_pa = (HV_PhysAddr)cache_pfn << PAGE_SHIFT;
867e359b CM	154	rc = hv_flush_remote(cache_pa, cache_control,
	155	cpumask_bits(cache_cpumask),
	156	tlb_va, tlb_length, tlb_pgsize,
	157	cpumask_bits(tlb_cpumask),
	158	asids, asidcount);
867e359b CM	159	if (rc == 0)
	160	return;
	161	cpumask_scnprintf(cache_buf, sizeof(cache_buf), &cache_cpumask_copy);
	162	cpumask_scnprintf(tlb_buf, sizeof(tlb_buf), &tlb_cpumask_copy);
	163
0707ad30	164	pr_err("hv_flush_remote(%#llx, %#lx, %p [%s],"
867e359b CM	165	" %#lx, %#lx, %#lx, %p [%s], %p, %d) = %d\n",
	166	cache_pa, cache_control, cache_cpumask, cache_buf,
	167	(unsigned long)tlb_va, tlb_length, tlb_pgsize,
	168	tlb_cpumask, tlb_buf,
	169	asids, asidcount, rc);
867e359b CM	170	panic("Unsafe to continue.");
	171	}
	172
bbaa22c3	173	static void homecache_finv_page_va(void* va, int home)
63b7ca6b	174	{
bc1a298f CM	175	int cpu = get_cpu();
bc1a298f CM	176	if (home == cpu) {
bbaa22c3 CM	177	finv_buffer_local(va, PAGE_SIZE);
	178	} else if (home == PAGE_HOME_HASH) {
	179	finv_buffer_remote(va, PAGE_SIZE, 1);
	180	} else {
	181	BUG_ON(home < 0 \|\| home >= NR_CPUS);
	182	finv_buffer_remote(va, PAGE_SIZE, 0);
63b7ca6b	183	}
bc1a298f	184	put_cpu();
63b7ca6b CM	185	}
63b7ca6b CM	186
bbaa22c3	187	void homecache_finv_map_page(struct page *page, int home)
867e359b	188	{
bbaa22c3 CM	189	unsigned long flags;
	190	unsigned long va;
	191	pte_t *ptep;
	192	pte_t pte;
	193
	194	if (home == PAGE_HOME_UNCACHED)
	195	return;
	196	local_irq_save(flags);
	197	#ifdef CONFIG_HIGHMEM
	198	va = __fix_to_virt(FIX_KMAP_BEGIN + kmap_atomic_idx_push() +
	199	(KM_TYPE_NR * smp_processor_id()));
	200	#else
	201	va = __fix_to_virt(FIX_HOMECACHE_BEGIN + smp_processor_id());
	202	#endif
	203	ptep = virt_to_pte(NULL, (unsigned long)va);
	204	pte = pfn_pte(page_to_pfn(page), PAGE_KERNEL);
	205	__set_pte(ptep, pte_set_home(pte, home));
	206	homecache_finv_page_va((void *)va, home);
	207	__pte_clear(ptep);
	208	hv_flush_page(va, PAGE_SIZE);
	209	#ifdef CONFIG_HIGHMEM
	210	kmap_atomic_idx_pop();
	211	#endif
	212	local_irq_restore(flags);
867e359b CM	213	}
867e359b CM	214
bbaa22c3	215	static void homecache_finv_page_home(struct page *page, int home)
867e359b	216	{
bbaa22c3 CM	217	if (!PageHighMem(page) && home == page_home(page))
	218	homecache_finv_page_va(page_address(page), home);
	219	else
	220	homecache_finv_map_page(page, home);
867e359b CM	221	}
867e359b CM	222
bbaa22c3	223	static inline bool incoherent_home(int home)
867e359b	224	{
bbaa22c3	225	return home == PAGE_HOME_IMMUTABLE \|\| home == PAGE_HOME_INCOHERENT;
867e359b CM	226	}
867e359b CM	227
bbaa22c3	228	static void homecache_finv_page_internal(struct page *page, int force_map)
867e359b	229	{
bbaa22c3 CM	230	int home = page_home(page);
	231	if (home == PAGE_HOME_UNCACHED)
	232	return;
	233	if (incoherent_home(home)) {
	234	int cpu;
	235	for_each_cpu(cpu, &cpu_cacheable_map)
	236	homecache_finv_map_page(page, cpu);
	237	} else if (force_map) {
	238	/* Force if, e.g., the normal mapping is migrating. */
	239	homecache_finv_map_page(page, home);
	240	} else {
	241	homecache_finv_page_home(page, home);
	242	}
	243	sim_validate_lines_evicted(PFN_PHYS(page_to_pfn(page)), PAGE_SIZE);
867e359b CM	244	}
867e359b CM	245
bbaa22c3 CM	246	void homecache_finv_page(struct page *page)
	247	{
	248	homecache_finv_page_internal(page, 0);
	249	}
	250
	251	void homecache_evict(const struct cpumask *mask)
	252	{
	253	flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
	254	}
867e359b CM	255
	256	/* Report the home corresponding to a given PTE. */
	257	static int pte_to_home(pte_t pte)
	258	{
	259	if (hv_pte_get_nc(pte))
	260	return PAGE_HOME_IMMUTABLE;
	261	switch (hv_pte_get_mode(pte)) {
	262	case HV_PTE_MODE_CACHE_TILE_L3:
	263	return get_remote_cache_cpu(pte);
	264	case HV_PTE_MODE_CACHE_NO_L3:
	265	return PAGE_HOME_INCOHERENT;
	266	case HV_PTE_MODE_UNCACHED:
	267	return PAGE_HOME_UNCACHED;
	268	#if CHIP_HAS_CBOX_HOME_MAP()
	269	case HV_PTE_MODE_CACHE_HASH_L3:
	270	return PAGE_HOME_HASH;
	271	#endif
	272	}
	273	panic("Bad PTE %#llx\n", pte.val);
	274	}
	275
	276	/* Update the home of a PTE if necessary (can also be used for a pgprot_t). */
	277	pte_t pte_set_home(pte_t pte, int home)
	278	{
	279	/* Check for non-linear file mapping "PTEs" and pass them through. */
	280	if (pte_file(pte))
	281	return pte;
	282
	283	#if CHIP_HAS_MMIO()
	284	/* Check for MMIO mappings and pass them through. */
	285	if (hv_pte_get_mode(pte) == HV_PTE_MODE_MMIO)
	286	return pte;
	287	#endif
	288
	289
	290	/*
	291	* Only immutable pages get NC mappings. If we have a
	292	* non-coherent PTE, but the underlying page is not
	293	* immutable, it's likely the result of a forced
	294	* caching setting running up against ptrace setting
	295	* the page to be writable underneath. In this case,
	296	* just keep the PTE coherent.
	297	*/
	298	if (hv_pte_get_nc(pte) && home != PAGE_HOME_IMMUTABLE) {
	299	pte = hv_pte_clear_nc(pte);
0707ad30	300	pr_err("non-immutable page incoherently referenced: %#llx\n",
867e359b CM	301	pte.val);
	302	}
	303
	304	switch (home) {
	305
	306	case PAGE_HOME_UNCACHED:
	307	pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
	308	break;
	309
	310	case PAGE_HOME_INCOHERENT:
	311	pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
	312	break;
	313
	314	case PAGE_HOME_IMMUTABLE:
	315	/*
	316	* We could home this page anywhere, since it's immutable,
	317	* but by default just home it to follow "hash_default".
	318	*/
	319	BUG_ON(hv_pte_get_writable(pte));
	320	if (pte_get_forcecache(pte)) {
	321	/* Upgrade "force any cpu" to "No L3" for immutable. */
	322	if (hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_TILE_L3
	323	&& pte_get_anyhome(pte)) {
	324	pte = hv_pte_set_mode(pte,
	325	HV_PTE_MODE_CACHE_NO_L3);
	326	}
	327	} else
	328	#if CHIP_HAS_CBOX_HOME_MAP()
	329	if (hash_default)
	330	pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
	331	else
	332	#endif
	333	pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
	334	pte = hv_pte_set_nc(pte);
	335	break;
	336
	337	#if CHIP_HAS_CBOX_HOME_MAP()
	338	case PAGE_HOME_HASH:
	339	pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
	340	break;
	341	#endif
	342
	343	default:
	344	BUG_ON(home < 0 \|\| home >= NR_CPUS \|\|
	345	!cpu_is_valid_lotar(home));
	346	pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_TILE_L3);
	347	pte = set_remote_cache_cpu(pte, home);
	348	break;
	349	}
	350
	351	#if CHIP_HAS_NC_AND_NOALLOC_BITS()
	352	if (noallocl2)
	353	pte = hv_pte_set_no_alloc_l2(pte);
	354
	355	/* Simplify "no local and no l3" to "uncached" */
	356	if (hv_pte_get_no_alloc_l2(pte) && hv_pte_get_no_alloc_l1(pte) &&
	357	hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_NO_L3) {
	358	pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
	359	}
	360	#endif
	361
	362	/* Checking this case here gives a better panic than from the hv. */
	363	BUG_ON(hv_pte_get_mode(pte) == 0);
	364
365	return pte;
366	}
c745a8a1	367	EXPORT_SYMBOL(pte_set_home);
867e359b CM	368
	369	/*
	370	* The routines in this section are the "static" versions of the normal
	371	* dynamic homecaching routines; they just set the home cache
	372	* of a kernel page once, and require a full-chip cache/TLB flush,
	373	* so they're not suitable for anything but infrequent use.
	374	*/
	375
	376	#if CHIP_HAS_CBOX_HOME_MAP()
	377	static inline int initial_page_home(void) { return PAGE_HOME_HASH; }
	378	#else
	379	static inline int initial_page_home(void) { return 0; }
	380	#endif
	381
	382	int page_home(struct page *page)
	383	{
	384	if (PageHighMem(page)) {
	385	return initial_page_home();
	386	} else {
	387	unsigned long kva = (unsigned long)page_address(page);
	388	return pte_to_home(*virt_to_pte(NULL, kva));
	389	}
	390	}
e81510e0	391	EXPORT_SYMBOL(page_home);
867e359b CM	392
	393	void homecache_change_page_home(struct page *page, int order, int home)
	394	{
	395	int i, pages = (1 << order);
	396	unsigned long kva;
	397
	398	BUG_ON(PageHighMem(page));
	399	BUG_ON(page_count(page) > 1);
	400	BUG_ON(page_mapcount(page) != 0);
	401	kva = (unsigned long) page_address(page);
	402	flush_remote(0, HV_FLUSH_EVICT_L2, &cpu_cacheable_map,
	403	kva, pages * PAGE_SIZE, PAGE_SIZE, cpu_online_mask,
	404	NULL, 0);
	405
	406	for (i = 0; i < pages; ++i, kva += PAGE_SIZE) {
	407	pte_t *ptep = virt_to_pte(NULL, kva);
	408	pte_t pteval = *ptep;
	409	BUG_ON(!pte_present(pteval) \|\| pte_huge(pteval));
76c567fb	410	__set_pte(ptep, pte_set_home(pteval, home));
867e359b CM	411	}
867e359b CM	412	}
7c63e1ee	413	EXPORT_SYMBOL(homecache_change_page_home);
867e359b CM	414
	415	struct page *homecache_alloc_pages(gfp_t gfp_mask,
	416	unsigned int order, int home)
	417	{
	418	struct page *page;
	419	BUG_ON(gfp_mask & __GFP_HIGHMEM); /* must be lowmem */
	420	page = alloc_pages(gfp_mask, order);
	421	if (page)
	422	homecache_change_page_home(page, order, home);
	423	return page;
	424	}
c745a8a1	425	EXPORT_SYMBOL(homecache_alloc_pages);
867e359b CM	426
	427	struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
	428	unsigned int order, int home)
	429	{
	430	struct page *page;
	431	BUG_ON(gfp_mask & __GFP_HIGHMEM); /* must be lowmem */
	432	page = alloc_pages_node(nid, gfp_mask, order);
	433	if (page)
	434	homecache_change_page_home(page, order, home);
	435	return page;
	436	}
	437
bbaa22c3	438	void __homecache_free_pages(struct page *page, unsigned int order)
867e359b	439	{
867e359b	440	if (put_page_testzero(page)) {
867e359b	441	homecache_change_page_home(page, order, initial_page_home());
c2851a9b CM	442	if (order == 0) {
	443	free_hot_cold_page(page, 0);
	444	} else {
	445	init_page_count(page);
	446	__free_pages(page, order);
	447	}
867e359b CM	448	}
867e359b CM	449	}
bbaa22c3 CM	450	EXPORT_SYMBOL(__homecache_free_pages);
	451
	452	void homecache_free_pages(unsigned long addr, unsigned int order)
	453	{
	454	if (addr != 0) {
	455	VM_BUG_ON(!virt_addr_valid((void *)addr));
	456	__homecache_free_pages(virt_to_page((void *)addr), order);
	457	}
	458	}
	459	EXPORT_SYMBOL(homecache_free_pages);