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700598ce G |
1 | /* |
2 | * linux/arch/unicore32/kernel/pci.c | |
3 | * | |
4 | * Code specific to PKUnity SoC and UniCore ISA | |
5 | * | |
6 | * Copyright (C) 2001-2010 GUAN Xue-tao | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * PCI bios-type initialisation for PCI machines | |
13 | * | |
14 | */ | |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
22 | ||
23 | static int debug_pci; | |
700598ce G |
24 | |
25 | #define CONFIG_CMD(bus, devfn, where) \ | |
26 | (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) | |
27 | ||
28 | static int | |
29 | puv3_read_config(struct pci_bus *bus, unsigned int devfn, int where, | |
30 | int size, u32 *value) | |
31 | { | |
e5abf78b | 32 | writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); |
700598ce G |
33 | switch (size) { |
34 | case 1: | |
e5abf78b | 35 | *value = (readl(PCICFG_DATA) >> ((where & 3) * 8)) & 0xFF; |
700598ce G |
36 | break; |
37 | case 2: | |
e5abf78b | 38 | *value = (readl(PCICFG_DATA) >> ((where & 2) * 8)) & 0xFFFF; |
700598ce G |
39 | break; |
40 | case 4: | |
e5abf78b | 41 | *value = readl(PCICFG_DATA); |
700598ce G |
42 | break; |
43 | } | |
44 | return PCIBIOS_SUCCESSFUL; | |
45 | } | |
46 | ||
47 | static int | |
48 | puv3_write_config(struct pci_bus *bus, unsigned int devfn, int where, | |
49 | int size, u32 value) | |
50 | { | |
e5abf78b | 51 | writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); |
700598ce G |
52 | switch (size) { |
53 | case 1: | |
e5abf78b G |
54 | writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8)) |
55 | | FIELD(value, 8, (where&3)*8), PCICFG_DATA); | |
700598ce G |
56 | break; |
57 | case 2: | |
e5abf78b G |
58 | writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8)) |
59 | | FIELD(value, 16, (where&2)*8), PCICFG_DATA); | |
700598ce G |
60 | break; |
61 | case 4: | |
e5abf78b | 62 | writel(value, PCICFG_DATA); |
700598ce G |
63 | break; |
64 | } | |
65 | return PCIBIOS_SUCCESSFUL; | |
66 | } | |
67 | ||
68 | struct pci_ops pci_puv3_ops = { | |
69 | .read = puv3_read_config, | |
70 | .write = puv3_write_config, | |
71 | }; | |
72 | ||
73 | void pci_puv3_preinit(void) | |
74 | { | |
75 | printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n"); | |
76 | /* config PCI bridge base */ | |
1cf46c42 | 77 | writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); |
700598ce | 78 | |
e5abf78b | 79 | writel(0, PCIBRI_AHBCTL0); |
1cf46c42 | 80 | writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); |
e5abf78b G |
81 | writel(0xFFFF0000, PCIBRI_AHBAMR0); |
82 | writel(0, PCIBRI_AHBTAR0); | |
700598ce | 83 | |
e5abf78b | 84 | writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1); |
1cf46c42 | 85 | writel(io_v2p(PKUNITY_PCILIO_BASE) | PCIBRI_BARx_IO, PCIBRI_AHBBAR1); |
e5abf78b G |
86 | writel(0xFFFF0000, PCIBRI_AHBAMR1); |
87 | writel(0x00000000, PCIBRI_AHBTAR1); | |
700598ce | 88 | |
e5abf78b | 89 | writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2); |
1cf46c42 | 90 | writel(io_v2p(PKUNITY_PCIMEM_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2); |
e5abf78b G |
91 | writel(0xF8000000, PCIBRI_AHBAMR2); |
92 | writel(0, PCIBRI_AHBTAR2); | |
700598ce | 93 | |
1cf46c42 | 94 | writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_BAR1); |
700598ce | 95 | |
e5abf78b | 96 | writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0); |
1cf46c42 | 97 | writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0); |
e5abf78b G |
98 | writel(0xF8000000, PCIBRI_PCIAMR0); |
99 | writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0); | |
700598ce | 100 | |
e5abf78b | 101 | writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD); |
700598ce G |
102 | } |
103 | ||
d5341942 | 104 | static int __init pci_puv3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
700598ce G |
105 | { |
106 | if (dev->bus->number == 0) { | |
107 | #ifdef CONFIG_ARCH_FPGA /* 4 pci slots */ | |
108 | if (dev->devfn == 0x00) | |
109 | return IRQ_PCIINTA; | |
110 | else if (dev->devfn == 0x08) | |
111 | return IRQ_PCIINTB; | |
112 | else if (dev->devfn == 0x10) | |
113 | return IRQ_PCIINTC; | |
114 | else if (dev->devfn == 0x18) | |
115 | return IRQ_PCIINTD; | |
116 | #endif | |
117 | #ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */ | |
118 | if (dev->devfn == 0x30) | |
119 | return IRQ_PCIINTB; | |
120 | else if (dev->devfn == 0x60) | |
121 | return IRQ_PCIINTC; | |
122 | else if (dev->devfn == 0x58) | |
123 | return IRQ_PCIINTD; | |
124 | #endif | |
125 | #if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919) | |
126 | /* only support 2 pci devices */ | |
127 | if (dev->devfn == 0x00) | |
128 | return IRQ_PCIINTC; /* sata */ | |
129 | #endif | |
130 | } | |
131 | return -1; | |
132 | } | |
133 | ||
134 | /* | |
135 | * Only first 128MB of memory can be accessed via PCI. | |
136 | * We use GFP_DMA to allocate safe buffers to do map/unmap. | |
137 | * This is really ugly and we need a better way of specifying | |
138 | * DMA-capable regions of memory. | |
139 | */ | |
140 | void __init puv3_pci_adjust_zones(unsigned long *zone_size, | |
141 | unsigned long *zhole_size) | |
142 | { | |
143 | unsigned int sz = SZ_128M >> PAGE_SHIFT; | |
144 | ||
145 | /* | |
146 | * Only adjust if > 128M on current system | |
147 | */ | |
148 | if (zone_size[0] <= sz) | |
149 | return; | |
150 | ||
151 | zone_size[1] = zone_size[0] - sz; | |
152 | zone_size[0] = sz; | |
153 | zhole_size[1] = zhole_size[0]; | |
154 | zhole_size[0] = 0; | |
155 | } | |
156 | ||
700598ce G |
157 | /* |
158 | * If the bus contains any of these devices, then we must not turn on | |
159 | * parity checking of any kind. | |
160 | */ | |
161 | static inline int pdev_bad_for_parity(struct pci_dev *dev) | |
162 | { | |
163 | return 0; | |
164 | } | |
165 | ||
166 | /* | |
167 | * pcibios_fixup_bus - Called after each bus is probed, | |
168 | * but before its children are examined. | |
169 | */ | |
b881bc46 | 170 | void pcibios_fixup_bus(struct pci_bus *bus) |
700598ce G |
171 | { |
172 | struct pci_dev *dev; | |
173 | u16 features = PCI_COMMAND_SERR | |
174 | | PCI_COMMAND_PARITY | |
175 | | PCI_COMMAND_FAST_BACK; | |
176 | ||
177 | bus->resource[0] = &ioport_resource; | |
178 | bus->resource[1] = &iomem_resource; | |
179 | ||
180 | /* | |
181 | * Walk the devices on this bus, working out what we can | |
182 | * and can't support. | |
183 | */ | |
184 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
185 | u16 status; | |
186 | ||
187 | pci_read_config_word(dev, PCI_STATUS, &status); | |
188 | ||
189 | /* | |
190 | * If any device on this bus does not support fast back | |
191 | * to back transfers, then the bus as a whole is not able | |
192 | * to support them. Having fast back to back transfers | |
193 | * on saves us one PCI cycle per transaction. | |
194 | */ | |
195 | if (!(status & PCI_STATUS_FAST_BACK)) | |
196 | features &= ~PCI_COMMAND_FAST_BACK; | |
197 | ||
198 | if (pdev_bad_for_parity(dev)) | |
199 | features &= ~(PCI_COMMAND_SERR | |
200 | | PCI_COMMAND_PARITY); | |
201 | ||
202 | switch (dev->class >> 8) { | |
203 | case PCI_CLASS_BRIDGE_PCI: | |
204 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); | |
205 | status |= PCI_BRIDGE_CTL_PARITY | |
206 | | PCI_BRIDGE_CTL_MASTER_ABORT; | |
207 | status &= ~(PCI_BRIDGE_CTL_BUS_RESET | |
208 | | PCI_BRIDGE_CTL_FAST_BACK); | |
209 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); | |
210 | break; | |
211 | ||
212 | case PCI_CLASS_BRIDGE_CARDBUS: | |
213 | pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, | |
214 | &status); | |
215 | status |= PCI_CB_BRIDGE_CTL_PARITY | |
216 | | PCI_CB_BRIDGE_CTL_MASTER_ABORT; | |
217 | pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, | |
218 | status); | |
219 | break; | |
220 | } | |
221 | } | |
222 | ||
223 | /* | |
224 | * Now walk the devices again, this time setting them up. | |
225 | */ | |
226 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
227 | u16 cmd; | |
228 | ||
229 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
230 | cmd |= features; | |
231 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
232 | ||
233 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, | |
234 | L1_CACHE_BYTES >> 2); | |
235 | } | |
236 | ||
237 | /* | |
238 | * Propagate the flags to the PCI bridge. | |
239 | */ | |
240 | if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
241 | if (features & PCI_COMMAND_FAST_BACK) | |
242 | bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; | |
243 | if (features & PCI_COMMAND_PARITY) | |
244 | bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; | |
245 | } | |
246 | ||
247 | /* | |
248 | * Report what we did for this bus | |
249 | */ | |
250 | printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", | |
251 | bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); | |
252 | } | |
700598ce | 253 | EXPORT_SYMBOL(pcibios_fixup_bus); |
700598ce G |
254 | |
255 | static int __init pci_common_init(void) | |
256 | { | |
257 | struct pci_bus *puv3_bus; | |
258 | ||
259 | pci_puv3_preinit(); | |
260 | ||
261 | puv3_bus = pci_scan_bus(0, &pci_puv3_ops, NULL); | |
262 | ||
263 | if (!puv3_bus) | |
264 | panic("PCI: unable to scan bus!"); | |
265 | ||
266 | pci_fixup_irqs(pci_common_swizzle, pci_puv3_map_irq); | |
267 | ||
ab2b750c BH |
268 | pci_bus_size_bridges(puv3_bus); |
269 | pci_bus_assign_resources(puv3_bus); | |
c90570d9 | 270 | pci_bus_add_devices(puv3_bus); |
700598ce G |
271 | return 0; |
272 | } | |
273 | subsys_initcall(pci_common_init); | |
274 | ||
5d9a19e8 | 275 | char * __init pcibios_setup(char *str) |
700598ce G |
276 | { |
277 | if (!strcmp(str, "debug")) { | |
278 | debug_pci = 1; | |
279 | return NULL; | |
700598ce G |
280 | } |
281 | return str; | |
282 | } | |
283 | ||
b73224fd MS |
284 | void pcibios_set_master(struct pci_dev *dev) |
285 | { | |
286 | /* No special bus mastering setup handling */ | |
287 | } | |
288 | ||
700598ce G |
289 | /* |
290 | * From arch/i386/kernel/pci-i386.c: | |
291 | * | |
292 | * We need to avoid collisions with `mirrored' VGA ports | |
293 | * and other strange ISA hardware, so we always want the | |
294 | * addresses to be allocated in the 0x000-0x0ff region | |
295 | * modulo 0x400. | |
296 | * | |
297 | * Why? Because some silly external IO cards only decode | |
298 | * the low 10 bits of the IO address. The 0x00-0xff region | |
299 | * is reserved for motherboard devices that decode all 16 | |
300 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
301 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
302 | * which might be mirrored at 0x0100-0x03ff.. | |
303 | */ | |
304 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, | |
305 | resource_size_t size, resource_size_t align) | |
306 | { | |
307 | resource_size_t start = res->start; | |
308 | ||
309 | if (res->flags & IORESOURCE_IO && start & 0x300) | |
310 | start = (start + 0x3ff) & ~0x3ff; | |
311 | ||
312 | start = (start + align - 1) & ~(align - 1); | |
313 | ||
314 | return start; | |
315 | } | |
316 | ||
317 | /** | |
318 | * pcibios_enable_device - Enable I/O and memory. | |
319 | * @dev: PCI device to be enabled | |
320 | */ | |
321 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
322 | { | |
323 | u16 cmd, old_cmd; | |
324 | int idx; | |
325 | struct resource *r; | |
326 | ||
327 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
328 | old_cmd = cmd; | |
329 | for (idx = 0; idx < 6; idx++) { | |
330 | /* Only set up the requested stuff */ | |
331 | if (!(mask & (1 << idx))) | |
332 | continue; | |
333 | ||
334 | r = dev->resource + idx; | |
335 | if (!r->start && r->end) { | |
336 | printk(KERN_ERR "PCI: Device %s not available because" | |
337 | " of resource collisions\n", pci_name(dev)); | |
338 | return -EINVAL; | |
339 | } | |
340 | if (r->flags & IORESOURCE_IO) | |
341 | cmd |= PCI_COMMAND_IO; | |
342 | if (r->flags & IORESOURCE_MEM) | |
343 | cmd |= PCI_COMMAND_MEMORY; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Bridges (eg, cardbus bridges) need to be fully enabled | |
348 | */ | |
349 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) | |
350 | cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY; | |
351 | ||
352 | if (cmd != old_cmd) { | |
353 | printk("PCI: enabling device %s (%04x -> %04x)\n", | |
354 | pci_name(dev), old_cmd, cmd); | |
355 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
356 | } | |
357 | return 0; | |
358 | } | |
359 | ||
360 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
361 | enum pci_mmap_state mmap_state, int write_combine) | |
362 | { | |
363 | unsigned long phys; | |
364 | ||
365 | if (mmap_state == pci_mmap_io) | |
366 | return -EINVAL; | |
367 | ||
368 | phys = vma->vm_pgoff; | |
369 | ||
370 | /* | |
371 | * Mark this as IO | |
372 | */ | |
373 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
374 | ||
375 | if (remap_pfn_range(vma, vma->vm_start, phys, | |
376 | vma->vm_end - vma->vm_start, | |
377 | vma->vm_page_prot)) | |
378 | return -EAGAIN; | |
379 | ||
380 | return 0; | |
381 | } |