Commit | Line | Data |
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b50f1704 G |
1 | comment "Processor Type" |
2 | ||
3 | # Select CPU types depending on the architecture selected. This selects | |
4 | # which CPUs we support in the kernel image, and the compiler instruction | |
5 | # optimiser behaviour. | |
6 | ||
7 | config CPU_UCV2 | |
8 | def_bool y | |
9 | ||
10 | comment "Processor Features" | |
11 | ||
12 | config CPU_ICACHE_DISABLE | |
13 | bool "Disable I-Cache (I-bit)" | |
14 | help | |
15 | Say Y here to disable the processor instruction cache. Unless | |
16 | you have a reason not to or are unsure, say N. | |
17 | ||
18 | config CPU_DCACHE_DISABLE | |
19 | bool "Disable D-Cache (D-bit)" | |
20 | help | |
21 | Say Y here to disable the processor data cache. Unless | |
22 | you have a reason not to or are unsure, say N. | |
23 | ||
24 | config CPU_DCACHE_WRITETHROUGH | |
25 | bool "Force write through D-cache" | |
26 | help | |
27 | Say Y here to use the data cache in writethrough mode. Unless you | |
28 | specifically require this or are unsure, say N. | |
29 | ||
30 | config CPU_DCACHE_LINE_DISABLE | |
31 | bool "Disable D-cache line ops" | |
32 | default y | |
33 | help | |
34 | Say Y here to disable the data cache line operations. | |
35 | ||
36 | config CPU_TLB_SINGLE_ENTRY_DISABLE | |
37 | bool "Disable TLB single entry ops" | |
38 | default y | |
39 | help | |
40 | Say Y here to disable the TLB single entry operations. | |
41 | ||
42 | config SWIOTLB | |
43 | def_bool y | |
44 | ||
45 | config IOMMU_HELPER | |
46 | def_bool SWIOTLB | |
47 | ||
48 | config NEED_SG_DMA_LENGTH | |
49 | def_bool SWIOTLB | |
50 |