Commit | Line | Data |
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96d55b88 | 1 | # Put here option for CPU selection and depending optimization |
96d55b88 PBG |
2 | choice |
3 | prompt "Processor family" | |
1032c0ba SR |
4 | default M686 if X86_32 |
5 | default GENERIC_CPU if X86_64 | |
96d55b88 PBG |
6 | |
7 | config M386 | |
8 | bool "386" | |
1032c0ba | 9 | depends on X86_32 && !UML |
96d55b88 PBG |
10 | ---help--- |
11 | This is the processor type of your CPU. This information is used for | |
12 | optimizing purposes. In order to compile a kernel that can run on | |
13 | all x86 CPU types (albeit not optimally fast), you can specify | |
14 | "386" here. | |
15 | ||
16 | The kernel will not necessarily run on earlier architectures than | |
17 | the one you have chosen, e.g. a Pentium optimized kernel will run on | |
18 | a PPro, but not necessarily on a i486. | |
19 | ||
20 | Here are the settings recommended for greatest speed: | |
21 | - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI | |
f7f17a67 DV |
22 | 486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386 |
23 | class machine. | |
96d55b88 PBG |
24 | - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or |
25 | SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. | |
26 | - "586" for generic Pentium CPUs lacking the TSC | |
27 | (time stamp counter) register. | |
28 | - "Pentium-Classic" for the Intel Pentium. | |
29 | - "Pentium-MMX" for the Intel Pentium MMX. | |
30 | - "Pentium-Pro" for the Intel Pentium Pro. | |
31 | - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. | |
32 | - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. | |
33 | - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. | |
34 | - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). | |
35 | - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). | |
36 | - "Crusoe" for the Transmeta Crusoe series. | |
37 | - "Efficeon" for the Transmeta Efficeon series. | |
38 | - "Winchip-C6" for original IDT Winchip. | |
69d45dd1 | 39 | - "Winchip-2" for IDT Winchips with 3dNow! capabilities. |
96d55b88 | 40 | - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). |
f90b8116 | 41 | - "Geode GX/LX" For AMD Geode GX and LX processors. |
96d55b88 | 42 | - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. |
48a1204c | 43 | - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). |
0949be35 | 44 | - "VIA C7" for VIA C7. |
96d55b88 PBG |
45 | |
46 | If you don't know what to do, choose "386". | |
47 | ||
48 | config M486 | |
49 | bool "486" | |
1032c0ba | 50 | depends on X86_32 |
8f9ca475 | 51 | ---help--- |
96d55b88 PBG |
52 | Select this for a 486 series processor, either Intel or one of the |
53 | compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX, | |
54 | DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or | |
55 | U5S. | |
56 | ||
57 | config M586 | |
58 | bool "586/K5/5x86/6x86/6x86MX" | |
1032c0ba | 59 | depends on X86_32 |
8f9ca475 | 60 | ---help--- |
96d55b88 PBG |
61 | Select this for an 586 or 686 series processor such as the AMD K5, |
62 | the Cyrix 5x86, 6x86 and 6x86MX. This choice does not | |
63 | assume the RDTSC (Read Time Stamp Counter) instruction. | |
64 | ||
65 | config M586TSC | |
66 | bool "Pentium-Classic" | |
1032c0ba | 67 | depends on X86_32 |
8f9ca475 | 68 | ---help--- |
96d55b88 PBG |
69 | Select this for a Pentium Classic processor with the RDTSC (Read |
70 | Time Stamp Counter) instruction for benchmarking. | |
71 | ||
72 | config M586MMX | |
73 | bool "Pentium-MMX" | |
1032c0ba | 74 | depends on X86_32 |
8f9ca475 | 75 | ---help--- |
96d55b88 PBG |
76 | Select this for a Pentium with the MMX graphics/multimedia |
77 | extended instructions. | |
78 | ||
79 | config M686 | |
80 | bool "Pentium-Pro" | |
1032c0ba | 81 | depends on X86_32 |
8f9ca475 | 82 | ---help--- |
96d55b88 PBG |
83 | Select this for Intel Pentium Pro chips. This enables the use of |
84 | Pentium Pro extended instructions, and disables the init-time guard | |
85 | against the f00f bug found in earlier Pentiums. | |
86 | ||
87 | config MPENTIUMII | |
88 | bool "Pentium-II/Celeron(pre-Coppermine)" | |
1032c0ba | 89 | depends on X86_32 |
8f9ca475 | 90 | ---help--- |
96d55b88 PBG |
91 | Select this for Intel chips based on the Pentium-II and |
92 | pre-Coppermine Celeron core. This option enables an unaligned | |
93 | copy optimization, compiles the kernel with optimization flags | |
94 | tailored for the chip, and applies any applicable Pentium Pro | |
95 | optimizations. | |
96 | ||
97 | config MPENTIUMIII | |
98 | bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" | |
1032c0ba | 99 | depends on X86_32 |
8f9ca475 | 100 | ---help--- |
96d55b88 PBG |
101 | Select this for Intel chips based on the Pentium-III and |
102 | Celeron-Coppermine core. This option enables use of some | |
103 | extended prefetch instructions in addition to the Pentium II | |
104 | extensions. | |
105 | ||
106 | config MPENTIUMM | |
107 | bool "Pentium M" | |
1032c0ba | 108 | depends on X86_32 |
8f9ca475 | 109 | ---help--- |
96d55b88 PBG |
110 | Select this for Intel Pentium M (not Pentium-4 M) |
111 | notebook chips. | |
112 | ||
113 | config MPENTIUM4 | |
c55d92d1 | 114 | bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
1032c0ba | 115 | depends on X86_32 |
8f9ca475 | 116 | ---help--- |
96d55b88 | 117 | Select this for Intel Pentium 4 chips. This includes the |
75e3808b OP |
118 | Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
119 | Pentium-4 M (not Pentium M) chips. This option enables compile | |
120 | flags optimized for the chip, uses the correct cache line size, and | |
121 | applies any applicable optimizations. | |
122 | ||
123 | CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 ) | |
124 | ||
125 | Select this for: | |
126 | Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename: | |
127 | -Willamette | |
128 | -Northwood | |
129 | -Mobile Pentium 4 | |
130 | -Mobile Pentium 4 M | |
131 | -Extreme Edition (Gallatin) | |
132 | -Prescott | |
133 | -Prescott 2M | |
134 | -Cedar Mill | |
135 | -Presler | |
136 | -Smithfiled | |
137 | Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: | |
138 | -Foster | |
139 | -Prestonia | |
140 | -Gallatin | |
141 | -Nocona | |
142 | -Irwindale | |
143 | -Cranford | |
144 | -Potomac | |
145 | -Paxville | |
146 | -Dempsey | |
147 | ||
96d55b88 PBG |
148 | |
149 | config MK6 | |
150 | bool "K6/K6-II/K6-III" | |
1032c0ba | 151 | depends on X86_32 |
8f9ca475 | 152 | ---help--- |
96d55b88 PBG |
153 | Select this for an AMD K6-family processor. Enables use of |
154 | some extended instructions, and passes appropriate optimization | |
155 | flags to GCC. | |
156 | ||
157 | config MK7 | |
158 | bool "Athlon/Duron/K7" | |
1032c0ba | 159 | depends on X86_32 |
8f9ca475 | 160 | ---help--- |
96d55b88 PBG |
161 | Select this for an AMD Athlon K7-family processor. Enables use of |
162 | some extended instructions, and passes appropriate optimization | |
163 | flags to GCC. | |
164 | ||
165 | config MK8 | |
166 | bool "Opteron/Athlon64/Hammer/K8" | |
8f9ca475 | 167 | ---help--- |
36723bfe BP |
168 | Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
169 | Enables use of some extended instructions, and passes appropriate | |
170 | optimization flags to GCC. | |
96d55b88 PBG |
171 | |
172 | config MCRUSOE | |
173 | bool "Crusoe" | |
1032c0ba | 174 | depends on X86_32 |
8f9ca475 | 175 | ---help--- |
96d55b88 PBG |
176 | Select this for a Transmeta Crusoe processor. Treats the processor |
177 | like a 586 with TSC, and sets some GCC optimization flags (like a | |
178 | Pentium Pro with no alignment requirements). | |
179 | ||
180 | config MEFFICEON | |
181 | bool "Efficeon" | |
1032c0ba | 182 | depends on X86_32 |
8f9ca475 | 183 | ---help--- |
96d55b88 PBG |
184 | Select this for a Transmeta Efficeon processor. |
185 | ||
186 | config MWINCHIPC6 | |
187 | bool "Winchip-C6" | |
1032c0ba | 188 | depends on X86_32 |
8f9ca475 | 189 | ---help--- |
96d55b88 PBG |
190 | Select this for an IDT Winchip C6 chip. Linux and GCC |
191 | treat this chip as a 586TSC with some extended instructions | |
192 | and alignment requirements. | |
193 | ||
96d55b88 | 194 | config MWINCHIP3D |
69d45dd1 | 195 | bool "Winchip-2/Winchip-2A/Winchip-3" |
1032c0ba | 196 | depends on X86_32 |
8f9ca475 | 197 | ---help--- |
69d45dd1 | 198 | Select this for an IDT Winchip-2, 2A or 3. Linux and GCC |
96d55b88 | 199 | treat this chip as a 586TSC with some extended instructions |
3dde6ad8 | 200 | and alignment requirements. Also enable out of order memory |
96d55b88 PBG |
201 | stores for this CPU, which can increase performance of some |
202 | operations. | |
203 | ||
ce9c99af IC |
204 | config MELAN |
205 | bool "AMD Elan" | |
206 | depends on X86_32 | |
207 | ---help--- | |
208 | Select this for an AMD Elan processor. | |
209 | ||
210 | Do not use this option for K6/Athlon/Opteron processors! | |
211 | ||
96d55b88 PBG |
212 | config MGEODEGX1 |
213 | bool "GeodeGX1" | |
1032c0ba | 214 | depends on X86_32 |
8f9ca475 | 215 | ---help--- |
96d55b88 PBG |
216 | Select this for a Geode GX1 (Cyrix MediaGX) chip. |
217 | ||
f90b8116 | 218 | config MGEODE_LX |
96daa8cd | 219 | bool "Geode GX/LX" |
1032c0ba | 220 | depends on X86_32 |
8f9ca475 | 221 | ---help--- |
96daa8cd | 222 | Select this for AMD Geode GX and LX processors. |
f90b8116 | 223 | |
96d55b88 PBG |
224 | config MCYRIXIII |
225 | bool "CyrixIII/VIA-C3" | |
1032c0ba | 226 | depends on X86_32 |
8f9ca475 | 227 | ---help--- |
96d55b88 PBG |
228 | Select this for a Cyrix III or C3 chip. Presently Linux and GCC |
229 | treat this chip as a generic 586. Whilst the CPU is 686 class, | |
230 | it lacks the cmov extension which gcc assumes is present when | |
231 | generating 686 code. | |
232 | Note that Nehemiah (Model 9) and above will not boot with this | |
233 | kernel due to them lacking the 3DNow! instructions used in earlier | |
234 | incarnations of the CPU. | |
235 | ||
236 | config MVIAC3_2 | |
237 | bool "VIA C3-2 (Nehemiah)" | |
1032c0ba | 238 | depends on X86_32 |
8f9ca475 | 239 | ---help--- |
96d55b88 PBG |
240 | Select this for a VIA C3 "Nehemiah". Selecting this enables usage |
241 | of SSE and tells gcc to treat the CPU as a 686. | |
242 | Note, this kernel will not boot on older (pre model 9) C3s. | |
243 | ||
0949be35 SA |
244 | config MVIAC7 |
245 | bool "VIA C7" | |
1032c0ba | 246 | depends on X86_32 |
8f9ca475 | 247 | ---help--- |
0949be35 SA |
248 | Select this for a VIA C7. Selecting this uses the correct cache |
249 | shift and tells gcc to treat the CPU as a 686. | |
250 | ||
1032c0ba SR |
251 | config MPSC |
252 | bool "Intel P4 / older Netburst based Xeon" | |
253 | depends on X86_64 | |
8f9ca475 | 254 | ---help--- |
1032c0ba SR |
255 | Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
256 | Xeon CPUs with Intel 64bit which is compatible with x86-64. | |
257 | Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the | |
96daa8cd | 258 | Netburst core and shouldn't use this option. You can distinguish them |
1032c0ba SR |
259 | using the cpu family field |
260 | in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. | |
261 | ||
262 | config MCORE2 | |
263 | bool "Core 2/newer Xeon" | |
8f9ca475 | 264 | ---help--- |
36723bfe BP |
265 | |
266 | Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and | |
267 | 53xx) CPUs. You can distinguish newer from older Xeons by the CPU | |
268 | family in /proc/cpuinfo. Newer ones have 6 and older ones 15 | |
269 | (not a typo) | |
1032c0ba | 270 | |
366d19e1 TD |
271 | config MATOM |
272 | bool "Intel Atom" | |
273 | ---help--- | |
274 | ||
275 | Select this for the Intel Atom platform. Intel Atom CPUs have an | |
276 | in-order pipelining architecture and thus can benefit from | |
277 | accordingly optimized code. Use a recent GCC with specific Atom | |
278 | support in order to fully benefit from selecting this option. | |
279 | ||
1032c0ba SR |
280 | config GENERIC_CPU |
281 | bool "Generic-x86-64" | |
282 | depends on X86_64 | |
8f9ca475 | 283 | ---help--- |
1032c0ba SR |
284 | Generic x86-64 CPU. |
285 | Run equally well on all x86-64 CPUs. | |
286 | ||
96d55b88 PBG |
287 | endchoice |
288 | ||
289 | config X86_GENERIC | |
1032c0ba SR |
290 | bool "Generic x86 support" |
291 | depends on X86_32 | |
8f9ca475 | 292 | ---help--- |
96d55b88 PBG |
293 | Instead of just including optimizations for the selected |
294 | x86 variant (e.g. PII, Crusoe or Athlon), include some more | |
295 | generic optimizations as well. This will make the kernel | |
296 | perform better on x86 CPUs other than that selected. | |
297 | ||
298 | This is really intended for distributors who need more | |
299 | generic optimizations. | |
300 | ||
96d55b88 PBG |
301 | # |
302 | # Define implied options from the CPU selection here | |
350f8f56 | 303 | config X86_INTERNODE_CACHE_SHIFT |
1032c0ba | 304 | int |
350f8f56 JB |
305 | default "12" if X86_VSMP |
306 | default "7" if NUMA | |
307 | default X86_L1_CACHE_SHIFT | |
1032c0ba | 308 | |
96d55b88 | 309 | config X86_CMPXCHG |
1032c0ba | 310 | def_bool X86_64 || (X86_32 && !M386) |
96d55b88 | 311 | |
7296e08a CL |
312 | config CMPXCHG_LOCAL |
313 | def_bool X86_64 || (X86_32 && !M386) | |
314 | ||
3824abd1 CL |
315 | config CMPXCHG_DOUBLE |
316 | def_bool y | |
317 | ||
96d55b88 PBG |
318 | config X86_L1_CACHE_SHIFT |
319 | int | |
0a2a18b7 | 320 | default "7" if MPENTIUM4 || MPSC |
350f8f56 | 321 | default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
ce9c99af | 322 | default "4" if MELAN || M486 || M386 || MGEODEGX1 |
69d45dd1 | 323 | default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
96d55b88 | 324 | |
c7f81c94 | 325 | config X86_XADD |
96daa8cd | 326 | def_bool y |
bafaecd1 | 327 | depends on X86_64 || !M386 |
96d55b88 PBG |
328 | |
329 | config X86_PPRO_FENCE | |
fb0328e2 | 330 | bool "PentiumPro memory ordering errata workaround" |
96d55b88 | 331 | depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1 |
8f9ca475 | 332 | ---help--- |
36723bfe BP |
333 | Old PentiumPro multiprocessor systems had errata that could cause |
334 | memory operations to violate the x86 ordering standard in rare cases. | |
335 | Enabling this option will attempt to work around some (but not all) | |
0d2eb44f | 336 | occurrences of this problem, at the cost of much heavier spinlock and |
36723bfe BP |
337 | memory barrier operations. |
338 | ||
339 | If unsure, say n here. Even distro kernels should think twice before | |
340 | enabling this: there are few systems, and an unlikely bug. | |
96d55b88 PBG |
341 | |
342 | config X86_F00F_BUG | |
96daa8cd | 343 | def_bool y |
96d55b88 | 344 | depends on M586MMX || M586TSC || M586 || M486 || M386 |
96d55b88 | 345 | |
40d2e763 BG |
346 | config X86_INVD_BUG |
347 | def_bool y | |
348 | depends on M486 || M386 | |
349 | ||
96d55b88 | 350 | config X86_WP_WORKS_OK |
96daa8cd | 351 | def_bool y |
293e6a25 | 352 | depends on !M386 |
96d55b88 PBG |
353 | |
354 | config X86_INVLPG | |
96daa8cd | 355 | def_bool y |
1032c0ba | 356 | depends on X86_32 && !M386 |
96d55b88 PBG |
357 | |
358 | config X86_BSWAP | |
96daa8cd | 359 | def_bool y |
1032c0ba | 360 | depends on X86_32 && !M386 |
96d55b88 PBG |
361 | |
362 | config X86_POPAD_OK | |
96daa8cd | 363 | def_bool y |
1032c0ba | 364 | depends on X86_32 && !M386 |
96d55b88 | 365 | |
96d55b88 | 366 | config X86_ALIGNMENT_16 |
96daa8cd | 367 | def_bool y |
ce9c99af | 368 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 |
96d55b88 | 369 | |
96d55b88 | 370 | config X86_INTEL_USERCOPY |
96daa8cd | 371 | def_bool y |
c55d92d1 | 372 | depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
96d55b88 PBG |
373 | |
374 | config X86_USE_PPRO_CHECKSUM | |
96daa8cd | 375 | def_bool y |
1eda75c1 | 376 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
96d55b88 PBG |
377 | |
378 | config X86_USE_3DNOW | |
96daa8cd | 379 | def_bool y |
1b4ad242 | 380 | depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
96d55b88 PBG |
381 | |
382 | config X86_OOSTORE | |
96daa8cd | 383 | def_bool y |
69d45dd1 | 384 | depends on (MWINCHIP3D || MWINCHIPC6) && MTRR |
96d55b88 | 385 | |
959b3be6 PA |
386 | # |
387 | # P6_NOPs are a relatively minor optimization that require a family >= | |
388 | # 6 processor, except that it is broken on certain VIA chips. | |
389 | # Furthermore, AMD chips prefer a totally different sequence of NOPs | |
14469a8d LT |
390 | # (which work on all CPUs). In addition, it looks like Virtual PC |
391 | # does not understand them. | |
392 | # | |
393 | # As a result, disallow these if we're not compiling for X86_64 (these | |
394 | # NOPs do work on all x86-64 capable chips); the list of processors in | |
395 | # the right-hand clause are the cores that benefit from this optimization. | |
959b3be6 | 396 | # |
7343b3b3 PA |
397 | config X86_P6_NOP |
398 | def_bool y | |
14469a8d LT |
399 | depends on X86_64 |
400 | depends on (MCORE2 || MPENTIUM4 || MPSC) | |
7343b3b3 | 401 | |
96d55b88 | 402 | config X86_TSC |
96daa8cd | 403 | def_bool y |
366d19e1 | 404 | depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64 |
c7f81c94 | 405 | |
f8096f92 JB |
406 | config X86_CMPXCHG64 |
407 | def_bool y | |
db677ffa | 408 | depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM |
f8096f92 | 409 | |
c7f81c94 AK |
410 | # this should be set for all -march=.. options where the compiler |
411 | # generates cmov. | |
412 | config X86_CMOV | |
96daa8cd | 413 | def_bool y |
98059e34 | 414 | depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) |
c7f81c94 | 415 | |
de32e041 | 416 | config X86_MINIMUM_CPU_FAMILY |
c7f81c94 | 417 | int |
1032c0ba | 418 | default "64" if X86_64 |
7343b3b3 | 419 | default "6" if X86_32 && X86_P6_NOP |
982d007a | 420 | default "5" if X86_32 && X86_CMPXCHG64 |
1032c0ba | 421 | default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK) |
de32e041 | 422 | default "3" |
c7f81c94 | 423 | |
0a049bb0 | 424 | config X86_DEBUGCTLMSR |
96daa8cd | 425 | def_bool y |
5641f1fd | 426 | depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML |
8d02c211 TP |
427 | |
428 | menuconfig PROCESSOR_SELECT | |
6a108a14 | 429 | bool "Supported processor vendors" if EXPERT |
8f9ca475 | 430 | ---help--- |
8d02c211 TP |
431 | This lets you choose what x86 vendor support code your kernel |
432 | will include. | |
433 | ||
879d792b | 434 | config CPU_SUP_INTEL |
8d02c211 TP |
435 | default y |
436 | bool "Support Intel processors" if PROCESSOR_SELECT | |
8f9ca475 | 437 | ---help--- |
b7b3a425 IM |
438 | This enables detection, tunings and quirks for Intel processors |
439 | ||
440 | You need this enabled if you want your kernel to run on an | |
441 | Intel CPU. Disabling this option on other types of CPUs | |
442 | makes the kernel a tiny bit smaller. Disabling it on an Intel | |
443 | CPU might render the kernel unbootable. | |
444 | ||
445 | If unsure, say N. | |
8d02c211 TP |
446 | |
447 | config CPU_SUP_CYRIX_32 | |
448 | default y | |
449 | bool "Support Cyrix processors" if PROCESSOR_SELECT | |
450 | depends on !64BIT | |
8f9ca475 | 451 | ---help--- |
b7b3a425 IM |
452 | This enables detection, tunings and quirks for Cyrix processors |
453 | ||
454 | You need this enabled if you want your kernel to run on a | |
455 | Cyrix CPU. Disabling this option on other types of CPUs | |
456 | makes the kernel a tiny bit smaller. Disabling it on a Cyrix | |
457 | CPU might render the kernel unbootable. | |
458 | ||
459 | If unsure, say N. | |
8d02c211 | 460 | |
ff73152c | 461 | config CPU_SUP_AMD |
8d02c211 TP |
462 | default y |
463 | bool "Support AMD processors" if PROCESSOR_SELECT | |
8f9ca475 | 464 | ---help--- |
b7b3a425 IM |
465 | This enables detection, tunings and quirks for AMD processors |
466 | ||
467 | You need this enabled if you want your kernel to run on an | |
468 | AMD CPU. Disabling this option on other types of CPUs | |
469 | makes the kernel a tiny bit smaller. Disabling it on an AMD | |
470 | CPU might render the kernel unbootable. | |
471 | ||
472 | If unsure, say N. | |
8d02c211 | 473 | |
48f4c485 | 474 | config CPU_SUP_CENTAUR |
8d02c211 TP |
475 | default y |
476 | bool "Support Centaur processors" if PROCESSOR_SELECT | |
8f9ca475 | 477 | ---help--- |
b7b3a425 IM |
478 | This enables detection, tunings and quirks for Centaur processors |
479 | ||
480 | You need this enabled if you want your kernel to run on a | |
481 | Centaur CPU. Disabling this option on other types of CPUs | |
482 | makes the kernel a tiny bit smaller. Disabling it on a Centaur | |
483 | CPU might render the kernel unbootable. | |
484 | ||
485 | If unsure, say N. | |
8d02c211 TP |
486 | |
487 | config CPU_SUP_TRANSMETA_32 | |
488 | default y | |
489 | bool "Support Transmeta processors" if PROCESSOR_SELECT | |
490 | depends on !64BIT | |
8f9ca475 | 491 | ---help--- |
b7b3a425 IM |
492 | This enables detection, tunings and quirks for Transmeta processors |
493 | ||
494 | You need this enabled if you want your kernel to run on a | |
495 | Transmeta CPU. Disabling this option on other types of CPUs | |
496 | makes the kernel a tiny bit smaller. Disabling it on a Transmeta | |
497 | CPU might render the kernel unbootable. | |
498 | ||
499 | If unsure, say N. | |
8d02c211 TP |
500 | |
501 | config CPU_SUP_UMC_32 | |
502 | default y | |
503 | bool "Support UMC processors" if PROCESSOR_SELECT | |
504 | depends on !64BIT | |
8f9ca475 | 505 | ---help--- |
b7b3a425 IM |
506 | This enables detection, tunings and quirks for UMC processors |
507 | ||
508 | You need this enabled if you want your kernel to run on a | |
509 | UMC CPU. Disabling this option on other types of CPUs | |
510 | makes the kernel a tiny bit smaller. Disabling it on a UMC | |
511 | CPU might render the kernel unbootable. | |
512 | ||
513 | If unsure, say N. |