[deliverable/linux.git] / arch / x86 / boot / cpucheck.c

/* -*- linux-c -*- ------------------------------------------------------- *
 *
 *   Copyright (C) 1991, 1992 Linus Torvalds
 *   Copyright 2007 rPath, Inc. - All Rights Reserved
 *
 *   This file is part of the Linux kernel, and is made available under
 *   the terms of the GNU General Public License version 2.
 *
 * ----------------------------------------------------------------------- */

/*
 * Check for obligatory CPU features and abort if the features are not
 * present.  This code should be compilable as 16-, 32- or 64-bit
 * code, so be very careful with types and inline assembly.
 *
 * This code should not contain any messages; that requires an
 * additional wrapper.
 *
 * As written, this code is not safe for inclusion into the kernel
 * proper (after FPU initialization, in particular).
 */

#ifdef _SETUP
# include "boot.h"
#endif
#include <linux/types.h>
#include <asm/processor-flags.h>
#include <asm/required-features.h>
#include <asm/msr-index.h>

static u32 err_flags[NCAPINTS];

static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;

static const u32 req_flags[NCAPINTS] =
{
	REQUIRED_MASK0,
	REQUIRED_MASK1,
	0, /* REQUIRED_MASK2 not implemented in this file */
	0, /* REQUIRED_MASK3 not implemented in this file */
	REQUIRED_MASK4,
	0, /* REQUIRED_MASK5 not implemented in this file */
	REQUIRED_MASK6,
	0, /* REQUIRED_MASK7 not implemented in this file */
};

#define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))

static int is_amd(void)
{
	return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
	       cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
	       cpu_vendor[2] == A32('c', 'A', 'M', 'D');
}

static int is_centaur(void)
{
	return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
	       cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
	       cpu_vendor[2] == A32('a', 'u', 'l', 's');
}

static int is_transmeta(void)
{
	return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
	       cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
	       cpu_vendor[2] == A32('M', 'x', '8', '6');
}

/* Returns a bitmask of which words we have error bits in */
static int check_cpuflags(void)
{
	u32 err;
	int i;

	err = 0;
	for (i = 0; i < NCAPINTS; i++) {
		err_flags[i] = req_flags[i] & ~cpu.flags[i];
		if (err_flags[i])
			err |= 1 << i;
	}

	return err;
}

/*
 * Returns -1 on error.
 *
 * *cpu_level is set to the current CPU level; *req_level to the required
 * level.  x86-64 is considered level 64 for this purpose.
 *
 * *err_flags_ptr is set to the flags error array if there are flags missing.
 */
int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
{
	int err;

	memset(&cpu.flags, 0, sizeof cpu.flags);
	cpu.level = 3;

	if (has_eflag(X86_EFLAGS_AC))
		cpu.level = 4;

	get_cpuflags();
	err = check_cpuflags();

	if (test_bit(X86_FEATURE_LM, cpu.flags))
		cpu.level = 64;

	if (err == 0x01 &&
	    !(err_flags[0] &
	      ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
	    is_amd()) {
		/* If this is an AMD and we're only missing SSE+SSE2, try to
		   turn them on */

		u32 ecx = MSR_K7_HWCR;
		u32 eax, edx;

		asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
		eax &= ~(1 << 15);
		asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));

		get_cpuflags();	/* Make sure it really did something */
		err = check_cpuflags();
	} else if (err == 0x01 &&
		   !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
		   is_centaur() && cpu.model >= 6) {
		/* If this is a VIA C3, we might have to enable CX8
		   explicitly */

		u32 ecx = MSR_VIA_FCR;
		u32 eax, edx;

		asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
		eax |= (1<<1)|(1<<7);
		asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));

		set_bit(X86_FEATURE_CX8, cpu.flags);
		err = check_cpuflags();
	} else if (err == 0x01 && is_transmeta()) {
		/* Transmeta might have masked feature bits in word 0 */

		u32 ecx = 0x80860004;
		u32 eax, edx;
		u32 level = 1;

		asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
		asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
		asm("cpuid"
		    : "+a" (level), "=d" (cpu.flags[0])
		    : : "ecx", "ebx");
		asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));

		err = check_cpuflags();
	}

	if (err_flags_ptr)
		*err_flags_ptr = err ? err_flags : NULL;
	if (cpu_level_ptr)
		*cpu_level_ptr = cpu.level;
	if (req_level_ptr)
		*req_level_ptr = req_level;

	return (cpu.level < req_level || err) ? -1 : 0;
}
Commit	Line	Data
31b54f40 PA	1	/* -- linux-c -- ------------------------------------------------------- *
	2	*
	3	* Copyright (C) 1991, 1992 Linus Torvalds
	4	* Copyright 2007 rPath, Inc. - All Rights Reserved
	5	*
	6	* This file is part of the Linux kernel, and is made available under
	7	* the terms of the GNU General Public License version 2.
	8	*
	9	* ----------------------------------------------------------------------- */
	10
	11	/*
31b54f40 PA	12	* Check for obligatory CPU features and abort if the features are not
	13	* present. This code should be compilable as 16-, 32- or 64-bit
	14	* code, so be very careful with types and inline assembly.
	15	*
	16	* This code should not contain any messages; that requires an
	17	* additional wrapper.
	18	*
	19	* As written, this code is not safe for inclusion into the kernel
	20	* proper (after FPU initialization, in particular).
	21	*/
	22
	23	#ifdef _SETUP
	24	# include "boot.h"
31b54f40 PA	25	#endif
31b54f40 PA	26	#include <linux/types.h>
31b54f40 PA	27	#include <asm/processor-flags.h>
	28	#include <asm/required-features.h>
	29	#include <asm/msr-index.h>
	30
31b54f40 PA	31	static u32 err_flags[NCAPINTS];
31b54f40 PA	32
31b54f40	33	static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
31b54f40 PA	34
	35	static const u32 req_flags[NCAPINTS] =
	36	{
	37	REQUIRED_MASK0,
	38	REQUIRED_MASK1,
b74b06c5 PA	39	0, /* REQUIRED_MASK2 not implemented in this file */
b74b06c5 PA	40	0, /* REQUIRED_MASK3 not implemented in this file */
31b54f40	41	REQUIRED_MASK4,
b74b06c5	42	0, /* REQUIRED_MASK5 not implemented in this file */
31b54f40	43	REQUIRED_MASK6,
b74b06c5	44	0, /* REQUIRED_MASK7 not implemented in this file */
31b54f40 PA	45	};
31b54f40 PA	46
7030760a	47	#define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
31b54f40 PA	48
	49	static int is_amd(void)
	50	{
7030760a PC	51	return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
	52	cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
	53	cpu_vendor[2] == A32('c', 'A', 'M', 'D');
31b54f40 PA	54	}
	55
	56	static int is_centaur(void)
	57	{
7030760a PC	58	return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
	59	cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
	60	cpu_vendor[2] == A32('a', 'u', 'l', 's');
31b54f40 PA	61	}
	62
	63	static int is_transmeta(void)
	64	{
7030760a PC	65	return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
	66	cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
	67	cpu_vendor[2] == A32('M', 'x', '8', '6');
31b54f40 PA	68	}
31b54f40 PA	69
31b54f40	70	/* Returns a bitmask of which words we have error bits in */
6e6a4932	71	static int check_cpuflags(void)
31b54f40 PA	72	{
	73	u32 err;
	74	int i;
	75
	76	err = 0;
	77	for (i = 0; i < NCAPINTS; i++) {
	78	err_flags[i] = req_flags[i] & ~cpu.flags[i];
	79	if (err_flags[i])
	80	err \|= 1 << i;
	81	}
	82
	83	return err;
	84	}
	85
	86	/*
	87	* Returns -1 on error.
	88	*
	89	* cpu_level is set to the current CPU level; req_level to the required
	90	* level. x86-64 is considered level 64 for this purpose.
	91	*
	92	* *err_flags_ptr is set to the flags error array if there are flags missing.
	93	*/
	94	int check_cpu(int cpu_level_ptr, int req_level_ptr, u32 **err_flags_ptr)
	95	{
	96	int err;
	97
	98	memset(&cpu.flags, 0, sizeof cpu.flags);
	99	cpu.level = 3;
	100
	101	if (has_eflag(X86_EFLAGS_AC))
	102	cpu.level = 4;
	103
6e6a4932 PA	104	get_cpuflags();
6e6a4932 PA	105	err = check_cpuflags();
31b54f40 PA	106
	107	if (test_bit(X86_FEATURE_LM, cpu.flags))
	108	cpu.level = 64;
	109
	110	if (err == 0x01 &&
	111	!(err_flags[0] &
	112	~((1 << X86_FEATURE_XMM)\|(1 << X86_FEATURE_XMM2))) &&
	113	is_amd()) {
	114	/* If this is an AMD and we're only missing SSE+SSE2, try to
	115	turn them on */
	116
	117	u32 ecx = MSR_K7_HWCR;
	118	u32 eax, edx;
	119
	120	asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
	121	eax &= ~(1 << 15);
	122	asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
	123
6e6a4932 PA	124	get_cpuflags(); /* Make sure it really did something */
6e6a4932 PA	125	err = check_cpuflags();
31b54f40 PA	126	} else if (err == 0x01 &&
	127	!(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
	128	is_centaur() && cpu.model >= 6) {
	129	/* If this is a VIA C3, we might have to enable CX8
	130	explicitly */
	131
	132	u32 ecx = MSR_VIA_FCR;
	133	u32 eax, edx;
	134
	135	asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
	136	eax \|= (1<<1)\|(1<<7);
	137	asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
	138
	139	set_bit(X86_FEATURE_CX8, cpu.flags);
6e6a4932	140	err = check_cpuflags();
31b54f40 PA	141	} else if (err == 0x01 && is_transmeta()) {
	142	/* Transmeta might have masked feature bits in word 0 */
	143
	144	u32 ecx = 0x80860004;
	145	u32 eax, edx;
	146	u32 level = 1;
	147
	148	asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
	149	asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
	150	asm("cpuid"
	151	: "+a" (level), "=d" (cpu.flags[0])
	152	: : "ecx", "ebx");
	153	asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
	154
6e6a4932	155	err = check_cpuflags();
31b54f40 PA	156	}
	157
	158	if (err_flags_ptr)
	159	*err_flags_ptr = err ? err_flags : NULL;
	160	if (cpu_level_ptr)
	161	*cpu_level_ptr = cpu.level;
	162	if (req_level_ptr)
	163	*req_level_ptr = req_level;
	164
	165	return (cpu.level < req_level \|\| err) ? -1 : 0;
	166	}