Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
90eec103 | 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
7911d3f7 | 34 | #include <asm/mmu_context.h> |
375074cc | 35 | #include <asm/tlbflush.h> |
e3f3541c | 36 | #include <asm/timer.h> |
d07bdfd3 PZ |
37 | #include <asm/desc.h> |
38 | #include <asm/ldt.h> | |
241771ef | 39 | |
27f6d22b | 40 | #include "perf_event.h" |
de0428a7 | 41 | |
de0428a7 | 42 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 43 | |
de0428a7 | 44 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
45 | .enabled = 1, |
46 | }; | |
241771ef | 47 | |
a6673429 AL |
48 | struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE; |
49 | ||
de0428a7 | 50 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
51 | [PERF_COUNT_HW_CACHE_MAX] |
52 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
53 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 54 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
55 | [PERF_COUNT_HW_CACHE_MAX] |
56 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
57 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 58 | |
ee06094f | 59 | /* |
cdd6c482 IM |
60 | * Propagate event elapsed time into the generic event. |
61 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
62 | * Returns the delta events processed. |
63 | */ | |
de0428a7 | 64 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 65 | { |
cc2ad4ba | 66 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 67 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 68 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 69 | int idx = hwc->idx; |
ec3232bd | 70 | s64 delta; |
ee06094f | 71 | |
15c7ad51 | 72 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
73 | return 0; |
74 | ||
ee06094f | 75 | /* |
cdd6c482 | 76 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
77 | * |
78 | * Our tactic to handle this is to first atomically read and | |
79 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 80 | * count to the generic event atomically: |
ee06094f IM |
81 | */ |
82 | again: | |
e7850595 | 83 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 84 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 85 | |
e7850595 | 86 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
87 | new_raw_count) != prev_raw_count) |
88 | goto again; | |
89 | ||
90 | /* | |
91 | * Now we have the new raw value and have updated the prev | |
92 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 93 | * (event-)time and add that to the generic event. |
ee06094f IM |
94 | * |
95 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 96 | * of the count. |
ee06094f | 97 | */ |
ec3232bd PZ |
98 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
99 | delta >>= shift; | |
ee06094f | 100 | |
e7850595 PZ |
101 | local64_add(delta, &event->count); |
102 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
103 | |
104 | return new_raw_count; | |
ee06094f IM |
105 | } |
106 | ||
a7e3ed1e AK |
107 | /* |
108 | * Find and validate any extra registers to set up. | |
109 | */ | |
110 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
111 | { | |
efc9f05d | 112 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
113 | struct extra_reg *er; |
114 | ||
efc9f05d | 115 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
116 | |
117 | if (!x86_pmu.extra_regs) | |
118 | return 0; | |
119 | ||
120 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
121 | if (er->event != (config & er->config_mask)) | |
122 | continue; | |
123 | if (event->attr.config1 & ~er->valid_mask) | |
124 | return -EINVAL; | |
338b522c KL |
125 | /* Check if the extra msrs can be safely accessed*/ |
126 | if (!er->extra_msr_access) | |
127 | return -ENXIO; | |
efc9f05d SE |
128 | |
129 | reg->idx = er->idx; | |
130 | reg->config = event->attr.config1; | |
131 | reg->reg = er->msr; | |
a7e3ed1e AK |
132 | break; |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
cdd6c482 | 137 | static atomic_t active_events; |
1b7b938f | 138 | static atomic_t pmc_refcount; |
4e935e47 PZ |
139 | static DEFINE_MUTEX(pmc_reserve_mutex); |
140 | ||
b27ea29c RR |
141 | #ifdef CONFIG_X86_LOCAL_APIC |
142 | ||
4e935e47 PZ |
143 | static bool reserve_pmc_hardware(void) |
144 | { | |
145 | int i; | |
146 | ||
948b1bb8 | 147 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 148 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
149 | goto perfctr_fail; |
150 | } | |
151 | ||
948b1bb8 | 152 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 153 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
154 | goto eventsel_fail; |
155 | } | |
156 | ||
157 | return true; | |
158 | ||
159 | eventsel_fail: | |
160 | for (i--; i >= 0; i--) | |
41bf4989 | 161 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 162 | |
948b1bb8 | 163 | i = x86_pmu.num_counters; |
4e935e47 PZ |
164 | |
165 | perfctr_fail: | |
166 | for (i--; i >= 0; i--) | |
41bf4989 | 167 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 168 | |
4e935e47 PZ |
169 | return false; |
170 | } | |
171 | ||
172 | static void release_pmc_hardware(void) | |
173 | { | |
174 | int i; | |
175 | ||
948b1bb8 | 176 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
177 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
178 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 179 | } |
4e935e47 PZ |
180 | } |
181 | ||
b27ea29c RR |
182 | #else |
183 | ||
184 | static bool reserve_pmc_hardware(void) { return true; } | |
185 | static void release_pmc_hardware(void) {} | |
186 | ||
187 | #endif | |
188 | ||
33c6d6a7 DZ |
189 | static bool check_hw_exists(void) |
190 | { | |
a5ebe0ba GD |
191 | u64 val, val_fail, val_new= ~0; |
192 | int i, reg, reg_fail, ret = 0; | |
193 | int bios_fail = 0; | |
68ab7476 | 194 | int reg_safe = -1; |
33c6d6a7 | 195 | |
4407204c PZ |
196 | /* |
197 | * Check to see if the BIOS enabled any of the counters, if so | |
198 | * complain and bail. | |
199 | */ | |
200 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 201 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
202 | ret = rdmsrl_safe(reg, &val); |
203 | if (ret) | |
204 | goto msr_fail; | |
a5ebe0ba GD |
205 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
206 | bios_fail = 1; | |
207 | val_fail = val; | |
208 | reg_fail = reg; | |
68ab7476 DZ |
209 | } else { |
210 | reg_safe = i; | |
a5ebe0ba | 211 | } |
4407204c PZ |
212 | } |
213 | ||
214 | if (x86_pmu.num_counters_fixed) { | |
215 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
216 | ret = rdmsrl_safe(reg, &val); | |
217 | if (ret) | |
218 | goto msr_fail; | |
219 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
220 | if (val & (0x03 << i*4)) { |
221 | bios_fail = 1; | |
222 | val_fail = val; | |
223 | reg_fail = reg; | |
224 | } | |
4407204c PZ |
225 | } |
226 | } | |
227 | ||
68ab7476 DZ |
228 | /* |
229 | * If all the counters are enabled, the below test will always | |
230 | * fail. The tools will also become useless in this scenario. | |
231 | * Just fail and disable the hardware counters. | |
232 | */ | |
233 | ||
234 | if (reg_safe == -1) { | |
235 | reg = reg_safe; | |
236 | goto msr_fail; | |
237 | } | |
238 | ||
4407204c | 239 | /* |
bffd5fc2 AP |
240 | * Read the current value, change it and read it back to see if it |
241 | * matches, this is needed to detect certain hardware emulators | |
242 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 243 | */ |
68ab7476 | 244 | reg = x86_pmu_event_addr(reg_safe); |
bffd5fc2 AP |
245 | if (rdmsrl_safe(reg, &val)) |
246 | goto msr_fail; | |
247 | val ^= 0xffffUL; | |
f285f92f RR |
248 | ret = wrmsrl_safe(reg, val); |
249 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 250 | if (ret || val != val_new) |
4407204c | 251 | goto msr_fail; |
33c6d6a7 | 252 | |
45daae57 IM |
253 | /* |
254 | * We still allow the PMU driver to operate: | |
255 | */ | |
a5ebe0ba | 256 | if (bios_fail) { |
1b74dde7 CY |
257 | pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); |
258 | pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", | |
259 | reg_fail, val_fail); | |
a5ebe0ba | 260 | } |
45daae57 IM |
261 | |
262 | return true; | |
4407204c PZ |
263 | |
264 | msr_fail: | |
1b74dde7 CY |
265 | pr_cont("Broken PMU hardware detected, using software events only.\n"); |
266 | pr_info("%sFailed to access perfctr msr (MSR %x is %Lx)\n", | |
65d71fe1 PZI |
267 | boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR, |
268 | reg, val_new); | |
45daae57 | 269 | |
4407204c | 270 | return false; |
33c6d6a7 DZ |
271 | } |
272 | ||
cdd6c482 | 273 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 274 | { |
6b099d9b | 275 | x86_release_hardware(); |
1b7b938f | 276 | atomic_dec(&active_events); |
4e935e47 PZ |
277 | } |
278 | ||
48070342 AS |
279 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
280 | { | |
281 | hw_perf_event_destroy(event); | |
282 | ||
283 | /* undo the lbr/bts event accounting */ | |
284 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
285 | } | |
286 | ||
85cf9dba RR |
287 | static inline int x86_pmu_initialized(void) |
288 | { | |
289 | return x86_pmu.handle_irq != NULL; | |
290 | } | |
291 | ||
8326f44d | 292 | static inline int |
e994d7d2 | 293 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 294 | { |
e994d7d2 | 295 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
296 | unsigned int cache_type, cache_op, cache_result; |
297 | u64 config, val; | |
298 | ||
299 | config = attr->config; | |
300 | ||
301 | cache_type = (config >> 0) & 0xff; | |
302 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
303 | return -EINVAL; | |
304 | ||
305 | cache_op = (config >> 8) & 0xff; | |
306 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
307 | return -EINVAL; | |
308 | ||
309 | cache_result = (config >> 16) & 0xff; | |
310 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
311 | return -EINVAL; | |
312 | ||
313 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
314 | ||
315 | if (val == 0) | |
316 | return -ENOENT; | |
317 | ||
318 | if (val == -1) | |
319 | return -EINVAL; | |
320 | ||
321 | hwc->config |= val; | |
e994d7d2 AK |
322 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
323 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
324 | } |
325 | ||
6b099d9b AS |
326 | int x86_reserve_hardware(void) |
327 | { | |
328 | int err = 0; | |
329 | ||
1b7b938f | 330 | if (!atomic_inc_not_zero(&pmc_refcount)) { |
6b099d9b | 331 | mutex_lock(&pmc_reserve_mutex); |
1b7b938f | 332 | if (atomic_read(&pmc_refcount) == 0) { |
6b099d9b AS |
333 | if (!reserve_pmc_hardware()) |
334 | err = -EBUSY; | |
335 | else | |
336 | reserve_ds_buffers(); | |
337 | } | |
338 | if (!err) | |
1b7b938f | 339 | atomic_inc(&pmc_refcount); |
6b099d9b AS |
340 | mutex_unlock(&pmc_reserve_mutex); |
341 | } | |
342 | ||
343 | return err; | |
344 | } | |
345 | ||
346 | void x86_release_hardware(void) | |
347 | { | |
1b7b938f | 348 | if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { |
6b099d9b AS |
349 | release_pmc_hardware(); |
350 | release_ds_buffers(); | |
351 | mutex_unlock(&pmc_reserve_mutex); | |
352 | } | |
353 | } | |
354 | ||
48070342 AS |
355 | /* |
356 | * Check if we can create event of a certain type (that no conflicting events | |
357 | * are present). | |
358 | */ | |
359 | int x86_add_exclusive(unsigned int what) | |
360 | { | |
93472aff | 361 | int i; |
48070342 | 362 | |
93472aff PZ |
363 | if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { |
364 | mutex_lock(&pmc_reserve_mutex); | |
365 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { | |
366 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
367 | goto fail_unlock; | |
368 | } | |
369 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
370 | mutex_unlock(&pmc_reserve_mutex); | |
6b099d9b | 371 | } |
48070342 | 372 | |
93472aff PZ |
373 | atomic_inc(&active_events); |
374 | return 0; | |
48070342 | 375 | |
93472aff | 376 | fail_unlock: |
48070342 | 377 | mutex_unlock(&pmc_reserve_mutex); |
93472aff | 378 | return -EBUSY; |
48070342 AS |
379 | } |
380 | ||
381 | void x86_del_exclusive(unsigned int what) | |
382 | { | |
383 | atomic_dec(&x86_pmu.lbr_exclusive[what]); | |
1b7b938f | 384 | atomic_dec(&active_events); |
48070342 AS |
385 | } |
386 | ||
de0428a7 | 387 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
388 | { |
389 | struct perf_event_attr *attr = &event->attr; | |
390 | struct hw_perf_event *hwc = &event->hw; | |
391 | u64 config; | |
392 | ||
6c7e550f | 393 | if (!is_sampling_event(event)) { |
c1726f34 RR |
394 | hwc->sample_period = x86_pmu.max_period; |
395 | hwc->last_period = hwc->sample_period; | |
e7850595 | 396 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
397 | } |
398 | ||
399 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 400 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
401 | |
402 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 403 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
404 | |
405 | if (attr->config >= x86_pmu.max_events) | |
406 | return -EINVAL; | |
407 | ||
408 | /* | |
409 | * The generic map: | |
410 | */ | |
411 | config = x86_pmu.event_map(attr->config); | |
412 | ||
413 | if (config == 0) | |
414 | return -ENOENT; | |
415 | ||
416 | if (config == -1LL) | |
417 | return -EINVAL; | |
418 | ||
419 | /* | |
420 | * Branch tracing: | |
421 | */ | |
18a073a3 PZ |
422 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
423 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 424 | /* BTS is not supported by this architecture. */ |
6809b6ea | 425 | if (!x86_pmu.bts_active) |
c1726f34 RR |
426 | return -EOPNOTSUPP; |
427 | ||
428 | /* BTS is currently only allowed for user-mode. */ | |
429 | if (!attr->exclude_kernel) | |
430 | return -EOPNOTSUPP; | |
48070342 AS |
431 | |
432 | /* disallow bts if conflicting events are present */ | |
433 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
434 | return -EBUSY; | |
435 | ||
436 | event->destroy = hw_perf_lbr_event_destroy; | |
c1726f34 RR |
437 | } |
438 | ||
439 | hwc->config |= config; | |
440 | ||
441 | return 0; | |
442 | } | |
4261e0e0 | 443 | |
ff3fb511 SE |
444 | /* |
445 | * check that branch_sample_type is compatible with | |
446 | * settings needed for precise_ip > 1 which implies | |
447 | * using the LBR to capture ALL taken branches at the | |
448 | * priv levels of the measurement | |
449 | */ | |
450 | static inline int precise_br_compat(struct perf_event *event) | |
451 | { | |
452 | u64 m = event->attr.branch_sample_type; | |
453 | u64 b = 0; | |
454 | ||
455 | /* must capture all branches */ | |
456 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
457 | return 0; | |
458 | ||
459 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
460 | ||
461 | if (!event->attr.exclude_user) | |
462 | b |= PERF_SAMPLE_BRANCH_USER; | |
463 | ||
464 | if (!event->attr.exclude_kernel) | |
465 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
466 | ||
467 | /* | |
468 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
469 | */ | |
470 | ||
471 | return m == b; | |
472 | } | |
473 | ||
de0428a7 | 474 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 475 | { |
ab608344 PZ |
476 | if (event->attr.precise_ip) { |
477 | int precise = 0; | |
478 | ||
479 | /* Support for constant skid */ | |
c93dc84c | 480 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
481 | precise++; |
482 | ||
5553be26 | 483 | /* Support for IP fixup */ |
03de874a | 484 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 | 485 | precise++; |
72469764 AK |
486 | |
487 | if (x86_pmu.pebs_prec_dist) | |
488 | precise++; | |
5553be26 | 489 | } |
ab608344 PZ |
490 | |
491 | if (event->attr.precise_ip > precise) | |
492 | return -EOPNOTSUPP; | |
4b854900 YZ |
493 | } |
494 | /* | |
495 | * check that PEBS LBR correction does not conflict with | |
496 | * whatever the user is asking with attr->branch_sample_type | |
497 | */ | |
498 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
499 | u64 *br_type = &event->attr.branch_sample_type; | |
500 | ||
501 | if (has_branch_stack(event)) { | |
502 | if (!precise_br_compat(event)) | |
503 | return -EOPNOTSUPP; | |
504 | ||
505 | /* branch_sample_type is compatible */ | |
506 | ||
507 | } else { | |
508 | /* | |
509 | * user did not specify branch_sample_type | |
510 | * | |
511 | * For PEBS fixups, we capture all | |
512 | * the branches at the priv level of the | |
513 | * event. | |
514 | */ | |
515 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
516 | ||
517 | if (!event->attr.exclude_user) | |
518 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
519 | ||
520 | if (!event->attr.exclude_kernel) | |
521 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 522 | } |
ab608344 PZ |
523 | } |
524 | ||
e18bf526 YZ |
525 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
526 | event->attach_state |= PERF_ATTACH_TASK_DATA; | |
527 | ||
a072738e CG |
528 | /* |
529 | * Generate PMC IRQs: | |
530 | * (keep 'enabled' bit clear for now) | |
531 | */ | |
b4cdc5c2 | 532 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
533 | |
534 | /* | |
535 | * Count user and OS events unless requested not to | |
536 | */ | |
b4cdc5c2 PZ |
537 | if (!event->attr.exclude_user) |
538 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
539 | if (!event->attr.exclude_kernel) | |
540 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 541 | |
b4cdc5c2 PZ |
542 | if (event->attr.type == PERF_TYPE_RAW) |
543 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 544 | |
294fe0f5 AK |
545 | if (event->attr.sample_period && x86_pmu.limit_period) { |
546 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
547 | event->attr.sample_period) | |
548 | return -EINVAL; | |
549 | } | |
550 | ||
9d0fcba6 | 551 | return x86_setup_perfctr(event); |
a098f448 RR |
552 | } |
553 | ||
241771ef | 554 | /* |
0d48696f | 555 | * Setup the hardware configuration for a given attr_type |
241771ef | 556 | */ |
b0a873eb | 557 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 558 | { |
4e935e47 | 559 | int err; |
241771ef | 560 | |
85cf9dba RR |
561 | if (!x86_pmu_initialized()) |
562 | return -ENODEV; | |
241771ef | 563 | |
6b099d9b | 564 | err = x86_reserve_hardware(); |
4e935e47 PZ |
565 | if (err) |
566 | return err; | |
567 | ||
1b7b938f | 568 | atomic_inc(&active_events); |
cdd6c482 | 569 | event->destroy = hw_perf_event_destroy; |
a1792cda | 570 | |
4261e0e0 RR |
571 | event->hw.idx = -1; |
572 | event->hw.last_cpu = -1; | |
573 | event->hw.last_tag = ~0ULL; | |
b690081d | 574 | |
efc9f05d SE |
575 | /* mark unused */ |
576 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
577 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
578 | ||
9d0fcba6 | 579 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
580 | } |
581 | ||
de0428a7 | 582 | void x86_pmu_disable_all(void) |
f87ad35d | 583 | { |
89cbc767 | 584 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
585 | int idx; |
586 | ||
948b1bb8 | 587 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
588 | u64 val; |
589 | ||
43f6201a | 590 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 591 | continue; |
41bf4989 | 592 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 593 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 594 | continue; |
bb1165d6 | 595 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 596 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 597 | } |
f87ad35d JSR |
598 | } |
599 | ||
a4eaf7f1 | 600 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 601 | { |
89cbc767 | 602 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 603 | |
85cf9dba | 604 | if (!x86_pmu_initialized()) |
9e35ad38 | 605 | return; |
1da53e02 | 606 | |
1a6e21f7 PZ |
607 | if (!cpuc->enabled) |
608 | return; | |
609 | ||
610 | cpuc->n_added = 0; | |
611 | cpuc->enabled = 0; | |
612 | barrier(); | |
1da53e02 SE |
613 | |
614 | x86_pmu.disable_all(); | |
b56a3802 | 615 | } |
241771ef | 616 | |
de0428a7 | 617 | void x86_pmu_enable_all(int added) |
f87ad35d | 618 | { |
89cbc767 | 619 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
620 | int idx; |
621 | ||
948b1bb8 | 622 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 623 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 624 | |
43f6201a | 625 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 626 | continue; |
984b838c | 627 | |
d45dd923 | 628 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
629 | } |
630 | } | |
631 | ||
51b0fe39 | 632 | static struct pmu pmu; |
1da53e02 SE |
633 | |
634 | static inline int is_x86_event(struct perf_event *event) | |
635 | { | |
636 | return event->pmu == &pmu; | |
637 | } | |
638 | ||
1e2ad28f RR |
639 | /* |
640 | * Event scheduler state: | |
641 | * | |
642 | * Assign events iterating over all events and counters, beginning | |
643 | * with events with least weights first. Keep the current iterator | |
644 | * state in struct sched_state. | |
645 | */ | |
646 | struct sched_state { | |
647 | int weight; | |
648 | int event; /* event index */ | |
649 | int counter; /* counter index */ | |
650 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 651 | int nr_gp; /* number of GP counters used */ |
1e2ad28f RR |
652 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
653 | }; | |
654 | ||
bc1738f6 RR |
655 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
656 | #define SCHED_STATES_MAX 2 | |
657 | ||
1e2ad28f RR |
658 | struct perf_sched { |
659 | int max_weight; | |
660 | int max_events; | |
cc1790cf PZ |
661 | int max_gp; |
662 | int saved_states; | |
b371b594 | 663 | struct event_constraint **constraints; |
1e2ad28f | 664 | struct sched_state state; |
bc1738f6 | 665 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
666 | }; |
667 | ||
668 | /* | |
669 | * Initialize interator that runs through all events and counters. | |
670 | */ | |
b371b594 | 671 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 672 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
673 | { |
674 | int idx; | |
675 | ||
676 | memset(sched, 0, sizeof(*sched)); | |
677 | sched->max_events = num; | |
678 | sched->max_weight = wmax; | |
cc1790cf | 679 | sched->max_gp = gpmax; |
b371b594 | 680 | sched->constraints = constraints; |
1e2ad28f RR |
681 | |
682 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 683 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
684 | break; |
685 | } | |
686 | ||
687 | sched->state.event = idx; /* start with min weight */ | |
688 | sched->state.weight = wmin; | |
689 | sched->state.unassigned = num; | |
690 | } | |
691 | ||
bc1738f6 RR |
692 | static void perf_sched_save_state(struct perf_sched *sched) |
693 | { | |
694 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
695 | return; | |
696 | ||
697 | sched->saved[sched->saved_states] = sched->state; | |
698 | sched->saved_states++; | |
699 | } | |
700 | ||
701 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
702 | { | |
703 | if (!sched->saved_states) | |
704 | return false; | |
705 | ||
706 | sched->saved_states--; | |
707 | sched->state = sched->saved[sched->saved_states]; | |
708 | ||
709 | /* continue with next counter: */ | |
710 | clear_bit(sched->state.counter++, sched->state.used); | |
711 | ||
712 | return true; | |
713 | } | |
714 | ||
1e2ad28f RR |
715 | /* |
716 | * Select a counter for the current event to schedule. Return true on | |
717 | * success. | |
718 | */ | |
bc1738f6 | 719 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
720 | { |
721 | struct event_constraint *c; | |
722 | int idx; | |
723 | ||
724 | if (!sched->state.unassigned) | |
725 | return false; | |
726 | ||
727 | if (sched->state.event >= sched->max_events) | |
728 | return false; | |
729 | ||
b371b594 | 730 | c = sched->constraints[sched->state.event]; |
4defea85 | 731 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
732 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
733 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 734 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
735 | if (!__test_and_set_bit(idx, sched->state.used)) |
736 | goto done; | |
737 | } | |
738 | } | |
cc1790cf | 739 | |
1e2ad28f RR |
740 | /* Grab the first unused counter starting with idx */ |
741 | idx = sched->state.counter; | |
15c7ad51 | 742 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
cc1790cf PZ |
743 | if (!__test_and_set_bit(idx, sched->state.used)) { |
744 | if (sched->state.nr_gp++ >= sched->max_gp) | |
745 | return false; | |
746 | ||
4defea85 | 747 | goto done; |
cc1790cf | 748 | } |
1e2ad28f | 749 | } |
1e2ad28f | 750 | |
4defea85 PZ |
751 | return false; |
752 | ||
753 | done: | |
754 | sched->state.counter = idx; | |
1e2ad28f | 755 | |
bc1738f6 RR |
756 | if (c->overlap) |
757 | perf_sched_save_state(sched); | |
758 | ||
759 | return true; | |
760 | } | |
761 | ||
762 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
763 | { | |
764 | while (!__perf_sched_find_counter(sched)) { | |
765 | if (!perf_sched_restore_state(sched)) | |
766 | return false; | |
767 | } | |
768 | ||
1e2ad28f RR |
769 | return true; |
770 | } | |
771 | ||
772 | /* | |
773 | * Go through all unassigned events and find the next one to schedule. | |
774 | * Take events with the least weight first. Return true on success. | |
775 | */ | |
776 | static bool perf_sched_next_event(struct perf_sched *sched) | |
777 | { | |
778 | struct event_constraint *c; | |
779 | ||
780 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
781 | return false; | |
782 | ||
783 | do { | |
784 | /* next event */ | |
785 | sched->state.event++; | |
786 | if (sched->state.event >= sched->max_events) { | |
787 | /* next weight */ | |
788 | sched->state.event = 0; | |
789 | sched->state.weight++; | |
790 | if (sched->state.weight > sched->max_weight) | |
791 | return false; | |
792 | } | |
b371b594 | 793 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
794 | } while (c->weight != sched->state.weight); |
795 | ||
796 | sched->state.counter = 0; /* start with first counter */ | |
797 | ||
798 | return true; | |
799 | } | |
800 | ||
801 | /* | |
802 | * Assign a counter for each event. | |
803 | */ | |
b371b594 | 804 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 805 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
806 | { |
807 | struct perf_sched sched; | |
808 | ||
cc1790cf | 809 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
810 | |
811 | do { | |
812 | if (!perf_sched_find_counter(&sched)) | |
813 | break; /* failed */ | |
814 | if (assign) | |
815 | assign[sched.state.event] = sched.state.counter; | |
816 | } while (perf_sched_next_event(&sched)); | |
817 | ||
818 | return sched.state.unassigned; | |
819 | } | |
4a3dc121 | 820 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 821 | |
de0428a7 | 822 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 823 | { |
43b45780 | 824 | struct event_constraint *c; |
1da53e02 | 825 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 826 | struct perf_event *e; |
e979121b | 827 | int i, wmin, wmax, unsched = 0; |
1da53e02 SE |
828 | struct hw_perf_event *hwc; |
829 | ||
830 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
831 | ||
c5362c0c MD |
832 | if (x86_pmu.start_scheduling) |
833 | x86_pmu.start_scheduling(cpuc); | |
834 | ||
1e2ad28f | 835 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b371b594 | 836 | cpuc->event_constraint[i] = NULL; |
79cba822 | 837 | c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); |
b371b594 | 838 | cpuc->event_constraint[i] = c; |
43b45780 | 839 | |
1e2ad28f RR |
840 | wmin = min(wmin, c->weight); |
841 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
842 | } |
843 | ||
8113070d SE |
844 | /* |
845 | * fastpath, try to reuse previous register | |
846 | */ | |
c933c1a6 | 847 | for (i = 0; i < n; i++) { |
8113070d | 848 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 849 | c = cpuc->event_constraint[i]; |
8113070d SE |
850 | |
851 | /* never assigned */ | |
852 | if (hwc->idx == -1) | |
853 | break; | |
854 | ||
855 | /* constraint still honored */ | |
63b14649 | 856 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
857 | break; |
858 | ||
859 | /* not already used */ | |
860 | if (test_bit(hwc->idx, used_mask)) | |
861 | break; | |
862 | ||
34538ee7 | 863 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
864 | if (assign) |
865 | assign[i] = hwc->idx; | |
866 | } | |
8113070d | 867 | |
1e2ad28f | 868 | /* slow path */ |
b371b594 | 869 | if (i != n) { |
cc1790cf PZ |
870 | int gpmax = x86_pmu.num_counters; |
871 | ||
872 | /* | |
873 | * Do not allow scheduling of more than half the available | |
874 | * generic counters. | |
875 | * | |
876 | * This helps avoid counter starvation of sibling thread by | |
877 | * ensuring at most half the counters cannot be in exclusive | |
878 | * mode. There is no designated counters for the limits. Any | |
879 | * N/2 counters can be used. This helps with events with | |
880 | * specific counter constraints. | |
881 | */ | |
882 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
883 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
884 | gpmax /= 2; | |
885 | ||
b371b594 | 886 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 887 | wmax, gpmax, assign); |
b371b594 | 888 | } |
8113070d | 889 | |
2f7f73a5 | 890 | /* |
e979121b MD |
891 | * In case of success (unsched = 0), mark events as committed, |
892 | * so we do not put_constraint() in case new events are added | |
893 | * and fail to be scheduled | |
894 | * | |
895 | * We invoke the lower level commit callback to lock the resource | |
896 | * | |
897 | * We do not need to do all of this in case we are called to | |
898 | * validate an event group (assign == NULL) | |
2f7f73a5 | 899 | */ |
e979121b | 900 | if (!unsched && assign) { |
2f7f73a5 SE |
901 | for (i = 0; i < n; i++) { |
902 | e = cpuc->event_list[i]; | |
903 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
c5362c0c | 904 | if (x86_pmu.commit_scheduling) |
b371b594 | 905 | x86_pmu.commit_scheduling(cpuc, i, assign[i]); |
2f7f73a5 | 906 | } |
8736e548 | 907 | } else { |
1da53e02 | 908 | for (i = 0; i < n; i++) { |
2f7f73a5 SE |
909 | e = cpuc->event_list[i]; |
910 | /* | |
911 | * do not put_constraint() on comitted events, | |
912 | * because they are good to go | |
913 | */ | |
914 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
915 | continue; | |
916 | ||
e979121b MD |
917 | /* |
918 | * release events that failed scheduling | |
919 | */ | |
1da53e02 | 920 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 921 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
922 | } |
923 | } | |
c5362c0c MD |
924 | |
925 | if (x86_pmu.stop_scheduling) | |
926 | x86_pmu.stop_scheduling(cpuc); | |
927 | ||
e979121b | 928 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
929 | } |
930 | ||
931 | /* | |
932 | * dogrp: true if must collect siblings events (group) | |
933 | * returns total number of events and error code | |
934 | */ | |
935 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
936 | { | |
937 | struct perf_event *event; | |
938 | int n, max_count; | |
939 | ||
948b1bb8 | 940 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
941 | |
942 | /* current number of events already accepted */ | |
943 | n = cpuc->n_events; | |
944 | ||
945 | if (is_x86_event(leader)) { | |
946 | if (n >= max_count) | |
aa2bc1ad | 947 | return -EINVAL; |
1da53e02 SE |
948 | cpuc->event_list[n] = leader; |
949 | n++; | |
950 | } | |
951 | if (!dogrp) | |
952 | return n; | |
953 | ||
954 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
955 | if (!is_x86_event(event) || | |
8113070d | 956 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
957 | continue; |
958 | ||
959 | if (n >= max_count) | |
aa2bc1ad | 960 | return -EINVAL; |
1da53e02 SE |
961 | |
962 | cpuc->event_list[n] = event; | |
963 | n++; | |
964 | } | |
965 | return n; | |
966 | } | |
967 | ||
1da53e02 | 968 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 969 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 970 | { |
447a194b SE |
971 | struct hw_perf_event *hwc = &event->hw; |
972 | ||
973 | hwc->idx = cpuc->assign[i]; | |
974 | hwc->last_cpu = smp_processor_id(); | |
975 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 976 | |
15c7ad51 | 977 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
978 | hwc->config_base = 0; |
979 | hwc->event_base = 0; | |
15c7ad51 | 980 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 981 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
982 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
983 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 984 | } else { |
73d6e522 RR |
985 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
986 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 987 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
988 | } |
989 | } | |
990 | ||
447a194b SE |
991 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
992 | struct cpu_hw_events *cpuc, | |
993 | int i) | |
994 | { | |
995 | return hwc->idx == cpuc->assign[i] && | |
996 | hwc->last_cpu == smp_processor_id() && | |
997 | hwc->last_tag == cpuc->tags[i]; | |
998 | } | |
999 | ||
a4eaf7f1 | 1000 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 1001 | |
a4eaf7f1 | 1002 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 1003 | { |
89cbc767 | 1004 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1005 | struct perf_event *event; |
1006 | struct hw_perf_event *hwc; | |
11164cd4 | 1007 | int i, added = cpuc->n_added; |
1da53e02 | 1008 | |
85cf9dba | 1009 | if (!x86_pmu_initialized()) |
2b9ff0db | 1010 | return; |
1a6e21f7 PZ |
1011 | |
1012 | if (cpuc->enabled) | |
1013 | return; | |
1014 | ||
1da53e02 | 1015 | if (cpuc->n_added) { |
19925ce7 | 1016 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
1017 | /* |
1018 | * apply assignment obtained either from | |
1019 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
1020 | * | |
1021 | * step1: save events moving to new counters | |
1da53e02 | 1022 | */ |
19925ce7 | 1023 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
1024 | event = cpuc->event_list[i]; |
1025 | hwc = &event->hw; | |
1026 | ||
447a194b SE |
1027 | /* |
1028 | * we can avoid reprogramming counter if: | |
1029 | * - assigned same counter as last time | |
1030 | * - running on same CPU as last time | |
1031 | * - no other event has used the counter since | |
1032 | */ | |
1033 | if (hwc->idx == -1 || | |
1034 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1035 | continue; |
1036 | ||
a4eaf7f1 PZ |
1037 | /* |
1038 | * Ensure we don't accidentally enable a stopped | |
1039 | * counter simply because we rescheduled. | |
1040 | */ | |
1041 | if (hwc->state & PERF_HES_STOPPED) | |
1042 | hwc->state |= PERF_HES_ARCH; | |
1043 | ||
1044 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1045 | } |
1046 | ||
c347a2f1 PZ |
1047 | /* |
1048 | * step2: reprogram moved events into new counters | |
1049 | */ | |
1da53e02 | 1050 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1051 | event = cpuc->event_list[i]; |
1052 | hwc = &event->hw; | |
1053 | ||
45e16a68 | 1054 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1055 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1056 | else if (i < n_running) |
1057 | continue; | |
1da53e02 | 1058 | |
a4eaf7f1 PZ |
1059 | if (hwc->state & PERF_HES_ARCH) |
1060 | continue; | |
1061 | ||
1062 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1063 | } |
1064 | cpuc->n_added = 0; | |
1065 | perf_events_lapic_init(); | |
1066 | } | |
1a6e21f7 PZ |
1067 | |
1068 | cpuc->enabled = 1; | |
1069 | barrier(); | |
1070 | ||
11164cd4 | 1071 | x86_pmu.enable_all(added); |
ee06094f | 1072 | } |
ee06094f | 1073 | |
245b2e70 | 1074 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1075 | |
ee06094f IM |
1076 | /* |
1077 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1078 | * To be called with the event disabled in hw: |
ee06094f | 1079 | */ |
de0428a7 | 1080 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1081 | { |
07088edb | 1082 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1083 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1084 | s64 period = hwc->sample_period; |
7645a24c | 1085 | int ret = 0, idx = hwc->idx; |
ee06094f | 1086 | |
15c7ad51 | 1087 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
1088 | return 0; |
1089 | ||
ee06094f | 1090 | /* |
af901ca1 | 1091 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1092 | */ |
1093 | if (unlikely(left <= -period)) { | |
1094 | left = period; | |
e7850595 | 1095 | local64_set(&hwc->period_left, left); |
9e350de3 | 1096 | hwc->last_period = period; |
e4abb5d4 | 1097 | ret = 1; |
ee06094f IM |
1098 | } |
1099 | ||
1100 | if (unlikely(left <= 0)) { | |
1101 | left += period; | |
e7850595 | 1102 | local64_set(&hwc->period_left, left); |
9e350de3 | 1103 | hwc->last_period = period; |
e4abb5d4 | 1104 | ret = 1; |
ee06094f | 1105 | } |
1c80f4b5 | 1106 | /* |
dfc65094 | 1107 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1108 | */ |
1109 | if (unlikely(left < 2)) | |
1110 | left = 2; | |
241771ef | 1111 | |
e4abb5d4 PZ |
1112 | if (left > x86_pmu.max_period) |
1113 | left = x86_pmu.max_period; | |
1114 | ||
294fe0f5 AK |
1115 | if (x86_pmu.limit_period) |
1116 | left = x86_pmu.limit_period(event, left); | |
1117 | ||
245b2e70 | 1118 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f | 1119 | |
851559e3 YZ |
1120 | if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) || |
1121 | local64_read(&hwc->prev_count) != (u64)-left) { | |
1122 | /* | |
1123 | * The hw event starts counting from this event offset, | |
1124 | * mark it to be able to extra future deltas: | |
1125 | */ | |
1126 | local64_set(&hwc->prev_count, (u64)-left); | |
ee06094f | 1127 | |
851559e3 YZ |
1128 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
1129 | } | |
68aa00ac CG |
1130 | |
1131 | /* | |
1132 | * Due to erratum on certan cpu we need | |
1133 | * a second write to be sure the register | |
1134 | * is updated properly | |
1135 | */ | |
1136 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1137 | wrmsrl(hwc->event_base, |
948b1bb8 | 1138 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1139 | } |
e4abb5d4 | 1140 | |
cdd6c482 | 1141 | perf_event_update_userpage(event); |
194002b2 | 1142 | |
e4abb5d4 | 1143 | return ret; |
2f18d1e8 IM |
1144 | } |
1145 | ||
de0428a7 | 1146 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1147 | { |
0a3aee0d | 1148 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1149 | __x86_pmu_enable_event(&event->hw, |
1150 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1151 | } |
1152 | ||
b690081d | 1153 | /* |
a4eaf7f1 | 1154 | * Add a single event to the PMU. |
1da53e02 SE |
1155 | * |
1156 | * The event is added to the group of enabled events | |
1157 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1158 | */ |
a4eaf7f1 | 1159 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1160 | { |
89cbc767 | 1161 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1162 | struct hw_perf_event *hwc; |
1163 | int assign[X86_PMC_IDX_MAX]; | |
1164 | int n, n0, ret; | |
fe9081cc | 1165 | |
1da53e02 | 1166 | hwc = &event->hw; |
fe9081cc | 1167 | |
1da53e02 | 1168 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1169 | ret = n = collect_events(cpuc, event, false); |
1170 | if (ret < 0) | |
1171 | goto out; | |
53b441a5 | 1172 | |
a4eaf7f1 PZ |
1173 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1174 | if (!(flags & PERF_EF_START)) | |
1175 | hwc->state |= PERF_HES_ARCH; | |
1176 | ||
4d1c52b0 LM |
1177 | /* |
1178 | * If group events scheduling transaction was started, | |
0d2eb44f | 1179 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1180 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1181 | */ |
8f3e5684 | 1182 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
24cd7f54 | 1183 | goto done_collect; |
4d1c52b0 | 1184 | |
a072738e | 1185 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1186 | if (ret) |
24cd7f54 | 1187 | goto out; |
1da53e02 SE |
1188 | /* |
1189 | * copy new assignment, now we know it is possible | |
1190 | * will be used by hw_perf_enable() | |
1191 | */ | |
1192 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1193 | |
24cd7f54 | 1194 | done_collect: |
c347a2f1 PZ |
1195 | /* |
1196 | * Commit the collect_events() state. See x86_pmu_del() and | |
1197 | * x86_pmu_*_txn(). | |
1198 | */ | |
1da53e02 | 1199 | cpuc->n_events = n; |
356e1f2e | 1200 | cpuc->n_added += n - n0; |
90151c35 | 1201 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1202 | |
24cd7f54 PZ |
1203 | ret = 0; |
1204 | out: | |
24cd7f54 | 1205 | return ret; |
241771ef IM |
1206 | } |
1207 | ||
a4eaf7f1 | 1208 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1209 | { |
89cbc767 | 1210 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1211 | int idx = event->hw.idx; |
1212 | ||
a4eaf7f1 PZ |
1213 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1214 | return; | |
1215 | ||
1216 | if (WARN_ON_ONCE(idx == -1)) | |
1217 | return; | |
1218 | ||
1219 | if (flags & PERF_EF_RELOAD) { | |
1220 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1221 | x86_perf_event_set_period(event); | |
1222 | } | |
1223 | ||
1224 | event->hw.state = 0; | |
d76a0812 | 1225 | |
c08053e6 PZ |
1226 | cpuc->events[idx] = event; |
1227 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1228 | __set_bit(idx, cpuc->running); |
aff3d91a | 1229 | x86_pmu.enable(event); |
c08053e6 | 1230 | perf_event_update_userpage(event); |
a78ac325 PZ |
1231 | } |
1232 | ||
cdd6c482 | 1233 | void perf_event_print_debug(void) |
241771ef | 1234 | { |
2f18d1e8 | 1235 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1236 | u64 pebs, debugctl; |
cdd6c482 | 1237 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1238 | unsigned long flags; |
1e125676 IM |
1239 | int cpu, idx; |
1240 | ||
948b1bb8 | 1241 | if (!x86_pmu.num_counters) |
1e125676 | 1242 | return; |
241771ef | 1243 | |
5bb9efe3 | 1244 | local_irq_save(flags); |
241771ef IM |
1245 | |
1246 | cpu = smp_processor_id(); | |
cdd6c482 | 1247 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1248 | |
faa28ae0 | 1249 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1250 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1251 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1252 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1253 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1254 | ||
1255 | pr_info("\n"); | |
1256 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1257 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1258 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1259 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
15fde110 AK |
1260 | if (x86_pmu.pebs_constraints) { |
1261 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); | |
1262 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1263 | } | |
da3e606d AK |
1264 | if (x86_pmu.lbr_nr) { |
1265 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1266 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1267 | } | |
f87ad35d | 1268 | } |
7645a24c | 1269 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1270 | |
948b1bb8 | 1271 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1272 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1273 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1274 | |
245b2e70 | 1275 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1276 | |
a1ef58f4 | 1277 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1278 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1279 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1280 | cpu, idx, pmc_count); |
a1ef58f4 | 1281 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1282 | cpu, idx, prev_left); |
241771ef | 1283 | } |
948b1bb8 | 1284 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1285 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1286 | ||
a1ef58f4 | 1287 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1288 | cpu, idx, pmc_count); |
1289 | } | |
5bb9efe3 | 1290 | local_irq_restore(flags); |
241771ef IM |
1291 | } |
1292 | ||
de0428a7 | 1293 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1294 | { |
89cbc767 | 1295 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1296 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1297 | |
a4eaf7f1 PZ |
1298 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1299 | x86_pmu.disable(event); | |
1300 | cpuc->events[hwc->idx] = NULL; | |
1301 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1302 | hwc->state |= PERF_HES_STOPPED; | |
1303 | } | |
30dd568c | 1304 | |
a4eaf7f1 PZ |
1305 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1306 | /* | |
1307 | * Drain the remaining delta count out of a event | |
1308 | * that we are disabling: | |
1309 | */ | |
1310 | x86_perf_event_update(event); | |
1311 | hwc->state |= PERF_HES_UPTODATE; | |
1312 | } | |
2e841873 PZ |
1313 | } |
1314 | ||
a4eaf7f1 | 1315 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1316 | { |
89cbc767 | 1317 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2e841873 PZ |
1318 | int i; |
1319 | ||
2f7f73a5 SE |
1320 | /* |
1321 | * event is descheduled | |
1322 | */ | |
1323 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1324 | ||
90151c35 SE |
1325 | /* |
1326 | * If we're called during a txn, we don't need to do anything. | |
1327 | * The events never got scheduled and ->cancel_txn will truncate | |
1328 | * the event_list. | |
c347a2f1 PZ |
1329 | * |
1330 | * XXX assumes any ->del() called during a TXN will only be on | |
1331 | * an event added during that same TXN. | |
90151c35 | 1332 | */ |
8f3e5684 | 1333 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
90151c35 SE |
1334 | return; |
1335 | ||
c347a2f1 PZ |
1336 | /* |
1337 | * Not a TXN, therefore cleanup properly. | |
1338 | */ | |
a4eaf7f1 | 1339 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1340 | |
1da53e02 | 1341 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1342 | if (event == cpuc->event_list[i]) |
1343 | break; | |
1344 | } | |
1da53e02 | 1345 | |
c347a2f1 PZ |
1346 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1347 | return; | |
26e61e89 | 1348 | |
c347a2f1 PZ |
1349 | /* If we have a newly added event; make sure to decrease n_added. */ |
1350 | if (i >= cpuc->n_events - cpuc->n_added) | |
1351 | --cpuc->n_added; | |
1da53e02 | 1352 | |
c347a2f1 PZ |
1353 | if (x86_pmu.put_event_constraints) |
1354 | x86_pmu.put_event_constraints(cpuc, event); | |
1355 | ||
1356 | /* Delete the array entry. */ | |
b371b594 | 1357 | while (++i < cpuc->n_events) { |
c347a2f1 | 1358 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 PZ |
1359 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
1360 | } | |
c347a2f1 | 1361 | --cpuc->n_events; |
1da53e02 | 1362 | |
cdd6c482 | 1363 | perf_event_update_userpage(event); |
241771ef IM |
1364 | } |
1365 | ||
de0428a7 | 1366 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1367 | { |
df1a132b | 1368 | struct perf_sample_data data; |
cdd6c482 IM |
1369 | struct cpu_hw_events *cpuc; |
1370 | struct perf_event *event; | |
11d1578f | 1371 | int idx, handled = 0; |
9029a5e3 IM |
1372 | u64 val; |
1373 | ||
89cbc767 | 1374 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1375 | |
2bce5dac DZ |
1376 | /* |
1377 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1378 | * inside the nmi handler. As a result, the unmasking was pushed | |
1379 | * into all the nmi handlers. | |
1380 | * | |
1381 | * This generic handler doesn't seem to have any issues where the | |
1382 | * unmasking occurs so it was left at the top. | |
1383 | */ | |
1384 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1385 | ||
948b1bb8 | 1386 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1387 | if (!test_bit(idx, cpuc->active_mask)) { |
1388 | /* | |
1389 | * Though we deactivated the counter some cpus | |
1390 | * might still deliver spurious interrupts still | |
1391 | * in flight. Catch them: | |
1392 | */ | |
1393 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1394 | handled++; | |
a29aa8a7 | 1395 | continue; |
63e6be6d | 1396 | } |
962bf7a6 | 1397 | |
cdd6c482 | 1398 | event = cpuc->events[idx]; |
a4016a79 | 1399 | |
cc2ad4ba | 1400 | val = x86_perf_event_update(event); |
948b1bb8 | 1401 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1402 | continue; |
962bf7a6 | 1403 | |
9e350de3 | 1404 | /* |
cdd6c482 | 1405 | * event overflow |
9e350de3 | 1406 | */ |
4177c42a | 1407 | handled++; |
fd0d000b | 1408 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1409 | |
07088edb | 1410 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1411 | continue; |
1412 | ||
a8b0ca17 | 1413 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1414 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1415 | } |
962bf7a6 | 1416 | |
9e350de3 PZ |
1417 | if (handled) |
1418 | inc_irq_stat(apic_perf_irqs); | |
1419 | ||
a29aa8a7 RR |
1420 | return handled; |
1421 | } | |
39d81eab | 1422 | |
cdd6c482 | 1423 | void perf_events_lapic_init(void) |
241771ef | 1424 | { |
04da8a43 | 1425 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1426 | return; |
85cf9dba | 1427 | |
241771ef | 1428 | /* |
c323d95f | 1429 | * Always use NMI for PMU |
241771ef | 1430 | */ |
c323d95f | 1431 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1432 | } |
1433 | ||
9326638c | 1434 | static int |
9c48f1c6 | 1435 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1436 | { |
14c63f17 DH |
1437 | u64 start_clock; |
1438 | u64 finish_clock; | |
e8a923cc | 1439 | int ret; |
14c63f17 | 1440 | |
1b7b938f AS |
1441 | /* |
1442 | * All PMUs/events that share this PMI handler should make sure to | |
1443 | * increment active_events for their events. | |
1444 | */ | |
cdd6c482 | 1445 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1446 | return NMI_DONE; |
4177c42a | 1447 | |
e8a923cc | 1448 | start_clock = sched_clock(); |
14c63f17 | 1449 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1450 | finish_clock = sched_clock(); |
14c63f17 DH |
1451 | |
1452 | perf_sample_event_took(finish_clock - start_clock); | |
1453 | ||
1454 | return ret; | |
241771ef | 1455 | } |
9326638c | 1456 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1457 | |
de0428a7 KW |
1458 | struct event_constraint emptyconstraint; |
1459 | struct event_constraint unconstrained; | |
f87ad35d | 1460 | |
148f9bb8 | 1461 | static int |
3f6da390 PZ |
1462 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
1463 | { | |
1464 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1465 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
90413464 | 1466 | int i, ret = NOTIFY_OK; |
3f6da390 PZ |
1467 | |
1468 | switch (action & ~CPU_TASKS_FROZEN) { | |
1469 | case CPU_UP_PREPARE: | |
90413464 SE |
1470 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1471 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1472 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1473 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1474 | break; |
1475 | ||
1476 | case CPU_STARTING: | |
1477 | if (x86_pmu.cpu_starting) | |
1478 | x86_pmu.cpu_starting(cpu); | |
1479 | break; | |
1480 | ||
7fdba1ca | 1481 | case CPU_ONLINE: |
90413464 SE |
1482 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1483 | kfree(cpuc->kfree_on_online[i]); | |
1484 | cpuc->kfree_on_online[i] = NULL; | |
1485 | } | |
7fdba1ca PZ |
1486 | break; |
1487 | ||
3f6da390 PZ |
1488 | case CPU_DYING: |
1489 | if (x86_pmu.cpu_dying) | |
1490 | x86_pmu.cpu_dying(cpu); | |
1491 | break; | |
1492 | ||
b38b24ea | 1493 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1494 | case CPU_DEAD: |
1495 | if (x86_pmu.cpu_dead) | |
1496 | x86_pmu.cpu_dead(cpu); | |
1497 | break; | |
1498 | ||
1499 | default: | |
1500 | break; | |
1501 | } | |
1502 | ||
b38b24ea | 1503 | return ret; |
3f6da390 PZ |
1504 | } |
1505 | ||
12558038 CG |
1506 | static void __init pmu_check_apic(void) |
1507 | { | |
1508 | if (cpu_has_apic) | |
1509 | return; | |
1510 | ||
1511 | x86_pmu.apic = 0; | |
1512 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1513 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1514 | |
1515 | /* | |
1516 | * If we have a PMU initialized but no APIC | |
1517 | * interrupts, we cannot sample hardware | |
1518 | * events (user-space has to fall back and | |
1519 | * sample via a hrtimer based software event): | |
1520 | */ | |
1521 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1522 | ||
12558038 CG |
1523 | } |
1524 | ||
641cc938 JO |
1525 | static struct attribute_group x86_pmu_format_group = { |
1526 | .name = "format", | |
1527 | .attrs = NULL, | |
1528 | }; | |
1529 | ||
8300daa2 JO |
1530 | /* |
1531 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1532 | * out of events_attr attributes. | |
1533 | */ | |
1534 | static void __init filter_events(struct attribute **attrs) | |
1535 | { | |
3a54aaa0 SE |
1536 | struct device_attribute *d; |
1537 | struct perf_pmu_events_attr *pmu_attr; | |
61b87cae | 1538 | int offset = 0; |
8300daa2 JO |
1539 | int i, j; |
1540 | ||
1541 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1542 | d = (struct device_attribute *)attrs[i]; |
1543 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1544 | /* str trumps id */ | |
1545 | if (pmu_attr->event_str) | |
1546 | continue; | |
61b87cae | 1547 | if (x86_pmu.event_map(i + offset)) |
8300daa2 JO |
1548 | continue; |
1549 | ||
1550 | for (j = i; attrs[j]; j++) | |
1551 | attrs[j] = attrs[j + 1]; | |
1552 | ||
1553 | /* Check the shifted attr. */ | |
1554 | i--; | |
61b87cae SE |
1555 | |
1556 | /* | |
1557 | * event_map() is index based, the attrs array is organized | |
1558 | * by increasing event index. If we shift the events, then | |
1559 | * we need to compensate for the event_map(), otherwise | |
1560 | * we are looking up the wrong event in the map | |
1561 | */ | |
1562 | offset++; | |
8300daa2 JO |
1563 | } |
1564 | } | |
1565 | ||
1a6461b1 | 1566 | /* Merge two pointer arrays */ |
47732d88 | 1567 | __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) |
1a6461b1 AK |
1568 | { |
1569 | struct attribute **new; | |
1570 | int j, i; | |
1571 | ||
1572 | for (j = 0; a[j]; j++) | |
1573 | ; | |
1574 | for (i = 0; b[i]; i++) | |
1575 | j++; | |
1576 | j++; | |
1577 | ||
1578 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1579 | if (!new) | |
1580 | return NULL; | |
1581 | ||
1582 | j = 0; | |
1583 | for (i = 0; a[i]; i++) | |
1584 | new[j++] = a[i]; | |
1585 | for (i = 0; b[i]; i++) | |
1586 | new[j++] = b[i]; | |
1587 | new[j] = NULL; | |
1588 | ||
1589 | return new; | |
1590 | } | |
1591 | ||
f20093ee | 1592 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, |
a4747393 JO |
1593 | char *page) |
1594 | { | |
1595 | struct perf_pmu_events_attr *pmu_attr = \ | |
1596 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1597 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1598 | |
3a54aaa0 SE |
1599 | /* string trumps id */ |
1600 | if (pmu_attr->event_str) | |
1601 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1602 | |
3a54aaa0 SE |
1603 | return x86_pmu.events_sysfs_show(page, config); |
1604 | } | |
a4747393 JO |
1605 | |
1606 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); | |
1607 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1608 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1609 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1610 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1611 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1612 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1613 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1614 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1615 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1616 | ||
1617 | static struct attribute *empty_attrs; | |
1618 | ||
95d18aa2 | 1619 | static struct attribute *events_attr[] = { |
a4747393 JO |
1620 | EVENT_PTR(CPU_CYCLES), |
1621 | EVENT_PTR(INSTRUCTIONS), | |
1622 | EVENT_PTR(CACHE_REFERENCES), | |
1623 | EVENT_PTR(CACHE_MISSES), | |
1624 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1625 | EVENT_PTR(BRANCH_MISSES), | |
1626 | EVENT_PTR(BUS_CYCLES), | |
1627 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1628 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1629 | EVENT_PTR(REF_CPU_CYCLES), | |
1630 | NULL, | |
1631 | }; | |
1632 | ||
1633 | static struct attribute_group x86_pmu_events_group = { | |
1634 | .name = "events", | |
1635 | .attrs = events_attr, | |
1636 | }; | |
1637 | ||
0bf79d44 | 1638 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1639 | { |
43c032fe JO |
1640 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1641 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1642 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1643 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1644 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1645 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1646 | ssize_t ret; | |
1647 | ||
1648 | /* | |
1649 | * We have whole page size to spend and just little data | |
1650 | * to write, so we can safely use sprintf. | |
1651 | */ | |
1652 | ret = sprintf(page, "event=0x%02llx", event); | |
1653 | ||
1654 | if (umask) | |
1655 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1656 | ||
1657 | if (edge) | |
1658 | ret += sprintf(page + ret, ",edge"); | |
1659 | ||
1660 | if (pc) | |
1661 | ret += sprintf(page + ret, ",pc"); | |
1662 | ||
1663 | if (any) | |
1664 | ret += sprintf(page + ret, ",any"); | |
1665 | ||
1666 | if (inv) | |
1667 | ret += sprintf(page + ret, ",inv"); | |
1668 | ||
1669 | if (cmask) | |
1670 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1671 | ||
1672 | ret += sprintf(page + ret, "\n"); | |
1673 | ||
1674 | return ret; | |
1675 | } | |
1676 | ||
dda99116 | 1677 | static int __init init_hw_perf_events(void) |
b56a3802 | 1678 | { |
c1d6f42f | 1679 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1680 | int err; |
1681 | ||
cdd6c482 | 1682 | pr_info("Performance Events: "); |
1123e3ad | 1683 | |
b56a3802 JSR |
1684 | switch (boot_cpu_data.x86_vendor) { |
1685 | case X86_VENDOR_INTEL: | |
72eae04d | 1686 | err = intel_pmu_init(); |
b56a3802 | 1687 | break; |
f87ad35d | 1688 | case X86_VENDOR_AMD: |
72eae04d | 1689 | err = amd_pmu_init(); |
f87ad35d | 1690 | break; |
4138960a | 1691 | default: |
8a3da6c7 | 1692 | err = -ENOTSUPP; |
b56a3802 | 1693 | } |
1123e3ad | 1694 | if (err != 0) { |
cdd6c482 | 1695 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1696 | return 0; |
1123e3ad | 1697 | } |
b56a3802 | 1698 | |
12558038 CG |
1699 | pmu_check_apic(); |
1700 | ||
33c6d6a7 | 1701 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1702 | if (!check_hw_exists()) |
004417a6 | 1703 | return 0; |
33c6d6a7 | 1704 | |
1123e3ad | 1705 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1706 | |
e97df763 PZ |
1707 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1708 | ||
c1d6f42f PZ |
1709 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1710 | quirk->func(); | |
3c44780b | 1711 | |
a1eac7ac RR |
1712 | if (!x86_pmu.intel_ctrl) |
1713 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1714 | |
cdd6c482 | 1715 | perf_events_lapic_init(); |
9c48f1c6 | 1716 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1717 | |
63b14649 | 1718 | unconstrained = (struct event_constraint) |
948b1bb8 | 1719 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1720 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1721 | |
641cc938 | 1722 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1723 | |
f20093ee SE |
1724 | if (x86_pmu.event_attrs) |
1725 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1726 | ||
a4747393 JO |
1727 | if (!x86_pmu.events_sysfs_show) |
1728 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1729 | else |
1730 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1731 | |
1a6461b1 AK |
1732 | if (x86_pmu.cpu_events) { |
1733 | struct attribute **tmp; | |
1734 | ||
1735 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1736 | if (!WARN_ON(!tmp)) | |
1737 | x86_pmu_events_group.attrs = tmp; | |
1738 | } | |
1739 | ||
57c0c15b | 1740 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1741 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1742 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1743 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1744 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1745 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1746 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1747 | |
2e80a82a | 1748 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1749 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1750 | |
1751 | return 0; | |
241771ef | 1752 | } |
004417a6 | 1753 | early_initcall(init_hw_perf_events); |
621a01ea | 1754 | |
cdd6c482 | 1755 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1756 | { |
cc2ad4ba | 1757 | x86_perf_event_update(event); |
ee06094f IM |
1758 | } |
1759 | ||
4d1c52b0 LM |
1760 | /* |
1761 | * Start group events scheduling transaction | |
1762 | * Set the flag to make pmu::enable() not perform the | |
1763 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1764 | * |
1765 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1766 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1767 | * transactions. | |
4d1c52b0 | 1768 | */ |
fbbe0701 | 1769 | static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
4d1c52b0 | 1770 | { |
fbbe0701 SB |
1771 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1772 | ||
1773 | WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ | |
1774 | ||
1775 | cpuc->txn_flags = txn_flags; | |
1776 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1777 | return; | |
1778 | ||
33696fc0 | 1779 | perf_pmu_disable(pmu); |
0a3aee0d | 1780 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
4d1c52b0 LM |
1781 | } |
1782 | ||
1783 | /* | |
1784 | * Stop group events scheduling transaction | |
1785 | * Clear the flag and pmu::enable() will perform the | |
1786 | * schedulability test. | |
1787 | */ | |
51b0fe39 | 1788 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1789 | { |
fbbe0701 SB |
1790 | unsigned int txn_flags; |
1791 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
1792 | ||
1793 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ | |
1794 | ||
1795 | txn_flags = cpuc->txn_flags; | |
1796 | cpuc->txn_flags = 0; | |
1797 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1798 | return; | |
1799 | ||
90151c35 | 1800 | /* |
c347a2f1 PZ |
1801 | * Truncate collected array by the number of events added in this |
1802 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1803 | */ |
0a3aee0d TH |
1804 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1805 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1806 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1807 | } |
1808 | ||
1809 | /* | |
1810 | * Commit group events scheduling transaction | |
1811 | * Perform the group schedulability test as a whole | |
1812 | * Return 0 if success | |
c347a2f1 PZ |
1813 | * |
1814 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1815 | */ |
51b0fe39 | 1816 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 1817 | { |
89cbc767 | 1818 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
1819 | int assign[X86_PMC_IDX_MAX]; |
1820 | int n, ret; | |
1821 | ||
fbbe0701 SB |
1822 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
1823 | ||
1824 | if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1825 | cpuc->txn_flags = 0; | |
1826 | return 0; | |
1827 | } | |
1828 | ||
4d1c52b0 LM |
1829 | n = cpuc->n_events; |
1830 | ||
1831 | if (!x86_pmu_initialized()) | |
1832 | return -EAGAIN; | |
1833 | ||
1834 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1835 | if (ret) | |
1836 | return ret; | |
1837 | ||
1838 | /* | |
1839 | * copy new assignment, now we know it is possible | |
1840 | * will be used by hw_perf_enable() | |
1841 | */ | |
1842 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1843 | ||
fbbe0701 | 1844 | cpuc->txn_flags = 0; |
33696fc0 | 1845 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1846 | return 0; |
1847 | } | |
cd8a38d3 SE |
1848 | /* |
1849 | * a fake_cpuc is used to validate event groups. Due to | |
1850 | * the extra reg logic, we need to also allocate a fake | |
1851 | * per_core and per_cpu structure. Otherwise, group events | |
1852 | * using extra reg may conflict without the kernel being | |
1853 | * able to catch this when the last event gets added to | |
1854 | * the group. | |
1855 | */ | |
1856 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1857 | { | |
1858 | kfree(cpuc->shared_regs); | |
1859 | kfree(cpuc); | |
1860 | } | |
1861 | ||
1862 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1863 | { | |
1864 | struct cpu_hw_events *cpuc; | |
1865 | int cpu = raw_smp_processor_id(); | |
1866 | ||
1867 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1868 | if (!cpuc) | |
1869 | return ERR_PTR(-ENOMEM); | |
1870 | ||
1871 | /* only needed, if we have extra_regs */ | |
1872 | if (x86_pmu.extra_regs) { | |
1873 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1874 | if (!cpuc->shared_regs) | |
1875 | goto error; | |
1876 | } | |
b430f7c4 | 1877 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1878 | return cpuc; |
1879 | error: | |
1880 | free_fake_cpuc(cpuc); | |
1881 | return ERR_PTR(-ENOMEM); | |
1882 | } | |
4d1c52b0 | 1883 | |
ca037701 PZ |
1884 | /* |
1885 | * validate that we can schedule this event | |
1886 | */ | |
1887 | static int validate_event(struct perf_event *event) | |
1888 | { | |
1889 | struct cpu_hw_events *fake_cpuc; | |
1890 | struct event_constraint *c; | |
1891 | int ret = 0; | |
1892 | ||
cd8a38d3 SE |
1893 | fake_cpuc = allocate_fake_cpuc(); |
1894 | if (IS_ERR(fake_cpuc)) | |
1895 | return PTR_ERR(fake_cpuc); | |
ca037701 | 1896 | |
79cba822 | 1897 | c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); |
ca037701 PZ |
1898 | |
1899 | if (!c || !c->weight) | |
aa2bc1ad | 1900 | ret = -EINVAL; |
ca037701 PZ |
1901 | |
1902 | if (x86_pmu.put_event_constraints) | |
1903 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1904 | ||
cd8a38d3 | 1905 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1906 | |
1907 | return ret; | |
1908 | } | |
1909 | ||
1da53e02 SE |
1910 | /* |
1911 | * validate a single event group | |
1912 | * | |
1913 | * validation include: | |
184f412c IM |
1914 | * - check events are compatible which each other |
1915 | * - events do not compete for the same counter | |
1916 | * - number of events <= number of counters | |
1da53e02 SE |
1917 | * |
1918 | * validation ensures the group can be loaded onto the | |
1919 | * PMU if it was the only group available. | |
1920 | */ | |
fe9081cc PZ |
1921 | static int validate_group(struct perf_event *event) |
1922 | { | |
1da53e02 | 1923 | struct perf_event *leader = event->group_leader; |
502568d5 | 1924 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1925 | int ret = -EINVAL, n; |
fe9081cc | 1926 | |
cd8a38d3 SE |
1927 | fake_cpuc = allocate_fake_cpuc(); |
1928 | if (IS_ERR(fake_cpuc)) | |
1929 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1930 | /* |
1931 | * the event is not yet connected with its | |
1932 | * siblings therefore we must first collect | |
1933 | * existing siblings, then add the new event | |
1934 | * before we can simulate the scheduling | |
1935 | */ | |
502568d5 | 1936 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1937 | if (n < 0) |
cd8a38d3 | 1938 | goto out; |
fe9081cc | 1939 | |
502568d5 PZ |
1940 | fake_cpuc->n_events = n; |
1941 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1942 | if (n < 0) |
cd8a38d3 | 1943 | goto out; |
fe9081cc | 1944 | |
502568d5 | 1945 | fake_cpuc->n_events = n; |
1da53e02 | 1946 | |
a072738e | 1947 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1948 | |
502568d5 | 1949 | out: |
cd8a38d3 | 1950 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1951 | return ret; |
fe9081cc PZ |
1952 | } |
1953 | ||
dda99116 | 1954 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1955 | { |
51b0fe39 | 1956 | struct pmu *tmp; |
621a01ea IM |
1957 | int err; |
1958 | ||
b0a873eb PZ |
1959 | switch (event->attr.type) { |
1960 | case PERF_TYPE_RAW: | |
1961 | case PERF_TYPE_HARDWARE: | |
1962 | case PERF_TYPE_HW_CACHE: | |
1963 | break; | |
1964 | ||
1965 | default: | |
1966 | return -ENOENT; | |
1967 | } | |
1968 | ||
1969 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1970 | if (!err) { |
8113070d SE |
1971 | /* |
1972 | * we temporarily connect event to its pmu | |
1973 | * such that validate_group() can classify | |
1974 | * it as an x86 event using is_x86_event() | |
1975 | */ | |
1976 | tmp = event->pmu; | |
1977 | event->pmu = &pmu; | |
1978 | ||
fe9081cc PZ |
1979 | if (event->group_leader != event) |
1980 | err = validate_group(event); | |
ca037701 PZ |
1981 | else |
1982 | err = validate_event(event); | |
8113070d SE |
1983 | |
1984 | event->pmu = tmp; | |
fe9081cc | 1985 | } |
a1792cda | 1986 | if (err) { |
cdd6c482 IM |
1987 | if (event->destroy) |
1988 | event->destroy(event); | |
a1792cda | 1989 | } |
621a01ea | 1990 | |
7911d3f7 AL |
1991 | if (ACCESS_ONCE(x86_pmu.attr_rdpmc)) |
1992 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; | |
1993 | ||
b0a873eb | 1994 | return err; |
621a01ea | 1995 | } |
d7d59fb3 | 1996 | |
7911d3f7 AL |
1997 | static void refresh_pce(void *ignored) |
1998 | { | |
1999 | if (current->mm) | |
2000 | load_mm_cr4(current->mm); | |
2001 | } | |
2002 | ||
2003 | static void x86_pmu_event_mapped(struct perf_event *event) | |
2004 | { | |
2005 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2006 | return; | |
2007 | ||
2008 | if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1) | |
2009 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2010 | } | |
2011 | ||
2012 | static void x86_pmu_event_unmapped(struct perf_event *event) | |
2013 | { | |
2014 | if (!current->mm) | |
2015 | return; | |
2016 | ||
2017 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2018 | return; | |
2019 | ||
2020 | if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed)) | |
2021 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2022 | } | |
2023 | ||
fe4a3308 PZ |
2024 | static int x86_pmu_event_idx(struct perf_event *event) |
2025 | { | |
2026 | int idx = event->hw.idx; | |
2027 | ||
7911d3f7 | 2028 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
c7206205 PZ |
2029 | return 0; |
2030 | ||
15c7ad51 RR |
2031 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
2032 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
2033 | idx |= 1 << 30; |
2034 | } | |
2035 | ||
2036 | return idx + 1; | |
2037 | } | |
2038 | ||
0c9d42ed PZ |
2039 | static ssize_t get_attr_rdpmc(struct device *cdev, |
2040 | struct device_attribute *attr, | |
2041 | char *buf) | |
2042 | { | |
2043 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
2044 | } | |
2045 | ||
0c9d42ed PZ |
2046 | static ssize_t set_attr_rdpmc(struct device *cdev, |
2047 | struct device_attribute *attr, | |
2048 | const char *buf, size_t count) | |
2049 | { | |
e2b297fc SK |
2050 | unsigned long val; |
2051 | ssize_t ret; | |
2052 | ||
2053 | ret = kstrtoul(buf, 0, &val); | |
2054 | if (ret) | |
2055 | return ret; | |
e97df763 | 2056 | |
a6673429 AL |
2057 | if (val > 2) |
2058 | return -EINVAL; | |
2059 | ||
e97df763 PZ |
2060 | if (x86_pmu.attr_rdpmc_broken) |
2061 | return -ENOTSUPP; | |
0c9d42ed | 2062 | |
a6673429 AL |
2063 | if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { |
2064 | /* | |
2065 | * Changing into or out of always available, aka | |
2066 | * perf-event-bypassing mode. This path is extremely slow, | |
2067 | * but only root can trigger it, so it's okay. | |
2068 | */ | |
2069 | if (val == 2) | |
2070 | static_key_slow_inc(&rdpmc_always_available); | |
2071 | else | |
2072 | static_key_slow_dec(&rdpmc_always_available); | |
2073 | on_each_cpu(refresh_pce, NULL, 1); | |
2074 | } | |
2075 | ||
2076 | x86_pmu.attr_rdpmc = val; | |
2077 | ||
0c9d42ed PZ |
2078 | return count; |
2079 | } | |
2080 | ||
2081 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2082 | ||
2083 | static struct attribute *x86_pmu_attrs[] = { | |
2084 | &dev_attr_rdpmc.attr, | |
2085 | NULL, | |
2086 | }; | |
2087 | ||
2088 | static struct attribute_group x86_pmu_attr_group = { | |
2089 | .attrs = x86_pmu_attrs, | |
2090 | }; | |
2091 | ||
2092 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
2093 | &x86_pmu_attr_group, | |
641cc938 | 2094 | &x86_pmu_format_group, |
a4747393 | 2095 | &x86_pmu_events_group, |
0c9d42ed PZ |
2096 | NULL, |
2097 | }; | |
2098 | ||
ba532500 | 2099 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d010b332 | 2100 | { |
ba532500 YZ |
2101 | if (x86_pmu.sched_task) |
2102 | x86_pmu.sched_task(ctx, sched_in); | |
d010b332 SE |
2103 | } |
2104 | ||
c93dc84c PZ |
2105 | void perf_check_microcode(void) |
2106 | { | |
2107 | if (x86_pmu.check_microcode) | |
2108 | x86_pmu.check_microcode(); | |
2109 | } | |
2110 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
2111 | ||
b0a873eb | 2112 | static struct pmu pmu = { |
d010b332 SE |
2113 | .pmu_enable = x86_pmu_enable, |
2114 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2115 | |
c93dc84c | 2116 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2117 | |
c93dc84c | 2118 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2119 | |
7911d3f7 AL |
2120 | .event_mapped = x86_pmu_event_mapped, |
2121 | .event_unmapped = x86_pmu_event_unmapped, | |
2122 | ||
d010b332 SE |
2123 | .add = x86_pmu_add, |
2124 | .del = x86_pmu_del, | |
2125 | .start = x86_pmu_start, | |
2126 | .stop = x86_pmu_stop, | |
2127 | .read = x86_pmu_read, | |
a4eaf7f1 | 2128 | |
c93dc84c PZ |
2129 | .start_txn = x86_pmu_start_txn, |
2130 | .cancel_txn = x86_pmu_cancel_txn, | |
2131 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2132 | |
c93dc84c | 2133 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2134 | .sched_task = x86_pmu_sched_task, |
e18bf526 | 2135 | .task_ctx_size = sizeof(struct x86_perf_task_context), |
b0a873eb PZ |
2136 | }; |
2137 | ||
c1317ec2 AL |
2138 | void arch_perf_update_userpage(struct perf_event *event, |
2139 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2140 | { |
20d1c86a PZ |
2141 | struct cyc2ns_data *data; |
2142 | ||
fa731587 PZ |
2143 | userpg->cap_user_time = 0; |
2144 | userpg->cap_user_time_zero = 0; | |
7911d3f7 AL |
2145 | userpg->cap_user_rdpmc = |
2146 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); | |
c7206205 PZ |
2147 | userpg->pmc_width = x86_pmu.cntval_bits; |
2148 | ||
35af99e6 | 2149 | if (!sched_clock_stable()) |
e3f3541c PZ |
2150 | return; |
2151 | ||
20d1c86a PZ |
2152 | data = cyc2ns_read_begin(); |
2153 | ||
34f43927 PZ |
2154 | /* |
2155 | * Internal timekeeping for enabled/running/stopped times | |
2156 | * is always in the local_clock domain. | |
2157 | */ | |
fa731587 | 2158 | userpg->cap_user_time = 1; |
20d1c86a PZ |
2159 | userpg->time_mult = data->cyc2ns_mul; |
2160 | userpg->time_shift = data->cyc2ns_shift; | |
2161 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 2162 | |
34f43927 PZ |
2163 | /* |
2164 | * cap_user_time_zero doesn't make sense when we're using a different | |
2165 | * time base for the records. | |
2166 | */ | |
2167 | if (event->clock == &local_clock) { | |
2168 | userpg->cap_user_time_zero = 1; | |
2169 | userpg->time_zero = data->cyc2ns_offset; | |
2170 | } | |
20d1c86a PZ |
2171 | |
2172 | cyc2ns_read_end(data); | |
e3f3541c PZ |
2173 | } |
2174 | ||
d7d59fb3 PZ |
2175 | /* |
2176 | * callchain support | |
2177 | */ | |
2178 | ||
d7d59fb3 PZ |
2179 | static int backtrace_stack(void *data, char *name) |
2180 | { | |
038e836e | 2181 | return 0; |
d7d59fb3 PZ |
2182 | } |
2183 | ||
2184 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
2185 | { | |
2186 | struct perf_callchain_entry *entry = data; | |
2187 | ||
70791ce9 | 2188 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
2189 | } |
2190 | ||
2191 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
2192 | .stack = backtrace_stack, |
2193 | .address = backtrace_address, | |
06d65bda | 2194 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
2195 | }; |
2196 | ||
56962b44 FW |
2197 | void |
2198 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 2199 | { |
927c7a9e FW |
2200 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2201 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2202 | return; |
927c7a9e FW |
2203 | } |
2204 | ||
70791ce9 | 2205 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2206 | |
e8e999cf | 2207 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
2208 | } |
2209 | ||
bc6ca7b3 AS |
2210 | static inline int |
2211 | valid_user_frame(const void __user *fp, unsigned long size) | |
2212 | { | |
2213 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
2214 | } | |
2215 | ||
d07bdfd3 PZ |
2216 | static unsigned long get_segment_base(unsigned int segment) |
2217 | { | |
2218 | struct desc_struct *desc; | |
2219 | int idx = segment >> 3; | |
2220 | ||
2221 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
a5b9e5a2 | 2222 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
37868fe1 AL |
2223 | struct ldt_struct *ldt; |
2224 | ||
d07bdfd3 PZ |
2225 | if (idx > LDT_ENTRIES) |
2226 | return 0; | |
2227 | ||
37868fe1 AL |
2228 | /* IRQs are off, so this synchronizes with smp_store_release */ |
2229 | ldt = lockless_dereference(current->active_mm->context.ldt); | |
2230 | if (!ldt || idx > ldt->size) | |
d07bdfd3 PZ |
2231 | return 0; |
2232 | ||
37868fe1 | 2233 | desc = &ldt->entries[idx]; |
a5b9e5a2 AL |
2234 | #else |
2235 | return 0; | |
2236 | #endif | |
d07bdfd3 PZ |
2237 | } else { |
2238 | if (idx > GDT_ENTRIES) | |
2239 | return 0; | |
2240 | ||
37868fe1 | 2241 | desc = raw_cpu_ptr(gdt_page.gdt) + idx; |
d07bdfd3 PZ |
2242 | } |
2243 | ||
37868fe1 | 2244 | return get_desc_base(desc); |
d07bdfd3 PZ |
2245 | } |
2246 | ||
10ed3493 | 2247 | #ifdef CONFIG_IA32_EMULATION |
d1a797f3 PA |
2248 | |
2249 | #include <asm/compat.h> | |
2250 | ||
257ef9d2 TE |
2251 | static inline int |
2252 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 2253 | { |
257ef9d2 | 2254 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2255 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2256 | struct stack_frame_ia32 frame; |
2257 | const void __user *fp; | |
74193ef0 | 2258 | |
257ef9d2 TE |
2259 | if (!test_thread_flag(TIF_IA32)) |
2260 | return 0; | |
2261 | ||
d07bdfd3 PZ |
2262 | cs_base = get_segment_base(regs->cs); |
2263 | ss_base = get_segment_base(regs->ss); | |
2264 | ||
2265 | fp = compat_ptr(ss_base + regs->bp); | |
75925e1a | 2266 | pagefault_disable(); |
257ef9d2 TE |
2267 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
2268 | unsigned long bytes; | |
2269 | frame.next_frame = 0; | |
2270 | frame.return_address = 0; | |
2271 | ||
75925e1a AK |
2272 | if (!access_ok(VERIFY_READ, fp, 8)) |
2273 | break; | |
2274 | ||
2275 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); | |
2276 | if (bytes != 0) | |
2277 | break; | |
2278 | bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); | |
0a196848 | 2279 | if (bytes != 0) |
257ef9d2 | 2280 | break; |
74193ef0 | 2281 | |
bc6ca7b3 AS |
2282 | if (!valid_user_frame(fp, sizeof(frame))) |
2283 | break; | |
2284 | ||
d07bdfd3 PZ |
2285 | perf_callchain_store(entry, cs_base + frame.return_address); |
2286 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 | 2287 | } |
75925e1a | 2288 | pagefault_enable(); |
257ef9d2 | 2289 | return 1; |
d7d59fb3 | 2290 | } |
257ef9d2 TE |
2291 | #else |
2292 | static inline int | |
2293 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2294 | { | |
2295 | return 0; | |
2296 | } | |
2297 | #endif | |
d7d59fb3 | 2298 | |
56962b44 FW |
2299 | void |
2300 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
2301 | { |
2302 | struct stack_frame frame; | |
2303 | const void __user *fp; | |
2304 | ||
927c7a9e FW |
2305 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2306 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2307 | return; |
927c7a9e | 2308 | } |
5a6cec3a | 2309 | |
d07bdfd3 PZ |
2310 | /* |
2311 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2312 | */ | |
2313 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2314 | return; | |
2315 | ||
74193ef0 | 2316 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2317 | |
70791ce9 | 2318 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2319 | |
20afc60f AV |
2320 | if (!current->mm) |
2321 | return; | |
2322 | ||
257ef9d2 TE |
2323 | if (perf_callchain_user32(regs, entry)) |
2324 | return; | |
2325 | ||
75925e1a | 2326 | pagefault_disable(); |
f9188e02 | 2327 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 2328 | unsigned long bytes; |
038e836e | 2329 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2330 | frame.return_address = 0; |
2331 | ||
75925e1a AK |
2332 | if (!access_ok(VERIFY_READ, fp, 16)) |
2333 | break; | |
2334 | ||
2335 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8); | |
2336 | if (bytes != 0) | |
2337 | break; | |
2338 | bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8); | |
0a196848 | 2339 | if (bytes != 0) |
d7d59fb3 PZ |
2340 | break; |
2341 | ||
bc6ca7b3 AS |
2342 | if (!valid_user_frame(fp, sizeof(frame))) |
2343 | break; | |
2344 | ||
70791ce9 | 2345 | perf_callchain_store(entry, frame.return_address); |
75925e1a | 2346 | fp = (void __user *)frame.next_frame; |
d7d59fb3 | 2347 | } |
75925e1a | 2348 | pagefault_enable(); |
d7d59fb3 PZ |
2349 | } |
2350 | ||
d07bdfd3 PZ |
2351 | /* |
2352 | * Deal with code segment offsets for the various execution modes: | |
2353 | * | |
2354 | * VM86 - the good olde 16 bit days, where the linear address is | |
2355 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2356 | * | |
2357 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2358 | * to figure out what the 32bit base address is. | |
2359 | * | |
2360 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2361 | * | |
2362 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2363 | */ | |
2364 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2365 | { |
383f3af3 AL |
2366 | /* |
2367 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2368 | * effective IP to a linear address. | |
2369 | */ | |
2370 | ||
2371 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2372 | /* |
2373 | * If we are in VM86 mode, add the segment offset to convert to a | |
2374 | * linear address. | |
2375 | */ | |
2376 | if (regs->flags & X86_VM_MASK) | |
2377 | return 0x10 * regs->cs; | |
2378 | ||
55474c48 | 2379 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2380 | return get_segment_base(regs->cs); |
2381 | #else | |
c56716af AL |
2382 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2383 | regs->cs != __USER32_CS) | |
2384 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2385 | #endif |
2386 | return 0; | |
2387 | } | |
dcf46b94 | 2388 | |
d07bdfd3 PZ |
2389 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2390 | { | |
39447b38 | 2391 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2392 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2393 | |
d07bdfd3 | 2394 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2395 | } |
2396 | ||
2397 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2398 | { | |
2399 | int misc = 0; | |
dcf46b94 | 2400 | |
39447b38 | 2401 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2402 | if (perf_guest_cbs->is_user_mode()) |
2403 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2404 | else | |
2405 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2406 | } else { | |
d07bdfd3 | 2407 | if (user_mode(regs)) |
dcf46b94 ZY |
2408 | misc |= PERF_RECORD_MISC_USER; |
2409 | else | |
2410 | misc |= PERF_RECORD_MISC_KERNEL; | |
2411 | } | |
2412 | ||
39447b38 | 2413 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2414 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2415 | |
2416 | return misc; | |
2417 | } | |
b3d9468a GN |
2418 | |
2419 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2420 | { | |
2421 | cap->version = x86_pmu.version; | |
2422 | cap->num_counters_gp = x86_pmu.num_counters; | |
2423 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2424 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2425 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2426 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2427 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2428 | } | |
2429 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |