Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
90eec103 | 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
eb008eb6 PG |
20 | #include <linux/export.h> |
21 | #include <linux/init.h> | |
241771ef IM |
22 | #include <linux/kdebug.h> |
23 | #include <linux/sched.h> | |
d7d59fb3 | 24 | #include <linux/uaccess.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
0c9d42ed | 28 | #include <linux/device.h> |
241771ef | 29 | |
241771ef | 30 | #include <asm/apic.h> |
d7d59fb3 | 31 | #include <asm/stacktrace.h> |
4e935e47 | 32 | #include <asm/nmi.h> |
69092624 | 33 | #include <asm/smp.h> |
c8e5910e | 34 | #include <asm/alternative.h> |
7911d3f7 | 35 | #include <asm/mmu_context.h> |
375074cc | 36 | #include <asm/tlbflush.h> |
e3f3541c | 37 | #include <asm/timer.h> |
d07bdfd3 PZ |
38 | #include <asm/desc.h> |
39 | #include <asm/ldt.h> | |
241771ef | 40 | |
27f6d22b | 41 | #include "perf_event.h" |
de0428a7 | 42 | |
de0428a7 | 43 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 44 | |
de0428a7 | 45 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
46 | .enabled = 1, |
47 | }; | |
241771ef | 48 | |
a6673429 AL |
49 | struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE; |
50 | ||
de0428a7 | 51 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
52 | [PERF_COUNT_HW_CACHE_MAX] |
53 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
54 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 55 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
56 | [PERF_COUNT_HW_CACHE_MAX] |
57 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
58 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 59 | |
ee06094f | 60 | /* |
cdd6c482 IM |
61 | * Propagate event elapsed time into the generic event. |
62 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
63 | * Returns the delta events processed. |
64 | */ | |
de0428a7 | 65 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 66 | { |
cc2ad4ba | 67 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 68 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 69 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 70 | int idx = hwc->idx; |
ec3232bd | 71 | s64 delta; |
ee06094f | 72 | |
15c7ad51 | 73 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
74 | return 0; |
75 | ||
ee06094f | 76 | /* |
cdd6c482 | 77 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
78 | * |
79 | * Our tactic to handle this is to first atomically read and | |
80 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 81 | * count to the generic event atomically: |
ee06094f IM |
82 | */ |
83 | again: | |
e7850595 | 84 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 85 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 86 | |
e7850595 | 87 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
88 | new_raw_count) != prev_raw_count) |
89 | goto again; | |
90 | ||
91 | /* | |
92 | * Now we have the new raw value and have updated the prev | |
93 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 94 | * (event-)time and add that to the generic event. |
ee06094f IM |
95 | * |
96 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 97 | * of the count. |
ee06094f | 98 | */ |
ec3232bd PZ |
99 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
100 | delta >>= shift; | |
ee06094f | 101 | |
e7850595 PZ |
102 | local64_add(delta, &event->count); |
103 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
104 | |
105 | return new_raw_count; | |
ee06094f IM |
106 | } |
107 | ||
a7e3ed1e AK |
108 | /* |
109 | * Find and validate any extra registers to set up. | |
110 | */ | |
111 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
112 | { | |
efc9f05d | 113 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
114 | struct extra_reg *er; |
115 | ||
efc9f05d | 116 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
117 | |
118 | if (!x86_pmu.extra_regs) | |
119 | return 0; | |
120 | ||
121 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
122 | if (er->event != (config & er->config_mask)) | |
123 | continue; | |
124 | if (event->attr.config1 & ~er->valid_mask) | |
125 | return -EINVAL; | |
338b522c KL |
126 | /* Check if the extra msrs can be safely accessed*/ |
127 | if (!er->extra_msr_access) | |
128 | return -ENXIO; | |
efc9f05d SE |
129 | |
130 | reg->idx = er->idx; | |
131 | reg->config = event->attr.config1; | |
132 | reg->reg = er->msr; | |
a7e3ed1e AK |
133 | break; |
134 | } | |
135 | return 0; | |
136 | } | |
137 | ||
cdd6c482 | 138 | static atomic_t active_events; |
1b7b938f | 139 | static atomic_t pmc_refcount; |
4e935e47 PZ |
140 | static DEFINE_MUTEX(pmc_reserve_mutex); |
141 | ||
b27ea29c RR |
142 | #ifdef CONFIG_X86_LOCAL_APIC |
143 | ||
4e935e47 PZ |
144 | static bool reserve_pmc_hardware(void) |
145 | { | |
146 | int i; | |
147 | ||
948b1bb8 | 148 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 149 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
150 | goto perfctr_fail; |
151 | } | |
152 | ||
948b1bb8 | 153 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 154 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
155 | goto eventsel_fail; |
156 | } | |
157 | ||
158 | return true; | |
159 | ||
160 | eventsel_fail: | |
161 | for (i--; i >= 0; i--) | |
41bf4989 | 162 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 163 | |
948b1bb8 | 164 | i = x86_pmu.num_counters; |
4e935e47 PZ |
165 | |
166 | perfctr_fail: | |
167 | for (i--; i >= 0; i--) | |
41bf4989 | 168 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 169 | |
4e935e47 PZ |
170 | return false; |
171 | } | |
172 | ||
173 | static void release_pmc_hardware(void) | |
174 | { | |
175 | int i; | |
176 | ||
948b1bb8 | 177 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
178 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
179 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 180 | } |
4e935e47 PZ |
181 | } |
182 | ||
b27ea29c RR |
183 | #else |
184 | ||
185 | static bool reserve_pmc_hardware(void) { return true; } | |
186 | static void release_pmc_hardware(void) {} | |
187 | ||
188 | #endif | |
189 | ||
33c6d6a7 DZ |
190 | static bool check_hw_exists(void) |
191 | { | |
a5ebe0ba GD |
192 | u64 val, val_fail, val_new= ~0; |
193 | int i, reg, reg_fail, ret = 0; | |
194 | int bios_fail = 0; | |
68ab7476 | 195 | int reg_safe = -1; |
33c6d6a7 | 196 | |
4407204c PZ |
197 | /* |
198 | * Check to see if the BIOS enabled any of the counters, if so | |
199 | * complain and bail. | |
200 | */ | |
201 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 202 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
203 | ret = rdmsrl_safe(reg, &val); |
204 | if (ret) | |
205 | goto msr_fail; | |
a5ebe0ba GD |
206 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
207 | bios_fail = 1; | |
208 | val_fail = val; | |
209 | reg_fail = reg; | |
68ab7476 DZ |
210 | } else { |
211 | reg_safe = i; | |
a5ebe0ba | 212 | } |
4407204c PZ |
213 | } |
214 | ||
215 | if (x86_pmu.num_counters_fixed) { | |
216 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
217 | ret = rdmsrl_safe(reg, &val); | |
218 | if (ret) | |
219 | goto msr_fail; | |
220 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
221 | if (val & (0x03 << i*4)) { |
222 | bios_fail = 1; | |
223 | val_fail = val; | |
224 | reg_fail = reg; | |
225 | } | |
4407204c PZ |
226 | } |
227 | } | |
228 | ||
68ab7476 DZ |
229 | /* |
230 | * If all the counters are enabled, the below test will always | |
231 | * fail. The tools will also become useless in this scenario. | |
232 | * Just fail and disable the hardware counters. | |
233 | */ | |
234 | ||
235 | if (reg_safe == -1) { | |
236 | reg = reg_safe; | |
237 | goto msr_fail; | |
238 | } | |
239 | ||
4407204c | 240 | /* |
bffd5fc2 AP |
241 | * Read the current value, change it and read it back to see if it |
242 | * matches, this is needed to detect certain hardware emulators | |
243 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 244 | */ |
68ab7476 | 245 | reg = x86_pmu_event_addr(reg_safe); |
bffd5fc2 AP |
246 | if (rdmsrl_safe(reg, &val)) |
247 | goto msr_fail; | |
248 | val ^= 0xffffUL; | |
f285f92f RR |
249 | ret = wrmsrl_safe(reg, val); |
250 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 251 | if (ret || val != val_new) |
4407204c | 252 | goto msr_fail; |
33c6d6a7 | 253 | |
45daae57 IM |
254 | /* |
255 | * We still allow the PMU driver to operate: | |
256 | */ | |
a5ebe0ba | 257 | if (bios_fail) { |
1b74dde7 CY |
258 | pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); |
259 | pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", | |
260 | reg_fail, val_fail); | |
a5ebe0ba | 261 | } |
45daae57 IM |
262 | |
263 | return true; | |
4407204c PZ |
264 | |
265 | msr_fail: | |
1b74dde7 | 266 | pr_cont("Broken PMU hardware detected, using software events only.\n"); |
eb019503 | 267 | printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n", |
65d71fe1 PZI |
268 | boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR, |
269 | reg, val_new); | |
45daae57 | 270 | |
4407204c | 271 | return false; |
33c6d6a7 DZ |
272 | } |
273 | ||
cdd6c482 | 274 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 275 | { |
6b099d9b | 276 | x86_release_hardware(); |
1b7b938f | 277 | atomic_dec(&active_events); |
4e935e47 PZ |
278 | } |
279 | ||
48070342 AS |
280 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
281 | { | |
282 | hw_perf_event_destroy(event); | |
283 | ||
284 | /* undo the lbr/bts event accounting */ | |
285 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
286 | } | |
287 | ||
85cf9dba RR |
288 | static inline int x86_pmu_initialized(void) |
289 | { | |
290 | return x86_pmu.handle_irq != NULL; | |
291 | } | |
292 | ||
8326f44d | 293 | static inline int |
e994d7d2 | 294 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 295 | { |
e994d7d2 | 296 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
297 | unsigned int cache_type, cache_op, cache_result; |
298 | u64 config, val; | |
299 | ||
300 | config = attr->config; | |
301 | ||
302 | cache_type = (config >> 0) & 0xff; | |
303 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
304 | return -EINVAL; | |
305 | ||
306 | cache_op = (config >> 8) & 0xff; | |
307 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
308 | return -EINVAL; | |
309 | ||
310 | cache_result = (config >> 16) & 0xff; | |
311 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
312 | return -EINVAL; | |
313 | ||
314 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
315 | ||
316 | if (val == 0) | |
317 | return -ENOENT; | |
318 | ||
319 | if (val == -1) | |
320 | return -EINVAL; | |
321 | ||
322 | hwc->config |= val; | |
e994d7d2 AK |
323 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
324 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
325 | } |
326 | ||
6b099d9b AS |
327 | int x86_reserve_hardware(void) |
328 | { | |
329 | int err = 0; | |
330 | ||
1b7b938f | 331 | if (!atomic_inc_not_zero(&pmc_refcount)) { |
6b099d9b | 332 | mutex_lock(&pmc_reserve_mutex); |
1b7b938f | 333 | if (atomic_read(&pmc_refcount) == 0) { |
6b099d9b AS |
334 | if (!reserve_pmc_hardware()) |
335 | err = -EBUSY; | |
336 | else | |
337 | reserve_ds_buffers(); | |
338 | } | |
339 | if (!err) | |
1b7b938f | 340 | atomic_inc(&pmc_refcount); |
6b099d9b AS |
341 | mutex_unlock(&pmc_reserve_mutex); |
342 | } | |
343 | ||
344 | return err; | |
345 | } | |
346 | ||
347 | void x86_release_hardware(void) | |
348 | { | |
1b7b938f | 349 | if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { |
6b099d9b AS |
350 | release_pmc_hardware(); |
351 | release_ds_buffers(); | |
352 | mutex_unlock(&pmc_reserve_mutex); | |
353 | } | |
354 | } | |
355 | ||
48070342 AS |
356 | /* |
357 | * Check if we can create event of a certain type (that no conflicting events | |
358 | * are present). | |
359 | */ | |
360 | int x86_add_exclusive(unsigned int what) | |
361 | { | |
93472aff | 362 | int i; |
48070342 | 363 | |
ccbebba4 AS |
364 | if (x86_pmu.lbr_pt_coexist) |
365 | return 0; | |
366 | ||
93472aff PZ |
367 | if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { |
368 | mutex_lock(&pmc_reserve_mutex); | |
369 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { | |
370 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
371 | goto fail_unlock; | |
372 | } | |
373 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
374 | mutex_unlock(&pmc_reserve_mutex); | |
6b099d9b | 375 | } |
48070342 | 376 | |
93472aff PZ |
377 | atomic_inc(&active_events); |
378 | return 0; | |
48070342 | 379 | |
93472aff | 380 | fail_unlock: |
48070342 | 381 | mutex_unlock(&pmc_reserve_mutex); |
93472aff | 382 | return -EBUSY; |
48070342 AS |
383 | } |
384 | ||
385 | void x86_del_exclusive(unsigned int what) | |
386 | { | |
ccbebba4 AS |
387 | if (x86_pmu.lbr_pt_coexist) |
388 | return; | |
389 | ||
48070342 | 390 | atomic_dec(&x86_pmu.lbr_exclusive[what]); |
1b7b938f | 391 | atomic_dec(&active_events); |
48070342 AS |
392 | } |
393 | ||
de0428a7 | 394 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
395 | { |
396 | struct perf_event_attr *attr = &event->attr; | |
397 | struct hw_perf_event *hwc = &event->hw; | |
398 | u64 config; | |
399 | ||
6c7e550f | 400 | if (!is_sampling_event(event)) { |
c1726f34 RR |
401 | hwc->sample_period = x86_pmu.max_period; |
402 | hwc->last_period = hwc->sample_period; | |
e7850595 | 403 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
404 | } |
405 | ||
406 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 407 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
408 | |
409 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 410 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
411 | |
412 | if (attr->config >= x86_pmu.max_events) | |
413 | return -EINVAL; | |
414 | ||
415 | /* | |
416 | * The generic map: | |
417 | */ | |
418 | config = x86_pmu.event_map(attr->config); | |
419 | ||
420 | if (config == 0) | |
421 | return -ENOENT; | |
422 | ||
423 | if (config == -1LL) | |
424 | return -EINVAL; | |
425 | ||
426 | /* | |
427 | * Branch tracing: | |
428 | */ | |
18a073a3 PZ |
429 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
430 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 431 | /* BTS is not supported by this architecture. */ |
6809b6ea | 432 | if (!x86_pmu.bts_active) |
c1726f34 RR |
433 | return -EOPNOTSUPP; |
434 | ||
435 | /* BTS is currently only allowed for user-mode. */ | |
436 | if (!attr->exclude_kernel) | |
437 | return -EOPNOTSUPP; | |
48070342 AS |
438 | |
439 | /* disallow bts if conflicting events are present */ | |
440 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
441 | return -EBUSY; | |
442 | ||
443 | event->destroy = hw_perf_lbr_event_destroy; | |
c1726f34 RR |
444 | } |
445 | ||
446 | hwc->config |= config; | |
447 | ||
448 | return 0; | |
449 | } | |
4261e0e0 | 450 | |
ff3fb511 SE |
451 | /* |
452 | * check that branch_sample_type is compatible with | |
453 | * settings needed for precise_ip > 1 which implies | |
454 | * using the LBR to capture ALL taken branches at the | |
455 | * priv levels of the measurement | |
456 | */ | |
457 | static inline int precise_br_compat(struct perf_event *event) | |
458 | { | |
459 | u64 m = event->attr.branch_sample_type; | |
460 | u64 b = 0; | |
461 | ||
462 | /* must capture all branches */ | |
463 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
464 | return 0; | |
465 | ||
466 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
467 | ||
468 | if (!event->attr.exclude_user) | |
469 | b |= PERF_SAMPLE_BRANCH_USER; | |
470 | ||
471 | if (!event->attr.exclude_kernel) | |
472 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
473 | ||
474 | /* | |
475 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
476 | */ | |
477 | ||
478 | return m == b; | |
479 | } | |
480 | ||
de0428a7 | 481 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 482 | { |
ab608344 PZ |
483 | if (event->attr.precise_ip) { |
484 | int precise = 0; | |
485 | ||
486 | /* Support for constant skid */ | |
c93dc84c | 487 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
488 | precise++; |
489 | ||
5553be26 | 490 | /* Support for IP fixup */ |
03de874a | 491 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 | 492 | precise++; |
72469764 AK |
493 | |
494 | if (x86_pmu.pebs_prec_dist) | |
495 | precise++; | |
5553be26 | 496 | } |
ab608344 PZ |
497 | |
498 | if (event->attr.precise_ip > precise) | |
499 | return -EOPNOTSUPP; | |
4b854900 YZ |
500 | } |
501 | /* | |
502 | * check that PEBS LBR correction does not conflict with | |
503 | * whatever the user is asking with attr->branch_sample_type | |
504 | */ | |
505 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
506 | u64 *br_type = &event->attr.branch_sample_type; | |
507 | ||
508 | if (has_branch_stack(event)) { | |
509 | if (!precise_br_compat(event)) | |
510 | return -EOPNOTSUPP; | |
511 | ||
512 | /* branch_sample_type is compatible */ | |
513 | ||
514 | } else { | |
515 | /* | |
516 | * user did not specify branch_sample_type | |
517 | * | |
518 | * For PEBS fixups, we capture all | |
519 | * the branches at the priv level of the | |
520 | * event. | |
521 | */ | |
522 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
523 | ||
524 | if (!event->attr.exclude_user) | |
525 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
526 | ||
527 | if (!event->attr.exclude_kernel) | |
528 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 529 | } |
ab608344 PZ |
530 | } |
531 | ||
e18bf526 YZ |
532 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
533 | event->attach_state |= PERF_ATTACH_TASK_DATA; | |
534 | ||
a072738e CG |
535 | /* |
536 | * Generate PMC IRQs: | |
537 | * (keep 'enabled' bit clear for now) | |
538 | */ | |
b4cdc5c2 | 539 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
540 | |
541 | /* | |
542 | * Count user and OS events unless requested not to | |
543 | */ | |
b4cdc5c2 PZ |
544 | if (!event->attr.exclude_user) |
545 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
546 | if (!event->attr.exclude_kernel) | |
547 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 548 | |
b4cdc5c2 PZ |
549 | if (event->attr.type == PERF_TYPE_RAW) |
550 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 551 | |
294fe0f5 AK |
552 | if (event->attr.sample_period && x86_pmu.limit_period) { |
553 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
554 | event->attr.sample_period) | |
555 | return -EINVAL; | |
556 | } | |
557 | ||
9d0fcba6 | 558 | return x86_setup_perfctr(event); |
a098f448 RR |
559 | } |
560 | ||
241771ef | 561 | /* |
0d48696f | 562 | * Setup the hardware configuration for a given attr_type |
241771ef | 563 | */ |
b0a873eb | 564 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 565 | { |
4e935e47 | 566 | int err; |
241771ef | 567 | |
85cf9dba RR |
568 | if (!x86_pmu_initialized()) |
569 | return -ENODEV; | |
241771ef | 570 | |
6b099d9b | 571 | err = x86_reserve_hardware(); |
4e935e47 PZ |
572 | if (err) |
573 | return err; | |
574 | ||
1b7b938f | 575 | atomic_inc(&active_events); |
cdd6c482 | 576 | event->destroy = hw_perf_event_destroy; |
a1792cda | 577 | |
4261e0e0 RR |
578 | event->hw.idx = -1; |
579 | event->hw.last_cpu = -1; | |
580 | event->hw.last_tag = ~0ULL; | |
b690081d | 581 | |
efc9f05d SE |
582 | /* mark unused */ |
583 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
584 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
585 | ||
9d0fcba6 | 586 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
587 | } |
588 | ||
de0428a7 | 589 | void x86_pmu_disable_all(void) |
f87ad35d | 590 | { |
89cbc767 | 591 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
592 | int idx; |
593 | ||
948b1bb8 | 594 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
595 | u64 val; |
596 | ||
43f6201a | 597 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 598 | continue; |
41bf4989 | 599 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 600 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 601 | continue; |
bb1165d6 | 602 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 603 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 604 | } |
f87ad35d JSR |
605 | } |
606 | ||
c3d266c8 KL |
607 | /* |
608 | * There may be PMI landing after enabled=0. The PMI hitting could be before or | |
609 | * after disable_all. | |
610 | * | |
611 | * If PMI hits before disable_all, the PMU will be disabled in the NMI handler. | |
612 | * It will not be re-enabled in the NMI handler again, because enabled=0. After | |
613 | * handling the NMI, disable_all will be called, which will not change the | |
614 | * state either. If PMI hits after disable_all, the PMU is already disabled | |
615 | * before entering NMI handler. The NMI handler will not change the state | |
616 | * either. | |
617 | * | |
618 | * So either situation is harmless. | |
619 | */ | |
a4eaf7f1 | 620 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 621 | { |
89cbc767 | 622 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 623 | |
85cf9dba | 624 | if (!x86_pmu_initialized()) |
9e35ad38 | 625 | return; |
1da53e02 | 626 | |
1a6e21f7 PZ |
627 | if (!cpuc->enabled) |
628 | return; | |
629 | ||
630 | cpuc->n_added = 0; | |
631 | cpuc->enabled = 0; | |
632 | barrier(); | |
1da53e02 SE |
633 | |
634 | x86_pmu.disable_all(); | |
b56a3802 | 635 | } |
241771ef | 636 | |
de0428a7 | 637 | void x86_pmu_enable_all(int added) |
f87ad35d | 638 | { |
89cbc767 | 639 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
640 | int idx; |
641 | ||
948b1bb8 | 642 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 643 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 644 | |
43f6201a | 645 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 646 | continue; |
984b838c | 647 | |
d45dd923 | 648 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
649 | } |
650 | } | |
651 | ||
51b0fe39 | 652 | static struct pmu pmu; |
1da53e02 SE |
653 | |
654 | static inline int is_x86_event(struct perf_event *event) | |
655 | { | |
656 | return event->pmu == &pmu; | |
657 | } | |
658 | ||
1e2ad28f RR |
659 | /* |
660 | * Event scheduler state: | |
661 | * | |
662 | * Assign events iterating over all events and counters, beginning | |
663 | * with events with least weights first. Keep the current iterator | |
664 | * state in struct sched_state. | |
665 | */ | |
666 | struct sched_state { | |
667 | int weight; | |
668 | int event; /* event index */ | |
669 | int counter; /* counter index */ | |
670 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 671 | int nr_gp; /* number of GP counters used */ |
1e2ad28f RR |
672 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
673 | }; | |
674 | ||
bc1738f6 RR |
675 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
676 | #define SCHED_STATES_MAX 2 | |
677 | ||
1e2ad28f RR |
678 | struct perf_sched { |
679 | int max_weight; | |
680 | int max_events; | |
cc1790cf PZ |
681 | int max_gp; |
682 | int saved_states; | |
b371b594 | 683 | struct event_constraint **constraints; |
1e2ad28f | 684 | struct sched_state state; |
bc1738f6 | 685 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
686 | }; |
687 | ||
688 | /* | |
689 | * Initialize interator that runs through all events and counters. | |
690 | */ | |
b371b594 | 691 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 692 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
693 | { |
694 | int idx; | |
695 | ||
696 | memset(sched, 0, sizeof(*sched)); | |
697 | sched->max_events = num; | |
698 | sched->max_weight = wmax; | |
cc1790cf | 699 | sched->max_gp = gpmax; |
b371b594 | 700 | sched->constraints = constraints; |
1e2ad28f RR |
701 | |
702 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 703 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
704 | break; |
705 | } | |
706 | ||
707 | sched->state.event = idx; /* start with min weight */ | |
708 | sched->state.weight = wmin; | |
709 | sched->state.unassigned = num; | |
710 | } | |
711 | ||
bc1738f6 RR |
712 | static void perf_sched_save_state(struct perf_sched *sched) |
713 | { | |
714 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
715 | return; | |
716 | ||
717 | sched->saved[sched->saved_states] = sched->state; | |
718 | sched->saved_states++; | |
719 | } | |
720 | ||
721 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
722 | { | |
723 | if (!sched->saved_states) | |
724 | return false; | |
725 | ||
726 | sched->saved_states--; | |
727 | sched->state = sched->saved[sched->saved_states]; | |
728 | ||
729 | /* continue with next counter: */ | |
730 | clear_bit(sched->state.counter++, sched->state.used); | |
731 | ||
732 | return true; | |
733 | } | |
734 | ||
1e2ad28f RR |
735 | /* |
736 | * Select a counter for the current event to schedule. Return true on | |
737 | * success. | |
738 | */ | |
bc1738f6 | 739 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
740 | { |
741 | struct event_constraint *c; | |
742 | int idx; | |
743 | ||
744 | if (!sched->state.unassigned) | |
745 | return false; | |
746 | ||
747 | if (sched->state.event >= sched->max_events) | |
748 | return false; | |
749 | ||
b371b594 | 750 | c = sched->constraints[sched->state.event]; |
4defea85 | 751 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
752 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
753 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 754 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
755 | if (!__test_and_set_bit(idx, sched->state.used)) |
756 | goto done; | |
757 | } | |
758 | } | |
cc1790cf | 759 | |
1e2ad28f RR |
760 | /* Grab the first unused counter starting with idx */ |
761 | idx = sched->state.counter; | |
15c7ad51 | 762 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
cc1790cf PZ |
763 | if (!__test_and_set_bit(idx, sched->state.used)) { |
764 | if (sched->state.nr_gp++ >= sched->max_gp) | |
765 | return false; | |
766 | ||
4defea85 | 767 | goto done; |
cc1790cf | 768 | } |
1e2ad28f | 769 | } |
1e2ad28f | 770 | |
4defea85 PZ |
771 | return false; |
772 | ||
773 | done: | |
774 | sched->state.counter = idx; | |
1e2ad28f | 775 | |
bc1738f6 RR |
776 | if (c->overlap) |
777 | perf_sched_save_state(sched); | |
778 | ||
779 | return true; | |
780 | } | |
781 | ||
782 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
783 | { | |
784 | while (!__perf_sched_find_counter(sched)) { | |
785 | if (!perf_sched_restore_state(sched)) | |
786 | return false; | |
787 | } | |
788 | ||
1e2ad28f RR |
789 | return true; |
790 | } | |
791 | ||
792 | /* | |
793 | * Go through all unassigned events and find the next one to schedule. | |
794 | * Take events with the least weight first. Return true on success. | |
795 | */ | |
796 | static bool perf_sched_next_event(struct perf_sched *sched) | |
797 | { | |
798 | struct event_constraint *c; | |
799 | ||
800 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
801 | return false; | |
802 | ||
803 | do { | |
804 | /* next event */ | |
805 | sched->state.event++; | |
806 | if (sched->state.event >= sched->max_events) { | |
807 | /* next weight */ | |
808 | sched->state.event = 0; | |
809 | sched->state.weight++; | |
810 | if (sched->state.weight > sched->max_weight) | |
811 | return false; | |
812 | } | |
b371b594 | 813 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
814 | } while (c->weight != sched->state.weight); |
815 | ||
816 | sched->state.counter = 0; /* start with first counter */ | |
817 | ||
818 | return true; | |
819 | } | |
820 | ||
821 | /* | |
822 | * Assign a counter for each event. | |
823 | */ | |
b371b594 | 824 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 825 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
826 | { |
827 | struct perf_sched sched; | |
828 | ||
cc1790cf | 829 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
830 | |
831 | do { | |
832 | if (!perf_sched_find_counter(&sched)) | |
833 | break; /* failed */ | |
834 | if (assign) | |
835 | assign[sched.state.event] = sched.state.counter; | |
836 | } while (perf_sched_next_event(&sched)); | |
837 | ||
838 | return sched.state.unassigned; | |
839 | } | |
4a3dc121 | 840 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 841 | |
de0428a7 | 842 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 843 | { |
43b45780 | 844 | struct event_constraint *c; |
1da53e02 | 845 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 846 | struct perf_event *e; |
e979121b | 847 | int i, wmin, wmax, unsched = 0; |
1da53e02 SE |
848 | struct hw_perf_event *hwc; |
849 | ||
850 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
851 | ||
c5362c0c MD |
852 | if (x86_pmu.start_scheduling) |
853 | x86_pmu.start_scheduling(cpuc); | |
854 | ||
1e2ad28f | 855 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b371b594 | 856 | cpuc->event_constraint[i] = NULL; |
79cba822 | 857 | c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); |
b371b594 | 858 | cpuc->event_constraint[i] = c; |
43b45780 | 859 | |
1e2ad28f RR |
860 | wmin = min(wmin, c->weight); |
861 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
862 | } |
863 | ||
8113070d SE |
864 | /* |
865 | * fastpath, try to reuse previous register | |
866 | */ | |
c933c1a6 | 867 | for (i = 0; i < n; i++) { |
8113070d | 868 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 869 | c = cpuc->event_constraint[i]; |
8113070d SE |
870 | |
871 | /* never assigned */ | |
872 | if (hwc->idx == -1) | |
873 | break; | |
874 | ||
875 | /* constraint still honored */ | |
63b14649 | 876 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
877 | break; |
878 | ||
879 | /* not already used */ | |
880 | if (test_bit(hwc->idx, used_mask)) | |
881 | break; | |
882 | ||
34538ee7 | 883 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
884 | if (assign) |
885 | assign[i] = hwc->idx; | |
886 | } | |
8113070d | 887 | |
1e2ad28f | 888 | /* slow path */ |
b371b594 | 889 | if (i != n) { |
cc1790cf PZ |
890 | int gpmax = x86_pmu.num_counters; |
891 | ||
892 | /* | |
893 | * Do not allow scheduling of more than half the available | |
894 | * generic counters. | |
895 | * | |
896 | * This helps avoid counter starvation of sibling thread by | |
897 | * ensuring at most half the counters cannot be in exclusive | |
898 | * mode. There is no designated counters for the limits. Any | |
899 | * N/2 counters can be used. This helps with events with | |
900 | * specific counter constraints. | |
901 | */ | |
902 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
903 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
904 | gpmax /= 2; | |
905 | ||
b371b594 | 906 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 907 | wmax, gpmax, assign); |
b371b594 | 908 | } |
8113070d | 909 | |
2f7f73a5 | 910 | /* |
e979121b MD |
911 | * In case of success (unsched = 0), mark events as committed, |
912 | * so we do not put_constraint() in case new events are added | |
913 | * and fail to be scheduled | |
914 | * | |
915 | * We invoke the lower level commit callback to lock the resource | |
916 | * | |
917 | * We do not need to do all of this in case we are called to | |
918 | * validate an event group (assign == NULL) | |
2f7f73a5 | 919 | */ |
e979121b | 920 | if (!unsched && assign) { |
2f7f73a5 SE |
921 | for (i = 0; i < n; i++) { |
922 | e = cpuc->event_list[i]; | |
923 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
c5362c0c | 924 | if (x86_pmu.commit_scheduling) |
b371b594 | 925 | x86_pmu.commit_scheduling(cpuc, i, assign[i]); |
2f7f73a5 | 926 | } |
8736e548 | 927 | } else { |
1da53e02 | 928 | for (i = 0; i < n; i++) { |
2f7f73a5 SE |
929 | e = cpuc->event_list[i]; |
930 | /* | |
931 | * do not put_constraint() on comitted events, | |
932 | * because they are good to go | |
933 | */ | |
934 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
935 | continue; | |
936 | ||
e979121b MD |
937 | /* |
938 | * release events that failed scheduling | |
939 | */ | |
1da53e02 | 940 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 941 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
942 | } |
943 | } | |
c5362c0c MD |
944 | |
945 | if (x86_pmu.stop_scheduling) | |
946 | x86_pmu.stop_scheduling(cpuc); | |
947 | ||
e979121b | 948 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
949 | } |
950 | ||
951 | /* | |
952 | * dogrp: true if must collect siblings events (group) | |
953 | * returns total number of events and error code | |
954 | */ | |
955 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
956 | { | |
957 | struct perf_event *event; | |
958 | int n, max_count; | |
959 | ||
948b1bb8 | 960 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
961 | |
962 | /* current number of events already accepted */ | |
963 | n = cpuc->n_events; | |
964 | ||
965 | if (is_x86_event(leader)) { | |
966 | if (n >= max_count) | |
aa2bc1ad | 967 | return -EINVAL; |
1da53e02 SE |
968 | cpuc->event_list[n] = leader; |
969 | n++; | |
970 | } | |
971 | if (!dogrp) | |
972 | return n; | |
973 | ||
974 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
975 | if (!is_x86_event(event) || | |
8113070d | 976 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
977 | continue; |
978 | ||
979 | if (n >= max_count) | |
aa2bc1ad | 980 | return -EINVAL; |
1da53e02 SE |
981 | |
982 | cpuc->event_list[n] = event; | |
983 | n++; | |
984 | } | |
985 | return n; | |
986 | } | |
987 | ||
1da53e02 | 988 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 989 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 990 | { |
447a194b SE |
991 | struct hw_perf_event *hwc = &event->hw; |
992 | ||
993 | hwc->idx = cpuc->assign[i]; | |
994 | hwc->last_cpu = smp_processor_id(); | |
995 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 996 | |
15c7ad51 | 997 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
998 | hwc->config_base = 0; |
999 | hwc->event_base = 0; | |
15c7ad51 | 1000 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 1001 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
1002 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
1003 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 1004 | } else { |
73d6e522 RR |
1005 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
1006 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 1007 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
1008 | } |
1009 | } | |
1010 | ||
447a194b SE |
1011 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
1012 | struct cpu_hw_events *cpuc, | |
1013 | int i) | |
1014 | { | |
1015 | return hwc->idx == cpuc->assign[i] && | |
1016 | hwc->last_cpu == smp_processor_id() && | |
1017 | hwc->last_tag == cpuc->tags[i]; | |
1018 | } | |
1019 | ||
a4eaf7f1 | 1020 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 1021 | |
a4eaf7f1 | 1022 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 1023 | { |
89cbc767 | 1024 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1025 | struct perf_event *event; |
1026 | struct hw_perf_event *hwc; | |
11164cd4 | 1027 | int i, added = cpuc->n_added; |
1da53e02 | 1028 | |
85cf9dba | 1029 | if (!x86_pmu_initialized()) |
2b9ff0db | 1030 | return; |
1a6e21f7 PZ |
1031 | |
1032 | if (cpuc->enabled) | |
1033 | return; | |
1034 | ||
1da53e02 | 1035 | if (cpuc->n_added) { |
19925ce7 | 1036 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
1037 | /* |
1038 | * apply assignment obtained either from | |
1039 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
1040 | * | |
1041 | * step1: save events moving to new counters | |
1da53e02 | 1042 | */ |
19925ce7 | 1043 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
1044 | event = cpuc->event_list[i]; |
1045 | hwc = &event->hw; | |
1046 | ||
447a194b SE |
1047 | /* |
1048 | * we can avoid reprogramming counter if: | |
1049 | * - assigned same counter as last time | |
1050 | * - running on same CPU as last time | |
1051 | * - no other event has used the counter since | |
1052 | */ | |
1053 | if (hwc->idx == -1 || | |
1054 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1055 | continue; |
1056 | ||
a4eaf7f1 PZ |
1057 | /* |
1058 | * Ensure we don't accidentally enable a stopped | |
1059 | * counter simply because we rescheduled. | |
1060 | */ | |
1061 | if (hwc->state & PERF_HES_STOPPED) | |
1062 | hwc->state |= PERF_HES_ARCH; | |
1063 | ||
1064 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1065 | } |
1066 | ||
c347a2f1 PZ |
1067 | /* |
1068 | * step2: reprogram moved events into new counters | |
1069 | */ | |
1da53e02 | 1070 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1071 | event = cpuc->event_list[i]; |
1072 | hwc = &event->hw; | |
1073 | ||
45e16a68 | 1074 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1075 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1076 | else if (i < n_running) |
1077 | continue; | |
1da53e02 | 1078 | |
a4eaf7f1 PZ |
1079 | if (hwc->state & PERF_HES_ARCH) |
1080 | continue; | |
1081 | ||
1082 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1083 | } |
1084 | cpuc->n_added = 0; | |
1085 | perf_events_lapic_init(); | |
1086 | } | |
1a6e21f7 PZ |
1087 | |
1088 | cpuc->enabled = 1; | |
1089 | barrier(); | |
1090 | ||
11164cd4 | 1091 | x86_pmu.enable_all(added); |
ee06094f | 1092 | } |
ee06094f | 1093 | |
245b2e70 | 1094 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1095 | |
ee06094f IM |
1096 | /* |
1097 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1098 | * To be called with the event disabled in hw: |
ee06094f | 1099 | */ |
de0428a7 | 1100 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1101 | { |
07088edb | 1102 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1103 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1104 | s64 period = hwc->sample_period; |
7645a24c | 1105 | int ret = 0, idx = hwc->idx; |
ee06094f | 1106 | |
15c7ad51 | 1107 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
1108 | return 0; |
1109 | ||
ee06094f | 1110 | /* |
af901ca1 | 1111 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1112 | */ |
1113 | if (unlikely(left <= -period)) { | |
1114 | left = period; | |
e7850595 | 1115 | local64_set(&hwc->period_left, left); |
9e350de3 | 1116 | hwc->last_period = period; |
e4abb5d4 | 1117 | ret = 1; |
ee06094f IM |
1118 | } |
1119 | ||
1120 | if (unlikely(left <= 0)) { | |
1121 | left += period; | |
e7850595 | 1122 | local64_set(&hwc->period_left, left); |
9e350de3 | 1123 | hwc->last_period = period; |
e4abb5d4 | 1124 | ret = 1; |
ee06094f | 1125 | } |
1c80f4b5 | 1126 | /* |
dfc65094 | 1127 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1128 | */ |
1129 | if (unlikely(left < 2)) | |
1130 | left = 2; | |
241771ef | 1131 | |
e4abb5d4 PZ |
1132 | if (left > x86_pmu.max_period) |
1133 | left = x86_pmu.max_period; | |
1134 | ||
294fe0f5 AK |
1135 | if (x86_pmu.limit_period) |
1136 | left = x86_pmu.limit_period(event, left); | |
1137 | ||
245b2e70 | 1138 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f | 1139 | |
851559e3 YZ |
1140 | if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) || |
1141 | local64_read(&hwc->prev_count) != (u64)-left) { | |
1142 | /* | |
1143 | * The hw event starts counting from this event offset, | |
1144 | * mark it to be able to extra future deltas: | |
1145 | */ | |
1146 | local64_set(&hwc->prev_count, (u64)-left); | |
ee06094f | 1147 | |
851559e3 YZ |
1148 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
1149 | } | |
68aa00ac CG |
1150 | |
1151 | /* | |
1152 | * Due to erratum on certan cpu we need | |
1153 | * a second write to be sure the register | |
1154 | * is updated properly | |
1155 | */ | |
1156 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1157 | wrmsrl(hwc->event_base, |
948b1bb8 | 1158 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1159 | } |
e4abb5d4 | 1160 | |
cdd6c482 | 1161 | perf_event_update_userpage(event); |
194002b2 | 1162 | |
e4abb5d4 | 1163 | return ret; |
2f18d1e8 IM |
1164 | } |
1165 | ||
de0428a7 | 1166 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1167 | { |
0a3aee0d | 1168 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1169 | __x86_pmu_enable_event(&event->hw, |
1170 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1171 | } |
1172 | ||
b690081d | 1173 | /* |
a4eaf7f1 | 1174 | * Add a single event to the PMU. |
1da53e02 SE |
1175 | * |
1176 | * The event is added to the group of enabled events | |
1177 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1178 | */ |
a4eaf7f1 | 1179 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1180 | { |
89cbc767 | 1181 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1182 | struct hw_perf_event *hwc; |
1183 | int assign[X86_PMC_IDX_MAX]; | |
1184 | int n, n0, ret; | |
fe9081cc | 1185 | |
1da53e02 | 1186 | hwc = &event->hw; |
fe9081cc | 1187 | |
1da53e02 | 1188 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1189 | ret = n = collect_events(cpuc, event, false); |
1190 | if (ret < 0) | |
1191 | goto out; | |
53b441a5 | 1192 | |
a4eaf7f1 PZ |
1193 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1194 | if (!(flags & PERF_EF_START)) | |
1195 | hwc->state |= PERF_HES_ARCH; | |
1196 | ||
4d1c52b0 LM |
1197 | /* |
1198 | * If group events scheduling transaction was started, | |
0d2eb44f | 1199 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1200 | * at commit time (->commit_txn) as a whole. |
4d1c52b0 | 1201 | */ |
8f3e5684 | 1202 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
24cd7f54 | 1203 | goto done_collect; |
4d1c52b0 | 1204 | |
a072738e | 1205 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1206 | if (ret) |
24cd7f54 | 1207 | goto out; |
1da53e02 SE |
1208 | /* |
1209 | * copy new assignment, now we know it is possible | |
1210 | * will be used by hw_perf_enable() | |
1211 | */ | |
1212 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1213 | |
24cd7f54 | 1214 | done_collect: |
c347a2f1 PZ |
1215 | /* |
1216 | * Commit the collect_events() state. See x86_pmu_del() and | |
1217 | * x86_pmu_*_txn(). | |
1218 | */ | |
1da53e02 | 1219 | cpuc->n_events = n; |
356e1f2e | 1220 | cpuc->n_added += n - n0; |
90151c35 | 1221 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1222 | |
24cd7f54 PZ |
1223 | ret = 0; |
1224 | out: | |
24cd7f54 | 1225 | return ret; |
241771ef IM |
1226 | } |
1227 | ||
a4eaf7f1 | 1228 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1229 | { |
89cbc767 | 1230 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1231 | int idx = event->hw.idx; |
1232 | ||
a4eaf7f1 PZ |
1233 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1234 | return; | |
1235 | ||
1236 | if (WARN_ON_ONCE(idx == -1)) | |
1237 | return; | |
1238 | ||
1239 | if (flags & PERF_EF_RELOAD) { | |
1240 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1241 | x86_perf_event_set_period(event); | |
1242 | } | |
1243 | ||
1244 | event->hw.state = 0; | |
d76a0812 | 1245 | |
c08053e6 PZ |
1246 | cpuc->events[idx] = event; |
1247 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1248 | __set_bit(idx, cpuc->running); |
aff3d91a | 1249 | x86_pmu.enable(event); |
c08053e6 | 1250 | perf_event_update_userpage(event); |
a78ac325 PZ |
1251 | } |
1252 | ||
cdd6c482 | 1253 | void perf_event_print_debug(void) |
241771ef | 1254 | { |
2f18d1e8 | 1255 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1256 | u64 pebs, debugctl; |
cdd6c482 | 1257 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1258 | unsigned long flags; |
1e125676 IM |
1259 | int cpu, idx; |
1260 | ||
948b1bb8 | 1261 | if (!x86_pmu.num_counters) |
1e125676 | 1262 | return; |
241771ef | 1263 | |
5bb9efe3 | 1264 | local_irq_save(flags); |
241771ef IM |
1265 | |
1266 | cpu = smp_processor_id(); | |
cdd6c482 | 1267 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1268 | |
faa28ae0 | 1269 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1270 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1271 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1272 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1273 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1274 | ||
1275 | pr_info("\n"); | |
1276 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1277 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1278 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1279 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
15fde110 AK |
1280 | if (x86_pmu.pebs_constraints) { |
1281 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); | |
1282 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1283 | } | |
da3e606d AK |
1284 | if (x86_pmu.lbr_nr) { |
1285 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1286 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1287 | } | |
f87ad35d | 1288 | } |
7645a24c | 1289 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1290 | |
948b1bb8 | 1291 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1292 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1293 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1294 | |
245b2e70 | 1295 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1296 | |
a1ef58f4 | 1297 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1298 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1299 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1300 | cpu, idx, pmc_count); |
a1ef58f4 | 1301 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1302 | cpu, idx, prev_left); |
241771ef | 1303 | } |
948b1bb8 | 1304 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1305 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1306 | ||
a1ef58f4 | 1307 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1308 | cpu, idx, pmc_count); |
1309 | } | |
5bb9efe3 | 1310 | local_irq_restore(flags); |
241771ef IM |
1311 | } |
1312 | ||
de0428a7 | 1313 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1314 | { |
89cbc767 | 1315 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1316 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1317 | |
a4eaf7f1 PZ |
1318 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1319 | x86_pmu.disable(event); | |
1320 | cpuc->events[hwc->idx] = NULL; | |
1321 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1322 | hwc->state |= PERF_HES_STOPPED; | |
1323 | } | |
30dd568c | 1324 | |
a4eaf7f1 PZ |
1325 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1326 | /* | |
1327 | * Drain the remaining delta count out of a event | |
1328 | * that we are disabling: | |
1329 | */ | |
1330 | x86_perf_event_update(event); | |
1331 | hwc->state |= PERF_HES_UPTODATE; | |
1332 | } | |
2e841873 PZ |
1333 | } |
1334 | ||
a4eaf7f1 | 1335 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1336 | { |
89cbc767 | 1337 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2e841873 PZ |
1338 | int i; |
1339 | ||
2f7f73a5 SE |
1340 | /* |
1341 | * event is descheduled | |
1342 | */ | |
1343 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1344 | ||
90151c35 SE |
1345 | /* |
1346 | * If we're called during a txn, we don't need to do anything. | |
1347 | * The events never got scheduled and ->cancel_txn will truncate | |
1348 | * the event_list. | |
c347a2f1 PZ |
1349 | * |
1350 | * XXX assumes any ->del() called during a TXN will only be on | |
1351 | * an event added during that same TXN. | |
90151c35 | 1352 | */ |
8f3e5684 | 1353 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
90151c35 SE |
1354 | return; |
1355 | ||
c347a2f1 PZ |
1356 | /* |
1357 | * Not a TXN, therefore cleanup properly. | |
1358 | */ | |
a4eaf7f1 | 1359 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1360 | |
1da53e02 | 1361 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1362 | if (event == cpuc->event_list[i]) |
1363 | break; | |
1364 | } | |
1da53e02 | 1365 | |
c347a2f1 PZ |
1366 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1367 | return; | |
26e61e89 | 1368 | |
c347a2f1 PZ |
1369 | /* If we have a newly added event; make sure to decrease n_added. */ |
1370 | if (i >= cpuc->n_events - cpuc->n_added) | |
1371 | --cpuc->n_added; | |
1da53e02 | 1372 | |
c347a2f1 PZ |
1373 | if (x86_pmu.put_event_constraints) |
1374 | x86_pmu.put_event_constraints(cpuc, event); | |
1375 | ||
1376 | /* Delete the array entry. */ | |
b371b594 | 1377 | while (++i < cpuc->n_events) { |
c347a2f1 | 1378 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 PZ |
1379 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
1380 | } | |
c347a2f1 | 1381 | --cpuc->n_events; |
1da53e02 | 1382 | |
cdd6c482 | 1383 | perf_event_update_userpage(event); |
241771ef IM |
1384 | } |
1385 | ||
de0428a7 | 1386 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1387 | { |
df1a132b | 1388 | struct perf_sample_data data; |
cdd6c482 IM |
1389 | struct cpu_hw_events *cpuc; |
1390 | struct perf_event *event; | |
11d1578f | 1391 | int idx, handled = 0; |
9029a5e3 IM |
1392 | u64 val; |
1393 | ||
89cbc767 | 1394 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1395 | |
2bce5dac DZ |
1396 | /* |
1397 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1398 | * inside the nmi handler. As a result, the unmasking was pushed | |
1399 | * into all the nmi handlers. | |
1400 | * | |
1401 | * This generic handler doesn't seem to have any issues where the | |
1402 | * unmasking occurs so it was left at the top. | |
1403 | */ | |
1404 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1405 | ||
948b1bb8 | 1406 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1407 | if (!test_bit(idx, cpuc->active_mask)) { |
1408 | /* | |
1409 | * Though we deactivated the counter some cpus | |
1410 | * might still deliver spurious interrupts still | |
1411 | * in flight. Catch them: | |
1412 | */ | |
1413 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1414 | handled++; | |
a29aa8a7 | 1415 | continue; |
63e6be6d | 1416 | } |
962bf7a6 | 1417 | |
cdd6c482 | 1418 | event = cpuc->events[idx]; |
a4016a79 | 1419 | |
cc2ad4ba | 1420 | val = x86_perf_event_update(event); |
948b1bb8 | 1421 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1422 | continue; |
962bf7a6 | 1423 | |
9e350de3 | 1424 | /* |
cdd6c482 | 1425 | * event overflow |
9e350de3 | 1426 | */ |
4177c42a | 1427 | handled++; |
fd0d000b | 1428 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1429 | |
07088edb | 1430 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1431 | continue; |
1432 | ||
a8b0ca17 | 1433 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1434 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1435 | } |
962bf7a6 | 1436 | |
9e350de3 PZ |
1437 | if (handled) |
1438 | inc_irq_stat(apic_perf_irqs); | |
1439 | ||
a29aa8a7 RR |
1440 | return handled; |
1441 | } | |
39d81eab | 1442 | |
cdd6c482 | 1443 | void perf_events_lapic_init(void) |
241771ef | 1444 | { |
04da8a43 | 1445 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1446 | return; |
85cf9dba | 1447 | |
241771ef | 1448 | /* |
c323d95f | 1449 | * Always use NMI for PMU |
241771ef | 1450 | */ |
c323d95f | 1451 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1452 | } |
1453 | ||
9326638c | 1454 | static int |
9c48f1c6 | 1455 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1456 | { |
14c63f17 DH |
1457 | u64 start_clock; |
1458 | u64 finish_clock; | |
e8a923cc | 1459 | int ret; |
14c63f17 | 1460 | |
1b7b938f AS |
1461 | /* |
1462 | * All PMUs/events that share this PMI handler should make sure to | |
1463 | * increment active_events for their events. | |
1464 | */ | |
cdd6c482 | 1465 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1466 | return NMI_DONE; |
4177c42a | 1467 | |
e8a923cc | 1468 | start_clock = sched_clock(); |
14c63f17 | 1469 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1470 | finish_clock = sched_clock(); |
14c63f17 DH |
1471 | |
1472 | perf_sample_event_took(finish_clock - start_clock); | |
1473 | ||
1474 | return ret; | |
241771ef | 1475 | } |
9326638c | 1476 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1477 | |
de0428a7 KW |
1478 | struct event_constraint emptyconstraint; |
1479 | struct event_constraint unconstrained; | |
f87ad35d | 1480 | |
95ca792c | 1481 | static int x86_pmu_prepare_cpu(unsigned int cpu) |
3f6da390 | 1482 | { |
7fdba1ca | 1483 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
95ca792c | 1484 | int i; |
3f6da390 | 1485 | |
95ca792c TG |
1486 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1487 | cpuc->kfree_on_online[i] = NULL; | |
1488 | if (x86_pmu.cpu_prepare) | |
1489 | return x86_pmu.cpu_prepare(cpu); | |
1490 | return 0; | |
1491 | } | |
7fdba1ca | 1492 | |
95ca792c TG |
1493 | static int x86_pmu_dead_cpu(unsigned int cpu) |
1494 | { | |
1495 | if (x86_pmu.cpu_dead) | |
1496 | x86_pmu.cpu_dead(cpu); | |
1497 | return 0; | |
1498 | } | |
3f6da390 | 1499 | |
95ca792c TG |
1500 | static int x86_pmu_online_cpu(unsigned int cpu) |
1501 | { | |
1502 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1503 | int i; | |
3f6da390 | 1504 | |
95ca792c TG |
1505 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1506 | kfree(cpuc->kfree_on_online[i]); | |
1507 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1508 | } |
95ca792c TG |
1509 | return 0; |
1510 | } | |
3f6da390 | 1511 | |
95ca792c TG |
1512 | static int x86_pmu_starting_cpu(unsigned int cpu) |
1513 | { | |
1514 | if (x86_pmu.cpu_starting) | |
1515 | x86_pmu.cpu_starting(cpu); | |
1516 | return 0; | |
1517 | } | |
1518 | ||
1519 | static int x86_pmu_dying_cpu(unsigned int cpu) | |
1520 | { | |
1521 | if (x86_pmu.cpu_dying) | |
1522 | x86_pmu.cpu_dying(cpu); | |
1523 | return 0; | |
3f6da390 PZ |
1524 | } |
1525 | ||
12558038 CG |
1526 | static void __init pmu_check_apic(void) |
1527 | { | |
93984fbd | 1528 | if (boot_cpu_has(X86_FEATURE_APIC)) |
12558038 CG |
1529 | return; |
1530 | ||
1531 | x86_pmu.apic = 0; | |
1532 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1533 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1534 | |
1535 | /* | |
1536 | * If we have a PMU initialized but no APIC | |
1537 | * interrupts, we cannot sample hardware | |
1538 | * events (user-space has to fall back and | |
1539 | * sample via a hrtimer based software event): | |
1540 | */ | |
1541 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1542 | ||
12558038 CG |
1543 | } |
1544 | ||
641cc938 JO |
1545 | static struct attribute_group x86_pmu_format_group = { |
1546 | .name = "format", | |
1547 | .attrs = NULL, | |
1548 | }; | |
1549 | ||
8300daa2 JO |
1550 | /* |
1551 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1552 | * out of events_attr attributes. | |
1553 | */ | |
1554 | static void __init filter_events(struct attribute **attrs) | |
1555 | { | |
3a54aaa0 SE |
1556 | struct device_attribute *d; |
1557 | struct perf_pmu_events_attr *pmu_attr; | |
61b87cae | 1558 | int offset = 0; |
8300daa2 JO |
1559 | int i, j; |
1560 | ||
1561 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1562 | d = (struct device_attribute *)attrs[i]; |
1563 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1564 | /* str trumps id */ | |
1565 | if (pmu_attr->event_str) | |
1566 | continue; | |
61b87cae | 1567 | if (x86_pmu.event_map(i + offset)) |
8300daa2 JO |
1568 | continue; |
1569 | ||
1570 | for (j = i; attrs[j]; j++) | |
1571 | attrs[j] = attrs[j + 1]; | |
1572 | ||
1573 | /* Check the shifted attr. */ | |
1574 | i--; | |
61b87cae SE |
1575 | |
1576 | /* | |
1577 | * event_map() is index based, the attrs array is organized | |
1578 | * by increasing event index. If we shift the events, then | |
1579 | * we need to compensate for the event_map(), otherwise | |
1580 | * we are looking up the wrong event in the map | |
1581 | */ | |
1582 | offset++; | |
8300daa2 JO |
1583 | } |
1584 | } | |
1585 | ||
1a6461b1 | 1586 | /* Merge two pointer arrays */ |
47732d88 | 1587 | __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) |
1a6461b1 AK |
1588 | { |
1589 | struct attribute **new; | |
1590 | int j, i; | |
1591 | ||
1592 | for (j = 0; a[j]; j++) | |
1593 | ; | |
1594 | for (i = 0; b[i]; i++) | |
1595 | j++; | |
1596 | j++; | |
1597 | ||
1598 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1599 | if (!new) | |
1600 | return NULL; | |
1601 | ||
1602 | j = 0; | |
1603 | for (i = 0; a[i]; i++) | |
1604 | new[j++] = a[i]; | |
1605 | for (i = 0; b[i]; i++) | |
1606 | new[j++] = b[i]; | |
1607 | new[j] = NULL; | |
1608 | ||
1609 | return new; | |
1610 | } | |
1611 | ||
c7ab62bf | 1612 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) |
a4747393 JO |
1613 | { |
1614 | struct perf_pmu_events_attr *pmu_attr = \ | |
1615 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1616 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1617 | |
3a54aaa0 SE |
1618 | /* string trumps id */ |
1619 | if (pmu_attr->event_str) | |
1620 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1621 | |
3a54aaa0 SE |
1622 | return x86_pmu.events_sysfs_show(page, config); |
1623 | } | |
c7ab62bf | 1624 | EXPORT_SYMBOL_GPL(events_sysfs_show); |
a4747393 | 1625 | |
fc07e9f9 AK |
1626 | ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, |
1627 | char *page) | |
1628 | { | |
1629 | struct perf_pmu_events_ht_attr *pmu_attr = | |
1630 | container_of(attr, struct perf_pmu_events_ht_attr, attr); | |
1631 | ||
1632 | /* | |
1633 | * Report conditional events depending on Hyper-Threading. | |
1634 | * | |
1635 | * This is overly conservative as usually the HT special | |
1636 | * handling is not needed if the other CPU thread is idle. | |
1637 | * | |
1638 | * Note this does not (and cannot) handle the case when thread | |
1639 | * siblings are invisible, for example with virtualization | |
1640 | * if they are owned by some other guest. The user tool | |
1641 | * has to re-read when a thread sibling gets onlined later. | |
1642 | */ | |
1643 | return sprintf(page, "%s", | |
1644 | topology_max_smt_threads() > 1 ? | |
1645 | pmu_attr->event_str_ht : | |
1646 | pmu_attr->event_str_noht); | |
1647 | } | |
1648 | ||
a4747393 JO |
1649 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); |
1650 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1651 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1652 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1653 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1654 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1655 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1656 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1657 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1658 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1659 | ||
1660 | static struct attribute *empty_attrs; | |
1661 | ||
95d18aa2 | 1662 | static struct attribute *events_attr[] = { |
a4747393 JO |
1663 | EVENT_PTR(CPU_CYCLES), |
1664 | EVENT_PTR(INSTRUCTIONS), | |
1665 | EVENT_PTR(CACHE_REFERENCES), | |
1666 | EVENT_PTR(CACHE_MISSES), | |
1667 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1668 | EVENT_PTR(BRANCH_MISSES), | |
1669 | EVENT_PTR(BUS_CYCLES), | |
1670 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1671 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1672 | EVENT_PTR(REF_CPU_CYCLES), | |
1673 | NULL, | |
1674 | }; | |
1675 | ||
1676 | static struct attribute_group x86_pmu_events_group = { | |
1677 | .name = "events", | |
1678 | .attrs = events_attr, | |
1679 | }; | |
1680 | ||
0bf79d44 | 1681 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1682 | { |
43c032fe JO |
1683 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1684 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1685 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1686 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1687 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1688 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1689 | ssize_t ret; | |
1690 | ||
1691 | /* | |
1692 | * We have whole page size to spend and just little data | |
1693 | * to write, so we can safely use sprintf. | |
1694 | */ | |
1695 | ret = sprintf(page, "event=0x%02llx", event); | |
1696 | ||
1697 | if (umask) | |
1698 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1699 | ||
1700 | if (edge) | |
1701 | ret += sprintf(page + ret, ",edge"); | |
1702 | ||
1703 | if (pc) | |
1704 | ret += sprintf(page + ret, ",pc"); | |
1705 | ||
1706 | if (any) | |
1707 | ret += sprintf(page + ret, ",any"); | |
1708 | ||
1709 | if (inv) | |
1710 | ret += sprintf(page + ret, ",inv"); | |
1711 | ||
1712 | if (cmask) | |
1713 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1714 | ||
1715 | ret += sprintf(page + ret, "\n"); | |
1716 | ||
1717 | return ret; | |
1718 | } | |
1719 | ||
dda99116 | 1720 | static int __init init_hw_perf_events(void) |
b56a3802 | 1721 | { |
c1d6f42f | 1722 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1723 | int err; |
1724 | ||
cdd6c482 | 1725 | pr_info("Performance Events: "); |
1123e3ad | 1726 | |
b56a3802 JSR |
1727 | switch (boot_cpu_data.x86_vendor) { |
1728 | case X86_VENDOR_INTEL: | |
72eae04d | 1729 | err = intel_pmu_init(); |
b56a3802 | 1730 | break; |
f87ad35d | 1731 | case X86_VENDOR_AMD: |
72eae04d | 1732 | err = amd_pmu_init(); |
f87ad35d | 1733 | break; |
4138960a | 1734 | default: |
8a3da6c7 | 1735 | err = -ENOTSUPP; |
b56a3802 | 1736 | } |
1123e3ad | 1737 | if (err != 0) { |
cdd6c482 | 1738 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1739 | return 0; |
1123e3ad | 1740 | } |
b56a3802 | 1741 | |
12558038 CG |
1742 | pmu_check_apic(); |
1743 | ||
33c6d6a7 | 1744 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1745 | if (!check_hw_exists()) |
004417a6 | 1746 | return 0; |
33c6d6a7 | 1747 | |
1123e3ad | 1748 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1749 | |
e97df763 PZ |
1750 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1751 | ||
c1d6f42f PZ |
1752 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1753 | quirk->func(); | |
3c44780b | 1754 | |
a1eac7ac RR |
1755 | if (!x86_pmu.intel_ctrl) |
1756 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1757 | |
cdd6c482 | 1758 | perf_events_lapic_init(); |
9c48f1c6 | 1759 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1760 | |
63b14649 | 1761 | unconstrained = (struct event_constraint) |
948b1bb8 | 1762 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1763 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1764 | |
641cc938 | 1765 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1766 | |
f20093ee SE |
1767 | if (x86_pmu.event_attrs) |
1768 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1769 | ||
a4747393 JO |
1770 | if (!x86_pmu.events_sysfs_show) |
1771 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1772 | else |
1773 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1774 | |
1a6461b1 AK |
1775 | if (x86_pmu.cpu_events) { |
1776 | struct attribute **tmp; | |
1777 | ||
1778 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1779 | if (!WARN_ON(!tmp)) | |
1780 | x86_pmu_events_group.attrs = tmp; | |
1781 | } | |
1782 | ||
57c0c15b | 1783 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1784 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1785 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1786 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1787 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1788 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1789 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1790 | |
95ca792c TG |
1791 | /* |
1792 | * Install callbacks. Core will call them for each online | |
1793 | * cpu. | |
1794 | */ | |
1795 | err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "PERF_X86_PREPARE", | |
1796 | x86_pmu_prepare_cpu, x86_pmu_dead_cpu); | |
1797 | if (err) | |
1798 | return err; | |
1799 | ||
1800 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, | |
1801 | "AP_PERF_X86_STARTING", x86_pmu_starting_cpu, | |
1802 | x86_pmu_dying_cpu); | |
1803 | if (err) | |
1804 | goto out; | |
1805 | ||
1806 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "AP_PERF_X86_ONLINE", | |
1807 | x86_pmu_online_cpu, NULL); | |
1808 | if (err) | |
1809 | goto out1; | |
1810 | ||
1811 | err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); | |
1812 | if (err) | |
1813 | goto out2; | |
004417a6 PZ |
1814 | |
1815 | return 0; | |
95ca792c TG |
1816 | |
1817 | out2: | |
1818 | cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE); | |
1819 | out1: | |
1820 | cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); | |
1821 | out: | |
1822 | cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); | |
1823 | return err; | |
241771ef | 1824 | } |
004417a6 | 1825 | early_initcall(init_hw_perf_events); |
621a01ea | 1826 | |
cdd6c482 | 1827 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1828 | { |
cc2ad4ba | 1829 | x86_perf_event_update(event); |
ee06094f IM |
1830 | } |
1831 | ||
4d1c52b0 LM |
1832 | /* |
1833 | * Start group events scheduling transaction | |
1834 | * Set the flag to make pmu::enable() not perform the | |
1835 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1836 | * |
1837 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1838 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1839 | * transactions. | |
4d1c52b0 | 1840 | */ |
fbbe0701 | 1841 | static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
4d1c52b0 | 1842 | { |
fbbe0701 SB |
1843 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1844 | ||
1845 | WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ | |
1846 | ||
1847 | cpuc->txn_flags = txn_flags; | |
1848 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1849 | return; | |
1850 | ||
33696fc0 | 1851 | perf_pmu_disable(pmu); |
0a3aee0d | 1852 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
4d1c52b0 LM |
1853 | } |
1854 | ||
1855 | /* | |
1856 | * Stop group events scheduling transaction | |
1857 | * Clear the flag and pmu::enable() will perform the | |
1858 | * schedulability test. | |
1859 | */ | |
51b0fe39 | 1860 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1861 | { |
fbbe0701 SB |
1862 | unsigned int txn_flags; |
1863 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
1864 | ||
1865 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ | |
1866 | ||
1867 | txn_flags = cpuc->txn_flags; | |
1868 | cpuc->txn_flags = 0; | |
1869 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1870 | return; | |
1871 | ||
90151c35 | 1872 | /* |
c347a2f1 PZ |
1873 | * Truncate collected array by the number of events added in this |
1874 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1875 | */ |
0a3aee0d TH |
1876 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1877 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1878 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1879 | } |
1880 | ||
1881 | /* | |
1882 | * Commit group events scheduling transaction | |
1883 | * Perform the group schedulability test as a whole | |
1884 | * Return 0 if success | |
c347a2f1 PZ |
1885 | * |
1886 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1887 | */ |
51b0fe39 | 1888 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 1889 | { |
89cbc767 | 1890 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
1891 | int assign[X86_PMC_IDX_MAX]; |
1892 | int n, ret; | |
1893 | ||
fbbe0701 SB |
1894 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
1895 | ||
1896 | if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1897 | cpuc->txn_flags = 0; | |
1898 | return 0; | |
1899 | } | |
1900 | ||
4d1c52b0 LM |
1901 | n = cpuc->n_events; |
1902 | ||
1903 | if (!x86_pmu_initialized()) | |
1904 | return -EAGAIN; | |
1905 | ||
1906 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1907 | if (ret) | |
1908 | return ret; | |
1909 | ||
1910 | /* | |
1911 | * copy new assignment, now we know it is possible | |
1912 | * will be used by hw_perf_enable() | |
1913 | */ | |
1914 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1915 | ||
fbbe0701 | 1916 | cpuc->txn_flags = 0; |
33696fc0 | 1917 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1918 | return 0; |
1919 | } | |
cd8a38d3 SE |
1920 | /* |
1921 | * a fake_cpuc is used to validate event groups. Due to | |
1922 | * the extra reg logic, we need to also allocate a fake | |
1923 | * per_core and per_cpu structure. Otherwise, group events | |
1924 | * using extra reg may conflict without the kernel being | |
1925 | * able to catch this when the last event gets added to | |
1926 | * the group. | |
1927 | */ | |
1928 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1929 | { | |
1930 | kfree(cpuc->shared_regs); | |
1931 | kfree(cpuc); | |
1932 | } | |
1933 | ||
1934 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1935 | { | |
1936 | struct cpu_hw_events *cpuc; | |
1937 | int cpu = raw_smp_processor_id(); | |
1938 | ||
1939 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1940 | if (!cpuc) | |
1941 | return ERR_PTR(-ENOMEM); | |
1942 | ||
1943 | /* only needed, if we have extra_regs */ | |
1944 | if (x86_pmu.extra_regs) { | |
1945 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1946 | if (!cpuc->shared_regs) | |
1947 | goto error; | |
1948 | } | |
b430f7c4 | 1949 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1950 | return cpuc; |
1951 | error: | |
1952 | free_fake_cpuc(cpuc); | |
1953 | return ERR_PTR(-ENOMEM); | |
1954 | } | |
4d1c52b0 | 1955 | |
ca037701 PZ |
1956 | /* |
1957 | * validate that we can schedule this event | |
1958 | */ | |
1959 | static int validate_event(struct perf_event *event) | |
1960 | { | |
1961 | struct cpu_hw_events *fake_cpuc; | |
1962 | struct event_constraint *c; | |
1963 | int ret = 0; | |
1964 | ||
cd8a38d3 SE |
1965 | fake_cpuc = allocate_fake_cpuc(); |
1966 | if (IS_ERR(fake_cpuc)) | |
1967 | return PTR_ERR(fake_cpuc); | |
ca037701 | 1968 | |
79cba822 | 1969 | c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); |
ca037701 PZ |
1970 | |
1971 | if (!c || !c->weight) | |
aa2bc1ad | 1972 | ret = -EINVAL; |
ca037701 PZ |
1973 | |
1974 | if (x86_pmu.put_event_constraints) | |
1975 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1976 | ||
cd8a38d3 | 1977 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1978 | |
1979 | return ret; | |
1980 | } | |
1981 | ||
1da53e02 SE |
1982 | /* |
1983 | * validate a single event group | |
1984 | * | |
1985 | * validation include: | |
184f412c IM |
1986 | * - check events are compatible which each other |
1987 | * - events do not compete for the same counter | |
1988 | * - number of events <= number of counters | |
1da53e02 SE |
1989 | * |
1990 | * validation ensures the group can be loaded onto the | |
1991 | * PMU if it was the only group available. | |
1992 | */ | |
fe9081cc PZ |
1993 | static int validate_group(struct perf_event *event) |
1994 | { | |
1da53e02 | 1995 | struct perf_event *leader = event->group_leader; |
502568d5 | 1996 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1997 | int ret = -EINVAL, n; |
fe9081cc | 1998 | |
cd8a38d3 SE |
1999 | fake_cpuc = allocate_fake_cpuc(); |
2000 | if (IS_ERR(fake_cpuc)) | |
2001 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
2002 | /* |
2003 | * the event is not yet connected with its | |
2004 | * siblings therefore we must first collect | |
2005 | * existing siblings, then add the new event | |
2006 | * before we can simulate the scheduling | |
2007 | */ | |
502568d5 | 2008 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 2009 | if (n < 0) |
cd8a38d3 | 2010 | goto out; |
fe9081cc | 2011 | |
502568d5 PZ |
2012 | fake_cpuc->n_events = n; |
2013 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 2014 | if (n < 0) |
cd8a38d3 | 2015 | goto out; |
fe9081cc | 2016 | |
502568d5 | 2017 | fake_cpuc->n_events = n; |
1da53e02 | 2018 | |
a072738e | 2019 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 2020 | |
502568d5 | 2021 | out: |
cd8a38d3 | 2022 | free_fake_cpuc(fake_cpuc); |
502568d5 | 2023 | return ret; |
fe9081cc PZ |
2024 | } |
2025 | ||
dda99116 | 2026 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 2027 | { |
51b0fe39 | 2028 | struct pmu *tmp; |
621a01ea IM |
2029 | int err; |
2030 | ||
b0a873eb PZ |
2031 | switch (event->attr.type) { |
2032 | case PERF_TYPE_RAW: | |
2033 | case PERF_TYPE_HARDWARE: | |
2034 | case PERF_TYPE_HW_CACHE: | |
2035 | break; | |
2036 | ||
2037 | default: | |
2038 | return -ENOENT; | |
2039 | } | |
2040 | ||
2041 | err = __x86_pmu_event_init(event); | |
fe9081cc | 2042 | if (!err) { |
8113070d SE |
2043 | /* |
2044 | * we temporarily connect event to its pmu | |
2045 | * such that validate_group() can classify | |
2046 | * it as an x86 event using is_x86_event() | |
2047 | */ | |
2048 | tmp = event->pmu; | |
2049 | event->pmu = &pmu; | |
2050 | ||
fe9081cc PZ |
2051 | if (event->group_leader != event) |
2052 | err = validate_group(event); | |
ca037701 PZ |
2053 | else |
2054 | err = validate_event(event); | |
8113070d SE |
2055 | |
2056 | event->pmu = tmp; | |
fe9081cc | 2057 | } |
a1792cda | 2058 | if (err) { |
cdd6c482 IM |
2059 | if (event->destroy) |
2060 | event->destroy(event); | |
a1792cda | 2061 | } |
621a01ea | 2062 | |
7911d3f7 AL |
2063 | if (ACCESS_ONCE(x86_pmu.attr_rdpmc)) |
2064 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; | |
2065 | ||
b0a873eb | 2066 | return err; |
621a01ea | 2067 | } |
d7d59fb3 | 2068 | |
7911d3f7 AL |
2069 | static void refresh_pce(void *ignored) |
2070 | { | |
2071 | if (current->mm) | |
2072 | load_mm_cr4(current->mm); | |
2073 | } | |
2074 | ||
2075 | static void x86_pmu_event_mapped(struct perf_event *event) | |
2076 | { | |
2077 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2078 | return; | |
2079 | ||
2080 | if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1) | |
2081 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2082 | } | |
2083 | ||
2084 | static void x86_pmu_event_unmapped(struct perf_event *event) | |
2085 | { | |
2086 | if (!current->mm) | |
2087 | return; | |
2088 | ||
2089 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2090 | return; | |
2091 | ||
2092 | if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed)) | |
2093 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2094 | } | |
2095 | ||
fe4a3308 PZ |
2096 | static int x86_pmu_event_idx(struct perf_event *event) |
2097 | { | |
2098 | int idx = event->hw.idx; | |
2099 | ||
7911d3f7 | 2100 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
c7206205 PZ |
2101 | return 0; |
2102 | ||
15c7ad51 RR |
2103 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
2104 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
2105 | idx |= 1 << 30; |
2106 | } | |
2107 | ||
2108 | return idx + 1; | |
2109 | } | |
2110 | ||
0c9d42ed PZ |
2111 | static ssize_t get_attr_rdpmc(struct device *cdev, |
2112 | struct device_attribute *attr, | |
2113 | char *buf) | |
2114 | { | |
2115 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
2116 | } | |
2117 | ||
0c9d42ed PZ |
2118 | static ssize_t set_attr_rdpmc(struct device *cdev, |
2119 | struct device_attribute *attr, | |
2120 | const char *buf, size_t count) | |
2121 | { | |
e2b297fc SK |
2122 | unsigned long val; |
2123 | ssize_t ret; | |
2124 | ||
2125 | ret = kstrtoul(buf, 0, &val); | |
2126 | if (ret) | |
2127 | return ret; | |
e97df763 | 2128 | |
a6673429 AL |
2129 | if (val > 2) |
2130 | return -EINVAL; | |
2131 | ||
e97df763 PZ |
2132 | if (x86_pmu.attr_rdpmc_broken) |
2133 | return -ENOTSUPP; | |
0c9d42ed | 2134 | |
a6673429 AL |
2135 | if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { |
2136 | /* | |
2137 | * Changing into or out of always available, aka | |
2138 | * perf-event-bypassing mode. This path is extremely slow, | |
2139 | * but only root can trigger it, so it's okay. | |
2140 | */ | |
2141 | if (val == 2) | |
2142 | static_key_slow_inc(&rdpmc_always_available); | |
2143 | else | |
2144 | static_key_slow_dec(&rdpmc_always_available); | |
2145 | on_each_cpu(refresh_pce, NULL, 1); | |
2146 | } | |
2147 | ||
2148 | x86_pmu.attr_rdpmc = val; | |
2149 | ||
0c9d42ed PZ |
2150 | return count; |
2151 | } | |
2152 | ||
2153 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2154 | ||
2155 | static struct attribute *x86_pmu_attrs[] = { | |
2156 | &dev_attr_rdpmc.attr, | |
2157 | NULL, | |
2158 | }; | |
2159 | ||
2160 | static struct attribute_group x86_pmu_attr_group = { | |
2161 | .attrs = x86_pmu_attrs, | |
2162 | }; | |
2163 | ||
2164 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
2165 | &x86_pmu_attr_group, | |
641cc938 | 2166 | &x86_pmu_format_group, |
a4747393 | 2167 | &x86_pmu_events_group, |
0c9d42ed PZ |
2168 | NULL, |
2169 | }; | |
2170 | ||
ba532500 | 2171 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d010b332 | 2172 | { |
ba532500 YZ |
2173 | if (x86_pmu.sched_task) |
2174 | x86_pmu.sched_task(ctx, sched_in); | |
d010b332 SE |
2175 | } |
2176 | ||
c93dc84c PZ |
2177 | void perf_check_microcode(void) |
2178 | { | |
2179 | if (x86_pmu.check_microcode) | |
2180 | x86_pmu.check_microcode(); | |
2181 | } | |
2182 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
2183 | ||
b0a873eb | 2184 | static struct pmu pmu = { |
d010b332 SE |
2185 | .pmu_enable = x86_pmu_enable, |
2186 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2187 | |
c93dc84c | 2188 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2189 | |
c93dc84c | 2190 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2191 | |
7911d3f7 AL |
2192 | .event_mapped = x86_pmu_event_mapped, |
2193 | .event_unmapped = x86_pmu_event_unmapped, | |
2194 | ||
d010b332 SE |
2195 | .add = x86_pmu_add, |
2196 | .del = x86_pmu_del, | |
2197 | .start = x86_pmu_start, | |
2198 | .stop = x86_pmu_stop, | |
2199 | .read = x86_pmu_read, | |
a4eaf7f1 | 2200 | |
c93dc84c PZ |
2201 | .start_txn = x86_pmu_start_txn, |
2202 | .cancel_txn = x86_pmu_cancel_txn, | |
2203 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2204 | |
c93dc84c | 2205 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2206 | .sched_task = x86_pmu_sched_task, |
e18bf526 | 2207 | .task_ctx_size = sizeof(struct x86_perf_task_context), |
b0a873eb PZ |
2208 | }; |
2209 | ||
c1317ec2 AL |
2210 | void arch_perf_update_userpage(struct perf_event *event, |
2211 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2212 | { |
20d1c86a PZ |
2213 | struct cyc2ns_data *data; |
2214 | ||
fa731587 PZ |
2215 | userpg->cap_user_time = 0; |
2216 | userpg->cap_user_time_zero = 0; | |
7911d3f7 AL |
2217 | userpg->cap_user_rdpmc = |
2218 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); | |
c7206205 PZ |
2219 | userpg->pmc_width = x86_pmu.cntval_bits; |
2220 | ||
35af99e6 | 2221 | if (!sched_clock_stable()) |
e3f3541c PZ |
2222 | return; |
2223 | ||
20d1c86a PZ |
2224 | data = cyc2ns_read_begin(); |
2225 | ||
34f43927 PZ |
2226 | /* |
2227 | * Internal timekeeping for enabled/running/stopped times | |
2228 | * is always in the local_clock domain. | |
2229 | */ | |
fa731587 | 2230 | userpg->cap_user_time = 1; |
20d1c86a PZ |
2231 | userpg->time_mult = data->cyc2ns_mul; |
2232 | userpg->time_shift = data->cyc2ns_shift; | |
2233 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 2234 | |
34f43927 PZ |
2235 | /* |
2236 | * cap_user_time_zero doesn't make sense when we're using a different | |
2237 | * time base for the records. | |
2238 | */ | |
f454bfdd | 2239 | if (!event->attr.use_clockid) { |
34f43927 PZ |
2240 | userpg->cap_user_time_zero = 1; |
2241 | userpg->time_zero = data->cyc2ns_offset; | |
2242 | } | |
20d1c86a PZ |
2243 | |
2244 | cyc2ns_read_end(data); | |
e3f3541c PZ |
2245 | } |
2246 | ||
d7d59fb3 PZ |
2247 | /* |
2248 | * callchain support | |
2249 | */ | |
2250 | ||
d7d59fb3 PZ |
2251 | static int backtrace_stack(void *data, char *name) |
2252 | { | |
038e836e | 2253 | return 0; |
d7d59fb3 PZ |
2254 | } |
2255 | ||
568b329a | 2256 | static int backtrace_address(void *data, unsigned long addr, int reliable) |
d7d59fb3 | 2257 | { |
cfbcf468 | 2258 | struct perf_callchain_entry_ctx *entry = data; |
d7d59fb3 | 2259 | |
568b329a | 2260 | return perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
2261 | } |
2262 | ||
2263 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
2264 | .stack = backtrace_stack, |
2265 | .address = backtrace_address, | |
06d65bda | 2266 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
2267 | }; |
2268 | ||
56962b44 | 2269 | void |
cfbcf468 | 2270 | perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 | 2271 | { |
927c7a9e FW |
2272 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2273 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2274 | return; |
927c7a9e FW |
2275 | } |
2276 | ||
70791ce9 | 2277 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2278 | |
e8e999cf | 2279 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
2280 | } |
2281 | ||
bc6ca7b3 AS |
2282 | static inline int |
2283 | valid_user_frame(const void __user *fp, unsigned long size) | |
2284 | { | |
2285 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
2286 | } | |
2287 | ||
d07bdfd3 PZ |
2288 | static unsigned long get_segment_base(unsigned int segment) |
2289 | { | |
2290 | struct desc_struct *desc; | |
2291 | int idx = segment >> 3; | |
2292 | ||
2293 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
a5b9e5a2 | 2294 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
37868fe1 AL |
2295 | struct ldt_struct *ldt; |
2296 | ||
d07bdfd3 PZ |
2297 | if (idx > LDT_ENTRIES) |
2298 | return 0; | |
2299 | ||
37868fe1 AL |
2300 | /* IRQs are off, so this synchronizes with smp_store_release */ |
2301 | ldt = lockless_dereference(current->active_mm->context.ldt); | |
2302 | if (!ldt || idx > ldt->size) | |
d07bdfd3 PZ |
2303 | return 0; |
2304 | ||
37868fe1 | 2305 | desc = &ldt->entries[idx]; |
a5b9e5a2 AL |
2306 | #else |
2307 | return 0; | |
2308 | #endif | |
d07bdfd3 PZ |
2309 | } else { |
2310 | if (idx > GDT_ENTRIES) | |
2311 | return 0; | |
2312 | ||
37868fe1 | 2313 | desc = raw_cpu_ptr(gdt_page.gdt) + idx; |
d07bdfd3 PZ |
2314 | } |
2315 | ||
37868fe1 | 2316 | return get_desc_base(desc); |
d07bdfd3 PZ |
2317 | } |
2318 | ||
10ed3493 | 2319 | #ifdef CONFIG_IA32_EMULATION |
d1a797f3 PA |
2320 | |
2321 | #include <asm/compat.h> | |
2322 | ||
257ef9d2 | 2323 | static inline int |
cfbcf468 | 2324 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
74193ef0 | 2325 | { |
257ef9d2 | 2326 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2327 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2328 | struct stack_frame_ia32 frame; |
2329 | const void __user *fp; | |
74193ef0 | 2330 | |
257ef9d2 TE |
2331 | if (!test_thread_flag(TIF_IA32)) |
2332 | return 0; | |
2333 | ||
d07bdfd3 PZ |
2334 | cs_base = get_segment_base(regs->cs); |
2335 | ss_base = get_segment_base(regs->ss); | |
2336 | ||
2337 | fp = compat_ptr(ss_base + regs->bp); | |
75925e1a | 2338 | pagefault_disable(); |
3b1fff08 | 2339 | while (entry->nr < entry->max_stack) { |
257ef9d2 TE |
2340 | unsigned long bytes; |
2341 | frame.next_frame = 0; | |
2342 | frame.return_address = 0; | |
2343 | ||
75925e1a AK |
2344 | if (!access_ok(VERIFY_READ, fp, 8)) |
2345 | break; | |
2346 | ||
2347 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); | |
2348 | if (bytes != 0) | |
2349 | break; | |
2350 | bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); | |
0a196848 | 2351 | if (bytes != 0) |
257ef9d2 | 2352 | break; |
74193ef0 | 2353 | |
bc6ca7b3 AS |
2354 | if (!valid_user_frame(fp, sizeof(frame))) |
2355 | break; | |
2356 | ||
d07bdfd3 PZ |
2357 | perf_callchain_store(entry, cs_base + frame.return_address); |
2358 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 | 2359 | } |
75925e1a | 2360 | pagefault_enable(); |
257ef9d2 | 2361 | return 1; |
d7d59fb3 | 2362 | } |
257ef9d2 TE |
2363 | #else |
2364 | static inline int | |
cfbcf468 | 2365 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
257ef9d2 TE |
2366 | { |
2367 | return 0; | |
2368 | } | |
2369 | #endif | |
d7d59fb3 | 2370 | |
56962b44 | 2371 | void |
cfbcf468 | 2372 | perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 PZ |
2373 | { |
2374 | struct stack_frame frame; | |
fc188225 | 2375 | const unsigned long __user *fp; |
d7d59fb3 | 2376 | |
927c7a9e FW |
2377 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2378 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2379 | return; |
927c7a9e | 2380 | } |
5a6cec3a | 2381 | |
d07bdfd3 PZ |
2382 | /* |
2383 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2384 | */ | |
2385 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2386 | return; | |
2387 | ||
fc188225 | 2388 | fp = (unsigned long __user *)regs->bp; |
d7d59fb3 | 2389 | |
70791ce9 | 2390 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2391 | |
20afc60f AV |
2392 | if (!current->mm) |
2393 | return; | |
2394 | ||
257ef9d2 TE |
2395 | if (perf_callchain_user32(regs, entry)) |
2396 | return; | |
2397 | ||
75925e1a | 2398 | pagefault_disable(); |
3b1fff08 | 2399 | while (entry->nr < entry->max_stack) { |
257ef9d2 | 2400 | unsigned long bytes; |
fc188225 | 2401 | |
038e836e | 2402 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2403 | frame.return_address = 0; |
2404 | ||
fc188225 | 2405 | if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2)) |
75925e1a AK |
2406 | break; |
2407 | ||
fc188225 | 2408 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp)); |
75925e1a AK |
2409 | if (bytes != 0) |
2410 | break; | |
fc188225 | 2411 | bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp)); |
0a196848 | 2412 | if (bytes != 0) |
d7d59fb3 PZ |
2413 | break; |
2414 | ||
bc6ca7b3 AS |
2415 | if (!valid_user_frame(fp, sizeof(frame))) |
2416 | break; | |
2417 | ||
70791ce9 | 2418 | perf_callchain_store(entry, frame.return_address); |
75925e1a | 2419 | fp = (void __user *)frame.next_frame; |
d7d59fb3 | 2420 | } |
75925e1a | 2421 | pagefault_enable(); |
d7d59fb3 PZ |
2422 | } |
2423 | ||
d07bdfd3 PZ |
2424 | /* |
2425 | * Deal with code segment offsets for the various execution modes: | |
2426 | * | |
2427 | * VM86 - the good olde 16 bit days, where the linear address is | |
2428 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2429 | * | |
2430 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2431 | * to figure out what the 32bit base address is. | |
2432 | * | |
2433 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2434 | * | |
2435 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2436 | */ | |
2437 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2438 | { |
383f3af3 AL |
2439 | /* |
2440 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2441 | * effective IP to a linear address. | |
2442 | */ | |
2443 | ||
2444 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2445 | /* |
2446 | * If we are in VM86 mode, add the segment offset to convert to a | |
2447 | * linear address. | |
2448 | */ | |
2449 | if (regs->flags & X86_VM_MASK) | |
2450 | return 0x10 * regs->cs; | |
2451 | ||
55474c48 | 2452 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2453 | return get_segment_base(regs->cs); |
2454 | #else | |
c56716af AL |
2455 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2456 | regs->cs != __USER32_CS) | |
2457 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2458 | #endif |
2459 | return 0; | |
2460 | } | |
dcf46b94 | 2461 | |
d07bdfd3 PZ |
2462 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2463 | { | |
39447b38 | 2464 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2465 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2466 | |
d07bdfd3 | 2467 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2468 | } |
2469 | ||
2470 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2471 | { | |
2472 | int misc = 0; | |
dcf46b94 | 2473 | |
39447b38 | 2474 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2475 | if (perf_guest_cbs->is_user_mode()) |
2476 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2477 | else | |
2478 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2479 | } else { | |
d07bdfd3 | 2480 | if (user_mode(regs)) |
dcf46b94 ZY |
2481 | misc |= PERF_RECORD_MISC_USER; |
2482 | else | |
2483 | misc |= PERF_RECORD_MISC_KERNEL; | |
2484 | } | |
2485 | ||
39447b38 | 2486 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2487 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2488 | |
2489 | return misc; | |
2490 | } | |
b3d9468a GN |
2491 | |
2492 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2493 | { | |
2494 | cap->version = x86_pmu.version; | |
2495 | cap->num_counters_gp = x86_pmu.num_counters; | |
2496 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2497 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2498 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2499 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2500 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2501 | } | |
2502 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |