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Merge tag 'iio-for-4.8b' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio...
[deliverable/linux.git] / arch / x86 / events / intel / core.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
aacfbe6a 15#include <linux/nmi.h>
de0428a7 16
3a632cb2 17#include <asm/cpufeature.h>
de0428a7
KW		 18#include <asm/hardirq.h>
19#include <asm/apic.h>
20
27f6d22b 21#include "../perf_event.h"
a7e3ed1e 22
f22f54f4 23/*
b622d644 24 * Intel PerfMon, used on Core and later.
f22f54f4 25 */
ec75a716 26static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 27{
c3b7cdf1
PE		 28 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 36};
37
5c543e3c 38static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 39{
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
46 EVENT_CONSTRAINT_END
47};
48
5c543e3c 49static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 50{
b622d644
PZ		 51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
64 EVENT_CONSTRAINT_END
65};
66
5c543e3c 67static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 68{
b622d644
PZ		 69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
80 EVENT_CONSTRAINT_END
81};
82
5c543e3c 83static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 84{
53ad0447
YZ		 85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 88 EVENT_EXTRA_END
89};
90
5c543e3c 91static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 92{
b622d644
PZ		 93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 100 EVENT_CONSTRAINT_END
101};
102
5c543e3c 103static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 104{
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c
MD		 117
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
122
b06b3d49
LM		 123 EVENT_CONSTRAINT_END
124};
125
69943182
SE		 126static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
127{
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c
MD		 141
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
146
69943182
SE		 147 EVENT_CONSTRAINT_END
148};
149
5c543e3c 150static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 151{
53ad0447
YZ		 152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 156 EVENT_EXTRA_END
157};
158
0af3ac1f
AK		 159static struct event_constraint intel_v1_event_constraints[] __read_mostly =
160{
161 EVENT_CONSTRAINT_END
162};
163
5c543e3c 164static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 165{
b622d644
PZ		 166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 169 EVENT_CONSTRAINT_END
170};
171
1fa64180
YZ		 172static struct event_constraint intel_slm_event_constraints[] __read_mostly =
173{
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
177 EVENT_CONSTRAINT_END
178};
179
9a92e16f
AK		 180struct event_constraint intel_skl_event_constraints[] = {
181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
185 EVENT_CONSTRAINT_END
186};
187
1e7b9390
HC		 188static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
189 INTEL_UEVENT_EXTRA_REG(0x01b7,
190 MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
191 INTEL_UEVENT_EXTRA_REG(0x02b7,
192 MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
193 EVENT_EXTRA_END
194};
195
ee89cbc2 196static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 197 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
198 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
199 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 200 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 201 EVENT_EXTRA_END
202};
203
204static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 205 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
206 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
207 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 208 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 209 EVENT_EXTRA_END
210};
211
9a92e16f
AK		 212static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
213 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
214 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
215 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
dfe1f3cb
AK		 216 /*
217 * Note the low 8 bits eventsel code is not a continuous field, containing
218 * some #GPing bits. These are masked out.
219 */
220 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
9a92e16f
AK		 221 EVENT_EXTRA_END
222};
223
7f2ee91f
IM		 224EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
225EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
226EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 227
228struct attribute *nhm_events_attrs[] = {
229 EVENT_PTR(mem_ld_nhm),
230 NULL,
231};
232
233struct attribute *snb_events_attrs[] = {
234 EVENT_PTR(mem_ld_snb),
9ad64c0f 235 EVENT_PTR(mem_st_snb),
f20093ee
SE		 236 NULL,
237};
238
3a632cb2
AK		 239static struct event_constraint intel_hsw_event_constraints[] = {
240 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
241 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
242 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
e0fbac1c 243 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
3a632cb2
AK		 244 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
245 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
246 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 247 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 248 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 249 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 250 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 251 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c
MD		 252
253 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
254 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
255 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
256 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
257
3a632cb2
AK		 258 EVENT_CONSTRAINT_END
259};
260
91f1b705
AK		 261struct event_constraint intel_bdw_event_constraints[] = {
262 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
263 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
264 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
265 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
b7883a1c 266 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
91f1b705
AK		 267 EVENT_CONSTRAINT_END
268};
269
f22f54f4
PZ		 270static u64 intel_pmu_event_map(int hw_event)
271{
272 return intel_perfmon_event_map[hw_event];
273}
274
9a92e16f
AK		 275/*
276 * Notes on the events:
277 * - data reads do not include code reads (comparable to earlier tables)
278 * - data counts include speculative execution (except L1 write, dtlb, bpu)
279 * - remote node access includes remote memory, remote cache, remote mmio.
280 * - prefetches are not included in the counts.
281 * - icache miss does not include decoded icache
282 */
283
284#define SKL_DEMAND_DATA_RD BIT_ULL(0)
285#define SKL_DEMAND_RFO BIT_ULL(1)
286#define SKL_ANY_RESPONSE BIT_ULL(16)
287#define SKL_SUPPLIER_NONE BIT_ULL(17)
288#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
289#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
290#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
291#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
292#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
293 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
294 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
295 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
296#define SKL_SPL_HIT BIT_ULL(30)
297#define SKL_SNOOP_NONE BIT_ULL(31)
298#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
299#define SKL_SNOOP_MISS BIT_ULL(33)
300#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
301#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
302#define SKL_SNOOP_HITM BIT_ULL(36)
303#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
304#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
305 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
306 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
307 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
308#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
309#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
310 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
311 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
312 SKL_SNOOP_HITM|SKL_SPL_HIT)
313#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
314#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
315#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
316 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
317 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
318
319static __initconst const u64 skl_hw_cache_event_ids
320 [PERF_COUNT_HW_CACHE_MAX]
321 [PERF_COUNT_HW_CACHE_OP_MAX]
322 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
323{
324 [ C(L1D ) ] = {
325 [ C(OP_READ) ] = {
326 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
327 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
328 },
329 [ C(OP_WRITE) ] = {
330 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
331 [ C(RESULT_MISS) ] = 0x0,
332 },
333 [ C(OP_PREFETCH) ] = {
334 [ C(RESULT_ACCESS) ] = 0x0,
335 [ C(RESULT_MISS) ] = 0x0,
336 },
337 },
338 [ C(L1I ) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = 0x0,
341 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
342 },
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = -1,
345 [ C(RESULT_MISS) ] = -1,
346 },
347 [ C(OP_PREFETCH) ] = {
348 [ C(RESULT_ACCESS) ] = 0x0,
349 [ C(RESULT_MISS) ] = 0x0,
350 },
351 },
352 [ C(LL ) ] = {
353 [ C(OP_READ) ] = {
354 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
355 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
356 },
357 [ C(OP_WRITE) ] = {
358 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
359 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
360 },
361 [ C(OP_PREFETCH) ] = {
362 [ C(RESULT_ACCESS) ] = 0x0,
363 [ C(RESULT_MISS) ] = 0x0,
364 },
365 },
366 [ C(DTLB) ] = {
367 [ C(OP_READ) ] = {
368 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
369 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
370 },
371 [ C(OP_WRITE) ] = {
372 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
373 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
374 },
375 [ C(OP_PREFETCH) ] = {
376 [ C(RESULT_ACCESS) ] = 0x0,
377 [ C(RESULT_MISS) ] = 0x0,
378 },
379 },
380 [ C(ITLB) ] = {
381 [ C(OP_READ) ] = {
382 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
383 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
384 },
385 [ C(OP_WRITE) ] = {
386 [ C(RESULT_ACCESS) ] = -1,
387 [ C(RESULT_MISS) ] = -1,
388 },
389 [ C(OP_PREFETCH) ] = {
390 [ C(RESULT_ACCESS) ] = -1,
391 [ C(RESULT_MISS) ] = -1,
392 },
393 },
394 [ C(BPU ) ] = {
395 [ C(OP_READ) ] = {
396 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
397 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
398 },
399 [ C(OP_WRITE) ] = {
400 [ C(RESULT_ACCESS) ] = -1,
401 [ C(RESULT_MISS) ] = -1,
402 },
403 [ C(OP_PREFETCH) ] = {
404 [ C(RESULT_ACCESS) ] = -1,
405 [ C(RESULT_MISS) ] = -1,
406 },
407 },
408 [ C(NODE) ] = {
409 [ C(OP_READ) ] = {
410 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
411 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
412 },
413 [ C(OP_WRITE) ] = {
414 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
415 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
416 },
417 [ C(OP_PREFETCH) ] = {
418 [ C(RESULT_ACCESS) ] = 0x0,
419 [ C(RESULT_MISS) ] = 0x0,
420 },
421 },
422};
423
424static __initconst const u64 skl_hw_cache_extra_regs
425 [PERF_COUNT_HW_CACHE_MAX]
426 [PERF_COUNT_HW_CACHE_OP_MAX]
427 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
428{
429 [ C(LL ) ] = {
430 [ C(OP_READ) ] = {
431 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
432 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
433 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
434 SKL_L3_MISS|SKL_ANY_SNOOP|
435 SKL_SUPPLIER_NONE,
436 },
437 [ C(OP_WRITE) ] = {
438 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
439 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
440 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
441 SKL_L3_MISS|SKL_ANY_SNOOP|
442 SKL_SUPPLIER_NONE,
443 },
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0x0,
447 },
448 },
449 [ C(NODE) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
452 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
453 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
454 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
455 },
456 [ C(OP_WRITE) ] = {
457 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
458 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
459 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
460 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
461 },
462 [ C(OP_PREFETCH) ] = {
463 [ C(RESULT_ACCESS) ] = 0x0,
464 [ C(RESULT_MISS) ] = 0x0,
465 },
466 },
467};
468
74e6543f
YZ		 469#define SNB_DMND_DATA_RD (1ULL << 0)
470#define SNB_DMND_RFO (1ULL << 1)
471#define SNB_DMND_IFETCH (1ULL << 2)
472#define SNB_DMND_WB (1ULL << 3)
473#define SNB_PF_DATA_RD (1ULL << 4)
474#define SNB_PF_RFO (1ULL << 5)
475#define SNB_PF_IFETCH (1ULL << 6)
476#define SNB_LLC_DATA_RD (1ULL << 7)
477#define SNB_LLC_RFO (1ULL << 8)
478#define SNB_LLC_IFETCH (1ULL << 9)
479#define SNB_BUS_LOCKS (1ULL << 10)
480#define SNB_STRM_ST (1ULL << 11)
481#define SNB_OTHER (1ULL << 15)
482#define SNB_RESP_ANY (1ULL << 16)
483#define SNB_NO_SUPP (1ULL << 17)
484#define SNB_LLC_HITM (1ULL << 18)
485#define SNB_LLC_HITE (1ULL << 19)
486#define SNB_LLC_HITS (1ULL << 20)
487#define SNB_LLC_HITF (1ULL << 21)
488#define SNB_LOCAL (1ULL << 22)
489#define SNB_REMOTE (0xffULL << 23)
490#define SNB_SNP_NONE (1ULL << 31)
491#define SNB_SNP_NOT_NEEDED (1ULL << 32)
492#define SNB_SNP_MISS (1ULL << 33)
493#define SNB_NO_FWD (1ULL << 34)
494#define SNB_SNP_FWD (1ULL << 35)
495#define SNB_HITM (1ULL << 36)
496#define SNB_NON_DRAM (1ULL << 37)
497
498#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
499#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
500#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
501
502#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
503 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
504 SNB_HITM)
505
506#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
507#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
508
509#define SNB_L3_ACCESS SNB_RESP_ANY
510#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
511
512static __initconst const u64 snb_hw_cache_extra_regs
513 [PERF_COUNT_HW_CACHE_MAX]
514 [PERF_COUNT_HW_CACHE_OP_MAX]
515 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
516{
517 [ C(LL ) ] = {
518 [ C(OP_READ) ] = {
519 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
520 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
521 },
522 [ C(OP_WRITE) ] = {
523 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
524 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
525 },
526 [ C(OP_PREFETCH) ] = {
527 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
528 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
529 },
530 },
531 [ C(NODE) ] = {
532 [ C(OP_READ) ] = {
533 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
534 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
535 },
536 [ C(OP_WRITE) ] = {
537 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
538 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
539 },
540 [ C(OP_PREFETCH) ] = {
541 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
542 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
543 },
544 },
545};
546
b06b3d49
LM		 547static __initconst const u64 snb_hw_cache_event_ids
548 [PERF_COUNT_HW_CACHE_MAX]
549 [PERF_COUNT_HW_CACHE_OP_MAX]
550 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
551{
552 [ C(L1D) ] = {
553 [ C(OP_READ) ] = {
554 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
555 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
556 },
557 [ C(OP_WRITE) ] = {
558 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
559 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
560 },
561 [ C(OP_PREFETCH) ] = {
562 [ C(RESULT_ACCESS) ] = 0x0,
563 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
564 },
565 },
566 [ C(L1I ) ] = {
567 [ C(OP_READ) ] = {
568 [ C(RESULT_ACCESS) ] = 0x0,
569 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
570 },
571 [ C(OP_WRITE) ] = {
572 [ C(RESULT_ACCESS) ] = -1,
573 [ C(RESULT_MISS) ] = -1,
574 },
575 [ C(OP_PREFETCH) ] = {
576 [ C(RESULT_ACCESS) ] = 0x0,
577 [ C(RESULT_MISS) ] = 0x0,
578 },
579 },
580 [ C(LL ) ] = {
b06b3d49 581 [ C(OP_READ) ] = {
63b6a675 582 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 583 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 584 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
585 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 586 },
587 [ C(OP_WRITE) ] = {
63b6a675 588 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 589 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 590 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
591 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 592 },
593 [ C(OP_PREFETCH) ] = {
63b6a675 594 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 595 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 596 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
597 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 598 },
599 },
600 [ C(DTLB) ] = {
601 [ C(OP_READ) ] = {
602 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
603 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
604 },
605 [ C(OP_WRITE) ] = {
606 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
607 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
608 },
609 [ C(OP_PREFETCH) ] = {
610 [ C(RESULT_ACCESS) ] = 0x0,
611 [ C(RESULT_MISS) ] = 0x0,
612 },
613 },
614 [ C(ITLB) ] = {
615 [ C(OP_READ) ] = {
616 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
617 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
618 },
619 [ C(OP_WRITE) ] = {
620 [ C(RESULT_ACCESS) ] = -1,
621 [ C(RESULT_MISS) ] = -1,
622 },
623 [ C(OP_PREFETCH) ] = {
624 [ C(RESULT_ACCESS) ] = -1,
625 [ C(RESULT_MISS) ] = -1,
626 },
627 },
628 [ C(BPU ) ] = {
629 [ C(OP_READ) ] = {
630 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
631 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
632 },
633 [ C(OP_WRITE) ] = {
634 [ C(RESULT_ACCESS) ] = -1,
635 [ C(RESULT_MISS) ] = -1,
636 },
637 [ C(OP_PREFETCH) ] = {
638 [ C(RESULT_ACCESS) ] = -1,
639 [ C(RESULT_MISS) ] = -1,
640 },
641 },
89d6c0b5
PZ		 642 [ C(NODE) ] = {
643 [ C(OP_READ) ] = {
74e6543f
YZ		 644 [ C(RESULT_ACCESS) ] = 0x01b7,
645 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 646 },
647 [ C(OP_WRITE) ] = {
74e6543f
YZ		 648 [ C(RESULT_ACCESS) ] = 0x01b7,
649 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 650 },
651 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 652 [ C(RESULT_ACCESS) ] = 0x01b7,
653 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 654 },
655 },
656
b06b3d49
LM		 657};
658
0f1b5ca2
AK		 659/*
660 * Notes on the events:
661 * - data reads do not include code reads (comparable to earlier tables)
662 * - data counts include speculative execution (except L1 write, dtlb, bpu)
663 * - remote node access includes remote memory, remote cache, remote mmio.
664 * - prefetches are not included in the counts because they are not
665 * reliably counted.
666 */
667
668#define HSW_DEMAND_DATA_RD BIT_ULL(0)
669#define HSW_DEMAND_RFO BIT_ULL(1)
670#define HSW_ANY_RESPONSE BIT_ULL(16)
671#define HSW_SUPPLIER_NONE BIT_ULL(17)
672#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
673#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
674#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
675#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
676#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
677 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
678 HSW_L3_MISS_REMOTE_HOP2P)
679#define HSW_SNOOP_NONE BIT_ULL(31)
680#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
681#define HSW_SNOOP_MISS BIT_ULL(33)
682#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
683#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
684#define HSW_SNOOP_HITM BIT_ULL(36)
685#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
686#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
687 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
688 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
689 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
690#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
691#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
692#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
693#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
694 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
695#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
696
91f1b705
AK		 697#define BDW_L3_MISS_LOCAL BIT(26)
698#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
699 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
700 HSW_L3_MISS_REMOTE_HOP2P)
701
702
0f1b5ca2
AK		 703static __initconst const u64 hsw_hw_cache_event_ids
704 [PERF_COUNT_HW_CACHE_MAX]
705 [PERF_COUNT_HW_CACHE_OP_MAX]
706 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
707{
708 [ C(L1D ) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
711 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
715 [ C(RESULT_MISS) ] = 0x0,
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = 0x0,
719 [ C(RESULT_MISS) ] = 0x0,
720 },
721 },
722 [ C(L1I ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0,
725 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0x0,
733 [ C(RESULT_MISS) ] = 0x0,
734 },
735 },
736 [ C(LL ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
739 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
743 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0x0,
747 [ C(RESULT_MISS) ] = 0x0,
748 },
749 },
750 [ C(DTLB) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
753 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
757 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0x0,
761 [ C(RESULT_MISS) ] = 0x0,
762 },
763 },
764 [ C(ITLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
767 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = -1,
771 [ C(RESULT_MISS) ] = -1,
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 },
778 [ C(BPU ) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
781 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792 [ C(NODE) ] = {
793 [ C(OP_READ) ] = {
794 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
795 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
796 },
797 [ C(OP_WRITE) ] = {
798 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
799 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
800 },
801 [ C(OP_PREFETCH) ] = {
802 [ C(RESULT_ACCESS) ] = 0x0,
803 [ C(RESULT_MISS) ] = 0x0,
804 },
805 },
806};
807
808static __initconst const u64 hsw_hw_cache_extra_regs
809 [PERF_COUNT_HW_CACHE_MAX]
810 [PERF_COUNT_HW_CACHE_OP_MAX]
811 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
812{
813 [ C(LL ) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
816 HSW_LLC_ACCESS,
817 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
818 HSW_L3_MISS|HSW_ANY_SNOOP,
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
822 HSW_LLC_ACCESS,
823 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
824 HSW_L3_MISS|HSW_ANY_SNOOP,
825 },
826 [ C(OP_PREFETCH) ] = {
827 [ C(RESULT_ACCESS) ] = 0x0,
828 [ C(RESULT_MISS) ] = 0x0,
829 },
830 },
831 [ C(NODE) ] = {
832 [ C(OP_READ) ] = {
833 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
834 HSW_L3_MISS_LOCAL_DRAM|
835 HSW_SNOOP_DRAM,
836 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
837 HSW_L3_MISS_REMOTE|
838 HSW_SNOOP_DRAM,
839 },
840 [ C(OP_WRITE) ] = {
841 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
842 HSW_L3_MISS_LOCAL_DRAM|
843 HSW_SNOOP_DRAM,
844 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
845 HSW_L3_MISS_REMOTE|
846 HSW_SNOOP_DRAM,
847 },
848 [ C(OP_PREFETCH) ] = {
849 [ C(RESULT_ACCESS) ] = 0x0,
850 [ C(RESULT_MISS) ] = 0x0,
851 },
852 },
853};
854
caaa8be3 855static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 856 [PERF_COUNT_HW_CACHE_MAX]
857 [PERF_COUNT_HW_CACHE_OP_MAX]
858 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
859{
860 [ C(L1D) ] = {
861 [ C(OP_READ) ] = {
862 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
863 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
864 },
865 [ C(OP_WRITE) ] = {
866 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
867 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
868 },
869 [ C(OP_PREFETCH) ] = {
870 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
871 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
872 },
873 },
874 [ C(L1I ) ] = {
875 [ C(OP_READ) ] = {
876 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
877 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
878 },
879 [ C(OP_WRITE) ] = {
880 [ C(RESULT_ACCESS) ] = -1,
881 [ C(RESULT_MISS) ] = -1,
882 },
883 [ C(OP_PREFETCH) ] = {
884 [ C(RESULT_ACCESS) ] = 0x0,
885 [ C(RESULT_MISS) ] = 0x0,
886 },
887 },
888 [ C(LL ) ] = {
889 [ C(OP_READ) ] = {
63b6a675 890 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 891 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 892 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
893 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 894 },
e994d7d2
AK		 895 /*
896 * Use RFO, not WRITEBACK, because a write miss would typically occur
897 * on RFO.
898 */
f22f54f4 899 [ C(OP_WRITE) ] = {
63b6a675
PZ		 900 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
901 [ C(RESULT_ACCESS) ] = 0x01b7,
902 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 903 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 904 },
905 [ C(OP_PREFETCH) ] = {
63b6a675 906 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 907 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 908 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
909 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 910 },
911 },
912 [ C(DTLB) ] = {
913 [ C(OP_READ) ] = {
914 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
915 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
916 },
917 [ C(OP_WRITE) ] = {
918 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
919 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
920 },
921 [ C(OP_PREFETCH) ] = {
922 [ C(RESULT_ACCESS) ] = 0x0,
923 [ C(RESULT_MISS) ] = 0x0,
924 },
925 },
926 [ C(ITLB) ] = {
927 [ C(OP_READ) ] = {
928 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
929 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
930 },
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = -1,
933 [ C(RESULT_MISS) ] = -1,
934 },
935 [ C(OP_PREFETCH) ] = {
936 [ C(RESULT_ACCESS) ] = -1,
937 [ C(RESULT_MISS) ] = -1,
938 },
939 },
940 [ C(BPU ) ] = {
941 [ C(OP_READ) ] = {
942 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
943 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
944 },
945 [ C(OP_WRITE) ] = {
946 [ C(RESULT_ACCESS) ] = -1,
947 [ C(RESULT_MISS) ] = -1,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = -1,
951 [ C(RESULT_MISS) ] = -1,
952 },
953 },
89d6c0b5
PZ		 954 [ C(NODE) ] = {
955 [ C(OP_READ) ] = {
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957 [ C(RESULT_MISS) ] = 0x01b7,
958 },
959 [ C(OP_WRITE) ] = {
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 [ C(RESULT_MISS) ] = 0x01b7,
962 },
963 [ C(OP_PREFETCH) ] = {
964 [ C(RESULT_ACCESS) ] = 0x01b7,
965 [ C(RESULT_MISS) ] = 0x01b7,
966 },
967 },
f22f54f4
PZ		 968};
969
e994d7d2 970/*
63b6a675
PZ		 971 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
972 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 973 */
974
63b6a675
PZ		 975#define NHM_DMND_DATA_RD (1 << 0)
976#define NHM_DMND_RFO (1 << 1)
977#define NHM_DMND_IFETCH (1 << 2)
978#define NHM_DMND_WB (1 << 3)
979#define NHM_PF_DATA_RD (1 << 4)
980#define NHM_PF_DATA_RFO (1 << 5)
981#define NHM_PF_IFETCH (1 << 6)
982#define NHM_OFFCORE_OTHER (1 << 7)
983#define NHM_UNCORE_HIT (1 << 8)
984#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
985#define NHM_OTHER_CORE_HITM (1 << 10)
986 /* reserved */
987#define NHM_REMOTE_CACHE_FWD (1 << 12)
988#define NHM_REMOTE_DRAM (1 << 13)
989#define NHM_LOCAL_DRAM (1 << 14)
990#define NHM_NON_DRAM (1 << 15)
991
87e24f4b
PZ		 992#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
993#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 994
995#define NHM_DMND_READ (NHM_DMND_DATA_RD)
996#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
997#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
998
999#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 1000#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 1001#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 1002
1003static __initconst const u64 nehalem_hw_cache_extra_regs
1004 [PERF_COUNT_HW_CACHE_MAX]
1005 [PERF_COUNT_HW_CACHE_OP_MAX]
1006 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1007{
1008 [ C(LL ) ] = {
1009 [ C(OP_READ) ] = {
63b6a675
PZ		 1010 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1011 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 1012 },
1013 [ C(OP_WRITE) ] = {
63b6a675
PZ		 1014 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1015 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 1016 },
1017 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 1018 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1019 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 1020 },
89d6c0b5
PZ		 1021 },
1022 [ C(NODE) ] = {
1023 [ C(OP_READ) ] = {
87e24f4b
PZ		 1024 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1025 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 1026 },
1027 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 1028 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1029 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 1030 },
1031 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 1032 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1033 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 1034 },
1035 },
e994d7d2
AK		 1036};
1037
caaa8be3 1038static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 1039 [PERF_COUNT_HW_CACHE_MAX]
1040 [PERF_COUNT_HW_CACHE_OP_MAX]
1041 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1042{
1043 [ C(L1D) ] = {
1044 [ C(OP_READ) ] = {
f4929bd3
PZ		 1045 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1046 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 1047 },
1048 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 1049 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1050 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 1051 },
1052 [ C(OP_PREFETCH) ] = {
1053 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1054 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1055 },
1056 },
1057 [ C(L1I ) ] = {
1058 [ C(OP_READ) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1060 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1061 },
1062 [ C(OP_WRITE) ] = {
1063 [ C(RESULT_ACCESS) ] = -1,
1064 [ C(RESULT_MISS) ] = -1,
1065 },
1066 [ C(OP_PREFETCH) ] = {
1067 [ C(RESULT_ACCESS) ] = 0x0,
1068 [ C(RESULT_MISS) ] = 0x0,
1069 },
1070 },
1071 [ C(LL ) ] = {
1072 [ C(OP_READ) ] = {
e994d7d2
AK		 1073 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1074 [ C(RESULT_ACCESS) ] = 0x01b7,
1075 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1076 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 1077 },
e994d7d2
AK		 1078 /*
1079 * Use RFO, not WRITEBACK, because a write miss would typically occur
1080 * on RFO.
1081 */
f22f54f4 1082 [ C(OP_WRITE) ] = {
e994d7d2
AK		 1083 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1084 [ C(RESULT_ACCESS) ] = 0x01b7,
1085 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1086 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1087 },
1088 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 1089 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1090 [ C(RESULT_ACCESS) ] = 0x01b7,
1091 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1092 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1093 },
1094 },
1095 [ C(DTLB) ] = {
1096 [ C(OP_READ) ] = {
1097 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1098 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1099 },
1100 [ C(OP_WRITE) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1102 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1103 },
1104 [ C(OP_PREFETCH) ] = {
1105 [ C(RESULT_ACCESS) ] = 0x0,
1106 [ C(RESULT_MISS) ] = 0x0,
1107 },
1108 },
1109 [ C(ITLB) ] = {
1110 [ C(OP_READ) ] = {
1111 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1112 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1113 },
1114 [ C(OP_WRITE) ] = {
1115 [ C(RESULT_ACCESS) ] = -1,
1116 [ C(RESULT_MISS) ] = -1,
1117 },
1118 [ C(OP_PREFETCH) ] = {
1119 [ C(RESULT_ACCESS) ] = -1,
1120 [ C(RESULT_MISS) ] = -1,
1121 },
1122 },
1123 [ C(BPU ) ] = {
1124 [ C(OP_READ) ] = {
1125 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1126 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1127 },
1128 [ C(OP_WRITE) ] = {
1129 [ C(RESULT_ACCESS) ] = -1,
1130 [ C(RESULT_MISS) ] = -1,
1131 },
1132 [ C(OP_PREFETCH) ] = {
1133 [ C(RESULT_ACCESS) ] = -1,
1134 [ C(RESULT_MISS) ] = -1,
1135 },
1136 },
89d6c0b5
PZ		 1137 [ C(NODE) ] = {
1138 [ C(OP_READ) ] = {
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 [ C(RESULT_MISS) ] = 0x01b7,
1141 },
1142 [ C(OP_WRITE) ] = {
1143 [ C(RESULT_ACCESS) ] = 0x01b7,
1144 [ C(RESULT_MISS) ] = 0x01b7,
1145 },
1146 [ C(OP_PREFETCH) ] = {
1147 [ C(RESULT_ACCESS) ] = 0x01b7,
1148 [ C(RESULT_MISS) ] = 0x01b7,
1149 },
1150 },
f22f54f4
PZ		 1151};
1152
caaa8be3 1153static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 1154 [PERF_COUNT_HW_CACHE_MAX]
1155 [PERF_COUNT_HW_CACHE_OP_MAX]
1156 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1157{
1158 [ C(L1D) ] = {
1159 [ C(OP_READ) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1161 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1162 },
1163 [ C(OP_WRITE) ] = {
1164 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1165 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1166 },
1167 [ C(OP_PREFETCH) ] = {
1168 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1169 [ C(RESULT_MISS) ] = 0,
1170 },
1171 },
1172 [ C(L1I ) ] = {
1173 [ C(OP_READ) ] = {
1174 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1175 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1176 },
1177 [ C(OP_WRITE) ] = {
1178 [ C(RESULT_ACCESS) ] = -1,
1179 [ C(RESULT_MISS) ] = -1,
1180 },
1181 [ C(OP_PREFETCH) ] = {
1182 [ C(RESULT_ACCESS) ] = 0,
1183 [ C(RESULT_MISS) ] = 0,
1184 },
1185 },
1186 [ C(LL ) ] = {
1187 [ C(OP_READ) ] = {
1188 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1189 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1190 },
1191 [ C(OP_WRITE) ] = {
1192 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1193 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1194 },
1195 [ C(OP_PREFETCH) ] = {
1196 [ C(RESULT_ACCESS) ] = 0,
1197 [ C(RESULT_MISS) ] = 0,
1198 },
1199 },
1200 [ C(DTLB) ] = {
1201 [ C(OP_READ) ] = {
1202 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1203 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1204 },
1205 [ C(OP_WRITE) ] = {
1206 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1207 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1208 },
1209 [ C(OP_PREFETCH) ] = {
1210 [ C(RESULT_ACCESS) ] = 0,
1211 [ C(RESULT_MISS) ] = 0,
1212 },
1213 },
1214 [ C(ITLB) ] = {
1215 [ C(OP_READ) ] = {
1216 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1217 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1218 },
1219 [ C(OP_WRITE) ] = {
1220 [ C(RESULT_ACCESS) ] = -1,
1221 [ C(RESULT_MISS) ] = -1,
1222 },
1223 [ C(OP_PREFETCH) ] = {
1224 [ C(RESULT_ACCESS) ] = -1,
1225 [ C(RESULT_MISS) ] = -1,
1226 },
1227 },
1228 [ C(BPU ) ] = {
1229 [ C(OP_READ) ] = {
1230 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1231 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1232 },
1233 [ C(OP_WRITE) ] = {
1234 [ C(RESULT_ACCESS) ] = -1,
1235 [ C(RESULT_MISS) ] = -1,
1236 },
1237 [ C(OP_PREFETCH) ] = {
1238 [ C(RESULT_ACCESS) ] = -1,
1239 [ C(RESULT_MISS) ] = -1,
1240 },
1241 },
1242};
1243
caaa8be3 1244static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1245 [PERF_COUNT_HW_CACHE_MAX]
1246 [PERF_COUNT_HW_CACHE_OP_MAX]
1247 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1248{
1249 [ C(L1D) ] = {
1250 [ C(OP_READ) ] = {
1251 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1252 [ C(RESULT_MISS) ] = 0,
1253 },
1254 [ C(OP_WRITE) ] = {
1255 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1256 [ C(RESULT_MISS) ] = 0,
1257 },
1258 [ C(OP_PREFETCH) ] = {
1259 [ C(RESULT_ACCESS) ] = 0x0,
1260 [ C(RESULT_MISS) ] = 0,
1261 },
1262 },
1263 [ C(L1I ) ] = {
1264 [ C(OP_READ) ] = {
1265 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1266 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1267 },
1268 [ C(OP_WRITE) ] = {
1269 [ C(RESULT_ACCESS) ] = -1,
1270 [ C(RESULT_MISS) ] = -1,
1271 },
1272 [ C(OP_PREFETCH) ] = {
1273 [ C(RESULT_ACCESS) ] = 0,
1274 [ C(RESULT_MISS) ] = 0,
1275 },
1276 },
1277 [ C(LL ) ] = {
1278 [ C(OP_READ) ] = {
1279 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1280 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1281 },
1282 [ C(OP_WRITE) ] = {
1283 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1284 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1285 },
1286 [ C(OP_PREFETCH) ] = {
1287 [ C(RESULT_ACCESS) ] = 0,
1288 [ C(RESULT_MISS) ] = 0,
1289 },
1290 },
1291 [ C(DTLB) ] = {
1292 [ C(OP_READ) ] = {
1293 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1294 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1295 },
1296 [ C(OP_WRITE) ] = {
1297 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1298 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1299 },
1300 [ C(OP_PREFETCH) ] = {
1301 [ C(RESULT_ACCESS) ] = 0,
1302 [ C(RESULT_MISS) ] = 0,
1303 },
1304 },
1305 [ C(ITLB) ] = {
1306 [ C(OP_READ) ] = {
1307 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1308 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1309 },
1310 [ C(OP_WRITE) ] = {
1311 [ C(RESULT_ACCESS) ] = -1,
1312 [ C(RESULT_MISS) ] = -1,
1313 },
1314 [ C(OP_PREFETCH) ] = {
1315 [ C(RESULT_ACCESS) ] = -1,
1316 [ C(RESULT_MISS) ] = -1,
1317 },
1318 },
1319 [ C(BPU ) ] = {
1320 [ C(OP_READ) ] = {
1321 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1322 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1323 },
1324 [ C(OP_WRITE) ] = {
1325 [ C(RESULT_ACCESS) ] = -1,
1326 [ C(RESULT_MISS) ] = -1,
1327 },
1328 [ C(OP_PREFETCH) ] = {
1329 [ C(RESULT_ACCESS) ] = -1,
1330 [ C(RESULT_MISS) ] = -1,
1331 },
1332 },
1333};
1334
1fa64180
YZ		 1335static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1336{
1337 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1 1338 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
ae3f011f 1339 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1fa64180
YZ		 1340 EVENT_EXTRA_END
1341};
1342
1343#define SLM_DMND_READ SNB_DMND_DATA_RD
1344#define SLM_DMND_WRITE SNB_DMND_RFO
1345#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1346
1347#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1348#define SLM_LLC_ACCESS SNB_RESP_ANY
1349#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1350
1351static __initconst const u64 slm_hw_cache_extra_regs
1352 [PERF_COUNT_HW_CACHE_MAX]
1353 [PERF_COUNT_HW_CACHE_OP_MAX]
1354 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1355{
1356 [ C(LL ) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
6d374056 1359 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1363 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1367 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1368 },
1369 },
1370};
1371
1372static __initconst const u64 slm_hw_cache_event_ids
1373 [PERF_COUNT_HW_CACHE_MAX]
1374 [PERF_COUNT_HW_CACHE_OP_MAX]
1375 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1376{
1377 [ C(L1D) ] = {
1378 [ C(OP_READ) ] = {
1379 [ C(RESULT_ACCESS) ] = 0,
1380 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1381 },
1382 [ C(OP_WRITE) ] = {
1383 [ C(RESULT_ACCESS) ] = 0,
1384 [ C(RESULT_MISS) ] = 0,
1385 },
1386 [ C(OP_PREFETCH) ] = {
1387 [ C(RESULT_ACCESS) ] = 0,
1388 [ C(RESULT_MISS) ] = 0,
1389 },
1390 },
1391 [ C(L1I ) ] = {
1392 [ C(OP_READ) ] = {
1393 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1394 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1395 },
1396 [ C(OP_WRITE) ] = {
1397 [ C(RESULT_ACCESS) ] = -1,
1398 [ C(RESULT_MISS) ] = -1,
1399 },
1400 [ C(OP_PREFETCH) ] = {
1401 [ C(RESULT_ACCESS) ] = 0,
1402 [ C(RESULT_MISS) ] = 0,
1403 },
1404 },
1405 [ C(LL ) ] = {
1406 [ C(OP_READ) ] = {
1407 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1408 [ C(RESULT_ACCESS) ] = 0x01b7,
6d374056 1409 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1410 },
1411 [ C(OP_WRITE) ] = {
1412 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1413 [ C(RESULT_ACCESS) ] = 0x01b7,
1414 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1415 [ C(RESULT_MISS) ] = 0x01b7,
1416 },
1417 [ C(OP_PREFETCH) ] = {
1418 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1419 [ C(RESULT_ACCESS) ] = 0x01b7,
1420 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1421 [ C(RESULT_MISS) ] = 0x01b7,
1422 },
1423 },
1424 [ C(DTLB) ] = {
1425 [ C(OP_READ) ] = {
1426 [ C(RESULT_ACCESS) ] = 0,
1427 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1428 },
1429 [ C(OP_WRITE) ] = {
1430 [ C(RESULT_ACCESS) ] = 0,
1431 [ C(RESULT_MISS) ] = 0,
1432 },
1433 [ C(OP_PREFETCH) ] = {
1434 [ C(RESULT_ACCESS) ] = 0,
1435 [ C(RESULT_MISS) ] = 0,
1436 },
1437 },
1438 [ C(ITLB) ] = {
1439 [ C(OP_READ) ] = {
1440 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
6d374056 1441 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1fa64180
YZ		 1442 },
1443 [ C(OP_WRITE) ] = {
1444 [ C(RESULT_ACCESS) ] = -1,
1445 [ C(RESULT_MISS) ] = -1,
1446 },
1447 [ C(OP_PREFETCH) ] = {
1448 [ C(RESULT_ACCESS) ] = -1,
1449 [ C(RESULT_MISS) ] = -1,
1450 },
1451 },
1452 [ C(BPU ) ] = {
1453 [ C(OP_READ) ] = {
1454 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1455 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1456 },
1457 [ C(OP_WRITE) ] = {
1458 [ C(RESULT_ACCESS) ] = -1,
1459 [ C(RESULT_MISS) ] = -1,
1460 },
1461 [ C(OP_PREFETCH) ] = {
1462 [ C(RESULT_ACCESS) ] = -1,
1463 [ C(RESULT_MISS) ] = -1,
1464 },
1465 },
1466};
1467
8b92c3a7
KL		 1468static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1469 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1470 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1471 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1472 EVENT_EXTRA_END
1473};
1474
1475#define GLM_DEMAND_DATA_RD BIT_ULL(0)
1476#define GLM_DEMAND_RFO BIT_ULL(1)
1477#define GLM_ANY_RESPONSE BIT_ULL(16)
1478#define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1479#define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1480#define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1481#define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1482#define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1483#define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1484#define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1485
1486static __initconst const u64 glm_hw_cache_event_ids
1487 [PERF_COUNT_HW_CACHE_MAX]
1488 [PERF_COUNT_HW_CACHE_OP_MAX]
1489 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1490 [C(L1D)] = {
1491 [C(OP_READ)] = {
1492 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1493 [C(RESULT_MISS)] = 0x0,
1494 },
1495 [C(OP_WRITE)] = {
1496 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1497 [C(RESULT_MISS)] = 0x0,
1498 },
1499 [C(OP_PREFETCH)] = {
1500 [C(RESULT_ACCESS)] = 0x0,
1501 [C(RESULT_MISS)] = 0x0,
1502 },
1503 },
1504 [C(L1I)] = {
1505 [C(OP_READ)] = {
1506 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1507 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1508 },
1509 [C(OP_WRITE)] = {
1510 [C(RESULT_ACCESS)] = -1,
1511 [C(RESULT_MISS)] = -1,
1512 },
1513 [C(OP_PREFETCH)] = {
1514 [C(RESULT_ACCESS)] = 0x0,
1515 [C(RESULT_MISS)] = 0x0,
1516 },
1517 },
1518 [C(LL)] = {
1519 [C(OP_READ)] = {
1520 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1521 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1522 },
1523 [C(OP_WRITE)] = {
1524 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1525 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1526 },
1527 [C(OP_PREFETCH)] = {
1528 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1529 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1530 },
1531 },
1532 [C(DTLB)] = {
1533 [C(OP_READ)] = {
1534 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1535 [C(RESULT_MISS)] = 0x0,
1536 },
1537 [C(OP_WRITE)] = {
1538 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1539 [C(RESULT_MISS)] = 0x0,
1540 },
1541 [C(OP_PREFETCH)] = {
1542 [C(RESULT_ACCESS)] = 0x0,
1543 [C(RESULT_MISS)] = 0x0,
1544 },
1545 },
1546 [C(ITLB)] = {
1547 [C(OP_READ)] = {
1548 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1549 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1550 },
1551 [C(OP_WRITE)] = {
1552 [C(RESULT_ACCESS)] = -1,
1553 [C(RESULT_MISS)] = -1,
1554 },
1555 [C(OP_PREFETCH)] = {
1556 [C(RESULT_ACCESS)] = -1,
1557 [C(RESULT_MISS)] = -1,
1558 },
1559 },
1560 [C(BPU)] = {
1561 [C(OP_READ)] = {
1562 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1563 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1564 },
1565 [C(OP_WRITE)] = {
1566 [C(RESULT_ACCESS)] = -1,
1567 [C(RESULT_MISS)] = -1,
1568 },
1569 [C(OP_PREFETCH)] = {
1570 [C(RESULT_ACCESS)] = -1,
1571 [C(RESULT_MISS)] = -1,
1572 },
1573 },
1574};
1575
1576static __initconst const u64 glm_hw_cache_extra_regs
1577 [PERF_COUNT_HW_CACHE_MAX]
1578 [PERF_COUNT_HW_CACHE_OP_MAX]
1579 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1580 [C(LL)] = {
1581 [C(OP_READ)] = {
1582 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1583 GLM_LLC_ACCESS,
1584 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1585 GLM_LLC_MISS,
1586 },
1587 [C(OP_WRITE)] = {
1588 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1589 GLM_LLC_ACCESS,
1590 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1591 GLM_LLC_MISS,
1592 },
1593 [C(OP_PREFETCH)] = {
1594 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1595 GLM_LLC_ACCESS,
1596 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1597 GLM_LLC_MISS,
1598 },
1599 },
1600};
1601
1e7b9390
HC		 1602#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1603#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1604#define KNL_MCDRAM_LOCAL BIT_ULL(21)
1605#define KNL_MCDRAM_FAR BIT_ULL(22)
1606#define KNL_DDR_LOCAL BIT_ULL(23)
1607#define KNL_DDR_FAR BIT_ULL(24)
1608#define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1609 KNL_DDR_LOCAL | KNL_DDR_FAR)
1610#define KNL_L2_READ SLM_DMND_READ
1611#define KNL_L2_WRITE SLM_DMND_WRITE
1612#define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1613#define KNL_L2_ACCESS SLM_LLC_ACCESS
1614#define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1615 KNL_DRAM_ANY | SNB_SNP_ANY | \
1616 SNB_NON_DRAM)
1617
1618static __initconst const u64 knl_hw_cache_extra_regs
1619 [PERF_COUNT_HW_CACHE_MAX]
1620 [PERF_COUNT_HW_CACHE_OP_MAX]
1621 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1622 [C(LL)] = {
1623 [C(OP_READ)] = {
1624 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1625 [C(RESULT_MISS)] = 0,
1626 },
1627 [C(OP_WRITE)] = {
1628 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1629 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1630 },
1631 [C(OP_PREFETCH)] = {
1632 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1633 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1634 },
1635 },
1636};
1637
1a78d937 1638/*
c3d266c8
KL		 1639 * Used from PMIs where the LBRs are already disabled.
1640 *
1641 * This function could be called consecutively. It is required to remain in
1642 * disabled state if called consecutively.
1643 *
1644 * During consecutive calls, the same disable value will be written to related
1645 * registers, so the PMU state remains unchanged. hw.state in
1646 * intel_bts_disable_local will remain PERF_HES_STOPPED too in consecutive
1647 * calls.
1a78d937
AK		 1648 */
1649static void __intel_pmu_disable_all(void)
f22f54f4 1650{
89cbc767 1651 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1652
1653 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1654
15c7ad51 1655 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1656 intel_pmu_disable_bts();
8062382c
AS		 1657 else
1658 intel_bts_disable_local();
ca037701
PZ		 1659
1660 intel_pmu_pebs_disable_all();
1a78d937
AK		 1661}
1662
1663static void intel_pmu_disable_all(void)
1664{
1665 __intel_pmu_disable_all();
caff2bef 1666 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1667}
1668
1a78d937 1669static void __intel_pmu_enable_all(int added, bool pmi)
f22f54f4 1670{
89cbc767 1671 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1672
d329527e 1673 intel_pmu_pebs_enable_all();
1a78d937 1674 intel_pmu_lbr_enable_all(pmi);
144d31e6
GN		 1675 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1676 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1677
15c7ad51 1678 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1679 struct perf_event *event =
15c7ad51 1680 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1681
1682 if (WARN_ON_ONCE(!event))
1683 return;
1684
1685 intel_pmu_enable_bts(event->hw.config);
8062382c
AS		 1686 } else
1687 intel_bts_enable_local();
f22f54f4
PZ		 1688}
1689
1a78d937
AK		 1690static void intel_pmu_enable_all(int added)
1691{
1692 __intel_pmu_enable_all(added, false);
1693}
1694
11164cd4
PZ		 1695/*
1696 * Workaround for:
1697 * Intel Errata AAK100 (model 26)
1698 * Intel Errata AAP53 (model 30)
40b91cd1 1699 * Intel Errata BD53 (model 44)
11164cd4 1700 *
351af072
ZY		 1701 * The official story:
1702 * These chips need to be 'reset' when adding counters by programming the
1703 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1704 * in sequence on the same PMC or on different PMCs.
1705 *
1706 * In practise it appears some of these events do in fact count, and
1707 * we need to programm all 4 events.
11164cd4 1708 */
351af072 1709static void intel_pmu_nhm_workaround(void)
11164cd4 1710{
89cbc767 1711 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1712 static const unsigned long nhm_magic[4] = {
1713 0x4300B5,
1714 0x4300D2,
1715 0x4300B1,
1716 0x4300B1
1717 };
1718 struct perf_event *event;
1719 int i;
11164cd4 1720
351af072
ZY		 1721 /*
1722 * The Errata requires below steps:
1723 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1724 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1725 * the corresponding PMCx;
1726 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1727 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1728 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1729 */
11164cd4 1730
351af072
ZY		 1731 /*
1732 * The real steps we choose are a little different from above.
1733 * A) To reduce MSR operations, we don't run step 1) as they
1734 * are already cleared before this function is called;
1735 * B) Call x86_perf_event_update to save PMCx before configuring
1736 * PERFEVTSELx with magic number;
1737 * C) With step 5), we do clear only when the PERFEVTSELx is
1738 * not used currently.
1739 * D) Call x86_perf_event_set_period to restore PMCx;
1740 */
11164cd4 1741
351af072
ZY		 1742 /* We always operate 4 pairs of PERF Counters */
1743 for (i = 0; i < 4; i++) {
1744 event = cpuc->events[i];
1745 if (event)
1746 x86_perf_event_update(event);
1747 }
11164cd4 1748
351af072
ZY		 1749 for (i = 0; i < 4; i++) {
1750 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1751 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1752 }
1753
1754 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1755 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1756
351af072
ZY		 1757 for (i = 0; i < 4; i++) {
1758 event = cpuc->events[i];
1759
1760 if (event) {
1761 x86_perf_event_set_period(event);
31fa58af 1762 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1763 ARCH_PERFMON_EVENTSEL_ENABLE);
1764 } else
1765 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1766 }
351af072
ZY		 1767}
1768
1769static void intel_pmu_nhm_enable_all(int added)
1770{
1771 if (added)
1772 intel_pmu_nhm_workaround();
11164cd4
PZ		 1773 intel_pmu_enable_all(added);
1774}
1775
f22f54f4
PZ		 1776static inline u64 intel_pmu_get_status(void)
1777{
1778 u64 status;
1779
1780 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1781
1782 return status;
1783}
1784
1785static inline void intel_pmu_ack_status(u64 ack)
1786{
1787 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1788}
1789
ca037701 1790static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1791{
15c7ad51 1792 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1793 u64 ctrl_val, mask;
1794
1795 mask = 0xfULL << (idx * 4);
1796
1797 rdmsrl(hwc->config_base, ctrl_val);
1798 ctrl_val &= ~mask;
7645a24c 1799 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1800}
1801
2b9e344d
PZ		 1802static inline bool event_is_checkpointed(struct perf_event *event)
1803{
1804 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1805}
1806
ca037701 1807static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1808{
aff3d91a 1809 struct hw_perf_event *hwc = &event->hw;
89cbc767 1810 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1811
15c7ad51 1812 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1813 intel_pmu_disable_bts();
1814 intel_pmu_drain_bts_buffer();
1815 return;
1816 }
1817
144d31e6
GN		 1818 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1819 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1820 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1821
60ce0fbd
SE		 1822 /*
1823 * must disable before any actual event
1824 * because any event may be combined with LBR
1825 */
a46a2300 1826 if (needs_branch_stack(event))
60ce0fbd
SE		 1827 intel_pmu_lbr_disable(event);
1828
f22f54f4 1829 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1830 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1831 return;
1832 }
1833
aff3d91a 1834 x86_pmu_disable_event(event);
ca037701 1835
ab608344 1836 if (unlikely(event->attr.precise_ip))
ef21f683 1837 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1838}
1839
ca037701 1840static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1841{
15c7ad51 1842 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1843 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1844
1845 /*
1846 * Enable IRQ generation (0x8),
1847 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1848 * if requested:
1849 */
1850 bits = 0x8ULL;
1851 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1852 bits |= 0x2;
1853 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1854 bits |= 0x1;
1855
1856 /*
1857 * ANY bit is supported in v3 and up
1858 */
1859 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1860 bits |= 0x4;
1861
1862 bits <<= (idx * 4);
1863 mask = 0xfULL << (idx * 4);
1864
1865 rdmsrl(hwc->config_base, ctrl_val);
1866 ctrl_val &= ~mask;
1867 ctrl_val |= bits;
7645a24c 1868 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1869}
1870
aff3d91a 1871static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1872{
aff3d91a 1873 struct hw_perf_event *hwc = &event->hw;
89cbc767 1874 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1875
15c7ad51 1876 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1877 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1878 return;
1879
1880 intel_pmu_enable_bts(hwc->config);
1881 return;
1882 }
60ce0fbd
SE		 1883 /*
1884 * must enabled before any actual event
1885 * because any event may be combined with LBR
1886 */
a46a2300 1887 if (needs_branch_stack(event))
60ce0fbd 1888 intel_pmu_lbr_enable(event);
f22f54f4 1889
144d31e6
GN		 1890 if (event->attr.exclude_host)
1891 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1892 if (event->attr.exclude_guest)
1893 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1894
2b9e344d
PZ		 1895 if (unlikely(event_is_checkpointed(event)))
1896 cpuc->intel_cp_status |= (1ull << hwc->idx);
1897
f22f54f4 1898 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1899 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1900 return;
1901 }
1902
ab608344 1903 if (unlikely(event->attr.precise_ip))
ef21f683 1904 intel_pmu_pebs_enable(event);
ca037701 1905
31fa58af 1906 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1907}
1908
1909/*
1910 * Save and restart an expired event. Called by NMI contexts,
1911 * so it has to be careful about preempting normal event ops:
1912 */
de0428a7 1913int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1914{
cc2ad4ba 1915 x86_perf_event_update(event);
2dbf0116
AK		 1916 /*
1917 * For a checkpointed counter always reset back to 0. This
1918 * avoids a situation where the counter overflows, aborts the
1919 * transaction and is then set back to shortly before the
1920 * overflow, and overflows and aborts again.
1921 */
1922 if (unlikely(event_is_checkpointed(event))) {
1923 /* No race with NMIs because the counter should not be armed */
1924 wrmsrl(event->hw.event_base, 0);
1925 local64_set(&event->hw.prev_count, 0);
1926 }
cc2ad4ba 1927 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1928}
1929
1930static void intel_pmu_reset(void)
1931{
0a3aee0d 1932 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1933 unsigned long flags;
1934 int idx;
1935
948b1bb8 1936 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1937 return;
1938
1939 local_irq_save(flags);
1940
c767a54b 1941 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1942
948b1bb8 1943 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1944 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1945 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1946 }
948b1bb8 1947 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1948 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1949
f22f54f4
PZ		 1950 if (ds)
1951 ds->bts_index = ds->bts_buffer_base;
1952
8882edf7
AK		 1953 /* Ack all overflows and disable fixed counters */
1954 if (x86_pmu.version >= 2) {
1955 intel_pmu_ack_status(intel_pmu_get_status());
1956 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1957 }
1958
1959 /* Reset LBRs and LBR freezing */
1960 if (x86_pmu.lbr_nr) {
1961 update_debugctlmsr(get_debugctlmsr() &
1962 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1963 }
1964
f22f54f4
PZ		 1965 local_irq_restore(flags);
1966}
1967
1968/*
1969 * This handler is triggered by the local APIC, so the APIC IRQ handling
1970 * rules apply:
1971 */
1972static int intel_pmu_handle_irq(struct pt_regs *regs)
1973{
1974 struct perf_sample_data data;
1975 struct cpu_hw_events *cpuc;
1976 int bit, loops;
2e556b5b 1977 u64 status;
b0b2072d 1978 int handled;
f22f54f4 1979
89cbc767 1980 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1981
2bce5dac 1982 /*
72db5596
AK		 1983 * No known reason to not always do late ACK,
1984 * but just in case do it opt-in.
2bce5dac 1985 */
72db5596
AK		 1986 if (!x86_pmu.late_ack)
1987 apic_write(APIC_LVTPC, APIC_DM_NMI);
1a78d937 1988 __intel_pmu_disable_all();
b0b2072d 1989 handled = intel_pmu_drain_bts_buffer();
8062382c 1990 handled += intel_bts_interrupt();
f22f54f4 1991 status = intel_pmu_get_status();
a3ef2229
MM		 1992 if (!status)
1993 goto done;
f22f54f4
PZ		 1994
1995 loops = 0;
1996again:
0f29e573 1997 intel_pmu_lbr_read();
2e556b5b 1998 intel_pmu_ack_status(status);
f22f54f4 1999 if (++loops > 100) {
ae0def05
DH		 2000 static bool warned = false;
2001 if (!warned) {
2002 WARN(1, "perfevents: irq loop stuck!\n");
2003 perf_event_print_debug();
2004 warned = true;
2005 }
f22f54f4 2006 intel_pmu_reset();
3fb2b8dd 2007 goto done;
f22f54f4
PZ		 2008 }
2009
2010 inc_irq_stat(apic_perf_irqs);
ca037701 2011
caff2bef 2012
b292d7a1 2013 /*
d8020bee
AK		 2014 * Ignore a range of extra bits in status that do not indicate
2015 * overflow by themselves.
b292d7a1 2016 */
d8020bee
AK		 2017 status &= ~(GLOBAL_STATUS_COND_CHG |
2018 GLOBAL_STATUS_ASIF |
2019 GLOBAL_STATUS_LBRS_FROZEN);
2020 if (!status)
2021 goto done;
b292d7a1 2022
ca037701
PZ		 2023 /*
2024 * PEBS overflow sets bit 62 in the global status register
2025 */
de725dec
PZ		 2026 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2027 handled++;
ca037701 2028 x86_pmu.drain_pebs(regs);
8077eca0
SE		 2029 /*
2030 * There are cases where, even though, the PEBS ovfl bit is set
2031 * in GLOBAL_OVF_STATUS, the PEBS events may also have their
2032 * overflow bits set for their counters. We must clear them
2033 * here because they have been processed as exact samples in
2034 * the drain_pebs() routine. They must not be processed again
2035 * in the for_each_bit_set() loop for regular samples below.
2036 */
2037 status &= ~cpuc->pebs_enabled;
2038 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
de725dec 2039 }
ca037701 2040
52ca9ced
AS		 2041 /*
2042 * Intel PT
2043 */
2044 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2045 handled++;
2046 intel_pt_interrupt();
2047 }
2048
2dbf0116 2049 /*
2b9e344d
PZ		 2050 * Checkpointed counters can lead to 'spurious' PMIs because the
2051 * rollback caused by the PMI will have cleared the overflow status
2052 * bit. Therefore always force probe these counters.
2dbf0116 2053 */
2b9e344d 2054 status |= cpuc->intel_cp_status;
2dbf0116 2055
984b3f57 2056 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 2057 struct perf_event *event = cpuc->events[bit];
2058
de725dec
PZ		 2059 handled++;
2060
f22f54f4
PZ		 2061 if (!test_bit(bit, cpuc->active_mask))
2062 continue;
2063
2064 if (!intel_pmu_save_and_restart(event))
2065 continue;
2066
fd0d000b 2067 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 2068
60ce0fbd
SE		 2069 if (has_branch_stack(event))
2070 data.br_stack = &cpuc->lbr_stack;
2071
a8b0ca17 2072 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 2073 x86_pmu_stop(event, 0);
f22f54f4
PZ		 2074 }
2075
f22f54f4
PZ		 2076 /*
2077 * Repeat if there is more work to be done:
2078 */
2079 status = intel_pmu_get_status();
2080 if (status)
2081 goto again;
2082
3fb2b8dd 2083done:
c3d266c8
KL		 2084 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2085 if (cpuc->enabled)
2086 __intel_pmu_enable_all(0, true);
2087
72db5596
AK		 2088 /*
2089 * Only unmask the NMI after the overflow counters
2090 * have been reset. This avoids spurious NMIs on
2091 * Haswell CPUs.
2092 */
2093 if (x86_pmu.late_ack)
2094 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 2095 return handled;
f22f54f4
PZ		 2096}
2097
f22f54f4 2098static struct event_constraint *
ca037701 2099intel_bts_constraints(struct perf_event *event)
f22f54f4 2100{
ca037701
PZ		 2101 struct hw_perf_event *hwc = &event->hw;
2102 unsigned int hw_event, bts_event;
f22f54f4 2103
18a073a3
PZ		 2104 if (event->attr.freq)
2105 return NULL;
2106
ca037701
PZ		 2107 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
2108 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 2109
ca037701 2110 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 2111 return &bts_constraint;
ca037701 2112
f22f54f4
PZ		 2113 return NULL;
2114}
2115
ae3f011f 2116static int intel_alt_er(int idx, u64 config)
b79e8941 2117{
e01d8718
PZ		 2118 int alt_idx = idx;
2119
9a5e3fb5 2120 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 2121 return idx;
b79e8941 2122
5a425294 2123 if (idx == EXTRA_REG_RSP_0)
ae3f011f 2124 alt_idx = EXTRA_REG_RSP_1;
5a425294
PZ		 2125
2126 if (idx == EXTRA_REG_RSP_1)
ae3f011f 2127 alt_idx = EXTRA_REG_RSP_0;
5a425294 2128
ae3f011f
KL		 2129 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2130 return idx;
2131
2132 return alt_idx;
5a425294
PZ		 2133}
2134
2135static void intel_fixup_er(struct perf_event *event, int idx)
2136{
2137 event->hw.extra_reg.idx = idx;
2138
2139 if (idx == EXTRA_REG_RSP_0) {
b79e8941 2140 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 2141 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 2142 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 2143 } else if (idx == EXTRA_REG_RSP_1) {
2144 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 2145 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 2146 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 2147 }
b79e8941
PZ		 2148}
2149
efc9f05d
SE		 2150/*
2151 * manage allocation of shared extra msr for certain events
2152 *
2153 * sharing can be:
2154 * per-cpu: to be shared between the various events on a single PMU
2155 * per-core: per-cpu + shared by HT threads
2156 */
a7e3ed1e 2157static struct event_constraint *
efc9f05d 2158__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 2159 struct perf_event *event,
2160 struct hw_perf_event_extra *reg)
a7e3ed1e 2161{
efc9f05d 2162 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 2163 struct er_account *era;
cd8a38d3 2164 unsigned long flags;
5a425294 2165 int idx = reg->idx;
a7e3ed1e 2166
5a425294
PZ		 2167 /*
2168 * reg->alloc can be set due to existing state, so for fake cpuc we
2169 * need to ignore this, otherwise we might fail to allocate proper fake
2170 * state for this extra reg constraint. Also see the comment below.
2171 */
2172 if (reg->alloc && !cpuc->is_fake)
b36817e8 2173 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 2174
b79e8941 2175again:
5a425294 2176 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 2177 /*
2178 * we use spin_lock_irqsave() to avoid lockdep issues when
2179 * passing a fake cpuc
2180 */
2181 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 2182
2183 if (!atomic_read(&era->ref) || era->config == reg->config) {
2184
5a425294
PZ		 2185 /*
2186 * If its a fake cpuc -- as per validate_{group,event}() we
2187 * shouldn't touch event state and we can avoid doing so
2188 * since both will only call get_event_constraints() once
2189 * on each event, this avoids the need for reg->alloc.
2190 *
2191 * Not doing the ER fixup will only result in era->reg being
2192 * wrong, but since we won't actually try and program hardware
2193 * this isn't a problem either.
2194 */
2195 if (!cpuc->is_fake) {
2196 if (idx != reg->idx)
2197 intel_fixup_er(event, idx);
2198
2199 /*
2200 * x86_schedule_events() can call get_event_constraints()
2201 * multiple times on events in the case of incremental
2202 * scheduling(). reg->alloc ensures we only do the ER
2203 * allocation once.
2204 */
2205 reg->alloc = 1;
2206 }
2207
efc9f05d
SE		 2208 /* lock in msr value */
2209 era->config = reg->config;
2210 era->reg = reg->reg;
2211
2212 /* one more user */
2213 atomic_inc(&era->ref);
2214
a7e3ed1e 2215 /*
b36817e8
SE		 2216 * need to call x86_get_event_constraint()
2217 * to check if associated event has constraints
a7e3ed1e 2218 */
b36817e8 2219 c = NULL;
5a425294 2220 } else {
ae3f011f 2221 idx = intel_alt_er(idx, reg->config);
5a425294
PZ		 2222 if (idx != reg->idx) {
2223 raw_spin_unlock_irqrestore(&era->lock, flags);
2224 goto again;
2225 }
a7e3ed1e 2226 }
cd8a38d3 2227 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 2228
efc9f05d
SE		 2229 return c;
2230}
2231
2232static void
2233__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2234 struct hw_perf_event_extra *reg)
2235{
2236 struct er_account *era;
2237
2238 /*
5a425294
PZ		 2239 * Only put constraint if extra reg was actually allocated. Also takes
2240 * care of event which do not use an extra shared reg.
2241 *
2242 * Also, if this is a fake cpuc we shouldn't touch any event state
2243 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2244 * either since it'll be thrown out.
efc9f05d 2245 */
5a425294 2246 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 2247 return;
2248
2249 era = &cpuc->shared_regs->regs[reg->idx];
2250
2251 /* one fewer user */
2252 atomic_dec(&era->ref);
2253
2254 /* allocate again next time */
2255 reg->alloc = 0;
2256}
2257
2258static struct event_constraint *
2259intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2260 struct perf_event *event)
2261{
b36817e8
SE		 2262 struct event_constraint *c = NULL, *d;
2263 struct hw_perf_event_extra *xreg, *breg;
2264
2265 xreg = &event->hw.extra_reg;
2266 if (xreg->idx != EXTRA_REG_NONE) {
2267 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2268 if (c == &emptyconstraint)
2269 return c;
2270 }
2271 breg = &event->hw.branch_reg;
2272 if (breg->idx != EXTRA_REG_NONE) {
2273 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2274 if (d == &emptyconstraint) {
2275 __intel_shared_reg_put_constraints(cpuc, xreg);
2276 c = d;
2277 }
2278 }
efc9f05d 2279 return c;
a7e3ed1e
AK		 2280}
2281
de0428a7 2282struct event_constraint *
79cba822
SE		 2283x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2284 struct perf_event *event)
de0428a7
KW		 2285{
2286 struct event_constraint *c;
2287
2288 if (x86_pmu.event_constraints) {
2289 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 2290 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 2291 event->hw.flags |= c->flags;
de0428a7 2292 return c;
9fac2cf3 2293 }
de0428a7
KW		 2294 }
2295 }
2296
2297 return &unconstrained;
2298}
2299
f22f54f4 2300static struct event_constraint *
e979121b 2301__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 2302 struct perf_event *event)
f22f54f4
PZ		 2303{
2304 struct event_constraint *c;
2305
ca037701
PZ		 2306 c = intel_bts_constraints(event);
2307 if (c)
2308 return c;
2309
687805e4 2310 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 2311 if (c)
2312 return c;
2313
687805e4 2314 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 2315 if (c)
2316 return c;
2317
79cba822 2318 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 2319}
2320
e979121b
MD		 2321static void
2322intel_start_scheduling(struct cpu_hw_events *cpuc)
2323{
2324 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2325 struct intel_excl_states *xl;
e979121b 2326 int tid = cpuc->excl_thread_id;
e979121b
MD		 2327
2328 /*
2329 * nothing needed if in group validation mode
2330 */
b37609c3 2331 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b 2332 return;
b37609c3 2333
e979121b
MD		 2334 /*
2335 * no exclusion needed
2336 */
17186ccd 2337 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2338 return;
2339
e979121b
MD		 2340 xl = &excl_cntrs->states[tid];
2341
2342 xl->sched_started = true;
e979121b
MD		 2343 /*
2344 * lock shared state until we are done scheduling
2345 * in stop_event_scheduling()
2346 * makes scheduling appear as a transaction
2347 */
e979121b 2348 raw_spin_lock(&excl_cntrs->lock);
e979121b
MD		 2349}
2350
0c41e756
PZ		 2351static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2352{
2353 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2354 struct event_constraint *c = cpuc->event_constraint[idx];
2355 struct intel_excl_states *xl;
2356 int tid = cpuc->excl_thread_id;
2357
2358 if (cpuc->is_fake || !is_ht_workaround_enabled())
2359 return;
2360
2361 if (WARN_ON_ONCE(!excl_cntrs))
2362 return;
2363
2364 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2365 return;
2366
2367 xl = &excl_cntrs->states[tid];
2368
2369 lockdep_assert_held(&excl_cntrs->lock);
2370
1fe684e3 2371 if (c->flags & PERF_X86_EVENT_EXCL)
43ef205b 2372 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
1fe684e3 2373 else
43ef205b 2374 xl->state[cntr] = INTEL_EXCL_SHARED;
0c41e756
PZ		 2375}
2376
e979121b
MD		 2377static void
2378intel_stop_scheduling(struct cpu_hw_events *cpuc)
2379{
2380 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2381 struct intel_excl_states *xl;
e979121b 2382 int tid = cpuc->excl_thread_id;
e979121b
MD		 2383
2384 /*
2385 * nothing needed if in group validation mode
2386 */
b37609c3 2387 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b
MD		 2388 return;
2389 /*
2390 * no exclusion needed
2391 */
17186ccd 2392 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2393 return;
2394
e979121b
MD		 2395 xl = &excl_cntrs->states[tid];
2396
e979121b
MD		 2397 xl->sched_started = false;
2398 /*
2399 * release shared state lock (acquired in intel_start_scheduling())
2400 */
2401 raw_spin_unlock(&excl_cntrs->lock);
2402}
2403
2404static struct event_constraint *
2405intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2406 int idx, struct event_constraint *c)
2407{
e979121b 2408 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2409 struct intel_excl_states *xlo;
e979121b 2410 int tid = cpuc->excl_thread_id;
1c565833 2411 int is_excl, i;
e979121b
MD		 2412
2413 /*
2414 * validating a group does not require
2415 * enforcing cross-thread exclusion
2416 */
b37609c3
SE		 2417 if (cpuc->is_fake || !is_ht_workaround_enabled())
2418 return c;
2419
2420 /*
2421 * no exclusion needed
2422 */
17186ccd 2423 if (WARN_ON_ONCE(!excl_cntrs))
e979121b 2424 return c;
e979121b 2425
e979121b
MD		 2426 /*
2427 * because we modify the constraint, we need
2428 * to make a copy. Static constraints come
2429 * from static const tables.
2430 *
2431 * only needed when constraint has not yet
2432 * been cloned (marked dynamic)
2433 */
2434 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
aaf932e8 2435 struct event_constraint *cx;
e979121b 2436
e979121b
MD		 2437 /*
2438 * grab pre-allocated constraint entry
2439 */
2440 cx = &cpuc->constraint_list[idx];
2441
2442 /*
2443 * initialize dynamic constraint
2444 * with static constraint
2445 */
aaf932e8 2446 *cx = *c;
e979121b
MD		 2447
2448 /*
2449 * mark constraint as dynamic, so we
2450 * can free it later on
2451 */
2452 cx->flags |= PERF_X86_EVENT_DYNAMIC;
aaf932e8 2453 c = cx;
e979121b
MD		 2454 }
2455
2456 /*
2457 * From here on, the constraint is dynamic.
2458 * Either it was just allocated above, or it
2459 * was allocated during a earlier invocation
2460 * of this function
2461 */
2462
1c565833
PZ		 2463 /*
2464 * state of sibling HT
2465 */
2466 xlo = &excl_cntrs->states[tid ^ 1];
2467
2468 /*
2469 * event requires exclusive counter access
2470 * across HT threads
2471 */
2472 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2473 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2474 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2475 if (!cpuc->n_excl++)
2476 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2477 }
2478
e979121b
MD		 2479 /*
2480 * Modify static constraint with current dynamic
2481 * state of thread
2482 *
2483 * EXCLUSIVE: sibling counter measuring exclusive event
2484 * SHARED : sibling counter measuring non-exclusive event
2485 * UNUSED : sibling counter unused
2486 */
aaf932e8 2487 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
e979121b
MD		 2488 /*
2489 * exclusive event in sibling counter
2490 * our corresponding counter cannot be used
2491 * regardless of our event
2492 */
1c565833 2493 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
aaf932e8 2494 __clear_bit(i, c->idxmsk);
e979121b
MD		 2495 /*
2496 * if measuring an exclusive event, sibling
2497 * measuring non-exclusive, then counter cannot
2498 * be used
2499 */
1c565833 2500 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
aaf932e8 2501 __clear_bit(i, c->idxmsk);
e979121b
MD		 2502 }
2503
2504 /*
2505 * recompute actual bit weight for scheduling algorithm
2506 */
aaf932e8 2507 c->weight = hweight64(c->idxmsk64);
e979121b
MD		 2508
2509 /*
2510 * if we return an empty mask, then switch
2511 * back to static empty constraint to avoid
2512 * the cost of freeing later on
2513 */
aaf932e8
PZ		 2514 if (c->weight == 0)
2515 c = &emptyconstraint;
e979121b 2516
aaf932e8 2517 return c;
e979121b
MD		 2518}
2519
2520static struct event_constraint *
2521intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2522 struct perf_event *event)
2523{
ebfb4988 2524 struct event_constraint *c1 = NULL;
a90738c2 2525 struct event_constraint *c2;
e979121b 2526
ebfb4988
PZ		 2527 if (idx >= 0) /* fake does < 0 */
2528 c1 = cpuc->event_constraint[idx];
2529
e979121b
MD		 2530 /*
2531 * first time only
2532 * - static constraint: no change across incremental scheduling calls
2533 * - dynamic constraint: handled by intel_get_excl_constraints()
2534 */
a90738c2
SE		 2535 c2 = __intel_get_event_constraints(cpuc, idx, event);
2536 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2537 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2538 c1->weight = c2->weight;
2539 c2 = c1;
2540 }
e979121b
MD		 2541
2542 if (cpuc->excl_cntrs)
a90738c2 2543 return intel_get_excl_constraints(cpuc, event, idx, c2);
e979121b 2544
a90738c2 2545 return c2;
e979121b
MD		 2546}
2547
2548static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2549 struct perf_event *event)
2550{
2551 struct hw_perf_event *hwc = &event->hw;
2552 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
e979121b 2553 int tid = cpuc->excl_thread_id;
1c565833 2554 struct intel_excl_states *xl;
e979121b
MD		 2555
2556 /*
2557 * nothing needed if in group validation mode
2558 */
2559 if (cpuc->is_fake)
2560 return;
2561
17186ccd 2562 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2563 return;
2564
cc1790cf
PZ		 2565 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2566 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2567 if (!--cpuc->n_excl)
2568 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2569 }
e979121b
MD		 2570
2571 /*
ba040653
PZ		 2572 * If event was actually assigned, then mark the counter state as
2573 * unused now.
e979121b 2574 */
ba040653
PZ		 2575 if (hwc->idx >= 0) {
2576 xl = &excl_cntrs->states[tid];
2577
2578 /*
2579 * put_constraint may be called from x86_schedule_events()
2580 * which already has the lock held so here make locking
2581 * conditional.
2582 */
2583 if (!xl->sched_started)
2584 raw_spin_lock(&excl_cntrs->lock);
e979121b 2585
1c565833 2586 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
e979121b 2587
ba040653
PZ		 2588 if (!xl->sched_started)
2589 raw_spin_unlock(&excl_cntrs->lock);
2590 }
e979121b
MD		 2591}
2592
efc9f05d
SE		 2593static void
2594intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2595 struct perf_event *event)
2596{
efc9f05d 2597 struct hw_perf_event_extra *reg;
a7e3ed1e 2598
efc9f05d
SE		 2599 reg = &event->hw.extra_reg;
2600 if (reg->idx != EXTRA_REG_NONE)
2601 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2602
2603 reg = &event->hw.branch_reg;
2604 if (reg->idx != EXTRA_REG_NONE)
2605 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2606}
a7e3ed1e 2607
efc9f05d
SE		 2608static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2609 struct perf_event *event)
2610{
2611 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2612
2613 /*
2614 * is PMU has exclusive counter restrictions, then
2615 * all events are subject to and must call the
2616 * put_excl_constraints() routine
2617 */
b371b594 2618 if (cpuc->excl_cntrs)
e979121b 2619 intel_put_excl_constraints(cpuc, event);
e979121b
MD		 2620}
2621
0780c927 2622static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2623{
0780c927 2624 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2625 /*
2626 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2627 * (0x003c) so that we can use it with PEBS.
2628 *
2629 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2630 * PEBS capable. However we can use INST_RETIRED.ANY_P
2631 * (0x00c0), which is a PEBS capable event, to get the same
2632 * count.
2633 *
2634 * INST_RETIRED.ANY_P counts the number of cycles that retires
2635 * CNTMASK instructions. By setting CNTMASK to a value (16)
2636 * larger than the maximum number of instructions that can be
2637 * retired per cycle (4) and then inverting the condition, we
2638 * count all cycles that retire 16 or less instructions, which
2639 * is every cycle.
2640 *
2641 * Thereby we gain a PEBS capable cycle counter.
2642 */
f9b4eeb8
PZ		 2643 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2644
0780c927
PZ		 2645 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2646 event->hw.config = alt_config;
2647 }
2648}
2649
2650static void intel_pebs_aliases_snb(struct perf_event *event)
2651{
2652 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2653 /*
2654 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2655 * (0x003c) so that we can use it with PEBS.
2656 *
2657 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2658 * PEBS capable. However we can use UOPS_RETIRED.ALL
2659 * (0x01c2), which is a PEBS capable event, to get the same
2660 * count.
2661 *
2662 * UOPS_RETIRED.ALL counts the number of cycles that retires
2663 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2664 * larger than the maximum number of micro-ops that can be
2665 * retired per cycle (4) and then inverting the condition, we
2666 * count all cycles that retire 16 or less micro-ops, which
2667 * is every cycle.
2668 *
2669 * Thereby we gain a PEBS capable cycle counter.
2670 */
2671 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 2672
2673 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2674 event->hw.config = alt_config;
2675 }
0780c927
PZ		 2676}
2677
72469764
AK		 2678static void intel_pebs_aliases_precdist(struct perf_event *event)
2679{
2680 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2681 /*
2682 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2683 * (0x003c) so that we can use it with PEBS.
2684 *
2685 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2686 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2687 * (0x01c0), which is a PEBS capable event, to get the same
2688 * count.
2689 *
2690 * The PREC_DIST event has special support to minimize sample
2691 * shadowing effects. One drawback is that it can be
2692 * only programmed on counter 1, but that seems like an
2693 * acceptable trade off.
2694 */
2695 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2696
2697 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2698 event->hw.config = alt_config;
2699 }
2700}
2701
2702static void intel_pebs_aliases_ivb(struct perf_event *event)
2703{
2704 if (event->attr.precise_ip < 3)
2705 return intel_pebs_aliases_snb(event);
2706 return intel_pebs_aliases_precdist(event);
2707}
2708
2709static void intel_pebs_aliases_skl(struct perf_event *event)
2710{
2711 if (event->attr.precise_ip < 3)
2712 return intel_pebs_aliases_core2(event);
2713 return intel_pebs_aliases_precdist(event);
2714}
2715
a7b58d21
AK		 2716static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2717{
2718 unsigned long flags = x86_pmu.free_running_flags;
2719
2720 if (event->attr.use_clockid)
2721 flags &= ~PERF_SAMPLE_TIME;
2722 return flags;
2723}
2724
0780c927
PZ		 2725static int intel_pmu_hw_config(struct perf_event *event)
2726{
2727 int ret = x86_pmu_hw_config(event);
2728
2729 if (ret)
2730 return ret;
2731
851559e3 2732 if (event->attr.precise_ip) {
3569c0d7 2733 if (!event->attr.freq) {
851559e3 2734 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
a7b58d21
AK		 2735 if (!(event->attr.sample_type &
2736 ~intel_pmu_free_running_flags(event)))
3569c0d7
YZ		 2737 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2738 }
851559e3
YZ		 2739 if (x86_pmu.pebs_aliases)
2740 x86_pmu.pebs_aliases(event);
2741 }
7639dae0 2742
a46a2300 2743 if (needs_branch_stack(event)) {
60ce0fbd
SE		 2744 ret = intel_pmu_setup_lbr_filter(event);
2745 if (ret)
2746 return ret;
48070342
AS		 2747
2748 /*
2749 * BTS is set up earlier in this path, so don't account twice
2750 */
2751 if (!intel_pmu_has_bts(event)) {
2752 /* disallow lbr if conflicting events are present */
2753 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2754 return -EBUSY;
2755
2756 event->destroy = hw_perf_lbr_event_destroy;
2757 }
60ce0fbd
SE		 2758 }
2759
b4cdc5c2
PZ		 2760 if (event->attr.type != PERF_TYPE_RAW)
2761 return 0;
2762
2763 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2764 return 0;
2765
2766 if (x86_pmu.version < 3)
2767 return -EINVAL;
2768
2769 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2770 return -EACCES;
2771
2772 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2773
2774 return 0;
2775}
2776
144d31e6
GN		 2777struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2778{
2779 if (x86_pmu.guest_get_msrs)
2780 return x86_pmu.guest_get_msrs(nr);
2781 *nr = 0;
2782 return NULL;
2783}
2784EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2785
2786static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2787{
89cbc767 2788 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2789 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2790
2791 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2792 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2793 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 2794 /*
2795 * If PMU counter has PEBS enabled it is not enough to disable counter
2796 * on a guest entry since PEBS memory write can overshoot guest entry
2797 * and corrupt guest memory. Disabling PEBS solves the problem.
2798 */
2799 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2800 arr[1].host = cpuc->pebs_enabled;
2801 arr[1].guest = 0;
144d31e6 2802
26a4f3c0 2803 *nr = 2;
144d31e6
GN		 2804 return arr;
2805}
2806
2807static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2808{
89cbc767 2809 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2810 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2811 int idx;
2812
2813 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2814 struct perf_event *event = cpuc->events[idx];
2815
2816 arr[idx].msr = x86_pmu_config_addr(idx);
2817 arr[idx].host = arr[idx].guest = 0;
2818
2819 if (!test_bit(idx, cpuc->active_mask))
2820 continue;
2821
2822 arr[idx].host = arr[idx].guest =
2823 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2824
2825 if (event->attr.exclude_host)
2826 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2827 else if (event->attr.exclude_guest)
2828 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2829 }
2830
2831 *nr = x86_pmu.num_counters;
2832 return arr;
2833}
2834
2835static void core_pmu_enable_event(struct perf_event *event)
2836{
2837 if (!event->attr.exclude_host)
2838 x86_pmu_enable_event(event);
2839}
2840
2841static void core_pmu_enable_all(int added)
2842{
89cbc767 2843 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2844 int idx;
2845
2846 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2847 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2848
2849 if (!test_bit(idx, cpuc->active_mask) ||
2850 cpuc->events[idx]->attr.exclude_host)
2851 continue;
2852
2853 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2854 }
2855}
2856
3a632cb2
AK		 2857static int hsw_hw_config(struct perf_event *event)
2858{
2859 int ret = intel_pmu_hw_config(event);
2860
2861 if (ret)
2862 return ret;
2863 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2864 return 0;
2865 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2866
2867 /*
2868 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2869 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2870 * this combination.
2871 */
2872 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2873 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2874 event->attr.precise_ip > 0))
2875 return -EOPNOTSUPP;
2876
2dbf0116
AK		 2877 if (event_is_checkpointed(event)) {
2878 /*
2879 * Sampling of checkpointed events can cause situations where
2880 * the CPU constantly aborts because of a overflow, which is
2881 * then checkpointed back and ignored. Forbid checkpointing
2882 * for sampling.
2883 *
2884 * But still allow a long sampling period, so that perf stat
2885 * from KVM works.
2886 */
2887 if (event->attr.sample_period > 0 &&
2888 event->attr.sample_period < 0x7fffffff)
2889 return -EOPNOTSUPP;
2890 }
3a632cb2
AK		 2891 return 0;
2892}
2893
2894static struct event_constraint counter2_constraint =
2895 EVENT_CONSTRAINT(0, 0x4, 0);
2896
2897static struct event_constraint *
79cba822
SE		 2898hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2899 struct perf_event *event)
3a632cb2 2900{
79cba822
SE		 2901 struct event_constraint *c;
2902
2903 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 2904
2905 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2906 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2907 if (c->idxmsk64 & (1U << 2))
2908 return &counter2_constraint;
2909 return &emptyconstraint;
2910 }
2911
2912 return c;
2913}
2914
294fe0f5
AK		 2915/*
2916 * Broadwell:
2917 *
2918 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2919 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2920 * the two to enforce a minimum period of 128 (the smallest value that has bits
2921 * 0-5 cleared and >= 100).
2922 *
2923 * Because of how the code in x86_perf_event_set_period() works, the truncation
2924 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2925 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2926 *
2927 * Therefore the effective (average) period matches the requested period,
2928 * despite coarser hardware granularity.
2929 */
2930static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2931{
2932 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2933 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2934 if (left < 128)
2935 left = 128;
2936 left &= ~0x3fu;
2937 }
2938 return left;
2939}
2940
641cc938
JO		 2941PMU_FORMAT_ATTR(event, "config:0-7" );
2942PMU_FORMAT_ATTR(umask, "config:8-15" );
2943PMU_FORMAT_ATTR(edge, "config:18" );
2944PMU_FORMAT_ATTR(pc, "config:19" );
2945PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2946PMU_FORMAT_ATTR(inv, "config:23" );
2947PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 2948PMU_FORMAT_ATTR(in_tx, "config:32");
2949PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 2950
2951static struct attribute *intel_arch_formats_attr[] = {
2952 &format_attr_event.attr,
2953 &format_attr_umask.attr,
2954 &format_attr_edge.attr,
2955 &format_attr_pc.attr,
2956 &format_attr_inv.attr,
2957 &format_attr_cmask.attr,
2958 NULL,
2959};
2960
0bf79d44
JO		 2961ssize_t intel_event_sysfs_show(char *page, u64 config)
2962{
2963 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2964
2965 return x86_event_sysfs_show(page, config, event);
2966}
2967
de0428a7 2968struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 2969{
2970 struct intel_shared_regs *regs;
2971 int i;
2972
2973 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2974 GFP_KERNEL, cpu_to_node(cpu));
2975 if (regs) {
2976 /*
2977 * initialize the locks to keep lockdep happy
2978 */
2979 for (i = 0; i < EXTRA_REG_MAX; i++)
2980 raw_spin_lock_init(&regs->regs[i].lock);
2981
2982 regs->core_id = -1;
2983 }
2984 return regs;
2985}
2986
6f6539ca
MD		 2987static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2988{
2989 struct intel_excl_cntrs *c;
6f6539ca
MD		 2990
2991 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2992 GFP_KERNEL, cpu_to_node(cpu));
2993 if (c) {
2994 raw_spin_lock_init(&c->lock);
6f6539ca
MD		 2995 c->core_id = -1;
2996 }
2997 return c;
2998}
2999
a7e3ed1e
AK		 3000static int intel_pmu_cpu_prepare(int cpu)
3001{
3002 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3003
6f6539ca
MD		 3004 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3005 cpuc->shared_regs = allocate_shared_regs(cpu);
3006 if (!cpuc->shared_regs)
dbc72b7a 3007 goto err;
6f6539ca 3008 }
69092624 3009
6f6539ca
MD		 3010 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3011 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3012
3013 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
3014 if (!cpuc->constraint_list)
dbc72b7a 3015 goto err_shared_regs;
6f6539ca
MD		 3016
3017 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
dbc72b7a
PZ		 3018 if (!cpuc->excl_cntrs)
3019 goto err_constraint_list;
3020
6f6539ca
MD		 3021 cpuc->excl_thread_id = 0;
3022 }
a7e3ed1e 3023
a7e3ed1e 3024 return NOTIFY_OK;
dbc72b7a
PZ		 3025
3026err_constraint_list:
3027 kfree(cpuc->constraint_list);
3028 cpuc->constraint_list = NULL;
3029
3030err_shared_regs:
3031 kfree(cpuc->shared_regs);
3032 cpuc->shared_regs = NULL;
3033
3034err:
3035 return NOTIFY_BAD;
a7e3ed1e
AK		 3036}
3037
74846d35
PZ		 3038static void intel_pmu_cpu_starting(int cpu)
3039{
a7e3ed1e
AK		 3040 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3041 int core_id = topology_core_id(cpu);
3042 int i;
3043
69092624
LM		 3044 init_debug_store_on_cpu(cpu);
3045 /*
3046 * Deal with CPUs that don't clear their LBRs on power-up.
3047 */
3048 intel_pmu_lbr_reset();
3049
b36817e8
SE		 3050 cpuc->lbr_sel = NULL;
3051
3052 if (!cpuc->shared_regs)
69092624
LM		 3053 return;
3054
9a5e3fb5 3055 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
06931e62 3056 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
b36817e8 3057 struct intel_shared_regs *pc;
a7e3ed1e 3058
b36817e8
SE		 3059 pc = per_cpu(cpu_hw_events, i).shared_regs;
3060 if (pc && pc->core_id == core_id) {
8f04b853 3061 cpuc->kfree_on_online[0] = cpuc->shared_regs;
b36817e8
SE		 3062 cpuc->shared_regs = pc;
3063 break;
3064 }
a7e3ed1e 3065 }
b36817e8
SE		 3066 cpuc->shared_regs->core_id = core_id;
3067 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 3068 }
3069
b36817e8
SE		 3070 if (x86_pmu.lbr_sel_map)
3071 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 3072
3073 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
06931e62 3074 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6f6539ca
MD		 3075 struct intel_excl_cntrs *c;
3076
3077 c = per_cpu(cpu_hw_events, i).excl_cntrs;
3078 if (c && c->core_id == core_id) {
3079 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3080 cpuc->excl_cntrs = c;
3081 cpuc->excl_thread_id = 1;
3082 break;
3083 }
3084 }
3085 cpuc->excl_cntrs->core_id = core_id;
3086 cpuc->excl_cntrs->refcnt++;
3087 }
74846d35
PZ		 3088}
3089
b37609c3 3090static void free_excl_cntrs(int cpu)
74846d35 3091{
a7e3ed1e 3092 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6f6539ca 3093 struct intel_excl_cntrs *c;
a7e3ed1e 3094
6f6539ca
MD		 3095 c = cpuc->excl_cntrs;
3096 if (c) {
3097 if (c->core_id == -1 || --c->refcnt == 0)
3098 kfree(c);
3099 cpuc->excl_cntrs = NULL;
3100 kfree(cpuc->constraint_list);
3101 cpuc->constraint_list = NULL;
3102 }
b37609c3 3103}
a7e3ed1e 3104
b37609c3
SE		 3105static void intel_pmu_cpu_dying(int cpu)
3106{
3107 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3108 struct intel_shared_regs *pc;
3109
3110 pc = cpuc->shared_regs;
3111 if (pc) {
3112 if (pc->core_id == -1 || --pc->refcnt == 0)
3113 kfree(pc);
3114 cpuc->shared_regs = NULL;
e979121b
MD		 3115 }
3116
b37609c3
SE		 3117 free_excl_cntrs(cpu);
3118
74846d35
PZ		 3119 fini_debug_store_on_cpu(cpu);
3120}
3121
9c964efa
YZ		 3122static void intel_pmu_sched_task(struct perf_event_context *ctx,
3123 bool sched_in)
3124{
3125 if (x86_pmu.pebs_active)
3126 intel_pmu_pebs_sched_task(ctx, sched_in);
3127 if (x86_pmu.lbr_nr)
3128 intel_pmu_lbr_sched_task(ctx, sched_in);
3129}
3130
641cc938
JO		 3131PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3132
a63fcab4
SE		 3133PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3134
d0dc8494
AK		 3135PMU_FORMAT_ATTR(frontend, "config1:0-23");
3136
641cc938
JO		 3137static struct attribute *intel_arch3_formats_attr[] = {
3138 &format_attr_event.attr,
3139 &format_attr_umask.attr,
3140 &format_attr_edge.attr,
3141 &format_attr_pc.attr,
3142 &format_attr_any.attr,
3143 &format_attr_inv.attr,
3144 &format_attr_cmask.attr,
3a632cb2
AK		 3145 &format_attr_in_tx.attr,
3146 &format_attr_in_tx_cp.attr,
641cc938
JO		 3147
3148 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 3149 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 3150 NULL,
3151};
3152
d0dc8494
AK		 3153static struct attribute *skl_format_attr[] = {
3154 &format_attr_frontend.attr,
3155 NULL,
3156};
3157
3b6e0421
JO		 3158static __initconst const struct x86_pmu core_pmu = {
3159 .name = "core",
3160 .handle_irq = x86_pmu_handle_irq,
3161 .disable_all = x86_pmu_disable_all,
3162 .enable_all = core_pmu_enable_all,
3163 .enable = core_pmu_enable_event,
3164 .disable = x86_pmu_disable_event,
3165 .hw_config = x86_pmu_hw_config,
3166 .schedule_events = x86_schedule_events,
3167 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3168 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3169 .event_map = intel_pmu_event_map,
3170 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3171 .apic = 1,
a7b58d21
AK		 3172 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3173
3b6e0421
JO		 3174 /*
3175 * Intel PMCs cannot be accessed sanely above 32-bit width,
3176 * so we install an artificial 1<<31 period regardless of
3177 * the generic event period:
3178 */
3179 .max_period = (1ULL<<31) - 1,
3180 .get_event_constraints = intel_get_event_constraints,
3181 .put_event_constraints = intel_put_event_constraints,
3182 .event_constraints = intel_core_event_constraints,
3183 .guest_get_msrs = core_guest_get_msrs,
3184 .format_attrs = intel_arch_formats_attr,
3185 .events_sysfs_show = intel_event_sysfs_show,
3186
3187 /*
3188 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3189 * together with PMU version 1 and thus be using core_pmu with
3190 * shared_regs. We need following callbacks here to allocate
3191 * it properly.
3192 */
3193 .cpu_prepare = intel_pmu_cpu_prepare,
3194 .cpu_starting = intel_pmu_cpu_starting,
3195 .cpu_dying = intel_pmu_cpu_dying,
3196};
3197
caaa8be3 3198static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 3199 .name = "Intel",
3200 .handle_irq = intel_pmu_handle_irq,
3201 .disable_all = intel_pmu_disable_all,
3202 .enable_all = intel_pmu_enable_all,
3203 .enable = intel_pmu_enable_event,
3204 .disable = intel_pmu_disable_event,
b4cdc5c2 3205 .hw_config = intel_pmu_hw_config,
a072738e 3206 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 3207 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3208 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3209 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 3210 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3211 .apic = 1,
a7b58d21 3212 .free_running_flags = PEBS_FREERUNNING_FLAGS,
f22f54f4
PZ		 3213 /*
3214 * Intel PMCs cannot be accessed sanely above 32 bit width,
3215 * so we install an artificial 1<<31 period regardless of
3216 * the generic event period:
3217 */
3218 .max_period = (1ULL << 31) - 1,
3f6da390 3219 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 3220 .put_event_constraints = intel_put_event_constraints,
0780c927 3221 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 3222
641cc938 3223 .format_attrs = intel_arch3_formats_attr,
0bf79d44 3224 .events_sysfs_show = intel_event_sysfs_show,
641cc938 3225
a7e3ed1e 3226 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 3227 .cpu_starting = intel_pmu_cpu_starting,
3228 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 3229 .guest_get_msrs = intel_guest_get_msrs,
9c964efa 3230 .sched_task = intel_pmu_sched_task,
f22f54f4
PZ		 3231};
3232
c1d6f42f 3233static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 3234{
3235 /*
3236 * PEBS is unreliable due to:
3237 *
3238 * AJ67 - PEBS may experience CPL leaks
3239 * AJ68 - PEBS PMI may be delayed by one event
3240 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3241 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3242 *
3243 * AJ67 could be worked around by restricting the OS/USR flags.
3244 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3245 *
3246 * AJ106 could possibly be worked around by not allowing LBR
3247 * usage from PEBS, including the fixup.
3248 * AJ68 could possibly be worked around by always programming
ec75a716 3249 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 3250 *
3251 * But taken together it might just make sense to not enable PEBS on
3252 * these chips.
3253 */
c767a54b 3254 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 3255 x86_pmu.pebs = 0;
3256 x86_pmu.pebs_constraints = NULL;
3257}
3258
c93dc84c
PZ		 3259static int intel_snb_pebs_broken(int cpu)
3260{
3261 u32 rev = UINT_MAX; /* default to broken for unknown models */
3262
3263 switch (cpu_data(cpu).x86_model) {
3264 case 42: /* SNB */
3265 rev = 0x28;
3266 break;
3267
3268 case 45: /* SNB-EP */
3269 switch (cpu_data(cpu).x86_mask) {
3270 case 6: rev = 0x618; break;
3271 case 7: rev = 0x70c; break;
3272 }
3273 }
3274
3275 return (cpu_data(cpu).microcode < rev);
3276}
3277
3278static void intel_snb_check_microcode(void)
3279{
3280 int pebs_broken = 0;
3281 int cpu;
3282
3283 get_online_cpus();
3284 for_each_online_cpu(cpu) {
3285 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3286 break;
3287 }
3288 put_online_cpus();
3289
3290 if (pebs_broken == x86_pmu.pebs_broken)
3291 return;
3292
3293 /*
3294 * Serialized by the microcode lock..
3295 */
3296 if (x86_pmu.pebs_broken) {
3297 pr_info("PEBS enabled due to microcode update\n");
3298 x86_pmu.pebs_broken = 0;
3299 } else {
3300 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3301 x86_pmu.pebs_broken = 1;
3302 }
3303}
3304
338b522c
KL		 3305/*
3306 * Under certain circumstances, access certain MSR may cause #GP.
3307 * The function tests if the input MSR can be safely accessed.
3308 */
3309static bool check_msr(unsigned long msr, u64 mask)
3310{
3311 u64 val_old, val_new, val_tmp;
3312
3313 /*
3314 * Read the current value, change it and read it back to see if it
3315 * matches, this is needed to detect certain hardware emulators
3316 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3317 */
3318 if (rdmsrl_safe(msr, &val_old))
3319 return false;
3320
3321 /*
3322 * Only change the bits which can be updated by wrmsrl.
3323 */
3324 val_tmp = val_old ^ mask;
3325 if (wrmsrl_safe(msr, val_tmp) ||
3326 rdmsrl_safe(msr, &val_new))
3327 return false;
3328
3329 if (val_new != val_tmp)
3330 return false;
3331
3332 /* Here it's sure that the MSR can be safely accessed.
3333 * Restore the old value and return.
3334 */
3335 wrmsrl(msr, val_old);
3336
3337 return true;
3338}
3339
c1d6f42f 3340static __init void intel_sandybridge_quirk(void)
6a600a8b 3341{
c93dc84c
PZ		 3342 x86_pmu.check_microcode = intel_snb_check_microcode;
3343 intel_snb_check_microcode();
6a600a8b
PZ		 3344}
3345
c1d6f42f
PZ		 3346static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3347 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3348 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3349 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3350 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3351 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3352 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3353 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 3354};
3355
c1d6f42f
PZ		 3356static __init void intel_arch_events_quirk(void)
3357{
3358 int bit;
3359
3360 /* disable event that reported as not presend by cpuid */
3361 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3362 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 3363 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3364 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 3365 }
3366}
3367
3368static __init void intel_nehalem_quirk(void)
3369{
3370 union cpuid10_ebx ebx;
3371
3372 ebx.full = x86_pmu.events_maskl;
3373 if (ebx.split.no_branch_misses_retired) {
3374 /*
3375 * Erratum AAJ80 detected, we work it around by using
3376 * the BR_MISP_EXEC.ANY event. This will over-count
3377 * branch-misses, but it's still much better than the
3378 * architectural event which is often completely bogus:
3379 */
3380 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3381 ebx.split.no_branch_misses_retired = 0;
3382 x86_pmu.events_maskl = ebx.full;
c767a54b 3383 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 3384 }
3385}
3386
93fcf72c
MD		 3387/*
3388 * enable software workaround for errata:
3389 * SNB: BJ122
3390 * IVB: BV98
3391 * HSW: HSD29
3392 *
3393 * Only needed when HT is enabled. However detecting
b37609c3
SE		 3394 * if HT is enabled is difficult (model specific). So instead,
3395 * we enable the workaround in the early boot, and verify if
3396 * it is needed in a later initcall phase once we have valid
3397 * topology information to check if HT is actually enabled
93fcf72c
MD		 3398 */
3399static __init void intel_ht_bug(void)
3400{
b37609c3 3401 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
93fcf72c 3402
93fcf72c 3403 x86_pmu.start_scheduling = intel_start_scheduling;
0c41e756 3404 x86_pmu.commit_scheduling = intel_commit_scheduling;
93fcf72c 3405 x86_pmu.stop_scheduling = intel_stop_scheduling;
93fcf72c
MD		 3406}
3407
7f2ee91f
IM		 3408EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3409EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 3410
4b2c4f1f 3411/* Haswell special events */
7f2ee91f
IM		 3412EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3413EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3414EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3415EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3416EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3417EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3418EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3419EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3420EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3421EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3422EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3423EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 3424
f9134f36 3425static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 3426 EVENT_PTR(tx_start),
3427 EVENT_PTR(tx_commit),
3428 EVENT_PTR(tx_abort),
3429 EVENT_PTR(tx_capacity),
3430 EVENT_PTR(tx_conflict),
3431 EVENT_PTR(el_start),
3432 EVENT_PTR(el_commit),
3433 EVENT_PTR(el_abort),
3434 EVENT_PTR(el_capacity),
3435 EVENT_PTR(el_conflict),
3436 EVENT_PTR(cycles_t),
3437 EVENT_PTR(cycles_ct),
f9134f36
AK		 3438 EVENT_PTR(mem_ld_hsw),
3439 EVENT_PTR(mem_st_hsw),
3440 NULL
3441};
3442
de0428a7 3443__init int intel_pmu_init(void)
f22f54f4
PZ		 3444{
3445 union cpuid10_edx edx;
3446 union cpuid10_eax eax;
ffb871bc 3447 union cpuid10_ebx ebx;
a1eac7ac 3448 struct event_constraint *c;
f22f54f4 3449 unsigned int unused;
338b522c
KL		 3450 struct extra_reg *er;
3451 int version, i;
f22f54f4
PZ		 3452
3453 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 3454 switch (boot_cpu_data.x86) {
3455 case 0x6:
3456 return p6_pmu_init();
e717bf4e
VW		 3457 case 0xb:
3458 return knc_pmu_init();
a072738e
CG		 3459 case 0xf:
3460 return p4_pmu_init();
3461 }
f22f54f4 3462 return -ENODEV;
f22f54f4
PZ		 3463 }
3464
3465 /*
3466 * Check whether the Architectural PerfMon supports
3467 * Branch Misses Retired hw_event or not.
3468 */
ffb871bc
GN		 3469 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3470 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 3471 return -ENODEV;
3472
3473 version = eax.split.version_id;
3474 if (version < 2)
3475 x86_pmu = core_pmu;
3476 else
3477 x86_pmu = intel_pmu;
3478
3479 x86_pmu.version = version;
948b1bb8
RR		 3480 x86_pmu.num_counters = eax.split.num_counters;
3481 x86_pmu.cntval_bits = eax.split.bit_width;
3482 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 3483
c1d6f42f
PZ		 3484 x86_pmu.events_maskl = ebx.full;
3485 x86_pmu.events_mask_len = eax.split.mask_length;
3486
70ab7003
AK		 3487 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3488
f22f54f4
PZ		 3489 /*
3490 * Quirk: v2 perfmon does not report fixed-purpose events, so
3491 * assume at least 3 events:
3492 */
3493 if (version > 1)
948b1bb8 3494 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 3495
c9b08884 3496 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 3497 u64 capabilities;
3498
3499 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3500 x86_pmu.intel_cap.capabilities = capabilities;
3501 }
3502
ca037701
PZ		 3503 intel_ds_init();
3504
c1d6f42f
PZ		 3505 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3506
f22f54f4
PZ		 3507 /*
3508 * Install the hw-cache-events table:
3509 */
3510 switch (boot_cpu_data.x86_model) {
0f7c29ce 3511 case 14: /* 65nm Core "Yonah" */
f22f54f4
PZ		 3512 pr_cont("Core events, ");
3513 break;
3514
0f7c29ce 3515 case 15: /* 65nm Core2 "Merom" */
c1d6f42f 3516 x86_add_quirk(intel_clovertown_quirk);
0f7c29ce
PZ		 3517 case 22: /* 65nm Core2 "Merom-L" */
3518 case 23: /* 45nm Core2 "Penryn" */
3519 case 29: /* 45nm Core2 "Dunnington (MP) */
f22f54f4
PZ		 3520 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3521 sizeof(hw_cache_event_ids));
3522
caff2bef
PZ		 3523 intel_pmu_lbr_init_core();
3524
f22f54f4 3525 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 3526 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 3527 pr_cont("Core2 events, ");
3528 break;
3529
0f7c29ce
PZ		 3530 case 30: /* 45nm Nehalem */
3531 case 26: /* 45nm Nehalem-EP */
3532 case 46: /* 45nm Nehalem-EX */
f22f54f4
PZ		 3533 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3534 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3535 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3536 sizeof(hw_cache_extra_regs));
f22f54f4 3537
caff2bef
PZ		 3538 intel_pmu_lbr_init_nhm();
3539
f22f54f4 3540 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 3541 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 3542 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 3543 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 3544
f20093ee
SE		 3545 x86_pmu.cpu_events = nhm_events_attrs;
3546
91fc4cc0 3547 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3548 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3549 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 3550 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3551 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3552 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 3553
e17dc653 3554 intel_pmu_pebs_data_source_nhm();
c1d6f42f 3555 x86_add_quirk(intel_nehalem_quirk);
ec75a716 3556
11164cd4 3557 pr_cont("Nehalem events, ");
f22f54f4 3558 break;
caff2bef 3559
0f7c29ce
PZ		 3560 case 28: /* 45nm Atom "Pineview" */
3561 case 38: /* 45nm Atom "Lincroft" */
3562 case 39: /* 32nm Atom "Penwell" */
3563 case 53: /* 32nm Atom "Cloverview" */
3564 case 54: /* 32nm Atom "Cedarview" */
f22f54f4
PZ		 3565 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3566 sizeof(hw_cache_event_ids));
3567
caff2bef
PZ		 3568 intel_pmu_lbr_init_atom();
3569
f22f54f4 3570 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 3571 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
673d188b 3572 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
f22f54f4
PZ		 3573 pr_cont("Atom events, ");
3574 break;
3575
0f7c29ce 3576 case 55: /* 22nm Atom "Silvermont" */
ef454cae 3577 case 76: /* 14nm Atom "Airmont" */
0f7c29ce 3578 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
1fa64180
YZ		 3579 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3580 sizeof(hw_cache_event_ids));
3581 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3582 sizeof(hw_cache_extra_regs));
3583
f21d5adc 3584 intel_pmu_lbr_init_slm();
1fa64180
YZ		 3585
3586 x86_pmu.event_constraints = intel_slm_event_constraints;
3587 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3588 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 3589 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
1fa64180
YZ		 3590 pr_cont("Silvermont events, ");
3591 break;
3592
8b92c3a7
KL		 3593 case 92: /* 14nm Atom "Goldmont" */
3594 case 95: /* 14nm Atom "Goldmont Denverton" */
3595 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
3596 sizeof(hw_cache_event_ids));
3597 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
3598 sizeof(hw_cache_extra_regs));
3599
3600 intel_pmu_lbr_init_skl();
3601
3602 x86_pmu.event_constraints = intel_slm_event_constraints;
3603 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
3604 x86_pmu.extra_regs = intel_glm_extra_regs;
3605 /*
3606 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
3607 * for precise cycles.
3608 * :pp is identical to :ppp
3609 */
3610 x86_pmu.pebs_aliases = NULL;
3611 x86_pmu.pebs_prec_dist = true;
ccbebba4 3612 x86_pmu.lbr_pt_coexist = true;
8b92c3a7
KL		 3613 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3614 pr_cont("Goldmont events, ");
3615 break;
3616
0f7c29ce
PZ		 3617 case 37: /* 32nm Westmere */
3618 case 44: /* 32nm Westmere-EP */
3619 case 47: /* 32nm Westmere-EX */
f22f54f4
PZ		 3620 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3621 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3622 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3623 sizeof(hw_cache_extra_regs));
f22f54f4 3624
caff2bef
PZ		 3625 intel_pmu_lbr_init_nhm();
3626
f22f54f4 3627 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 3628 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 3629 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 3630 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 3631 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 3632
f20093ee
SE		 3633 x86_pmu.cpu_events = nhm_events_attrs;
3634
30112039 3635 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3636 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3637 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 3638 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3639 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3640 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 3641
e17dc653 3642 intel_pmu_pebs_data_source_nhm();
f22f54f4
PZ		 3643 pr_cont("Westmere events, ");
3644 break;
b622d644 3645
0f7c29ce
PZ		 3646 case 42: /* 32nm SandyBridge */
3647 case 45: /* 32nm SandyBridge-E/EN/EP */
47a8863d 3648 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 3649 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 3650 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3651 sizeof(hw_cache_event_ids));
74e6543f
YZ		 3652 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3653 sizeof(hw_cache_extra_regs));
b06b3d49 3654
c5cc2cd9 3655 intel_pmu_lbr_init_snb();
b06b3d49
LM		 3656
3657 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 3658 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 3659 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3660 if (boot_cpu_data.x86_model == 45)
3661 x86_pmu.extra_regs = intel_snbep_extra_regs;
3662 else
3663 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 3664
3665
ee89cbc2 3666 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3667 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3668 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 3669
f20093ee
SE		 3670 x86_pmu.cpu_events = snb_events_attrs;
3671
e04d1b23 3672 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 3673 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3674 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3675 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 3676 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3677 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3678
b06b3d49
LM		 3679 pr_cont("SandyBridge events, ");
3680 break;
0f7c29ce
PZ		 3681
3682 case 58: /* 22nm IvyBridge */
3683 case 62: /* 22nm IvyBridge-EP/EX */
93fcf72c 3684 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 3685 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3686 sizeof(hw_cache_event_ids));
1996388e
VW		 3687 /* dTLB-load-misses on IVB is different than SNB */
3688 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3689
20a36e39
SE		 3690 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3691 sizeof(hw_cache_extra_regs));
3692
3693 intel_pmu_lbr_init_snb();
3694
69943182 3695 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39 3696 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
72469764
AK		 3697 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3698 x86_pmu.pebs_prec_dist = true;
f1923820
SE		 3699 if (boot_cpu_data.x86_model == 62)
3700 x86_pmu.extra_regs = intel_snbep_extra_regs;
3701 else
3702 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 3703 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3704 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3705 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 3706
f20093ee
SE		 3707 x86_pmu.cpu_events = snb_events_attrs;
3708
20a36e39
SE		 3709 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3710 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3711 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3712
3713 pr_cont("IvyBridge events, ");
3714 break;
3715
b06b3d49 3716
d86c8eaf
AK		 3717 case 60: /* 22nm Haswell Core */
3718 case 63: /* 22nm Haswell Server */
3719 case 69: /* 22nm Haswell ULT */
3720 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
93fcf72c 3721 x86_add_quirk(intel_ht_bug);
72db5596 3722 x86_pmu.late_ack = true;
0f1b5ca2
AK		 3723 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3724 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 3725
e9d7f7cd 3726 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 3727
3728 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 3729 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 3730 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 3731 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3732 x86_pmu.pebs_prec_dist = true;
3a632cb2 3733 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3734 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3735 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 3736
3737 x86_pmu.hw_config = hsw_hw_config;
3738 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 3739 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 3740 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 3741 pr_cont("Haswell events, ");
3742 break;
3743
91f1b705
AK		 3744 case 61: /* 14nm Broadwell Core-M */
3745 case 86: /* 14nm Broadwell Xeon D */
4b36f1a4
AK		 3746 case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
3747 case 79: /* 14nm Broadwell Server */
91f1b705
AK		 3748 x86_pmu.late_ack = true;
3749 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3750 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3751
3752 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3753 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3754 BDW_L3_MISS|HSW_SNOOP_DRAM;
3755 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3756 HSW_SNOOP_DRAM;
3757 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3758 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3759 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3760 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3761
78d504bc 3762 intel_pmu_lbr_init_hsw();
91f1b705
AK		 3763
3764 x86_pmu.event_constraints = intel_bdw_event_constraints;
b3e62463 3765 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
91f1b705 3766 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 3767 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3768 x86_pmu.pebs_prec_dist = true;
91f1b705 3769 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3770 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3771 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 3772
3773 x86_pmu.hw_config = hsw_hw_config;
3774 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3775 x86_pmu.cpu_events = hsw_events_attrs;
294fe0f5 3776 x86_pmu.limit_period = bdw_limit_period;
91f1b705
AK		 3777 pr_cont("Broadwell events, ");
3778 break;
3779
1e7b9390
HC		 3780 case 87: /* Knights Landing Xeon Phi */
3781 memcpy(hw_cache_event_ids,
3782 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3783 memcpy(hw_cache_extra_regs,
3784 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3785 intel_pmu_lbr_init_knl();
3786
3787 x86_pmu.event_constraints = intel_slm_event_constraints;
3788 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3789 x86_pmu.extra_regs = intel_knl_extra_regs;
3790
3791 /* all extra regs are per-cpu when HT is on */
3792 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3793 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3794
3795 pr_cont("Knights Landing events, ");
3796 break;
3797
cba1b379
AK		 3798 case 142: /* 14nm Kabylake Mobile */
3799 case 158: /* 14nm Kabylake Desktop */
9a92e16f
AK		 3800 case 78: /* 14nm Skylake Mobile */
3801 case 94: /* 14nm Skylake Desktop */
b89c1737 3802 case 85: /* 14nm Skylake Server */
9a92e16f
AK		 3803 x86_pmu.late_ack = true;
3804 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3805 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3806 intel_pmu_lbr_init_skl();
3807
3808 x86_pmu.event_constraints = intel_skl_event_constraints;
3809 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3810 x86_pmu.extra_regs = intel_skl_extra_regs;
72469764
AK		 3811 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
3812 x86_pmu.pebs_prec_dist = true;
9a92e16f
AK		 3813 /* all extra regs are per-cpu when HT is on */
3814 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3815 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3816
3817 x86_pmu.hw_config = hsw_hw_config;
3818 x86_pmu.get_event_constraints = hsw_get_event_constraints;
d0dc8494
AK		 3819 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3820 skl_format_attr);
9a92e16f
AK		 3821 WARN_ON(!x86_pmu.format_attrs);
3822 x86_pmu.cpu_events = hsw_events_attrs;
3823 pr_cont("Skylake events, ");
3824 break;
3825
f22f54f4 3826 default:
0af3ac1f
AK		 3827 switch (x86_pmu.version) {
3828 case 1:
3829 x86_pmu.event_constraints = intel_v1_event_constraints;
3830 pr_cont("generic architected perfmon v1, ");
3831 break;
3832 default:
3833 /*
3834 * default constraints for v2 and up
3835 */
3836 x86_pmu.event_constraints = intel_gen_event_constraints;
3837 pr_cont("generic architected perfmon, ");
3838 break;
3839 }
f22f54f4 3840 }
ffb871bc 3841
a1eac7ac
RR		 3842 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3843 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3844 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3845 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3846 }
3847 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3848
3849 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3850 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3851 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3852 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3853 }
3854
3855 x86_pmu.intel_ctrl |=
3856 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3857
3858 if (x86_pmu.event_constraints) {
3859 /*
3860 * event on fixed counter2 (REF_CYCLES) only works on this
3861 * counter, so do not extend mask to generic counters
3862 */
3863 for_each_event_constraint(c, x86_pmu.event_constraints) {
2c33645d
PI		 3864 if (c->cmask == FIXED_EVENT_FLAGS
3865 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3866 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
a1eac7ac 3867 }
2c33645d 3868 c->idxmsk64 &=
6d6f2833 3869 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
2c33645d 3870 c->weight = hweight64(c->idxmsk64);
a1eac7ac
RR		 3871 }
3872 }
3873
338b522c
KL		 3874 /*
3875 * Access LBR MSR may cause #GP under certain circumstances.
3876 * E.g. KVM doesn't support LBR MSR
3877 * Check all LBT MSR here.
3878 * Disable LBR access if any LBR MSRs can not be accessed.
3879 */
3880 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3881 x86_pmu.lbr_nr = 0;
3882 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3883 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3884 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3885 x86_pmu.lbr_nr = 0;
3886 }
3887
3888 /*
3889 * Access extra MSR may cause #GP under certain circumstances.
3890 * E.g. KVM doesn't support offcore event
3891 * Check all extra_regs here.
3892 */
3893 if (x86_pmu.extra_regs) {
3894 for (er = x86_pmu.extra_regs; er->msr; er++) {
8c4fe709 3895 er->extra_msr_access = check_msr(er->msr, 0x11UL);
338b522c
KL		 3896 /* Disable LBR select mapping */
3897 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3898 x86_pmu.lbr_sel_map = NULL;
3899 }
3900 }
3901
069e0c3c
AK		 3902 /* Support full width counters using alternative MSR range */
3903 if (x86_pmu.intel_cap.full_width_write) {
3904 x86_pmu.max_period = x86_pmu.cntval_mask;
3905 x86_pmu.perfctr = MSR_IA32_PMC0;
3906 pr_cont("full-width counters, ");
3907 }
3908
f22f54f4
PZ		 3909 return 0;
3910}
b37609c3
SE		 3911
3912/*
3913 * HT bug: phase 2 init
3914 * Called once we have valid topology information to check
3915 * whether or not HT is enabled
3916 * If HT is off, then we disable the workaround
3917 */
3918static __init int fixup_ht_bug(void)
3919{
3920 int cpu = smp_processor_id();
3921 int w, c;
3922 /*
3923 * problem not present on this CPU model, nothing to do
3924 */
3925 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3926 return 0;
3927
06931e62 3928 w = cpumask_weight(topology_sibling_cpumask(cpu));
b37609c3
SE		 3929 if (w > 1) {
3930 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3931 return 0;
3932 }
3933
ec6a9066 3934 if (lockup_detector_suspend() != 0) {
999bbe49
UO		 3935 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
3936 return 0;
3937 }
b37609c3
SE		 3938
3939 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3940
b37609c3 3941 x86_pmu.start_scheduling = NULL;
0c41e756 3942 x86_pmu.commit_scheduling = NULL;
b37609c3
SE		 3943 x86_pmu.stop_scheduling = NULL;
3944
ec6a9066 3945 lockup_detector_resume();
b37609c3
SE		 3946
3947 get_online_cpus();
3948
3949 for_each_online_cpu(c) {
3950 free_excl_cntrs(c);
3951 }
3952
3953 put_online_cpus();
3954 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3955 return 0;
3956}
3957subsys_initcall(fixup_ht_bug)
Linux kernel - Deliverables
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