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Merge tag 'iio-for-4.8b' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio...
[deliverable/linux.git] / arch / x86 / events / intel / rapl.c
CommitLineData
4788e5b4
SE		 1/*
2 * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters
3 * Copyright (C) 2013 Google, Inc., Stephane Eranian
4 *
5 * Intel RAPL interface is specified in the IA-32 Manual Vol3b
6 * section 14.7.1 (September 2013)
7 *
8 * RAPL provides more controls than just reporting energy consumption
9 * however here we only expose the 3 energy consumption free running
10 * counters (pp0, pkg, dram).
11 *
12 * Each of those counters increments in a power unit defined by the
13 * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules
14 * but it can vary.
15 *
16 * Counter to rapl events mappings:
17 *
18 * pp0 counter: consumption of all physical cores (power plane 0)
19 * event: rapl_energy_cores
20 * perf code: 0x1
21 *
22 * pkg counter: consumption of the whole processor package
23 * event: rapl_energy_pkg
24 * perf code: 0x2
25 *
26 * dram counter: consumption of the dram domain (servers only)
27 * event: rapl_energy_dram
28 * perf code: 0x3
29 *
dcee75b3 30 * gpu counter: consumption of the builtin-gpu domain (client only)
f228c5b8
SE		 31 * event: rapl_energy_gpu
32 * perf code: 0x4
33 *
dcee75b3
SP		 34 * psys counter: consumption of the builtin-psys domain (client only)
35 * event: rapl_energy_psys
36 * perf code: 0x5
37 *
4788e5b4
SE		 38 * We manage those counters as free running (read-only). They may be
39 * use simultaneously by other tools, such as turbostat.
40 *
41 * The events only support system-wide mode counting. There is no
42 * sampling support because it does not make sense and is not
43 * supported by the RAPL hardware.
44 *
45 * Because we want to avoid floating-point operations in the kernel,
46 * the events are all reported in fixed point arithmetic (32.32).
47 * Tools must adjust the counts to convert them to Watts using
48 * the duration of the measurement. Tools may use a function such as
49 * ldexp(raw_count, -32);
50 */
512089d9
TG		 51
52#define pr_fmt(fmt) "RAPL PMU: " fmt
53
4788e5b4
SE		 54#include <linux/module.h>
55#include <linux/slab.h>
56#include <linux/perf_event.h>
57#include <asm/cpu_device_id.h>
27f6d22b 58#include "../perf_event.h"
4788e5b4 59
4b6e2571
KL		 60MODULE_LICENSE("GPL");
61
4788e5b4
SE		 62/*
63 * RAPL energy status counters
64 */
65#define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */
66#define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */
67#define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */
68#define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */
69#define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */
70#define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */
e69af465 71#define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */
f228c5b8 72#define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */
dcee75b3
SP		 73#define RAPL_IDX_PSYS_NRG_STAT 4 /* psys */
74#define INTEL_RAPL_PSYS 0x5 /* pseudo-encoding */
4788e5b4 75
dcee75b3 76#define NR_RAPL_DOMAINS 0x5
da008ee7 77static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = {
64552396
JP		 78 "pp0-core",
79 "package",
80 "dram",
81 "pp1-gpu",
dcee75b3 82 "psys",
64552396
JP		 83};
84
4788e5b4
SE		 85/* Clients have PP0, PKG */
86#define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
f228c5b8
SE		 87 1<<RAPL_IDX_PKG_NRG_STAT|\
88 1<<RAPL_IDX_PP1_NRG_STAT)
4788e5b4
SE		 89
90/* Servers have PP0, PKG, RAM */
91#define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\
92 1<<RAPL_IDX_PKG_NRG_STAT|\
93 1<<RAPL_IDX_RAM_NRG_STAT)
94
e69af465
VW		 95/* Servers have PP0, PKG, RAM, PP1 */
96#define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\
97 1<<RAPL_IDX_PKG_NRG_STAT|\
98 1<<RAPL_IDX_RAM_NRG_STAT|\
99 1<<RAPL_IDX_PP1_NRG_STAT)
100
dcee75b3
SP		 101/* SKL clients have PP0, PKG, RAM, PP1, PSYS */
102#define RAPL_IDX_SKL_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\
103 1<<RAPL_IDX_PKG_NRG_STAT|\
104 1<<RAPL_IDX_RAM_NRG_STAT|\
105 1<<RAPL_IDX_PP1_NRG_STAT|\
106 1<<RAPL_IDX_PSYS_NRG_STAT)
107
3a2a7797
DC		 108/* Knights Landing has PKG, RAM */
109#define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\
110 1<<RAPL_IDX_RAM_NRG_STAT)
111
4788e5b4
SE		 112/*
113 * event code: LSB 8 bits, passed in attr->config
114 * any other bit is reserved
115 */
116#define RAPL_EVENT_MASK 0xFFULL
117
118#define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \
119static ssize_t __rapl_##_var##_show(struct kobject *kobj, \
120 struct kobj_attribute *attr, \
121 char *page) \
122{ \
123 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
124 return sprintf(page, _format "\n"); \
125} \
126static struct kobj_attribute format_attr_##_var = \
127 __ATTR(_name, 0444, __rapl_##_var##_show, NULL)
128
7162b8fe 129#define RAPL_CNTR_WIDTH 32
4788e5b4 130
d3bcd64b
HR		 131#define RAPL_EVENT_ATTR_STR(_name, v, str) \
132static struct perf_pmu_events_attr event_attr_##v = { \
133 .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \
134 .id = 0, \
135 .event_str = str, \
433678bd
SE		 136};
137
4788e5b4 138struct rapl_pmu {
a208749c 139 raw_spinlock_t lock;
7162b8fe 140 int n_active;
8a6d2f8f 141 int cpu;
7162b8fe
TG		 142 struct list_head active_list;
143 struct pmu *pmu;
144 ktime_t timer_interval;
145 struct hrtimer hrtimer;
4788e5b4
SE		 146};
147
9de8d686
TG		 148struct rapl_pmus {
149 struct pmu pmu;
150 unsigned int maxpkg;
151 struct rapl_pmu *pmus[];
152};
153
7162b8fe
TG		 154 /* 1/2^hw_unit Joule */
155static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly;
9de8d686 156static struct rapl_pmus *rapl_pmus;
4788e5b4 157static cpumask_t rapl_cpu_mask;
9de8d686 158static unsigned int rapl_cntr_mask;
75c7003f 159static u64 rapl_timer_ms;
4788e5b4 160
9de8d686
TG		 161static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu)
162{
163 return rapl_pmus->pmus[topology_logical_package_id(cpu)];
164}
4788e5b4
SE		 165
166static inline u64 rapl_read_counter(struct perf_event *event)
167{
168 u64 raw;
169 rdmsrl(event->hw.event_base, raw);
170 return raw;
171}
172
64552396 173static inline u64 rapl_scale(u64 v, int cfg)
4788e5b4 174{
64552396 175 if (cfg > NR_RAPL_DOMAINS) {
512089d9 176 pr_warn("Invalid domain %d, failed to scale data\n", cfg);
64552396
JP		 177 return v;
178 }
4788e5b4
SE		 179 /*
180 * scale delta to smallest unit (1/2^32)
181 * users must then scale back: count * 1/(1e9*2^32) to get Joules
182 * or use ldexp(count, -32).
183 * Watts = Joules/Time delta
184 */
64552396 185 return v << (32 - rapl_hw_unit[cfg - 1]);
4788e5b4
SE		 186}
187
188static u64 rapl_event_update(struct perf_event *event)
189{
190 struct hw_perf_event *hwc = &event->hw;
191 u64 prev_raw_count, new_raw_count;
192 s64 delta, sdelta;
193 int shift = RAPL_CNTR_WIDTH;
194
195again:
196 prev_raw_count = local64_read(&hwc->prev_count);
197 rdmsrl(event->hw.event_base, new_raw_count);
198
199 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
200 new_raw_count) != prev_raw_count) {
201 cpu_relax();
202 goto again;
203 }
204
205 /*
206 * Now we have the new raw value and have updated the prev
207 * timestamp already. We can now calculate the elapsed delta
208 * (event-)time and add that to the generic event.
209 *
210 * Careful, not all hw sign-extends above the physical width
211 * of the count.
212 */
213 delta = (new_raw_count << shift) - (prev_raw_count << shift);
214 delta >>= shift;
215
64552396 216 sdelta = rapl_scale(delta, event->hw.config);
4788e5b4
SE		 217
218 local64_add(sdelta, &event->count);
219
220 return new_raw_count;
221}
222
65661f96
SE		 223static void rapl_start_hrtimer(struct rapl_pmu *pmu)
224{
514c2304
TG		 225 hrtimer_start(&pmu->hrtimer, pmu->timer_interval,
226 HRTIMER_MODE_REL_PINNED);
65661f96
SE		 227}
228
65661f96
SE		 229static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer)
230{
8a6d2f8f 231 struct rapl_pmu *pmu = container_of(hrtimer, struct rapl_pmu, hrtimer);
65661f96
SE		 232 struct perf_event *event;
233 unsigned long flags;
234
235 if (!pmu->n_active)
236 return HRTIMER_NORESTART;
237
a208749c 238 raw_spin_lock_irqsave(&pmu->lock, flags);
65661f96 239
7162b8fe 240 list_for_each_entry(event, &pmu->active_list, active_entry)
65661f96 241 rapl_event_update(event);
65661f96 242
a208749c 243 raw_spin_unlock_irqrestore(&pmu->lock, flags);
65661f96
SE		 244
245 hrtimer_forward_now(hrtimer, pmu->timer_interval);
246
247 return HRTIMER_RESTART;
248}
249
250static void rapl_hrtimer_init(struct rapl_pmu *pmu)
251{
252 struct hrtimer *hr = &pmu->hrtimer;
253
254 hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
255 hr->function = rapl_hrtimer_handle;
256}
257
4788e5b4
SE		 258static void __rapl_pmu_event_start(struct rapl_pmu *pmu,
259 struct perf_event *event)
260{
261 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
262 return;
263
264 event->hw.state = 0;
265
266 list_add_tail(&event->active_entry, &pmu->active_list);
267
268 local64_set(&event->hw.prev_count, rapl_read_counter(event));
269
270 pmu->n_active++;
65661f96
SE		 271 if (pmu->n_active == 1)
272 rapl_start_hrtimer(pmu);
4788e5b4
SE		 273}
274
275static void rapl_pmu_event_start(struct perf_event *event, int mode)
276{
8a6d2f8f 277 struct rapl_pmu *pmu = event->pmu_private;
4788e5b4
SE		 278 unsigned long flags;
279
a208749c 280 raw_spin_lock_irqsave(&pmu->lock, flags);
4788e5b4 281 __rapl_pmu_event_start(pmu, event);
a208749c 282 raw_spin_unlock_irqrestore(&pmu->lock, flags);
4788e5b4
SE		 283}
284
285static void rapl_pmu_event_stop(struct perf_event *event, int mode)
286{
8a6d2f8f 287 struct rapl_pmu *pmu = event->pmu_private;
4788e5b4
SE		 288 struct hw_perf_event *hwc = &event->hw;
289 unsigned long flags;
290
a208749c 291 raw_spin_lock_irqsave(&pmu->lock, flags);
4788e5b4
SE		 292
293 /* mark event as deactivated and stopped */
294 if (!(hwc->state & PERF_HES_STOPPED)) {
295 WARN_ON_ONCE(pmu->n_active <= 0);
296 pmu->n_active--;
65661f96 297 if (pmu->n_active == 0)
7162b8fe 298 hrtimer_cancel(&pmu->hrtimer);
4788e5b4
SE		 299
300 list_del(&event->active_entry);
301
302 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
303 hwc->state |= PERF_HES_STOPPED;
304 }
305
306 /* check if update of sw counter is necessary */
307 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
308 /*
309 * Drain the remaining delta count out of a event
310 * that we are disabling:
311 */
312 rapl_event_update(event);
313 hwc->state |= PERF_HES_UPTODATE;
314 }
315
a208749c 316 raw_spin_unlock_irqrestore(&pmu->lock, flags);
4788e5b4
SE		 317}
318
319static int rapl_pmu_event_add(struct perf_event *event, int mode)
320{
8a6d2f8f 321 struct rapl_pmu *pmu = event->pmu_private;
4788e5b4
SE		 322 struct hw_perf_event *hwc = &event->hw;
323 unsigned long flags;
324
a208749c 325 raw_spin_lock_irqsave(&pmu->lock, flags);
4788e5b4
SE		 326
327 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
328
329 if (mode & PERF_EF_START)
330 __rapl_pmu_event_start(pmu, event);
331
a208749c 332 raw_spin_unlock_irqrestore(&pmu->lock, flags);
4788e5b4
SE		 333
334 return 0;
335}
336
337static void rapl_pmu_event_del(struct perf_event *event, int flags)
338{
339 rapl_pmu_event_stop(event, PERF_EF_UPDATE);
340}
341
342static int rapl_pmu_event_init(struct perf_event *event)
343{
344 u64 cfg = event->attr.config & RAPL_EVENT_MASK;
345 int bit, msr, ret = 0;
9de8d686 346 struct rapl_pmu *pmu;
4788e5b4
SE		 347
348 /* only look at RAPL events */
9de8d686 349 if (event->attr.type != rapl_pmus->pmu.type)
4788e5b4
SE		 350 return -ENOENT;
351
352 /* check only supported bits are set */
353 if (event->attr.config & ~RAPL_EVENT_MASK)
354 return -EINVAL;
355
8a6d2f8f
TG		 356 if (event->cpu < 0)
357 return -EINVAL;
358
4788e5b4
SE		 359 /*
360 * check event is known (determines counter)
361 */
362 switch (cfg) {
363 case INTEL_RAPL_PP0:
364 bit = RAPL_IDX_PP0_NRG_STAT;
365 msr = MSR_PP0_ENERGY_STATUS;
366 break;
367 case INTEL_RAPL_PKG:
368 bit = RAPL_IDX_PKG_NRG_STAT;
369 msr = MSR_PKG_ENERGY_STATUS;
370 break;
371 case INTEL_RAPL_RAM:
372 bit = RAPL_IDX_RAM_NRG_STAT;
373 msr = MSR_DRAM_ENERGY_STATUS;
374 break;
f228c5b8
SE		 375 case INTEL_RAPL_PP1:
376 bit = RAPL_IDX_PP1_NRG_STAT;
377 msr = MSR_PP1_ENERGY_STATUS;
378 break;
dcee75b3
SP		 379 case INTEL_RAPL_PSYS:
380 bit = RAPL_IDX_PSYS_NRG_STAT;
381 msr = MSR_PLATFORM_ENERGY_STATUS;
382 break;
4788e5b4
SE		 383 default:
384 return -EINVAL;
385 }
386 /* check event supported */
387 if (!(rapl_cntr_mask & (1 << bit)))
388 return -EINVAL;
389
390 /* unsupported modes and filters */
391 if (event->attr.exclude_user ||
392 event->attr.exclude_kernel ||
393 event->attr.exclude_hv ||
394 event->attr.exclude_idle ||
395 event->attr.exclude_host ||
396 event->attr.exclude_guest ||
397 event->attr.sample_period) /* no sampling */
398 return -EINVAL;
399
400 /* must be done before validate_group */
9de8d686 401 pmu = cpu_to_rapl_pmu(event->cpu);
8a6d2f8f
TG		 402 event->cpu = pmu->cpu;
403 event->pmu_private = pmu;
4788e5b4
SE		 404 event->hw.event_base = msr;
405 event->hw.config = cfg;
406 event->hw.idx = bit;
407
408 return ret;
409}
410
411static void rapl_pmu_event_read(struct perf_event *event)
412{
413 rapl_event_update(event);
414}
415
416static ssize_t rapl_get_attr_cpumask(struct device *dev,
417 struct device_attribute *attr, char *buf)
418{
5aaba363 419 return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask);
4788e5b4
SE		 420}
421
422static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL);
423
424static struct attribute *rapl_pmu_attrs[] = {
425 &dev_attr_cpumask.attr,
426 NULL,
427};
428
429static struct attribute_group rapl_pmu_attr_group = {
430 .attrs = rapl_pmu_attrs,
431};
432
433678bd
SE		 433RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
434RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02");
435RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03");
436RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04");
dcee75b3 437RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=0x05");
4788e5b4 438
433678bd
SE		 439RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
440RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules");
441RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules");
442RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules");
dcee75b3 443RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_psys_unit, "Joules");
4788e5b4
SE		 444
445/*
446 * we compute in 0.23 nJ increments regardless of MSR
447 */
433678bd
SE		 448RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
449RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10");
450RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10");
451RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
dcee75b3 452RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386962890625e-10");
4788e5b4
SE		 453
454static struct attribute *rapl_events_srv_attr[] = {
455 EVENT_PTR(rapl_cores),
456 EVENT_PTR(rapl_pkg),
457 EVENT_PTR(rapl_ram),
458
459 EVENT_PTR(rapl_cores_unit),
460 EVENT_PTR(rapl_pkg_unit),
461 EVENT_PTR(rapl_ram_unit),
462
463 EVENT_PTR(rapl_cores_scale),
464 EVENT_PTR(rapl_pkg_scale),
465 EVENT_PTR(rapl_ram_scale),
466 NULL,
467};
468
469static struct attribute *rapl_events_cln_attr[] = {
470 EVENT_PTR(rapl_cores),
471 EVENT_PTR(rapl_pkg),
f228c5b8 472 EVENT_PTR(rapl_gpu),
4788e5b4
SE		 473
474 EVENT_PTR(rapl_cores_unit),
475 EVENT_PTR(rapl_pkg_unit),
f228c5b8 476 EVENT_PTR(rapl_gpu_unit),
4788e5b4
SE		 477
478 EVENT_PTR(rapl_cores_scale),
479 EVENT_PTR(rapl_pkg_scale),
f228c5b8 480 EVENT_PTR(rapl_gpu_scale),
4788e5b4
SE		 481 NULL,
482};
483
e69af465
VW		 484static struct attribute *rapl_events_hsw_attr[] = {
485 EVENT_PTR(rapl_cores),
486 EVENT_PTR(rapl_pkg),
487 EVENT_PTR(rapl_gpu),
488 EVENT_PTR(rapl_ram),
489
490 EVENT_PTR(rapl_cores_unit),
491 EVENT_PTR(rapl_pkg_unit),
492 EVENT_PTR(rapl_gpu_unit),
493 EVENT_PTR(rapl_ram_unit),
494
495 EVENT_PTR(rapl_cores_scale),
496 EVENT_PTR(rapl_pkg_scale),
497 EVENT_PTR(rapl_gpu_scale),
498 EVENT_PTR(rapl_ram_scale),
499 NULL,
500};
501
dcee75b3
SP		 502static struct attribute *rapl_events_skl_attr[] = {
503 EVENT_PTR(rapl_cores),
504 EVENT_PTR(rapl_pkg),
505 EVENT_PTR(rapl_gpu),
506 EVENT_PTR(rapl_ram),
507 EVENT_PTR(rapl_psys),
508
509 EVENT_PTR(rapl_cores_unit),
510 EVENT_PTR(rapl_pkg_unit),
511 EVENT_PTR(rapl_gpu_unit),
512 EVENT_PTR(rapl_ram_unit),
513 EVENT_PTR(rapl_psys_unit),
514
515 EVENT_PTR(rapl_cores_scale),
516 EVENT_PTR(rapl_pkg_scale),
517 EVENT_PTR(rapl_gpu_scale),
518 EVENT_PTR(rapl_ram_scale),
519 EVENT_PTR(rapl_psys_scale),
520 NULL,
521};
522
3a2a7797
DC		 523static struct attribute *rapl_events_knl_attr[] = {
524 EVENT_PTR(rapl_pkg),
525 EVENT_PTR(rapl_ram),
526
527 EVENT_PTR(rapl_pkg_unit),
528 EVENT_PTR(rapl_ram_unit),
529
530 EVENT_PTR(rapl_pkg_scale),
531 EVENT_PTR(rapl_ram_scale),
532 NULL,
533};
534
4788e5b4
SE		 535static struct attribute_group rapl_pmu_events_group = {
536 .name = "events",
537 .attrs = NULL, /* patched at runtime */
538};
539
540DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7");
541static struct attribute *rapl_formats_attr[] = {
542 &format_attr_event.attr,
543 NULL,
544};
545
546static struct attribute_group rapl_pmu_format_group = {
547 .name = "format",
548 .attrs = rapl_formats_attr,
549};
550
551const struct attribute_group *rapl_attr_groups[] = {
552 &rapl_pmu_attr_group,
553 &rapl_pmu_format_group,
554 &rapl_pmu_events_group,
555 NULL,
556};
557
4788e5b4
SE		 558static void rapl_cpu_exit(int cpu)
559{
9de8d686
TG		 560 struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu);
561 int target;
4788e5b4 562
9de8d686
TG		 563 /* Check if exiting cpu is used for collecting rapl events */
564 if (!cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask))
565 return;
4788e5b4 566
9de8d686
TG		 567 pmu->cpu = -1;
568 /* Find a new cpu to collect rapl events */
569 target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
65661f96 570
9de8d686
TG		 571 /* Migrate rapl events to the new target */
572 if (target < nr_cpu_ids) {
573 cpumask_set_cpu(target, &rapl_cpu_mask);
574 pmu->cpu = target;
575 perf_pmu_migrate_context(pmu->pmu, cpu, target);
576 }
4788e5b4
SE		 577}
578
579static void rapl_cpu_init(int cpu)
580{
9de8d686
TG		 581 struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu);
582 int target;
583
584 /*
585 * Check if there is an online cpu in the package which collects rapl
586 * events already.
587 */
588 target = cpumask_any_and(&rapl_cpu_mask, topology_core_cpumask(cpu));
589 if (target < nr_cpu_ids)
590 return;
4788e5b4 591
4788e5b4 592 cpumask_set_cpu(cpu, &rapl_cpu_mask);
9de8d686 593 pmu->cpu = cpu;
4788e5b4
SE		 594}
595
596static int rapl_cpu_prepare(int cpu)
597{
9de8d686 598 struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu);
4788e5b4
SE		 599
600 if (pmu)
601 return 0;
602
4788e5b4
SE		 603 pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu));
604 if (!pmu)
9de8d686 605 return -ENOMEM;
4788e5b4 606
9de8d686 607 raw_spin_lock_init(&pmu->lock);
4788e5b4 608 INIT_LIST_HEAD(&pmu->active_list);
9de8d686 609 pmu->pmu = &rapl_pmus->pmu;
75c7003f 610 pmu->timer_interval = ms_to_ktime(rapl_timer_ms);
9de8d686 611 pmu->cpu = -1;
65661f96 612 rapl_hrtimer_init(pmu);
9de8d686 613 rapl_pmus->pmus[topology_logical_package_id(cpu)] = pmu;
4788e5b4
SE		 614 return 0;
615}
616
617static int rapl_cpu_notifier(struct notifier_block *self,
618 unsigned long action, void *hcpu)
619{
620 unsigned int cpu = (long)hcpu;
621
622 switch (action & ~CPU_TASKS_FROZEN) {
623 case CPU_UP_PREPARE:
624 rapl_cpu_prepare(cpu);
625 break;
9de8d686
TG		 626
627 case CPU_DOWN_FAILED:
4788e5b4 628 case CPU_ONLINE:
9de8d686 629 rapl_cpu_init(cpu);
4788e5b4 630 break;
9de8d686 631
4788e5b4
SE		 632 case CPU_DOWN_PREPARE:
633 rapl_cpu_exit(cpu);
634 break;
4788e5b4 635 }
4788e5b4
SE		 636 return NOTIFY_OK;
637}
638
4b6e2571
KL		 639static struct notifier_block rapl_cpu_nb = {
640 .notifier_call = rapl_cpu_notifier,
641 .priority = CPU_PRI_PERF + 1,
642};
643
7a869805 644static int rapl_check_hw_unit(bool apply_quirk)
64552396
JP		 645{
646 u64 msr_rapl_power_unit_bits;
647 int i;
648
649 /* protect rdmsrl() to handle virtualization */
650 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits))
651 return -1;
652 for (i = 0; i < NR_RAPL_DOMAINS; i++)
653 rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
654
7a869805
BP		 655 /*
656 * DRAM domain on HSW server and KNL has fixed energy unit which can be
657 * different than the unit from power unit MSR. See
658 * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
659 * of 2. Datasheet, September 2014, Reference Number: 330784-001 "
660 */
661 if (apply_quirk)
662 rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16;
75c7003f
TG		 663
664 /*
665 * Calculate the timer rate:
666 * Use reference of 200W for scaling the timeout to avoid counter
667 * overflows. 200W = 200 Joules/sec
668 * Divide interval by 2 to avoid lockstep (2 * 100)
669 * if hw unit is 32, then we use 2 ms 1/200/2
670 */
671 rapl_timer_ms = 2;
672 if (rapl_hw_unit[0] < 32) {
673 rapl_timer_ms = (1000 / (2 * 100));
674 rapl_timer_ms *= (1ULL << (32 - rapl_hw_unit[0] - 1));
675 }
64552396
JP		 676 return 0;
677}
678
512089d9
TG		 679static void __init rapl_advertise(void)
680{
681 int i;
682
683 pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\n",
684 hweight32(rapl_cntr_mask), rapl_timer_ms);
685
686 for (i = 0; i < NR_RAPL_DOMAINS; i++) {
687 if (rapl_cntr_mask & (1 << i)) {
688 pr_info("hw unit of domain %s 2^-%d Joules\n",
689 rapl_domain_names[i], rapl_hw_unit[i]);
690 }
691 }
692}
693
7162b8fe
TG		 694static int __init rapl_prepare_cpus(void)
695{
9de8d686 696 unsigned int cpu, pkg;
7162b8fe
TG		 697 int ret;
698
699 for_each_online_cpu(cpu) {
9de8d686
TG		 700 pkg = topology_logical_package_id(cpu);
701 if (rapl_pmus->pmus[pkg])
702 continue;
703
7162b8fe
TG		 704 ret = rapl_cpu_prepare(cpu);
705 if (ret)
706 return ret;
707 rapl_cpu_init(cpu);
708 }
709 return 0;
710}
711
4b6e2571 712static void cleanup_rapl_pmus(void)
55f2890f 713{
9de8d686
TG		 714 int i;
715
716 for (i = 0; i < rapl_pmus->maxpkg; i++)
275ae411 717 kfree(rapl_pmus->pmus[i]);
9de8d686
TG		 718 kfree(rapl_pmus);
719}
55f2890f 720
9de8d686
TG		 721static int __init init_rapl_pmus(void)
722{
723 int maxpkg = topology_max_packages();
724 size_t size;
725
726 size = sizeof(*rapl_pmus) + maxpkg * sizeof(struct rapl_pmu *);
727 rapl_pmus = kzalloc(size, GFP_KERNEL);
728 if (!rapl_pmus)
729 return -ENOMEM;
730
731 rapl_pmus->maxpkg = maxpkg;
732 rapl_pmus->pmu.attr_groups = rapl_attr_groups;
733 rapl_pmus->pmu.task_ctx_nr = perf_invalid_context;
734 rapl_pmus->pmu.event_init = rapl_pmu_event_init;
735 rapl_pmus->pmu.add = rapl_pmu_event_add;
736 rapl_pmus->pmu.del = rapl_pmu_event_del;
737 rapl_pmus->pmu.start = rapl_pmu_event_start;
738 rapl_pmus->pmu.stop = rapl_pmu_event_stop;
739 rapl_pmus->pmu.read = rapl_pmu_event_read;
740 return 0;
55f2890f
TG		 741}
742
4b6e2571
KL		 743#define X86_RAPL_MODEL_MATCH(model, init) \
744 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init }
745
746struct intel_rapl_init_fun {
747 bool apply_quirk;
748 int cntr_mask;
749 struct attribute **attrs;
750};
751
752static const struct intel_rapl_init_fun snb_rapl_init __initconst = {
753 .apply_quirk = false,
754 .cntr_mask = RAPL_IDX_CLN,
755 .attrs = rapl_events_cln_attr,
756};
757
758static const struct intel_rapl_init_fun hsx_rapl_init __initconst = {
759 .apply_quirk = true,
760 .cntr_mask = RAPL_IDX_SRV,
761 .attrs = rapl_events_srv_attr,
762};
763
764static const struct intel_rapl_init_fun hsw_rapl_init __initconst = {
765 .apply_quirk = false,
766 .cntr_mask = RAPL_IDX_HSW,
767 .attrs = rapl_events_hsw_attr,
768};
769
770static const struct intel_rapl_init_fun snbep_rapl_init __initconst = {
771 .apply_quirk = false,
772 .cntr_mask = RAPL_IDX_SRV,
773 .attrs = rapl_events_srv_attr,
774};
775
776static const struct intel_rapl_init_fun knl_rapl_init __initconst = {
777 .apply_quirk = true,
778 .cntr_mask = RAPL_IDX_KNL,
779 .attrs = rapl_events_knl_attr,
780};
781
dcee75b3
SP		 782static const struct intel_rapl_init_fun skl_rapl_init __initconst = {
783 .apply_quirk = false,
784 .cntr_mask = RAPL_IDX_SKL_CLN,
785 .attrs = rapl_events_skl_attr,
786};
787
7162b8fe 788static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
4b6e2571 789 X86_RAPL_MODEL_MATCH(42, snb_rapl_init), /* Sandy Bridge */
c416e5aa
PZ		 790 X86_RAPL_MODEL_MATCH(45, snbep_rapl_init), /* Sandy Bridge-EP */
791
4b6e2571 792 X86_RAPL_MODEL_MATCH(58, snb_rapl_init), /* Ivy Bridge */
c416e5aa
PZ		 793 X86_RAPL_MODEL_MATCH(62, snbep_rapl_init), /* IvyTown */
794
4b6e2571 795 X86_RAPL_MODEL_MATCH(60, hsw_rapl_init), /* Haswell */
c416e5aa 796 X86_RAPL_MODEL_MATCH(63, hsx_rapl_init), /* Haswell-Server */
4b6e2571 797 X86_RAPL_MODEL_MATCH(69, hsw_rapl_init), /* Haswell-Celeron */
65cbbd03 798 X86_RAPL_MODEL_MATCH(70, hsw_rapl_init), /* Haswell GT3e */
c416e5aa 799
4b6e2571
KL		 800 X86_RAPL_MODEL_MATCH(61, hsw_rapl_init), /* Broadwell */
801 X86_RAPL_MODEL_MATCH(71, hsw_rapl_init), /* Broadwell-H */
c416e5aa 802 X86_RAPL_MODEL_MATCH(79, hsx_rapl_init), /* Broadwell-Server */
31b84310 803 X86_RAPL_MODEL_MATCH(86, hsx_rapl_init), /* Broadwell Xeon D */
c416e5aa 804
4b6e2571 805 X86_RAPL_MODEL_MATCH(87, knl_rapl_init), /* Knights Landing */
c416e5aa 806
dcee75b3
SP		 807 X86_RAPL_MODEL_MATCH(78, skl_rapl_init), /* Skylake */
808 X86_RAPL_MODEL_MATCH(94, skl_rapl_init), /* Skylake H/S */
4b6e2571 809 {},
4788e5b4
SE		 810};
811
4b6e2571
KL		 812MODULE_DEVICE_TABLE(x86cpu, rapl_cpu_match);
813
4788e5b4
SE		 814static int __init rapl_pmu_init(void)
815{
4b6e2571
KL		 816 const struct x86_cpu_id *id;
817 struct intel_rapl_init_fun *rapl_init;
818 bool apply_quirk;
7162b8fe 819 int ret;
4788e5b4 820
4b6e2571
KL		 821 id = x86_match_cpu(rapl_cpu_match);
822 if (!id)
55f2890f 823 return -ENODEV;
4788e5b4 824
4b6e2571
KL		 825 rapl_init = (struct intel_rapl_init_fun *)id->driver_data;
826 apply_quirk = rapl_init->apply_quirk;
827 rapl_cntr_mask = rapl_init->cntr_mask;
828 rapl_pmu_events_group.attrs = rapl_init->attrs;
55f2890f 829
7a869805 830 ret = rapl_check_hw_unit(apply_quirk);
64552396
JP		 831 if (ret)
832 return ret;
fd537e56 833
9de8d686
TG		 834 ret = init_rapl_pmus();
835 if (ret)
836 return ret;
837
fd537e56 838 cpu_notifier_register_begin();
4788e5b4 839
7162b8fe
TG		 840 ret = rapl_prepare_cpus();
841 if (ret)
842 goto out;
4788e5b4 843
9de8d686 844 ret = perf_pmu_register(&rapl_pmus->pmu, "power", -1);
512089d9 845 if (ret)
55f2890f 846 goto out;
4788e5b4 847
4b6e2571 848 __register_cpu_notifier(&rapl_cpu_nb);
75c7003f 849 cpu_notifier_register_done();
512089d9 850 rapl_advertise();
4788e5b4 851 return 0;
55f2890f
TG		 852
853out:
512089d9 854 pr_warn("Initialization failed (%d), disabled\n", ret);
55f2890f
TG		 855 cleanup_rapl_pmus();
856 cpu_notifier_register_done();
857 return ret;
4788e5b4 858}
4b6e2571
KL		 859module_init(rapl_pmu_init);
860
861static void __exit intel_rapl_exit(void)
862{
863 cpu_notifier_register_begin();
864 __unregister_cpu_notifier(&rapl_cpu_nb);
865 perf_pmu_unregister(&rapl_pmus->pmu);
866 cleanup_rapl_pmus();
867 cpu_notifier_register_done();
868}
869module_exit(intel_rapl_exit);
Linux kernel - Deliverables
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